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Change in coreboot[master]: sb/intel/i82801ix: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37141 ) Change subject: sb/intel/i82801ix: Use common AHCI ...................................................................... sb/intel/i82801ix: Use common AHCI Untested. Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/sata.c 2 files changed, 12 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37141/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8363978..9ef680b 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fa6c1df..7143fa2 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -24,60 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - struct resource *res; - - /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (!res) - return; - - u8 *abar = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -228,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Gerrit-Change-Number: 37141 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37142 ) Change subject: sb/intel/i82801gx: Use common AHCI ...................................................................... sb/intel/i82801gx: Use common AHCI Untested. Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/sata.c 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37142/1 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2..b8f8731 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 47c35ba..f902013 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "i82801gx.h" #include "sata.h" @@ -154,11 +156,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (ahci_res != NULL) - /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + sb_ahci_init(dev, config->sata_ports_implemented, false, false, 0, false, 0); break; default: case SATA_MODE_IDE_PLAIN: -- To view, visit https://review.coreboot.org/c/coreboot/+/37142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Gerrit-Change-Number: 37142 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37143 ) Change subject: sb/intel/i82801jx: Use common AHCI ...................................................................... sb/intel/i82801jx: Use common AHCI Untested. Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/sata.c 2 files changed, 12 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37143/1 diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 161290f..81da68f 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..b18f465 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -24,55 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - - /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -223,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Gerrit-Change-Number: 37143 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x131e: remove non-applicable options from CMOS
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37146 ) Change subject: mb/lenovo/x131e: remove non-applicable options from CMOS ...................................................................... mb/lenovo/x131e: remove non-applicable options from CMOS These options do not work in the same way as on the Lenovo H8 EC. Since they don't work correctly, drop them from the CMOS settings. Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/cmos.default M src/mainboard/lenovo/x131e/cmos.layout 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37146/1 diff --git a/src/mainboard/lenovo/x131e/cmos.default b/src/mainboard/lenovo/x131e/cmos.default index b01978a..ca10a85 100644 --- a/src/mainboard/lenovo/x131e/cmos.default +++ b/src/mainboard/lenovo/x131e/cmos.default @@ -3,12 +3,7 @@ power_on_after_fail=Disable nmi=Enable volume=0x3 -bluetooth=Enable wwan=Enable -wlan=Enable -touchpad=Enable sata_mode=AHCI -fn_ctrl_swap=Disable sticky_fn=Disable -trackpoint=Enable usb_always_on=Disable diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..7696046 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -60,12 +60,9 @@ 411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 bluetooth +#412 1 r 0 unused 413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap +#414 4 r 0 unused 418 1 e 1 sticky_fn 419 2 e 12 usb_always_on #421 3 r 0 unused -- To view, visit https://review.coreboot.org/c/coreboot/+/37146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Gerrit-Change-Number: 37146 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: James <jye836(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit
by Petr K (Code Review) 07 Aug '23

07 Aug '23

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37153 ) Change subject: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit ...................................................................... mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on ideas from 32500 Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/early_init.c 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37153/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e0436..2770937 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,28 @@ end end + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 74c8b60..d30a621 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -77,3 +78,12 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 Gerrit-Change-Number: 37153 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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Change in coreboot[master]: {northbridge,soc,southbridge}: Don't use both of _ADR and _HID
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37532 ) Change subject: {northbridge,soc,southbridge}: Don't use both of _ADR and _HID ...................................................................... {northbridge,soc,southbridge}: Don't use both of _ADR and _HID ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I48fb3e9e48893336416eb90f80957e5bd21d1711 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37532/1 diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985..4a48aaf 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,7 +16,7 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +/* Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48fb3e9e48893336416eb90f80957e5bd21d1711 Gerrit-Change-Number: 37532 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: New PCI ID for FCH SATA Controller (AHCI Mode)
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37546 ) Change subject: New PCI ID for FCH SATA Controller (AHCI Mode) ...................................................................... New PCI ID for FCH SATA Controller (AHCI Mode) The 1022:7904 FCH SATA Controller is found in the AMD Bettong board. Support is added to configure properly the SATA device in initialization. Change-Id: Id8e5d67cded0588e84ad81f7d5e6fa4b6907ebc9 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/sata/sata.c M src/southbridge/amd/pi/hudson/sata.c 3 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37546/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c05640f..6444bc1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -444,14 +444,15 @@ #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 #define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 -#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A -#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E -#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 -#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 -#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 -#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 -#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 -#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B +#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A +#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD 0x7904 +#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 +#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 +#define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 +#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e #define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index 5aa2088..1cd342e 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -30,6 +30,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 08e967d..77365ef 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -70,6 +70,7 @@ PCI_DEVICE_ID_AMD_SB900_SATA_AHCI, PCI_DEVICE_ID_AMD_CZ_SATA, PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI_AMD, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e5d67cded0588e84ad81f7d5e6fa4b6907ebc9 Gerrit-Change-Number: 37546 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002701 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37548 ) Change subject: New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit ...................................................................... New PCI ID for Family 15h (Models 60h-6fh) I/O Memory Management Unit The 1022:1577 IOMMU device is found in the AMD Bettong board. Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/iommu/iommu.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37548/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6444bc1..1276994 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -303,6 +303,7 @@ #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 +#define PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU 0x15d1 diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 18c8e66..c8b1ff7 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -47,6 +47,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB_IOMMU, 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536ec4f24e210fa2e85e87eb4cbfde179f8c7f0f Gerrit-Change-Number: 37548 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002701 Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37589 to review the following change. Change subject: mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf ...................................................................... mb/google/hatch/variant/kohaku: Drop early gpio MEM_STRAP conf No need to configure the mem_strap in the early gpio block and again later. Fixes commit 5a0edcbde1537. BUG=b:144895517 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37589/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 61d3375..4ebd258 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -119,14 +119,6 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : PCH_MEM_STRAP2 */ - PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/37589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963d0ade9941ebbb57856baecb8b126a51ed9ded Gerrit-Change-Number: 37589 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/hatch: Move GPP_A11 config into variants from baseboard
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37590 to review the following change. Change subject: mainboard/hatch: Move GPP_A11 config into variants from baseboard ...................................................................... mainboard/hatch: Move GPP_A11 config into variants from baseboard Not all Hatch variants have a FP reader and so the baseboard should not assume one is connected. Instead the baseboard defines A11 as NC unless the variant defines it otherwise by override. Also, kindred has no FP so fix that while we are here. BUG=b:144809606 BRANCH=hatch TEST=none Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/hatch/gpio.c M src/mainboard/google/hatch/variants/helios/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37590/1 diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 4be3c34..0be39b7 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ @@ -98,8 +96,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A18 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 029aba16..2bc843e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -35,8 +35,8 @@ /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : SUSWARN_L */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d7..0b5d0de 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : NC */ PAD_NC(GPP_A18, NONE), /* A19 : NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 56f587b..def6ff0 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -19,6 +19,8 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C13 : EC_PCH_INT_L */ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c index 85eb3fc..89c6b41 100644 --- a/src/mainboard/google/hatch/variants/helios/gpio.c +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -23,6 +23,8 @@ PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa..bf94edb 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -27,6 +27,8 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), /* F1 : NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 4ebd258..49798c3 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -25,6 +25,8 @@ PAD_NC(GPP_A6, NONE), /* A10 : GPP_A10 ==> NC */ PAD_NC(GPP_A10, NONE), + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index 4d27554..814f2a6 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -27,8 +27,6 @@ PAD_NC(GPP_A8, NONE), /* A10 : NC */ PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A22 : NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fa6ccfe746fe8e8b64b082c68d76cdc34cf8fb Gerrit-Change-Number: 37590 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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