coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: Chrome EC SOCs: Integrate Chrome EC check
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42258 ) Change subject: Chrome EC SOCs: Integrate Chrome EC check ...................................................................... Chrome EC SOCs: Integrate Chrome EC check Behave the same as newer platforms. Skylake has the same code. This also adds brackets around &(gnvs->chromeos), so the it’s clear, what pointer is meant. Change-Id: I43ff551c717f598c7a65547ec49157853681314f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/apollolake/acpi.c 3 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/42258/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index fe5879c..7068ac0 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -254,8 +254,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ea67aa3..54b5521 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -229,8 +229,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 595e6a2..f9962e9 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -83,8 +83,13 @@ if (CONFIG(CHROMEOS)) { /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&gnvs->chromeos); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Set unknown wake source */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ff551c717f598c7a65547ec49157853681314f Gerrit-Change-Number: 42258 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/*/acpi: Put braces around *else* branch
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42257 ) Change subject: soc/intel/*/acpi: Put braces around *else* branch ...................................................................... soc/intel/*/acpi: Put braces around *else* branch From `Documentation/coding_style.md`: > This does not apply if only one branch of a conditional statement is a > single statement; in the latter case use braces in both branches: Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42257/1 diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 796e770..12ce34c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -198,8 +198,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 88ec5fe..250ff3b 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 0991134..e965c48 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -292,8 +292,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) { gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else + } else { gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } } /* Enable DPTF based on mainboard configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4427f7ae9f7b99ba74f7e84aed6b8a901ca9fc Gerrit-Change-Number: 42257 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: soc/intel/cannonlake: Make `acpi_create_gnvs()` static
by Paul Menzel (Code Review) 18 Feb '21

18 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42199 ) Change subject: soc/intel/cannonlake: Make `acpi_create_gnvs()` static ...................................................................... soc/intel/cannonlake: Make `acpi_create_gnvs()` static The function `acpi_create_gnvs()` is only used in this translation unit, so make it `static`. This unifies it with the Skylake version `src/soc/intel/skylake/acpi.c`. Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42199/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 12758e1..886cba2 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -182,7 +182,7 @@ return read32((void *)pmc_bar + IRQ_REG); } -void acpi_create_gnvs(struct global_nvs_t *gnvs) +static void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; config = config_of_soc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/42199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f817aa46c75332ec5a5fa77e8772ae0f0e3a366 Gerrit-Change-Number: 42199 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: nb/intel/pineview: Drop unused `GPIO32` macro
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45423 ) Change subject: nb/intel/pineview: Drop unused `GPIO32` macro ...................................................................... nb/intel/pineview: Drop unused `GPIO32` macro It's not used, and GPIO registers are on the southbridge. Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/pineview.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45423/1 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 82ae3ff..48ee263 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -26,8 +26,6 @@ #define GTTADR 0x1c #define BSM 0x5c -#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) - /* * MCHBAR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c Gerrit-Change-Number: 45423 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45503 ) Change subject: nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 ...................................................................... nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400 The 100 MHz reference clock seems to be unstable when using high multipliers. Use the 133 MHz reference clock instead. Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45503/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 6b74405..19e0e1d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -136,7 +136,7 @@ { if (ctrl->tCK <= TCK_1200MHZ) { ctrl->tCK = TCK_1200MHZ; - ctrl->base_freq = 100; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_1100MHZ) { ctrl->tCK = TCK_1100MHZ; ctrl->base_freq = 100; -- To view, visit https://review.coreboot.org/c/coreboot/+/45503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b Gerrit-Change-Number: 45503 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_freq` function
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45502 ) Change subject: nb/intel/sandybridge: Clean up `dram_freq` function ...................................................................... nb/intel/sandybridge: Clean up `dram_freq` function The thing that this function initializes is the MPLL (Memory PLL). So, call it by its name. Also add a missing newline in a printk, and update a comment on the callsite of this function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/45502/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 64a381d..6b74405 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -459,7 +459,7 @@ if (ctrl->tCK > TCK_400MHZ) { printk(BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). " - "Increasing to 400 MHz as last resort"); + "Increasing to 400 MHz as last resort.\n"); ctrl->tCK = TCK_400MHZ; } @@ -467,11 +467,11 @@ u8 val2; u32 reg1 = 0; - /* Step 1 - Set target PCU frequency */ + /* Step 1 - Determine target MPLL frequency */ find_cas_tck(ctrl); /* - * The PLL will never lock if the required frequency is already set. + * The MPLL will never lock if the requested frequency is already set. * Exit early to prevent a system hang. */ reg1 = MCHBAR32(MC_BIOS_DATA); @@ -479,16 +479,16 @@ if (val2) return; - /* Step 2 - Select frequency in the MCU */ + /* Step 2 - Request MPLL frequency */ reg1 = ctrl->FRQ; if (ctrl->base_freq == 100) - reg1 |= 0x100; /* Enable 100Mhz REF clock */ + reg1 |= 0x100; /* Use 100MHz reference clock */ - reg1 |= 0x80000000; /* set running bit */ + reg1 |= (1 << 31); /* Set running bit */ MCHBAR32(MC_BIOS_REQ) = reg1; int i = 0; - printk(BIOS_DEBUG, "PLL busy... "); - while (reg1 & 0x80000000) { + printk(BIOS_DEBUG, "MPLL busy... "); + while (reg1 & (1 << 31)) { udelay(10); i++; reg1 = MCHBAR32(MC_BIOS_REQ); @@ -499,11 +499,11 @@ reg1 = MCHBAR32(MC_BIOS_DATA); val2 = (u8) reg1; if (val2 >= ctrl->FRQ) { - printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", + printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", (1000 << 8) / ctrl->tCK); return; } - printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); + printk(BIOS_DEBUG, "MPLL didn't lock. Retrying at lower frequency\n"); ctrl->tCK++; } } @@ -571,7 +571,7 @@ dram_dimm_mapping(ctrl); } - /* Set MC frequency */ + /* Set MPLL frequency */ dram_freq(ctrl); if (!fast_boot) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3 Gerrit-Change-Number: 45502 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: src/cpu: Remove unused symbols
by Patrick Rudolph (Code Review) 18 Feb '21

18 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47709 ) Change subject: src/cpu: Remove unused symbols ...................................................................... src/cpu: Remove unused symbols Remove the unused Kconfig symbol CPU_MICROCODE_MULTIPLE_FILES. Change-Id: I18115e07694658a2f77c447d3ab5c899c1bdcc61 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/Kconfig M src/cpu/Makefile.inc 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47709/1 diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 933e50f..297b1a1 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -111,7 +111,6 @@ config CPU_MICROCODE_CBFS_EXTERNAL_BINS bool "Include external microcode binary" select USE_CPU_MICROCODE_CBFS_BINS - depends on !CPU_MICROCODE_MULTIPLE_FILES help Select this option if you want to include external binary files in the CPUs native format. They will be included as a separate @@ -128,7 +127,6 @@ config CPU_MICROCODE_CBFS_EXTERNAL_HEADER bool "Include external microcode header files" - depends on !CPU_MICROCODE_MULTIPLE_FILES help Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate @@ -179,12 +177,6 @@ endchoice -config CPU_MICROCODE_MULTIPLE_FILES - bool - help - Select this option to install separate microcode container files into - CBFS instead of using the traditional monolithic microcode file format. - config CPU_MICROCODE_HEADER_FILES string "List of space separated microcode header files with the path" depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index a072a8b..ec2f19f 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -13,9 +13,7 @@ ## Rules for building the microcode blob in CBFS ################################################################################ -ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin -endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) cbfs-files-y += cpu_microcode_blob.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/47709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18115e07694658a2f77c447d3ab5c899c1bdcc61 Gerrit-Change-Number: 47709 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: sb/intel/ibexpeak: Drop invalid SATA registers
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47864 ) Change subject: sb/intel/ibexpeak: Drop invalid SATA registers ...................................................................... sb/intel/ibexpeak: Drop invalid SATA registers Code was copy-pasted from older chips and has no effect on ibexpeak. Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47864/1 diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 76d0ad6..94f927a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -154,48 +154,8 @@ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d148570..2c6b0ca 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -63,18 +63,8 @@ pci_write_config8(dev, INTR_LN, 0x0b); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; // | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); @@ -137,18 +127,8 @@ pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); -- To view, visit https://review.coreboot.org/c/coreboot/+/47864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Gerrit-Change-Number: 47864 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46994 ) Change subject: nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write ...................................................................... nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write This write was copied from Sandy Bridge. Neither Haswell reference code nor Broadwell perform this write. Therefore, it is safe to remove it. Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46994/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e31337b..bbc6bf6 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -585,9 +585,6 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); - - /* Set here before graphics PM init. */ - MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } static struct device_operations mc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Gerrit-Change-Number: 46994 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/intel/lynxpoint: Correct read width in RMW cycle
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47098 ) Change subject: sb/intel/lynxpoint: Correct read width in RMW cycle ...................................................................... sb/intel/lynxpoint: Correct read width in RMW cycle The register is 32 bits wide, so do not read 16 bits out of it. Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47098/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index fdbe062..8fb6a94 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -67,7 +67,7 @@ udelay(2); /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); + reg32 = pci_read_config32(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); -- To view, visit https://review.coreboot.org/c/coreboot/+/47098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Gerrit-Change-Number: 47098 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020