coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
by Tim Wawrzynczak (Code Review) 24 Feb '21

24 Feb '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47397 ) Change subject: soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support ...................................................................... soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support Add MMIO offsets for USB2 and USB3 port status registers; implement soc_get_xhci_usb_info() to return the info for elog. Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/soc/intel/alderlake/xhci.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47397/1 diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c new file mode 100644 index 0000000..ab2a48c --- /dev/null +++ b/src/soc/intel/alderlake/xhci.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/xhci.h> + +/* + * Information obtained from Intel doc# 630094, ADL-P PCH EDS Vol. 2, + * as well as doc# 626817, ADL-P PCH EDS Vol. 1 + */ + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 4 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Gerrit-Change-Number: 47397 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: Doc/releases/checklist.md: Clarify tag push command
by Angel Pons (Code Review) 23 Feb '21

23 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47813 ) Change subject: Doc/releases/checklist.md: Clarify tag push command ...................................................................... Doc/releases/checklist.md: Clarify tag push command Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/releases/checklist.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47813/1 diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index d777f0e..e4fb5e9 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -178,7 +178,8 @@ ```` When you used the script to generate the release, a tag was generated in the tree that was downloaded. -From the coreboot-X.Y tree, just run: `git push -f origin <TAG (X.Y)>` +From the coreboot-X.Y tree, just run: `git push origin X.Y`. Force-pushing may sometimes be +necessary to push the new tag. You will need write access for tags to the coreboot git repo to do this. -- To view, visit https://review.coreboot.org/c/coreboot/+/47813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201 Gerrit-Change-Number: 47813 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/intel/cannonlake: Improve memcfg comments
by Angel Pons (Code Review) 23 Feb '21

23 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46250 ) Change subject: soc/intel/cannonlake: Improve memcfg comments ...................................................................... soc/intel/cannonlake: Improve memcfg comments Instead of repeating what the FSP-M UPDs say, explain how to correctly configure these settings. DQ and DQS byte maps differ between actual Cannon Lake and Coffee Lake et alia, so skip these comments for now. Change-Id: I1142ab500fd18176b174a5080f78c5c566c9ce25 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 1 file changed, 29 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46250/1 diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index 28af731..2e4dfcf 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -32,7 +32,7 @@ enum mem_info_read_type { NOT_EXISTING, /* No memory in this slot */ - READ_SMBUS, /* Read on-module spd by SMBUS. */ + READ_SMBUS, /* Read on-module spd by SMBUS */ READ_SPD_CBFS, /* Find spd file in CBFS. */ READ_SPD_MEMPTR /* Find spd data from pointer. */ }; @@ -40,20 +40,23 @@ struct spd_info { enum mem_info_read_type read_type; union spd_data_by { - /* To read on-module spd when read_type is READ_SMBUS. */ + /* To read on-module spd when read_type is READ_SMBUS */ uint8_t spd_smbus_address; - /* To identify spd file when read_type is READ_SPD_CBFS. */ + /* To identify spd file when read_type is READ_SPD_CBFS */ int spd_index; - /* To find spd data when read_type is READ_SPD_MEMPTR. */ + /* To find spd data when read_type is READ_SPD_MEMPTR */ struct spd_by_pointer spd_data_ptr_info; } spd_spec; }; -/* Board-specific memory dq mapping information */ +/* Board-specific memory parameters */ struct cnl_mb_cfg { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + /* + * Specify where to find the memory parameters for each slot, or the + * memory-down equivalent of a slot. Leave unpopulated slots blank. + */ struct spd_info spd[NUM_DIMM_SLOT]; /* @@ -83,39 +86,45 @@ uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]; /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + * Rcomp resistor values in ohms. For socketed platforms, they are + * located on the CPU package itself and their values are always + * the same. For soldered CPUs, the resistors are on the mainboard, + * connected to the DDR_RCOMP_[2:0] pins of the processor. The PDG + * can provide the RCOMP resistor values for each memory topology. + * + * For socketed CPUs, the resistor values are: { 121, 75, 100 }; + * For soldered-down CPUs, check schematics or use the PDG values. */ uint16_t rcomp_resistor[3]; /* - * Rcomp target values. These will typically be the following - * values for Cannon Lake : { 80, 40, 40, 40, 30 } + * Rcomp target values. These depend on the platform topology and + * can be determined using Intel document #573387 or left blank. */ uint16_t rcomp_targets[5]; /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. + * Indicates whether memory is interleaved. Refer to volume 1 of + * the datasheet for pictures of interleaved and non-interleaved + * configurations. Memory will never work with the wrong value. */ uint8_t dq_pins_interleaved; /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + * VREF_CA configuration. For DDR3 and LPDDR, choose config 0. + * Config 1 is not meant to be used. For DDR4, use config 2. */ uint8_t vref_ca_config; - /* Early Command Training Enabled */ + /* + * Early Command Training is a no-op for DDR4, and is necessary + * for LPDDR. If unsure, set to 1. MRC will skip ECT on DDR4. + */ uint8_t ect; }; /* - * Initialize default memory configurations for CannonLake. + * Write memory settings into the corresponding FSP-M UPDs. */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, const struct cnl_mb_cfg *cnl_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/46250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1142ab500fd18176b174a5080f78c5c566c9ce25 Gerrit-Change-Number: 46250 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines
by Angel Pons (Code Review) 23 Feb '21

23 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43160 ) Change subject: sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines ...................................................................... sb/intel/i82801gx/acpi/globalnvs.h: Add some Offset lines Looks like i82801ix and i82801jx have those. Adding them does no harm. Change-Id: Iad9699709f3e90670f2d4f9b5664a048971ea412 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/acpi/globalnvs.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43160/1 diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 848005d..0a0f255 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -15,6 +15,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ + Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter @@ -32,6 +33,7 @@ LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ + Offset (0x14), ACTT, 8, // 0x14 - active trip point TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 @@ -70,6 +72,7 @@ UTIL, 8, // 0x3a - ACIN, 8, // 0x3b - /* Integrated Graphics Device */ + Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List -- To view, visit https://review.coreboot.org/c/coreboot/+/43160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad9699709f3e90670f2d4f9b5664a048971ea412 Gerrit-Change-Number: 43160 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: device/pci: Ensure full 16-bit VGA port i/o decoding
by Nico Huber (Code Review) 22 Feb '21

22 Feb '21

Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35516 to review the following change. Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding ...................................................................... device/pci: Ensure full 16-bit VGA port i/o decoding So, the PCI to PCI bridge specification had a pitfall for us: Originally, when decoding i/o ports for legacy VGA cycles, bridges should only consider the 10 least significant bits of the port address. This means all VGA registers were aliased every 1024 ports! e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. However, it seems, we never reserved the aliased ports, resulting in random conflicts. We neither use much external VGA nor many i/o ports these days, so nobody noticed. To avoid this mess, a bridge control bit (VGA16) was introduced in 2003 to enable decoding of 16-bit port addresses. As we don't want to clutter our i/o port space, we'll now simply fail for VGA behind bridges that don't support it. Famous last words: I assume there can't be many bridges left that don't support this bit ;) Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/device.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h 4 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1 diff --git a/src/device/device.c b/src/device/device.c index 44d1f95..523bd1c 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -757,6 +757,12 @@ while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { if (!dev->enabled) continue; + if (dev->bus->no_vga) { + printk(BIOS_WARNING, "Ignoring VGA at %s" + ", a bridge on the path isn't supported", + dev_path(dev)); + continue; + } printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); @@ -797,7 +803,7 @@ while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); - bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; + bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ecb652..2fadb55 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -788,6 +788,43 @@ }; /** + * Check for compatibility to route legacy VGA cycles through a bridge. + * + * Originally, when decoding i/o ports for legacy VGA cycles, bridges + * should only consider the 10 least significant bits of the port address. + * This means all VGA registers were aliased every 1024 ports! + * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. + * + * To avoid this mess, a bridge control bit (VGA16) was introduced in + * 2003 to enable decoding of 16-bit port addresses. As we don't want + * to clutter our i/o port space, we simply fail for VGA behind bridges + * that don't support it (set .no_vga = 1). + */ +static void pci_bridge_vga_compat(struct bus *const bus) +{ + uint16_t bridge_ctrl; + + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + /* Ensure VGA decoding is disabled during probing (it should + be by default, but we run blobs nowadays) */ + bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + + /* If the upstream bridge doesn't support VGA, we don't have to check */ + bus->no_vga |= bus->dev->bus->no_vga; + if (bus->no_vga) + return; + + /* Test if we can enable 16-bit decoding */ + bridge_ctrl |= PCI_BRIDGE_CTL_VGA16; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); + bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); + + bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); +} + +/** * Detect the type of downstream bridge. * * This function is a heuristic to detect which type of bus is downstream @@ -1288,6 +1325,8 @@ bus = dev->link_list; + pci_bridge_vga_compat(bus); + pci_bridge_route(bus, PCI_ROUTE_SCAN); do_scan_bus(bus, 0x00, 0xff); diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221cc..78e234e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -94,6 +94,7 @@ unsigned int reset_needed : 1; unsigned int disable_relaxed_ordering : 1; unsigned int ht_link_up : 1; + unsigned int no_vga : 1; /* We can't support VGA behind this bridge */ }; /* diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..c8b86d5 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -138,6 +138,7 @@ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ /* Fast Back2Back enabled on secondary interface */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d Gerrit-Change-Number: 35516 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"
by Angel Pons (Code Review) 22 Feb '21

22 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46955 ) Change subject: Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL" ...................................................................... Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL" This reverts commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8. Reason for revert: No longer necessary. Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/gpio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46955/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 358bdec..6ae1f0f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -18,7 +18,7 @@ 0x00000000, // AddressMinimum 0x00000000, // AddressMaximum 0x00000000, // AddressTranslation - 0x00000001, // RangeLength + 0x00000000, // RangeLength , // ResourceSourceIndex , // ResourceSource BAR0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Gerrit-Change-Number: 46955 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by Mike Banon (Code Review) 21 Feb '21

21 Feb '21

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44582 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... tint: introduce the new tint build system with checksum verification Three stages of the new tint build system: 1) generate_core.sh extracts the core part from buildgcc script, most importantly the checksum calculation/verification functions. 2) tintify_core.sh adds the tint-specific footer/header to the core, such as the properties of current version including its checksum. 3) tint.sh - generated and "tintified" core script - builds a tint. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2f540676521ac33558d9f1c131bd1ed70bcc82e2 --- M payloads/external/tint/Makefile A payloads/external/tint/generate_core.sh R payloads/external/tint/tint-0.04-nmu1_libpayload.patch A payloads/external/tint/tintify_core.sh 4 files changed, 252 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44582/1 diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 9473c02..95cbd87 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -1,5 +1,25 @@ -project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz -archive_name=tint_0.04+nmu1.tar.gz +# +# TINT build system - helps to securely download TINT with a checksum verification and build it. +# + +# +# Properties of the current TINT version +# + +TINT_VERSION=0.04-nmu1 +TINT_EXT_VERSION=0.04+nmu1 +TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.t…" +TINT_ARCHIVE="tint_${TINT_VERSION}.tar.gz" +TINT_DIR="tint-${TINT_VERSION}" +TINT_CHECKSUM="7fcaa428c6d0de7096d1e4fbfd14848096ae5aad" + +# +# Locations of the input/output scripts +# + +buildgcc="./../../../util/crossgcc/buildgcc" +corescript="./core.sh" +tintified="./tint.sh" unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -10,28 +30,39 @@ all: tint -tint: patch - echo " MAKE TINT " - $(MAKE) -C tint +################################################################################ +# +# Three stages of TINT build system: +# +# 1) generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# 2) tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current version including its checksum. +# +# 3) tint.sh - generated and "tintified" core script - builds a TINT. +# +################################################################################ -patch: download - cd tint; \ - if [ -e debian ]; then \ - rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi - -download: - test -d tint || { wget $(project_url); \ - tar -xvf $(archive_name); \ - rm $(archive_name); \ - mv tint-0.04+nmu1 tint; } +tint: + if [ ! -f ${tintified} ]; then \ + chmod +x "./generate_core.sh" ; \ + "./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \ + chmod +x "./tintify_core.sh" ; \ + "./tintify_core.sh" ${corescript} ${tintified} \ + ${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_CHECKSUM} ; \ + fi ; \ + chmod +x ${tintified} + ${tintified} clean: - test -d tint && $(MAKE) -C tint clean || exit 0 + test -d "./tint/" && $(MAKE) -C "./tint/" clean || exit 0 distclean: - rm -rf tint + rm -rf "./tint/" + rm -f ${corescript} + rm -f ${tintified} -.PHONY: download patch tint clean distclean +.PHONY: tint clean distclean + +# diff --git a/payloads/external/tint/generate_core.sh b/payloads/external/tint/generate_core.sh new file mode 100755 index 0000000..bb0de2d --- /dev/null +++ b/payloads/external/tint/generate_core.sh @@ -0,0 +1,102 @@ +#!/bin/sh +# +# generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +############################################################################## +# +# USAGE: +# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch +# where +# buildgcc - path to input buildgcc script +# corescript - path to output core part script +# prepare_before_patch - optional argument to insert prepare_${package} +# call into the unpack_and_patch function, e.g. +# for removing some files with rm command +# in order to reduce the size of patch file +# +############################################################################## + +buildgcc="$1" +corescript="$2" +prepare_before_patch="$3" + +# +# Imports the source file fragment between start and end into the +# destination file, optionally excluding the last line if not needed +# + +import_from_file() { + source="$1" + destination="$2" + start="$3" + end="$4" + last_line_disabled="$5" + if [ -z "${last_line_disabled}" ] ; then + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" "$source" >> "$destination" + else + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" "$source" >> "$destination" + fi +} + +# +# Import the color defines together with UNAME/HALT_FOR_TOOLS variables +# + +import_from_file "$buildgcc" "$corescript" "red=" "HALT_FOR_TOOLS=0" || exit "$?" + +# +# Import the core functions +# + +FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" + +for F in $FUNCTIONS ; do + import_from_file "$buildgcc" "$corescript" "$F()" "}" || exit "$?" +done + +# +# Import a fragment where we find tar/patch/make and other essential tools +# + +import_from_file "$buildgcc" "$corescript" "# Find all the required tools" "# Allow" "last_line_disabled" || exit "$?" + +# +# Import a fragment with conditional exit if some required tools were not found +# + +import_from_file "$buildgcc" "$corescript" "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" + +# +# Avoid the unnecessary subdirectories holding a single file each +# + +sed -i -e "s/patches\///g" "$corescript" +sed -i -e "s/sum\///g" "$corescript" +sed -i -e "s/tarballs\///g" "$corescript" +sed -i -e "s/cd tarballs || exit 1//g" "$corescript" +sed -i -e "s/cd \.\.//g" "$corescript" + +# +# Get the known checksum without using a dedicated single-line file +# + +sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" "$corescript" + +# +# Update the paths printed at the error messages +# + +sed -i -e "s/util\/crossgcc\///g" "$corescript" + +# +# Insert prepare_${package} function call between the unpack and patch operations +# + +if [ ! -z "${prepare_before_patch}" ] ; then + sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript" +fi + +# diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/tint-0.04-nmu1_libpayload.patch similarity index 100% rename from payloads/external/tint/libpayload_tint.patch rename to payloads/external/tint/tint-0.04-nmu1_libpayload.patch diff --git a/payloads/external/tint/tintify_core.sh b/payloads/external/tint/tintify_core.sh new file mode 100755 index 0000000..77abc14 --- /dev/null +++ b/payloads/external/tint/tintify_core.sh @@ -0,0 +1,98 @@ +#!/bin/sh +# +# tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current TINT version including its checksum. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +################################################################################ +# +# USAGE: +# ./tintify_core.sh <corescript> <tintified> \ +# <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> +# where +# corescript - path to input core script +# tintified - path to output tint script +# +################################################################################ + +corescript="$1" +tintified="$2" + +# +# TINT-specific header +# + +# +# Insert the properties of the current TINT version +# + +echo "#!/bin/sh" > "$tintified" +echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified" +echo "TINT_ARCHIVE=${4}" >> "$tintified" +echo "TINT_DIR=${5}" >> "$tintified" +echo "TINT_CHECKSUM=${6}" >> "$tintified" + +# +# Add the replace_plus_with_minus() function - needed to fix the version number +# + +echo "replace_plus_with_minus() {" >> "$tintified" +echo "for x in *\"+\"*; do" >> "$tintified" +echo "y=\$(printf %sa \"\$x\" | tr \"+\" \"-\")" >> "$tintified" +echo "mv -- \"\$x\" \"\${y%a}\"" >> "$tintified" +echo "done" >> "$tintified" +echo "}" >> "$tintified" + +# +# Add the prepare_TINT() function, it will remove the unneeded debian directory +# as well as typedefs.h and old Makefile to significantly reduce the patch size +# + +echo "prepare_TINT() {" >> "$tintified" +echo "replace_plus_with_minus" >> "$tintified" +echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ] ; then" >> "$tintified" +echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "touch ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "fi" >> "$tintified" +echo "}" >> "$tintified" + +# +# Importing the core script +# + +cat "$corescript" >> "$tintified" + +# +# download() function adjustments - became necessary after a version number fix +# + +sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" "$tintified" +sed -i -e "s/downloading from \$archive/&_link/g" "$tintified" +sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" "$tintified" + +# +# TINT-specific footer +# + +echo "if [ ! -d tint ] ; then" >> "$tintified" + +echo "printf \"Downloading and verifying TINT tarball ... \\n\"" >> "$tintified" +echo "download TINT || exit \"\$?\"" >> "$tintified" +echo "verify_hash TINT \${TINT_CHECKSUM} || exit \"\$?\"" >> "$tintified" +echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "printf \"Unpacking and patching TINT... \\n\"" >> "$tintified" +echo "unpack_and_patch TINT || exit 1" >> "$tintified" +echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "mv ./\${TINT_DIR} ./tint" >> "$tintified" +echo "fi" >> "$tintified" + +echo "printf \"Building TINT ... \\n\"" >> "$tintified" +echo "make -C ./tint" >> "$tintified" +echo "printf \"TINT built ... \${green}ok\${NC}\\n\"" >> "$tintified" + +chmod +x "$tintified" + +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f540676521ac33558d9f1c131bd1ed70bcc82e2 Gerrit-Change-Number: 44582 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/amd/hda: Move HDA PCI device from DSDT to SSDT
by Furquan Shaikh (Code Review) 19 Feb '21

19 Feb '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40785 ) Change subject: soc/amd/hda: Move HDA PCI device from DSDT to SSDT ...................................................................... soc/amd/hda: Move HDA PCI device from DSDT to SSDT This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/hda/hda.c A src/soc/amd/common/block/include/amdblocks/hda.h M src/soc/amd/picasso/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 79 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40785/1 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index ea42b84..2028f09 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <arch/acpigen.h> +#include <amdblocks/hda.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -19,12 +21,23 @@ return "AZHD"; } +__weak void hda_soc_ssdt_quirks(const struct device *dev) +{ +} + +static void hda_fill_ssdt(const struct device *dev) +{ + acpi_device_write_pci_dev(dev); + hda_soc_ssdt_quirks(dev); +} + static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, .acpi_name = hda_acpi_name, + .acpi_fill_ssdt = hda_fill_ssdt, }; static const struct pci_driver hdaaudio_driver __pci_driver = { diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h new file mode 100644 index 0000000..b59a7b0 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_HDA_H__ +#define __AMDBLOCKS_HDA_H__ + +#include <device/device.h> + +/* SoC callback to add any quirks to HDA device node in SSDT. */ +void hda_soc_ssdt_quirks(const struct device *dev); + +#endif /* __AMDBLOCKS_HDA_H__ */ diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 0a3a979..67ae6f2 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -76,6 +76,3 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c807601..91e43aa 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -81,40 +81,3 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6c), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } -} /* end AZHD */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index db71509..b551426 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <assert.h> #include <amdblocks/biosram.h> +#include <amdblocks/hda.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -501,3 +503,55 @@ params->iGpuVgaMode = 0; params->GnbIoapicAddress = IO_APIC2_ADDR; } + +void hda_soc_ssdt_quirks(const struct device *dev) +{ + const char *scope = acpi_device_path(dev); + static const struct fieldlist list[] = { + FIELDLIST_OFFSET(0x42), + FIELDLIST_NAMESTR("NSDI", 1), + FIELDLIST_NAMESTR("NSDO", 1), + FIELDLIST_NAMESTR("NSEN", 1), + }; + struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100); + + assert(scope); + + acpigen_write_scope(scope); + + /* + * OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + * Field (AZPD, AnyAcc, NoLock, Preserve) { + * Offset (0x42), + * NSDI, 1, + * NSDO, 1, + * NSEN, 1, + * } + */ + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* + * Method (_INI, 0, NotSerialized) { + * If (LEqual (OSVR, 0x03)) { + * Store (Zero, NSEN) + * Store (One, NSDO) + * Store (One, NSDI) + * } + * } + */ + acpigen_write_method("_INI", 0); + + acpigen_write_if_lequal_namestr_int("OSVR", 0x03); + + acpigen_write_store_op_to_namestr(ONE_OP, "NSEN"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDO"); + acpigen_write_store_op_to_namestr(ZERO_OP, "NSDI"); + + acpigen_pop_len(); /* If */ + + acpigen_pop_len(); /* Method _INI */ + + acpigen_pop_len(); /* Scope */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Gerrit-Change-Number: 40785 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: soc/intel/apollolake: Make SMI_STS offset macro definition consistent
by Subrata Banik (Code Review) 19 Feb '21

19 Feb '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39022 ) Change subject: soc/intel/apollolake: Make SMI_STS offset macro definition consistent ...................................................................... soc/intel/apollolake: Make SMI_STS offset macro definition consistent This patch makes all bit field macro definition for SMI_STS register (offset 0x44) be consistent i.e. ending with "_STS_BIT". Also modified relevant files where those macros are getting used. Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/smihandler.c 3 files changed, 52 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39022/1 diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 22e414c..0cf06b2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -105,29 +105,30 @@ (ESPI_SMI_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS | GPIO_EN) #define SMI_STS 0x44 +#define SMI_STS_BITS 32 /* Bits for SMI status */ #define ESPI_SMI_STS_BIT 28 -#define PMC_OCP_SMI_STS 27 -#define SPI_SMI_STS 26 -#define SPI_SSMI_STS 25 -#define SCC2_SMI_STS 21 -#define PCIE_SMI_STS 20 -#define SCS_SMI_STS 19 -#define HSMBUS_SMI_STS 18 -#define XHCI_SMI_STS 17 -#define SMBUS_SMI_STS 16 -#define SERIRQ_SMI_STS 15 -#define PERIODIC_SMI_STS 14 -#define TCO_SMI_STS 13 -#define MC_SMI_STS 12 -#define GPIO_UNLOCK_SMI_STS 11 -#define GPIO_SMI_STS 10 -#define FAKE_PM1_SMI_STS 8 -#define SWSMI_TMR_SMI_STS 6 -#define APM_SMI_STS 5 -#define SLP_SMI_STS 4 -#define LEGACY_USB_SMI_STS 3 -#define BIOS_SMI_STS 2 +#define PMC_OCP_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SPI_SSMI_STS_BIT 25 +#define SCC2_SMI_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SCS_SMI_STS_BIT 19 +#define HSMBUS_SMI_STS_BIT 18 +#define XHCI_SMI_STS_BIT 17 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define MC_SMI_STS_BIT 12 +#define GPIO_UNLOCK_SMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 #define GPE_CNTL 0x50 #define DEVACT_STS 0x4c diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 8151afc..4a08827 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -57,27 +57,27 @@ const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { - [BIOS_SMI_STS] = "BIOS", - [LEGACY_USB_SMI_STS] = "LEGACY USB", - [SLP_SMI_STS] = "SLP_SMI", - [APM_SMI_STS] = "APM", - [SWSMI_TMR_SMI_STS] = "SWSMI_TMR", - [FAKE_PM1_SMI_STS] = "PM1", - [GPIO_SMI_STS] = "GPIO_SMI", - [GPIO_UNLOCK_SMI_STS] = "GPIO_UNLOCK_SSMI", - [MC_SMI_STS] = "MCSMI", - [TCO_SMI_STS] = "TCO", - [PERIODIC_SMI_STS] = "PERIODIC", - [SERIRQ_SMI_STS] = "SERIRQ", - [SMBUS_SMI_STS] = "SMBUS_SMI", - [XHCI_SMI_STS] = "XHCI", - [HSMBUS_SMI_STS] = "HOST_SMBUS", - [SCS_SMI_STS] = "SCS", - [PCIE_SMI_STS] = "PCI_EXP_SMI", - [SCC2_SMI_STS] = "SCC2", - [SPI_SSMI_STS] = "SPI_SSMI", - [SPI_SMI_STS] = "SPI", - [PMC_OCP_SMI_STS] = "OCP_CSE", + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPIO_STS_BIT] = "GPIO_SMI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI", + [MC_SMI_STS_BIT] = "MCSMI", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [XHCI_SMI_STS_BIT] = "XHCI", + [SCS_SMI_STS_BIT] = "HOST_SMBUS", + [SCS_SMI_STS_BIT] = "SCS", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [SCC2_SMI_STS_BIT] = "SCC2", + [SPI_SSMI_STS_BIT] = "SPI_SSMI", + [SPI_SMI_STS_BIT] = "SPI", + [PMC_OCP_SMI_STS_BIT] = "OCP_CSE", }; *a = ARRAY_SIZE(smi_sts_bits); @@ -98,7 +98,7 @@ /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) - generic_sts |= (1 << FAKE_PM1_SMI_STS); + generic_sts |= (1 << PM1_STS_BIT); } return generic_sts; diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..424d66f 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -38,19 +38,19 @@ uint32_t smihandler_soc_get_sci_mask(void) { uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_SMI_STS) | - SMI_HANDLER_SCI_EN(SLP_SMI_STS); + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; } const smi_handler_t southbridge_smi[32] = { - [SLP_SMI_STS] = smihandler_southbridge_sleep, - [APM_SMI_STS] = smihandler_southbridge_apmc, - [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, - [GPIO_SMI_STS] = smihandler_southbridge_gpi, - [TCO_SMI_STS] = smihandler_southbridge_tco, - [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, + [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, + [GPIO_STS_BIT] = smihandler_southbridge_gpi, + [TCO_STS_BIT] = smihandler_southbridge_tco, + [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82 Gerrit-Change-Number: 39022 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000
by Raul Rangel (Code Review) 18 Feb '21

18 Feb '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42886 ) Change subject: soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 ...................................................................... soc/amd/picasso: Move EARLY_RESERVED_DRAM_BASE to 0x100000 This places EARLY_RESERVED_DRAM_BASE right after the Option ROM. This closes the ~31 MiB gap between the Option ROM and Early RAM. [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000003bcfff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000003bd000-0x00000000cc51bfff] usable [ 0.000000] BIOS-e820: [mem 0x00000000cc51c000-0x00000000cd7fffff] type 16 [ 0.000000] BIOS-e820: [mem 0x00000000cd800000-0x00000000cfffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000042f33ffff] usable [ 0.000000] BIOS-e820: [mem 0x000000042f340000-0x000000042fffffff] reserved BUG=b:159081993 TEST=Boot picasso trembyle and run suspend_stress_test a few times. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5944abce19f17458ea3017d04f6dfdfe8e8050bf --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42886/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9630ad3..0d87c1f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -63,7 +63,7 @@ config EARLY_RESERVED_DRAM_BASE hex - default 0x2000000 + default 0x100000 help This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). @@ -77,14 +77,14 @@ config PSP_APOB_DRAM_ADDRESS hex - default 0x2001000 + default 0x101000 help Location in DRAM where the PSP will copy the AGESA PSP Output Block. config PSP_SHAREDMEM_BASE hex - default 0x2011000 if VBOOT + default 0x111000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies @@ -111,7 +111,7 @@ config BOOTBLOCK_ADDR hex - default 0x2030000 + default 0x120000 help Sets the address in DRAM where bootblock should be loaded. @@ -126,7 +126,7 @@ config X86_RESET_VECTOR hex depends on ARCH_X86 - default 0x203fff0 + default 0x12fff0 help Sets the reset vector within bootblock where x86 starts execution. Reset vector is supposed to live at offset -0x10 from end of @@ -134,7 +134,7 @@ config ROMSTAGE_ADDR hex - default 0x2040000 + default 0x130000 help Sets the address in DRAM where romstage should be loaded. @@ -146,7 +146,7 @@ config FSP_M_ADDR hex - default 0x20C0000 + default 0x1B0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. @@ -160,7 +160,7 @@ config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2140000 + default 0x230000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..e94c3ba 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -39,7 +39,7 @@ * | (C_ENV_BOOTBLOCK_SIZE) | * +--------------------------------+ BOOTBLOCK_ADDR * | Unused hole | - * | (86KiB) | + * | (21KiB) | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 -- To view, visit https://review.coreboot.org/c/coreboot/+/42886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5944abce19f17458ea3017d04f6dfdfe8e8050bf Gerrit-Change-Number: 42886 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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