coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
by Maxim Polyakov (Code Review) 26 Feb '21

26 Feb '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39979 ) Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ...................................................................... soc/intel/xeon_sp: add ACPI to control GPIO [WIP] Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/soc/intel/xeon_sp/acpi/gpio.asl 1 file changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1 diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl new file mode 100644 index 0000000..4a981b7 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <soc/gpio.h> + +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 + +Device (GPIO) +{ + Name (_HID, "INT3536") + Name (_UID, 1) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { 0 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) + And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), + GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) + + /* TODO: Check this! + If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { + Store (GPIO_IRQ14, IRQN) + } Else { + Store (GPIO_IRQ15, IRQN) + } + */ + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3 */ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + /* GPIO Community 4 */ + If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_J0, Local1) + } + /* GPIO Community 5 */ + If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19))) + { + Store (PID_GPIOCOM5, Local0) + Subtract (Arg0, GPP_G0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 8))) +} + +/* + * Get GPIO Rx Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Gerrit-Change-Number: 39979 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
by Angel Pons (Code Review) 26 Feb '21

26 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47208 ) Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ...................................................................... sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code. Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI. Tested on Asrock B85M Pro4, still boots. Registers have the new values. Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 114 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47208/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a87..6830051 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -114,6 +114,17 @@ RCBA32_OR(FD, PCH_DISABLE_ALWAYS); + RCBA32(0x2088) = 0x00109000; + + RCBA32_OR(0x20ac, 1 << 30); + + if (!pch_is_lp()) { + RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); + RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); + + RCBA32(0x2324) = 0x00854c74; + } + wake_from_s3 = southbridge_detect_s3_resume(); elog_boot_notify(wake_from_s3); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 64515e9..a046099 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,10 +289,111 @@ RCBA16(0x3f02) = reg16; } +static void configure_dmi_pm(struct device *dev) +{ + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + + /* Additional PCH DMI programming steps */ + + /* EL0 */ + u32 reg32 = 3 << 12; + + /* EL1 */ + if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0)) + reg32 |= 2 << 15; + else + reg32 |= 4 << 15; + + RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32); + + RCBA32_AND_OR(0x2348, ~0xf, 0); + + /* Clear prior to enabling DMI ASPM */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); + + RCBA32_OR(0x21a4, 3 << 10); + + RCBA16(0x21a8) |= 3 << 0; + + /* Set again after enabling DMI ASPM */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); +} + /* LynxPoint PCH Power Management init */ static void lpt_pm_init(struct device *dev) { + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + printk(BIOS_DEBUG, "LynxPoint PM init\n"); + + /* Configure additional PM */ + + pci_write_config8(dev, 0xa9, 0x46); + + pci_or_config32(dev, PMIR, PMIR_CF9LOCK); + + /* Step 3 is skipped */ + + /* Program DMI Hardware Width Control (thermal throttling) */ + u32 reg32 = 0; + reg32 |= 1 << 0; /* DMI Thermal Sensor Autonomous Width Enable */ + reg32 |= 0 << 4; /* Thermal Sensor 0 Target Width */ + reg32 |= 1 << 6; /* Thermal Sensor 1 Target Width */ + reg32 |= 1 << 8; /* Thermal Sensor 2 Target Width */ + reg32 |= 2 << 10; /* Thermal Sensor 3 Target Width */ + RCBA32(0x2238) = reg32; + + RCBA32_OR(0x232c, 1 << 0); + RCBA32_OR(0x1100, 3 << 13); /* Assume trunk clock gating is to be enabled */ + + RCBA32(0x2304) = 0xc07b8400; /* DMI misc control */ + + RCBA32_OR(0x2314, 1 << 23 | 1 << 5); + + if (pcie_dev) + pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5); + + RCBA32_OR(0x2320, 1 << 1); + + RCBA32(0x3314) = 0x000007bf; + + RCBA32_OR(0x3318, 0x0dcf0020); + + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3340) = 0x020ddbff; + + RCBA32_OR(0x3344, 1 << 0); + + RCBA32(0x3368) = 0x00041000; + RCBA32(0x3378) = 0x3f8ddbff; + RCBA32(0x337c) = 0x000001e1; + RCBA32(0x3388) = 0x00001000; + RCBA32(0x33a0) = 0x00000800; + RCBA32(0x33ac) = 0x00001000; + RCBA32(0x33b0) = 0x00001000; + RCBA32(0x33c0) = 0x00011900; + RCBA32(0x33d0) = 0x06000802; + RCBA32(0x3a28) = 0x01010000; + RCBA32(0x3a2c) = 0x01010404; + + /* Step 31 */ + RCBA32_OR(0x33a4, 1 << 0); + + /* DMI power optimizer */ + RCBA32_OR(0x33d4, 1 << 27); + RCBA32_OR(0x33c8, 1 << 27); + RCBA32(0x2b14) = 0x1e0a0317; + RCBA32(0x2b24) = 0x4000000b; + RCBA32(0x2b28) = 0x00000002; + RCBA32(0x2b2c) = 0x00008813; + + /* Step 55 */ + RCBA32(0x3a80) = 0x01040000; + RCBA32(0x3a84) = 0x01041001; + RCBA32(0x3a88) = 0x00000001; + RCBA32(0x33d4) = 0xc80bc000; + + configure_dmi_pm(dev); } /* LynxPoint LP PCH Power Management init */ @@ -485,19 +586,6 @@ pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); } -static void pch_fixups(struct device *dev) -{ - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - - /* - * Enable DMI ASPM in the PCH - */ - RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); - RCBA32_OR(0x21a8, 0x3); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -545,7 +633,8 @@ pch_set_acpi_mode(); - pch_fixups(dev); + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); } static void pch_lpc_add_mmio_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/47208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Gerrit-Change-Number: 47208 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: sb/intel/lynxpoint/acpi: Add missing USB ports
by Angel Pons (Code Review) 25 Feb '21

25 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46959 ) Change subject: sb/intel/lynxpoint/acpi: Add missing USB ports ...................................................................... sb/intel/lynxpoint/acpi: Add missing USB ports Broadwell has these, so add them to Lynxpoint as well. Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/xhci.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46959/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbeb562..2b3d433 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -338,9 +338,12 @@ Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 Device (PRT7) { Name (_ADR, 7) } // USB Port 6 + Device (PRT8) { Name (_ADR, 8) } // USB Port 7 Device (SSP1) { Name (_ADR, 10) } // USB Port 10 Device (SSP2) { Name (_ADR, 11) } // USB Port 11 Device (SSP3) { Name (_ADR, 12) } // USB Port 12 Device (SSP4) { Name (_ADR, 13) } // USB Port 13 + Device (SSP5) { Name (_ADR, 14) } // USB Port 14 + Device (SSP6) { Name (_ADR, 15) } // USB Port 15 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Gerrit-Change-Number: 46959 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/amd/agesa/hudson/lpc: Remove space between function and signature
by Paul Menzel (Code Review) 25 Feb '21

25 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46638 ) Change subject: sb/amd/agesa/hudson/lpc: Remove space between function and signature ...................................................................... sb/amd/agesa/hudson/lpc: Remove space between function and signature Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46638/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 3fde291..f811302 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -68,10 +68,10 @@ cmos_init(0); /* Initialize i8259 pic */ - setup_i8259 (); + setup_i8259(); /* Initialize i8254 timers */ - setup_i8254 (); + setup_i8254(); } static void hudson_lpc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Gerrit-Change-Number: 46638 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/amd/agesa/hudson: Use comment style from style guide
by Paul Menzel (Code Review) 25 Feb '21

25 Feb '21

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46637 ) Change subject: sb/amd/agesa/hudson: Use comment style from style guide ...................................................................... sb/amd/agesa/hudson: Use comment style from style guide Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/southbridge/amd/agesa/hudson/lpc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46637/1 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 89c9a6b..3fde291 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -59,7 +59,8 @@ cmos_check_update_date(); - /* Initialize the real time clock. + /* + * Initialize the real time clock. * The 0 argument tells cmos_init not to * update CMOS unless it is invalid. * 1 tells cmos_init to always initialize the CMOS. -- To view, visit https://review.coreboot.org/c/coreboot/+/46637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Gerrit-Change-Number: 46637 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/prodrive: Disable power of KeyM slot on S5
by Patrick Rudolph (Code Review) 25 Feb '21

25 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47498 ) Change subject: mb/prodrive: Disable power of KeyM slot on S5 ...................................................................... mb/prodrive: Disable power of KeyM slot on S5 Manually disable power to KeyM slot on S5 and enable it in bootblock on S0. As GPP_K7 is in the VCCPGPPHK power well it's keept powered even in S5 and doesn't reset its value. Change-Id: I3504eed5a9f5b194fcd8b5432a8472886eec8307 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/variants/baseboard/gpio.c 2 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47498/1 diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 22534c9..9dc4872 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -74,7 +74,7 @@ uint8_t value = 1; const char *method; - /* Disable USB power on S0->S5 transition */ + /* Disable USB power on S0->S5 transition depending on EEPROM board settings */ if (check_board_settings_signature()) { read_write_config(&value, offsetof(struct eeprom_layout, BoardSettings) + offsetof(struct eeprom_board_settings, usb_powered_in_s5), @@ -100,8 +100,12 @@ acpigen_write_integer(GPP_G3); acpigen_write_name(method); acpigen_write_integer(GPP_G4); - acpigen_pop_len(); + /* Always disable EN_3V3_KEYM_PCH on S5 */ + acpigen_write_name("\\_SB.PCI0.CTXS"); + acpigen_write_integer(GPP_K7); + + acpigen_pop_len(); acpigen_pop_len(); } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 9c01d24..4f35188 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -373,6 +373,9 @@ PAD_CFG_GPO(GPP_K1, 1, DEEP), /* PERST_CPU_SLOTS_n */ PAD_CFG_GPO(GPP_K2, 1, DEEP), /* PERST_CNVI_SLOTS_n */ + /* Power KeyM slot */ + PAD_CFG_GPO(GPP_K7, 1, DEEP), /* EN_3V3_KEYM_PCH */ + /* SMB */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_SMB_CLK */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_SMB_DATA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3504eed5a9f5b194fcd8b5432a8472886eec8307 Gerrit-Change-Number: 47498 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: [WIP]mb/prodrive/hermes: Improve board config EEPROM handling
by Patrick Rudolph (Code Review) 25 Feb '21

25 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45686 ) Change subject: [WIP]mb/prodrive/hermes: Improve board config EEPROM handling ...................................................................... [WIP]mb/prodrive/hermes: Improve board config EEPROM handling * Check and print errors returned reading from I2C * Rework offset calculation by using more macros * Get rid of stage specific preprocessor code * Define the EEPROM layout as struct * Make use of the defined EEPROM layout to calculate the offset * Read the UPD to disable Vtd from EEPROM * Verify the checksum of the 'board settings' * Enable DeepS5 depending on the configuration value in 'board settings' Untested. Change-Id: I7f83d1ddb455a3d0aaec9757666d161f2091cec2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/ramstage.c M src/mainboard/prodrive/hermes/romstage.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 5 files changed, 119 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/45686/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index bd5db5c..763f8bd 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -3,19 +3,20 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/smbus_host.h> +#include <crc_byte.h> #include "variants/baseboard/include/eeprom.h" /* * Check Signature in EEPROM (M24C32-FMN6TP) * If signature is there we assume that that the content is valid */ -int check_signature(u8 addr) +int check_fsp_signature(u8 addr, size_t offset, uint64_t fsp_signature) { u8 blob[8] = {0}; - if (!read_write_config(addr, blob, EEPROM_OFFSET_FSP_SIGNATURE, 0, ARRAY_SIZE(blob))) { + if (!read_write_config(addr, blob, offset, 0, ARRAY_SIZE(blob))) { // Check Signature - if (*(uint64_t *)blob == FSP_UPD_SIGNATURE) { + if (*(uint64_t *)blob == fsp_signature) { printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n"); return 1; } @@ -25,6 +26,30 @@ return 0; } +/* + * Check Checksum of board settings in EEPROM (M24C32-FMN6TP) + * If signature is valid we assume that the settings are also sane. + */ +int check_board_settings_signature(u8 addr) +{ + const size_t off = offsetof(struct eeprom_layout, BoardSettings); + struct eeprom_board_settings BoardSettings; + uint32_t crc; + + if (read_write_config(addr, &BoardSettings, off, 0, sizeof(BoardSettings))) { + printk(BIOS_ERR, "CFG EEPROM: Failed to read board settings\n"); + return 0; + } + + crc = CRC(((uint8_t *)&BoardSettings) + sizeof(uint32_t), + sizeof(BoardSettings) - sizeof(uint32_t), crc32_byte); + if (crc != BoardSettings.signature) { + printk(BIOS_ERR, "CFG EEPROM: Board settings have invalid checksum\n"); + return 0; + } + return 1; +} + // Read data from offset and write it to offset in UPD bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, size_t size) diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b24dd56..ca42afb 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include "variants/baseboard/include/eeprom.h" #include "gpio.h" /* FIXME: Example code below */ @@ -84,6 +85,24 @@ mb_usb2_fp2_pwr_enable(1); } +static void mainboard_init(void *chip_info) +{ + uint8_t value = 0; + + if (!check_board_settings_signature(I2C_ADDR_EEPROM)) { + return; + } + + read_write_config(I2C_ADDR_EEPROM, &value, offsetof(struct eeprom_layout, BoardSettings) + + offsetof(struct eeprom_board_settings, deep_s5), 0, + sizeof(value)); + + config_t *config = config_of_soc(); + config->deep_s5_enable_ac = value; + config->deep_s5_enable_dc = value; +} + struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 18fc915..9130823 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -1,16 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include "variants/baseboard/include/eeprom.h" -static fsp_params parmas_list[] = { - // FIXME: Fill with additional options +static const fsp_params parmas_list[] = { + GET_VALUE_FSP_S_TEST_CONFIG(VtdDisableDeprecated), }; void mainboard_silicon_init_params(FSP_S_CONFIG *params) { size_t num = 0; + bool ret; const struct pad_config *gpio_table = get_gpio_table(&num); /* Configure pads prior to SiliconInit() in case there's any @@ -20,15 +22,19 @@ params->SataLedEnable = 1; // Overwrite params - if (!check_signature(I2C_ADDR_EEPROM)) + if (!check_fsp_signature(I2C_ADDR_EEPROM, + offsetof(struct eeprom_layout, FSPS_UPD), + FSPS_UPD_SIGNATURE)) return; - for (u8 i = 0; i <= ARRAY_SIZE(parmas_list); i++) { - if (ARRAY_SIZE(parmas_list) == 0) - break; - read_write_config(I2C_ADDR_EEPROM, params, EEPROM_OFFSET_FSP_CONFIG + - parmas_list[i].offset, - EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, - parmas_list[i].size); + for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { + ret = read_write_config(I2C_ADDR_EEPROM, params, + parmas_list[i].eeprom_offset, + parmas_list[i].fsp_upd_offset, + parmas_list[i].size); + if (ret) { + printk(BIOS_ERR, "MB: Failed to read from EEPROM at addr. 0x%zx\n", + parmas_list[i].eeprom_offset); + } } } diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index a25c43a..9202ad8 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -1,31 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <variant/variants.h> #include "variants/baseboard/include/eeprom.h" -static fsp_params parmas_list[] = { - GET_VALUE(RMT), - GET_VALUE(HyperThreading), - GET_VALUE(BootFrequency) +static const fsp_params parmas_list[] = { + GET_VALUE_FSP_M_CONFIG(RMT), + GET_VALUE_FSP_M_CONFIG(HyperThreading), + GET_VALUE_FSP_M_CONFIG(BootFrequency), + GET_VALUE_FSP_M_TEST_CONFIG(VtdDisable), }; void mainboard_memory_init_params(FSPM_UPD *memupd) { + bool ret; memupd->FspmConfig.UserBd = 7; memupd->FspmTestConfig.SmbusSpdWriteDisable = 0; memupd->FspmConfig.IedSize = 0x400000; cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); // Overwrite memupd - if (!check_signature(I2C_ADDR_EEPROM)) + if (!check_fsp_signature(I2C_ADDR_EEPROM, + offsetof(struct eeprom_layout, FSPM_UPD), + FSPM_UPD_SIGNATURE)) return; for (size_t i = 0; i < ARRAY_SIZE(parmas_list); i++) { - read_write_config(I2C_ADDR_EEPROM, memupd, EEPROM_OFFSET_FSP_CONFIG + - parmas_list[i].offset, - EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset, - parmas_list[i].size); + ret = read_write_config(I2C_ADDR_EEPROM, memupd, + parmas_list[i].eeprom_offset, + parmas_list[i].fsp_upd_offset, + parmas_list[i].size); + if (ret) { + printk(BIOS_ERR, "MB: Failed to read from EEPROM at addr. 0x%zx\n", + parmas_list[i].eeprom_offset); + } } } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index c41ead2..2da4317 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -7,27 +7,50 @@ #define HOSTC_I2C_EN (1 << 2) #define I2C_ADDR_EEPROM 0x57 -#if ENV_ROMSTAGE -#define FSP_UPD_SIGNATURE FSPM_UPD_SIGNATURE -#define EEPROM_OFFSET_FSP_SIGNATURE 0 -#define EEPROM_OFFSET_FSP_CONFIG 0 +struct eeprom_board_settings { + uint32_t signature; + uint8_t secureboot; + uint8_t primary_video; + uint8_t deep_s5; + uint8_t wake_on_usb; + uint8_t wake_on_lan; +} __packed; -#define GET_VALUE(x) {.offset = sizeof(FSP_UPD_HEADER) + sizeof(FSPM_ARCH_UPD) \ - + offsetof(FSP_M_CONFIG, x), .size = member_size(FSP_M_CONFIG, x)} -#else +/* The EEPROM on address 0x57 has the following vendor defined layout: */ +struct eeprom_layout { + uint8_t FSPM_UPD[0x600]; + uint8_t FSPS_UPD[0x600]; + uint8_t BoardLayout[0x400]; + uint8_t BootOrder[0xF00]; + union { + uint8_t RawBoardSetting[0x100]; + struct eeprom_board_settings BoardSettings; + }; +} __packed; -#define FSP_UPD_SIGNATURE FSPS_UPD_SIGNATURE -#define EEPROM_OFFSET_FSP_SIGNATURE 0x0600 -#define EEPROM_OFFSET_FSP_CONFIG (EEPROM_OFFSET_FSP_SIGNATURE + sizeof(FSP_UPD_HEADER)) -#define GET_VALUE(x) {.offset = offsetof(FSP_S_CONFIG, x), \ - .size = member_size(FSP_S_CONFIG, x)} -#endif // ENV_ROMSTAGE +_Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size missmatch"); +/* + * As reading the whole FSP UPD would take too much time only single UPDs of interrest are + * loaded at runtime. The following code eases the EEPROM to FSP UPD offset mappings. + */ typedef struct { - size_t offset; + size_t eeprom_offset; + size_t fsp_upd_offset; size_t size; } fsp_params; +/* Example: RMT, FSP_M_CONFIG, x:FspmTestConfig, y: FSPM_UPD */ +#define GET_VALUE(a, b, x, y) {.eeprom_offset = offsetof(struct eeprom_layout, y) + \ + offsetof(y, x) + offsetof(b, a), .fsp_upd_offset = \ + offsetof(y, x) + offsetof(b, a), .size = member_size(b, a)} + +#define GET_VALUE_FSP_M_CONFIG(x) GET_VALUE(x, FSP_M_CONFIG, FspmConfig, FSPM_UPD) +#define GET_VALUE_FSP_M_TEST_CONFIG(x) GET_VALUE(x, FSP_M_TEST_CONFIG, FspmTestConfig, FSPM_UPD) +#define GET_VALUE_FSP_S_CONFIG(x) GET_VALUE(x, FSP_S_CONFIG, FspsConfig, FSPS_UPD) +#define GET_VALUE_FSP_S_TEST_CONFIG(x) GET_VALUE(x, FSP_S_TEST_CONFIG, FspsTestConfig, FSPS_UPD) + bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, size_t size); -int check_signature(u8 addr); +int check_fsp_signature(u8 addr, size_t offset, uint64_t fsp_signature); +int check_board_settings_signature(u8 addr); -- To view, visit https://review.coreboot.org/c/coreboot/+/45686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f83d1ddb455a3d0aaec9757666d161f2091cec2 Gerrit-Change-Number: 45686 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: [WIP]mb/prodrive/hermes: Write board layout
by Patrick Rudolph (Code Review) 25 Feb '21

25 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47521 ) Change subject: [WIP]mb/prodrive/hermes: Write board layout ...................................................................... [WIP]mb/prodrive/hermes: Write board layout Change-Id: I11782cf2363be94983fbdd0b156a2213f9ee80f6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/eeprom.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h 3 files changed, 136 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/47521/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index f371b64..e374c60 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -95,3 +95,69 @@ return ret; } + +/* Write a single byte into the EEPROM at specified offset */ +static bool write_byte_eeprom(uint8_t data, uint16_t write_offset) +{ + int ret; + uint8_t buffer[2]; +#if ENV_ROMSTAGE + pci_devfn_t dev = PCI_DEV(0, PCH_DEV_SLOT_LPC, 4); +#else + const struct device *dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 4); +#endif + + u32 smb_ctrl_reg = pci_read_config32(dev, HOSTC); + pci_write_config32(dev, HOSTC, smb_ctrl_reg | I2C_EN); + + /* + * The EEPROM expects two address bytes. + * Use the first byte of the block as second address byte. + */ + buffer[0] = write_offset & 0xff; + buffer[1] = data; + ret = do_smbus_block_write(SMBUS_IO_BASE, I2C_ADDR_EEPROM, (write_offset >> 8) & 0xff, + sizeof(buffer), buffer); + + /* Restore I2C_EN bit */ + pci_write_config32(dev, HOSTC, smb_ctrl_reg); + + return ret == 0; +} + +/* + * Write board layout if it has changed into EEPROM. + * Return true on error, false on success. + */ +bool write_board_settings(const struct eeprom_board_layout *l) +{ + const size_t off = offsetof(struct eeprom_layout, BoardLayout); + struct eeprom_board_layout cmp; + bool ret = false; + bool changed = false; + + /* Read old settings */ + if (read_write_config(&cmp, off, 0, sizeof(*l))) { + printk(BIOS_ERR, "CFG EEPROM: Read operation failed\n"); + return true; + } + + /* Compare with new settings */ + for (size_t i = 0; i < sizeof(*l); i++) { + uint8_t data = ((uint8_t *)l)[i]; + uint8_t ref = ((uint8_t *)&cmp)[i]; + if (ref != data) { + changed = true; + if (write_byte_eeprom(data, off + i)) { + printk(BIOS_ERR, "CFG EEPROM: Write operation failed\n"); + ret = true; + break; + } + } + } + + printk(BIOS_DEBUG, "CFG EEPROM: Board Layout up%s\n", + changed ? "dated": " to date"); + + return ret; +} diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 7063c3e..e2182bc 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -3,6 +3,9 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <soc/soc_chip.h> +#include <crc_byte.h> +#include <cbmem.h> +#include <console/console.h> #include "variants/baseboard/include/eeprom.h" #include "gpio.h" @@ -129,6 +132,51 @@ #endif } +static void update_board_layout(void) +{ + struct eeprom_board_layout l = {0}; + struct memory_info *m; + struct device *cpu; + + printk(BIOS_DEBUG, "MB: Collecting Board Layout information\n"); + + /* Update CPU fields */ + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) + continue; + if (!cpu->enabled) + continue; + l.cpu_count ++; + if (l.cpu[0] == 0) + strcpy(l.cpu, cpu->name); + } + + /* PCH */ + strcpy(l.pch, "Cannonlake-H C246"); + + /* DRAM */ + m = cbmem_find(CBMEM_ID_MEMINFO); + for (size_t i = 0; m != NULL && i < m->dimm_cnt && i < ARRAY_SIZE(m->dimm) && + i < ARRAY_SIZE(l.dram_size); i++) { + struct dimm_info *dimm; + dimm = &m->dimm[i]; + if (dimm->dimm_size == 0) + continue; + + l.dram_size[i] = 1; + l.dram_ecc |= 1 << i; + } + /* Update CRC */ + + l.signature = CRC(((uint8_t *)&l) + sizeof(uint32_t), + sizeof(l) - sizeof(uint32_t), crc32_byte); + + if (write_board_settings(&l)) + printk(BIOS_ERR, "MB: Failed to update Board Layout\n"); +} + + static void mainboard_init(void *chip_info) { uint8_t value = 0; @@ -144,9 +192,16 @@ config_t *config = config_of_soc(); config->deep_s5_enable_ac = value; config->deep_s5_enable_dc = value; + +} + +static void mainboard_final(void *chip_info) +{ + update_board_layout(); } struct chip_operations mainboard_ops = { .init = mainboard_init, + .final = mainboard_final, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index f9e9a71..f3a143c 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -11,11 +11,24 @@ uint8_t usb_powered_in_s5; } __packed; +struct eeprom_board_layout { + uint32_t signature; + char cpu[50]; + uint8_t cpu_count; + char pch[50]; + uint8_t dram_size[4]; /* byte mask. 1 if slot is populated */ + uint8_t dram_ecc; /* bit mask. 1 if ECC is supported */ +} __packed; + + /* The EEPROM on address 0x57 has the following vendor defined layout: */ struct eeprom_layout { uint8_t FSPM_UPD[0x600]; uint8_t FSPS_UPD[0x600]; - uint8_t BoardLayout[0x400]; + union { + uint8_t RawBoardLayout[0x400]; + struct eeprom_board_layout BoardLayout; + }; uint8_t BootOrder[0xF00]; union { uint8_t RawBoardSetting[0x100]; @@ -49,3 +62,4 @@ size_t size); int check_fsp_signature(size_t offset, uint64_t fsp_signature); int check_board_settings_signature(void); +bool write_board_settings(const struct eeprom_board_layout *l); -- To view, visit https://review.coreboot.org/c/coreboot/+/47521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11782cf2363be94983fbdd0b156a2213f9ee80f6 Gerrit-Change-Number: 47521 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: [UNTESTED] nb/intel/ironlake: Fix some replay issues
by Angel Pons (Code Review) 24 Feb '21

24 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45606 ) Change subject: [UNTESTED] nb/intel/ironlake: Fix some replay issues ...................................................................... [UNTESTED] nb/intel/ironlake: Fix some replay issues Dummy reads followed by writes are actually read-modify-write operations in disassembled binaries. Handling of the scratchpad register 0x2ca8 is still nonsense, but that should be taken care of in a separate commit. Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 64 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45606/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 6c480de..6293c0e 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -316,12 +316,22 @@ MCHBAR16(0x2b9 + (channel << 10)) = si; } +static void toggle_1d0_142_5ff(void) +{ + u32 reg32 = gav(read_1d0(0x142, 3)); + if (reg32 & (1 << 1)) + write_1d0(0, 0x142, 3, 1); + + MCHBAR8(0x5ff) = 0x0; + MCHBAR8(0x5ff) = 0x80; + if (reg32 & (1 << 1)) + write_1d0(0x2, 0x142, 3, 1); +} + static u32 get_580(int channel, u8 addr) { u32 ret; - gav(read_1d0(0x142, 3)); - MCHBAR8(0x5ff) = 0x0; - MCHBAR8(0x5ff) = 0x80; + toggle_1d0_142_5ff(); MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; MCHBAR8_OR(0x580 + (channel << 10), 1); while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) @@ -373,10 +383,9 @@ gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); } - gav(read_1d0(0x142, 3)); // = 0x10408118 - MCHBAR8(0x5ff) = 0x0; - MCHBAR8(0x5ff) = 0x80; + toggle_1d0_142_5ff(); write_1d0(0x2, 0x142, 3, 1); + for (lane = 0; lane < 8; lane++) { // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[2][channel][slot][rank][lane] = @@ -4176,11 +4185,10 @@ MCHBAR16(0x1220) = 0x1388; } - MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! - MCHBAR32(0x1c04); // !!!! - MCHBAR32(0x1804) = 0x406080; + MCHBAR32_OR(0x2c80, (1 << 24)); + MCHBAR32(0x1804) = MCHBAR32(0x1c04) & ~(1 << 27); - MCHBAR8(0x2ca8); + MCHBAR8(0x2ca8); // !!!! if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); @@ -4195,15 +4203,26 @@ MCHBAR32_OR(0x1af0, 0x10); halt(); } + MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); // !!!! - MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); - MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! + MCHBAR32_AND(0x2c80, ~(1 << 24)); + pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); - MCHBAR16(0x2c20); // !!!! - MCHBAR16(0x2c10); // !!!! - MCHBAR16(0x2c00); // !!!! - MCHBAR16(0x2c00) = 0x8c0; - udelay(1000); + + { + u8 x2c20 = (MCHBAR16(0x2c20) >> 8) & 3; + u16 x2c10 = MCHBAR16(0x2c10); + u16 value = MCHBAR16(0x2c00); + if (x2c20 == 0 && (x2c10 & 0x300) == 0) + value |= (1 << 7); + else + value &= ~(1 << 0); + + MCHBAR16(0x2c00) = value; + } + + udelay(1000); // !!!! + write_1d0(0, 0x33d, 0, 0); write_500(&info, 0, 0, 0xb61, 0, 0); write_500(&info, 1, 0, 0xb61, 0, 0); @@ -4306,8 +4325,9 @@ MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; - MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! - MCHBAR8(0x1f0); // !!!! + MCHBAR8_OR(0x1f0, 0x1); + while (MCHBAR8(0x1f0) & 1) + ; program_board_delay(&info); @@ -4318,25 +4338,20 @@ MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? while (MCHBAR32(0x130) & 1) ; - gav(read_1d0(0x14b, 7)); // = 0x81023100 - write_1d0(0x30, 0x14b, 7, 1); - read_1d0(0xd6, 6); // = 0xfa008080 // !!!! - write_1d0(7, 0xd6, 6, 1); - read_1d0(0x328, 6); // = 0xfa018080 // !!!! - write_1d0(7, 0x328, 6, 1); + + rmw_1d0(0x14b, 0x47, 0x30, 7, 1); + rmw_1d0(0xd6, 0x38, 7, 6, 1); + rmw_1d0(0x328, 0x38, 7, 6, 1); for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0); - read_1d0(0x116, 4); // = 0x4040432 // !!!! - write_1d0(2, 0x116, 4, 1); - read_1d0(0xae, 6); // = 0xe8088080 // !!!! - write_1d0(0, 0xae, 6, 1); - read_1d0(0x300, 4); // = 0x48088080 // !!!! - write_1d0(0, 0x300, 6, 1); - MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!! - MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!! + rmw_1d0(0x116, 0xe, 0, 4, 1); + rmw_1d0(0xae, 0x3e, 0, 6, 1); + rmw_1d0(0x300, 0x3e, 0, 6, 1); + MCHBAR16_AND(0x356, 0x7fff); + MCHBAR16_AND(0x756, 0x7fff); MCHBAR32_AND(0x140, ~0x07000000); MCHBAR32_AND(0x138, ~0x07000000); MCHBAR32(0x130) = 0x31111301; @@ -4370,10 +4385,8 @@ write_1d0(2, 0xae, 6, 1); write_1d0(2, 0x300, 6, 1); write_1d0(2, 0x121, 3, 1); - read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!! - write_1d0(4, 0xd6, 6, 1); - read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!! - write_1d0(4, 0x328, 6, 1); + rmw_1d0(0xd6, 0x38, 4, 6, 1); + rmw_1d0(0x328, 0x38, 4, 6, 1); for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, @@ -4383,12 +4396,17 @@ (info.populated_ranks[0][0][0] << 29); while (MCHBAR8(0x130) & 1) ; - read_1d0(0xa1, 6); // = 0x1cf4054 // !!!! - read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! - read_1d0(0x21c, 6); // = 0xafa00c0 // !!!! - write_1d0(0, 0x21c, 6, 1); - read_1d0(0x14b, 7); // = 0x810231b0 // !!!! - write_1d0(0x35, 0x14b, 7, 1); + + { + u32 reg32 = read_1d0(0xa1, 6); + read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! + rmw_1d0(0x21c, 0x38, 0, 6, 1); + u8 reg8 = 0; + reg8 |= (reg32 >> 4) & (1 << 0); + reg8 |= (reg32 >> 2) & (1 << 1); + reg8 |= (reg32 >> 0) & (1 << 2); + rmw_1d0(0x14b, 0x78, reg8, 7, 1); + } for (channel = 0; channel < NUM_CHANNELS; channel++) set_4cf(&info, channel, @@ -4443,8 +4461,8 @@ MCHBAR8(0x12c) = 0x9f; - MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!! - MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! + MCHBAR8_AND_OR(0x271, 0xcf, 0xe); + MCHBAR8_AND_OR(0x671, 0xcf, 0xe); if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -4469,8 +4487,7 @@ write_1d0(7, 0x1c0, 3, 1); write_1d0(4, 0x1c6, 4, 1); write_1d0(4, 0x1cc, 4, 1); - read_1d0(0x151, 4); // = 0x408c6d74 // !!!! - write_1d0(4, 0x151, 4, 1); + rmw_1d0(0x151, 0xf, 0x4, 4, 1); MCHBAR32(0x584) = 0xfffff; MCHBAR32(0x984) = 0xfffff; -- To view, visit https://review.coreboot.org/c/coreboot/+/45606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec Gerrit-Change-Number: 45606 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes/hda_verb: Fix some issues
by Patrick Rudolph (Code Review) 24 Feb '21

24 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44772 ) Change subject: mb/prodrive/hermes/hda_verb: Fix some issues ...................................................................... mb/prodrive/hermes/hda_verb: Fix some issues * Use correct NID port mapping * Fix verb count in ACL888 header * Fix NID in Intel codec verbs * Add more NIDs Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/hda_verb.c 1 file changed, 74 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44772/1 diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 59b8aa6..6cde639 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -5,47 +5,11 @@ const u32 cim_verb_data[] = { 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ 0x10ec0888, /* Subsystem ID */ - 10, /* Number of 4 dword sets */ + 13, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10ec0888), - /* Port A: Front, Audio Header #1 */ - AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - SPECIAL7, - LINE_OUT, - OTHER_ANALOG, - COLOR_UNKNOWN, - false, - 0xf, - 0 - )), - /* Port B: Mic1, Line input (pink) */ - AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( - JACK, - EXTERNAL_PRIMARY_CHASSIS, - REAR, //FIXME - LINE_IN, - STEREO_MONO_1_8, - PINK, - false, - 0xf, - 0 - )), - /* Port C: Line, Speaker (only L) */ - AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - NA, - SPEAKER, - TYPE_UNKNOWN, - COLOR_UNKNOWN, - false, - 0xf, - 0 - )), /* Port D: Sidesurr, Line out (green) */ - AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( //JACK, LINE_OUT, EXTERNAL_PRIMARY_CHASSIS, @@ -57,14 +21,50 @@ 0xf, 0 )), - /* Port E: Line2, Line input (blue) */ + /* Port A: Front, Audio Header #1 */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC( + INTEGRATED, + INTERNAL, + SPECIAL7, + LINE_OUT, + OTHER_ANALOG, + COLOR_UNKNOWN, + false, + 0xf, + 0 + )), + /* Port G: Not connected */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_DESC( + NC, + LOCATION_OTHER, + NA, + DEVICE_OTHER, + TYPE_OTHER, + COLOR_OTHER, + true, + 0, + 0 + )), + /* Port H: Not connected */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_DESC( + NC, + LOCATION_OTHER, + NA, + DEVICE_OTHER, + TYPE_OTHER, + COLOR_OTHER, + true, + 0, + 0 + )), + /* Port B: Mic1, Line input (pink) */ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( JACK, EXTERNAL_PRIMARY_CHASSIS, REAR, //FIXME LINE_IN, STEREO_MONO_1_8, - BLUE, + PINK, false, 0xf, 0 @@ -81,20 +81,32 @@ 0xf, 0 )), - /* Port G: Not connected */ + /* Port C: Line, Speaker (only L) */ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( - NC, - LOCATION_OTHER, + INTEGRATED, + INTERNAL, NA, - DEVICE_OTHER, - TYPE_OTHER, - COLOR_OTHER, - true, - 0, + SPEAKER, + TYPE_UNKNOWN, + COLOR_UNKNOWN, + false, + 0xf, 0 )), - /* Port H: Not connected */ + /* Port E: Line2, Line input (blue) */ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + JACK, + EXTERNAL_PRIMARY_CHASSIS, + REAR, //FIXME + LINE_IN, + STEREO_MONO_1_8, + BLUE, + false, + 0xf, + 0 + )), + /* Port CD: Not connected */ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_DESC( NC, LOCATION_OTHER, NA, @@ -105,6 +117,8 @@ 0, 0 )), + /* BEEPIN: This NID is also used as SSID. Use magic constant to satisfy the driver. */ + AZALIA_PIN_CFG(0, 0x1d, 0x4000c601), /* S/PDIF-OUT */ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_DESC( @@ -131,16 +145,16 @@ 0 )), - //FIXME COdec ID /* * VerbTable: CFL Display Audio Codec * Revision ID = 0xFF * Codec Vendor: 0x8086280B */ - 0x8086280B, 0xFFFFFFFF, - 5, /* Number of 4 dword sets */ + 6, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), /* * Display Audio Verb Table @@ -148,10 +162,10 @@ * Port to be exposed to the inbox driver in the vanilla mode * PORT C - BIT[7:6] = 01b */ - 0x00878140, - 0x00878140, - 0x00878140, - 0x00878140, + 0x02878140, + 0x02878140, + 0x02878140, + 0x02878140, /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ AZALIA_PIN_CFG(2, 0x05, 0x18560010), /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ @@ -159,10 +173,10 @@ /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ AZALIA_PIN_CFG(2, 0x07, 0x18560030), /* Disable the third converter and third Pin (NID 08h) */ - 0x00878140, - 0x00878140, - 0x00878140, - 0x00878140, + 0x02878140, + 0x02878140, + 0x02878140, + 0x02878140, }; const u32 pc_beep_verbs[0] = {}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Gerrit-Change-Number: 44772 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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