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Change in coreboot[master]: soc/mediatek/mt8192: add dramc power control
by Xi Chen (Code Review) 09 Mar '21

09 Mar '21

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48073 ) Change subject: soc/mediatek/mt8192: add dramc power control ...................................................................... soc/mediatek/mt8192: add dramc power control Controls HV or LV of VDD1/VDD2/VDDQ/VMDDR. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I50645e3a53d5c3c9d0b1237e32fafa8745734e8a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_power.c M src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h A src/soc/mediatek/mt8192/include/soc/dramc_power.h 6 files changed, 203 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/48073/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index c01d716..76a28d0 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c dramc_power.c romstage-y += dramc_subsys_config.c dramc_ana_init_config.c dramc_dig_config.c romstage-y += emi.c romstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index e7c6ecb..f7bca77 100755 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,9 +2,7 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> -#include <soc/pll.h> -#include <soc/pll_common.h> -#include <soc/mt6359p.h> +#include <soc/dramc_power.h> static void dramc_write_shift_mck_write_DBI(const struct ddr_cali *cali, s8 shift_value) { @@ -209,14 +207,6 @@ } } -static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) -{ - u32 vcore = get_vcore_value(cali); - - dramc_info("Set DRAM vcore voltage to %u\n", vcore); - mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); -} - static void get_dram_info_after_cal(struct ddr_cali *cali) { u8 vendor_id, density, max_density = 0; @@ -451,7 +441,8 @@ set_cali_datas(&cali, dparam, k_seq_idx); dramc_info("start calibration frequency %d\n", cali.frequency); - set_vcore_voltage_for_each_freq(&cali); + dramc_set_voltage(&cali); + dramc_dump_voltage(); dfs_init_for_calibration(&cali); if (first_freq_k) @@ -485,7 +476,8 @@ dram_dfs_shu bootup_shu = get_shu_save_by_k_shu(bootup_cali_seq); set_cali_datas(&cali, dparam, bootup_cali_seq); - set_vcore_voltage_for_each_freq(&cali); + dramc_set_voltage(&cali); + dramc_dump_voltage(); dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, DRAM_DFS_SHU1); dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, bootup_shu); diff --git a/src/soc/mediatek/mt8192/dramc_power.c b/src/soc/mediatek/mt8192/dramc_power.c new file mode 100644 index 0000000..b6d1c03 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_power.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_power.h> + +void __weak mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + dramc_info("%s not implemented!\n", __func__); +} + +uint32_t __weak mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + dramc_info("%s not implemented!\n", __func__); + return 0; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ +#ifdef HQA_HV + return cali->vcore_voltage / 100 * 105; +#elif defined(HQA_LV) + return cali->vcore_voltage / 100 * 95; +#else + return cali->vcore_voltage; +#endif +} + +u32 get_vdd1_value() +{ + return VDD1_VOL; +} + +u32 get_vdd2_value() +{ + return VDD2_VOL; +} + +u32 get_vddq_value() +{ + return VDDQ_VOL; +} + +u32 get_vmddr_value() +{ + return VMDDR_VOL; +} + +void dramc_set_vcore_voltage(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("[%s]Set vcore voltage to %u\n", HQA_TAG, vcore); + mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); +} + +void dramc_set_vdd1_voltage() +{ + u32 vdd1 = get_vdd1_value(); + + dramc_info("[%s]Set DRAM vdd1 voltage to %u\n", HQA_TAG, vdd1); + mainboard_set_regulator_vol(MTK_REGULATOR_VDD1, vdd1); +} + +void dramc_set_vdd2_voltage() +{ + u32 vdd2 = get_vdd2_value(); + + dramc_info("[%s]Set DRAM vdd2 voltage to %u\n", HQA_TAG, vdd2); + mainboard_set_regulator_vol(MTK_REGULATOR_VDD2, vdd2); +} + +void dramc_set_vddq_voltage() +{ + u32 vddq = get_vddq_value(); + + dramc_info("[%s]Set DRAM vddq voltage to %u\n", HQA_TAG, vddq); + mainboard_set_regulator_vol(MTK_REGULATOR_VDDQ, vddq); +} + +void dramc_set_vmddr_voltage() +{ + u32 vmddr = get_vmddr_value(); + + dramc_info("[%s]Set vmddr voltage to %u\n", HQA_TAG, vmddr); + mainboard_set_regulator_vol(MTK_REGULATOR_VMDDR, vmddr); +} + +u32 dramc_get_vcore_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VCORE); +} + +// TODO: use real interface +u32 dramc_get_vdd1_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD1); +} + +u32 dramc_get_vdd2_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD2); +} + +u32 dramc_get_vddq_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDDQ); +} + +u32 dramc_get_vmddr_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VMDDR); +} + +void dramc_set_voltage(const struct ddr_cali *cali) +{ + dramc_set_vcore_voltage(cali); + + dramc_set_vdd1_voltage(); + dramc_set_vdd2_voltage(); + dramc_set_vddq_voltage(); + + dramc_set_vmddr_voltage(); +} + +void dramc_dump_voltage() +{ + u32 vcore, vdd1, vdd2, vddq, vmddr; + + vcore = dramc_get_vcore_voltage(); + + vdd1 = dramc_get_vdd1_voltage(); + vdd2 = dramc_get_vdd2_voltage(); + vddq = dramc_get_vddq_voltage(); + + vmddr = dramc_get_vmddr_voltage(); + dramc_info("[Dump Dram Voltage] vcore: %u, vdd1:%u, vdd2:%u, vddq:%u, vmddr:%u\n" + , vcore, vdd1, vdd2, vddq, vmddr); +} + diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c old mode 100644 new mode 100755 index e8878c1..fdfbd63 --- a/src/soc/mediatek/mt8192/dramc_utility.c +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -2,6 +2,7 @@ #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_power.h> #include <soc/infracfg.h> struct dfs_frequency_table { @@ -105,11 +106,6 @@ return cali->cbt_mode[cali->rank]; } -u32 get_vcore_value(const struct ddr_cali *cali) -{ - return cali->vcore_voltage; -} - u32 get_frequency(const struct ddr_cali *cali) { return cali->frequency; diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h old mode 100644 new mode 100755 index e0b887a..8ac0a64 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -301,7 +301,6 @@ dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu); dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali); u32 get_frequency_by_shu(dram_dfs_shu shu); -u32 get_vcore_value(const struct ddr_cali *cali); void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_seq); u8 get_mck2ui_div_shift(const struct ddr_cali *cali); diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_power.h b/src/soc/mediatek/mt8192/include/soc/dramc_power.h new file mode 100755 index 0000000..22771e3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_power.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_POWER_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_POWER_H__ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_common_mt8192.h> +#include <soc/dramc_pi_api.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/mt6359p.h> +#include <soc/regulator.h> + +#ifdef HQA_HV +#define HQA_TAG "HV" +#define VDD1_VOL 1950000 +#define VDD2_VOL 1170000 +#define VDDQ_VOL 650000 +#define VMDDR_VOL 790000 +#elif defined(HQA_LV) +#define HQA_TAG "LV" +#define VDD1_VOL 1730000 +#define VDD2_VOL 1060000 +#define VDDQ_VOL 570000 +#define VMDDR_VOL 710000 +#else // by default: HQA_NV +#define HQA_TAG "NV" +#define VDD1_VOL 1800000 +#define VDD2_VOL 1125000 +#define VDDQ_VOL 600000 +#define VMDDR_VOL 750000 +#endif + +u32 get_vcore_value(const struct ddr_cali *cali); +u32 get_vdd1_value(void); +u32 get_vdd2_value(void); +u32 get_vddq_value(void); +u32 get_vmddr_value(void); + +u32 dramc_get_vcore_voltage(void); +u32 dramc_get_vdd1_voltage(void); +u32 dramc_get_vdd2_voltage(void); +u32 dramc_get_vddq_voltage(void); +u32 dramc_get_vmddr_voltage(void); +void dramc_dump_voltage(void); + +void dramc_set_vcore_voltage(const struct ddr_cali *cali); +void dramc_set_vdd1_voltage(void); +void dramc_set_vdd2_voltage(void); +void dramc_set_vddq_voltage(void); +void dramc_set_vmddr_voltage(void); + +void dramc_set_voltage(const struct ddr_cali *cali); + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */ + -- To view, visit https://review.coreboot.org/c/coreboot/+/48073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50645e3a53d5c3c9d0b1237e32fafa8745734e8a Gerrit-Change-Number: 48073 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/google/octopus/var/fleex: Add new SKU for LTE touch
by Amanda Hwang (Code Review) 05 Mar '21

05 Mar '21

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46643 ) Change subject: mb/google/octopus/var/fleex: Add new SKU for LTE touch ...................................................................... mb/google/octopus/var/fleex: Add new SKU for LTE touch BUG=b:168001586 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4 and 5. Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/variant.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/46643/1 diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c index f1ec818..fcc8be0 100644 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -5,11 +5,9 @@ #include <ec/google/chromeec/ec.h> #include <sar.h> -#define LTE_SKU 4 - static bool is_lte_sku(void) { - return (google_chromeec_get_board_sku() == LTE_SKU); + return (google_chromeec_get_board_sku() > 3); } void variant_smi_sleep(u8 slp_typ) -- To view, visit https://review.coreboot.org/c/coreboot/+/46643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4 Gerrit-Change-Number: 46643 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/broadwell/pch: Rename USB files
by Angel Pons (Code Review) 05 Mar '21

05 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47021 ) Change subject: soc/intel/broadwell/pch: Rename USB files ...................................................................... soc/intel/broadwell/pch: Rename USB files Done to ease diffing against Lynxpoint. Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/Makefile.inc R src/soc/intel/broadwell/pch/usb_ehci.c R src/soc/intel/broadwell/pch/usb_xhci.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/47021/1 diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1c19613..1ebe324f 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -32,8 +32,8 @@ bootblock-y += usb_debug.c romstage-y += usb_debug.c ramstage-y += usb_debug.c -ramstage-y += ehci.c -ramstage-y += xhci.c -smm-y += xhci.c +ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c +smm-y += usb_xhci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/soc/intel/broadwell/pch/ehci.c b/src/soc/intel/broadwell/pch/usb_ehci.c similarity index 100% rename from src/soc/intel/broadwell/pch/ehci.c rename to src/soc/intel/broadwell/pch/usb_ehci.c diff --git a/src/soc/intel/broadwell/pch/xhci.c b/src/soc/intel/broadwell/pch/usb_xhci.c similarity index 100% rename from src/soc/intel/broadwell/pch/xhci.c rename to src/soc/intel/broadwell/pch/usb_xhci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Gerrit-Change-Number: 47021 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/tigerlake: Update early TCSS code to not call back and forth betw...
by Brandon Breitenstein (Code Review) 05 Mar '21

05 Mar '21

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47684 ) Change subject: soc/tigerlake: Update early TCSS code to not call back and forth between mainboard and soc ...................................................................... soc/tigerlake: Update early TCSS code to not call back and forth between mainboard and soc The original implementation of early tcss resulted in calling to mainboard then back to soc then back to mainboard to properly configure the muxes. This patch addresses that issue and instead just gets all the mux information from mainboard and does all config in the soc code. This also adds a new check for early display support which removes the requirement for the system to be a vboot compatible system before executing. Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/early_tcss.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/early_tcss.h 3 files changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/47684/1 diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c index 3944f61..8616bb1 100644 --- a/src/soc/intel/tigerlake/early_tcss.c +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci.h> #include <intelblocks/pmc_ipc.h> +#include <security/vboot/vboot_common.h> #include <soc/early_tcss.h> #include <soc/pci_devs.h> #include <stdlib.h> @@ -240,7 +241,7 @@ return 0; } -void update_tcss_mux(int port, struct tcss_mux mux_data) +static void update_tcss_mux(int port, struct tcss_mux mux_data) { struct pmc_ipc_buffer *rbuf = NULL; int ret = 0; @@ -265,7 +266,34 @@ printk(BIOS_ERR, "Port C%d mux set failed with error %d\n", port, ret); } -__weak void mainboard_early_tcss_enable(void) +static int system_requires_early_display(void) +{ + if (!CONFIG(VBOOT)) + return 1; + else if (vboot_recovery_mode_enabled() || vboot_developer_mode_enabled()) + return 1; + else + return 0; +} + +void tcss_early_configure(void) +{ + + struct tcss_mux *mux_info = NULL; + unsigned int num_ports; + int i; + + if (!system_requires_early_display()) + return; + + mainboard_early_tcss_enable(mux_info, &num_ports); + + for (i = 0; i < num_ports; i++) + update_tcss_mux(i, mux_info[i]); + +} + +__weak void mainboard_early_tcss_enable(struct tcss_mux *mux_info, unsigned int *num_ports) { /* to be overwritten by each mainboard that needs early tcss */ } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 6de098a..2bec43e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -387,9 +387,8 @@ /* TCSS specific initialization here */ printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", __FILE__, __func__); - if (CONFIG(EARLY_TCSS_DISPLAY) && (vboot_recovery_mode_enabled() || - vboot_developer_mode_enabled())) - mainboard_early_tcss_enable(); + if (CONFIG(EARLY_TCSS_DISPLAY)) + tcss_early_configure(); break; default: break; diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h index c009e84..cee4c12 100644 --- a/src/soc/intel/tigerlake/include/soc/early_tcss.h +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -126,7 +126,9 @@ uint8_t usb2_port; /* USB3 Port Number */ }; -void update_tcss_mux(int port, struct tcss_mux mux_data); +//void update_tcss_mux(int port, struct tcss_mux mux_data); + +void tcss_early_configure(void); /* * Weak mainboard method to setup any mux configuration needed for early TCSS operations. @@ -136,4 +138,4 @@ * must be overridden by the mainboard with its specific mux data stored in a struct tcss_mux * struct as defined above. */ -void mainboard_early_tcss_enable(void); +void mainboard_early_tcss_enable(struct tcss_mux *mux_info, unsigned int *num_ports); -- To view, visit https://review.coreboot.org/c/coreboot/+/47684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73 Gerrit-Change-Number: 47684 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 29

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 04 Mar '21

04 Mar '21

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42079 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42079/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..55c06b1 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -208,4 +208,10 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 + +config EARLY_TCSS + bool "Enable early TCSS" + help + Enable devices to be detected over Type-C ports during boot. + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..5e60114 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-$(CONFIG_EARLY_TCSS) += early_tcss.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 00db2a4..3da5d9a 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -10,6 +10,7 @@ #include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> +#include <soc/early_tcss.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> @@ -129,6 +130,10 @@ * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* Check for early TCSS and connect devices */ + if (CONFIG(EARLY_TCSS)) + early_tcss_enable(); + /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c new file mode 100644 index 0000000..942d490 --- /dev/null +++ b/src/soc/intel/tigerlake/early_tcss.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/pmclib.h> +#include <soc/early_tcss.h> +#include <soc/pci_devs.h> +#include <stdlib.h> + +/* send the ipc_command */ +static int send_ipc_command(uint32_t cmd, uint8_t *tcss_req, int req_size, + struct pmc_ipc_buffer *rbuf) +{ + struct pmc_ipc_buffer *wbuf = malloc(sizeof(*tcss_req)); + + /* copy the tcss_req into a buffer for ipc command */ + memcpy(wbuf, tcss_req, req_size); + + return pmc_send_ipc_cmd(cmd, wbuf, rbuf); +} + +static int send_pmc_connect_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_CONN_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */ + mux_data.usb3_port << 4; + tcss_req[1] = mux_data.usb2_port | + mux_data.ufp << 4 | /* 1=UFP/0=DFP */ + mux_data.polarity << 5 | /* ORI-HSL */ + mux_data.polarity << 6 | /* ORI-SBU */ + mux_data.acc << 7; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]); + + tcss_cmd.len = PMC_IPC_CONN_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_CONN_REQ_SIZE, rbuf); +} + +static int send_pmc_safe_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_SAFE_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_SAFE_MODE_REQ_RES | + mux_data.usb3_port << 4; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n", tcss_req[0]); + + tcss_cmd.cmd.len = PMC_IPC_SAFE_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_SAFE_REQ_SIZE, rbuf); +} + +static int send_pmc_alt_mode_request(struct tcss_mux mux_data, + struct pmc_ipc_buffer *rbuf) +{ + union pmc_ipc_cmd tcss_cmd = { 0 }; + uint8_t tcss_req[PMC_IPC_ALT_REQ_SIZE] = { 0 }; + + tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID; + tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID; + + tcss_req[0] = PMC_IPC_TCSS_ALTMODE_REQ_RES | mux_data.usb3_port << 4; + tcss_req[1] |= PMC_IPC_DP_MODE; + + tcss_req[4] = mux_data.polarity << 1 | + mux_data.cable << 2 | + mux_data.ufp << 3 | + mux_data.polarity << 4 | + mux_data.polarity << 5; + + if (mux_data.dp_mode <= MODE_DP_PIN_F) { + switch (mux_data.dp_mode) { + case MODE_DP_PIN_A: + tcss_req[5] = 0; + break; + case MODE_DP_PIN_B: + tcss_req[5] = 1; + break; + case MODE_DP_PIN_C: + tcss_req[5] = 2; + break; + case MODE_DP_PIN_D: + tcss_req[5] = 3; + break; + case MODE_DP_PIN_E: + tcss_req[5] = 4; + break; + case MODE_DP_PIN_F: + tcss_req[5] = 5; + break; + } + } + + tcss_req[5] |= mux_data.hpd_lvl << 6; + printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n" + "tcss_req[1]-> 0x%x\n" + "tcss_req[4]-> 0x%x\n" + "tcss_req[5]-> 0x%x\n\t", + tcss_req[0], tcss_req[1], tcss_req[4], tcss_req[5]); + + tcss_cmd.len = PMC_IPC_ALT_REQ_SIZE; + + return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_ALT_REQ_SIZE, rbuf); +} + +static void update_tcss_mux(int port, struct tcss_mux mux_data) +{ + struct pmc_ipc_buffer *rbuf = malloc(sizeof(*rbuf)); + int ret = 0; + + /* Check if the mux has a USB device */ + if (mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + + /* check if mux has a DP device */ + if (mux_data.dp) { + + if (!mux_data.usb) { + ret = send_pmc_connect_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d connect request failed\n", port); + return; + } + } + ret = send_pmc_safe_mode_request(mux_data, rbuf); + if (ret) { + printk(BIOS_ERR, "Port %d safe mode request failed\n", port); + return; + } + + ret = send_pmc_alt_mode_request(mux_data, rbuf); + } + + if (ret) + printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret); +} + +void early_tcss_enable(void) +{ + uint8_t num_ports; + int ret, i; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) + return; + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) + continue; + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) + continue; + + ret = google_chromeec_usb_pd_control(i, &mux_data.ufp, &mux_data.acc, + &mux_data.dp_mode); + if (ret < 0) + continue; + + mux_data.usb = !!(mux_flags & USB_PD_CTRL_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_CTRL_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_MUX_TBT_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_CTRL_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_CTRL_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_CTRL_HPD_LVL); + mux_data.usb2_port = port_map & 0x0F; + mux_data.usb3_port = (port_map & 0xF0) >> 4; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "ufp = %d dbg_acc=%d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.ufp, mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h new file mode 100644 index 0000000..29b7cdd --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PMC IPC related offsets and commands */ +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_USBC_SUBCMD_ID 0x0 +#define PMC_IPC_CMD 0x0 +#define PMC_IPC_TCSS_CONN_REQ_RES 0x0 +#define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2 +#define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3 +#define PMC_IPC_CONN_REQ_SIZE 2 +#define PMC_IPC_ALT_REQ_SIZE 8 +#define PMC_IPC_SAFE_REQ_SIZE 1 +#define PMC_IPC_DP_MODE BIT(4) + +/* connection modes for pmc */ +enum pmc_ipc_conn_mode { + PMC_IPC_TCSS_DISCONNECT_MODE, + PMC_IPC_TCSS_USB_MODE, + PMC_IPC_TCSS_ALTERNATE_MODE, + PMC_IPC_TCSS_SAFE_MODE, + PMC_IPC_TCSS_HPD_MODE, + PMC_IPC_TCSS_TOTAL_MODES, +}; + +/* DP Mode pin definitions */ +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) + +/* struct to hold all tcss_mux related variables */ +struct tcss_mux { + bool dp; /* DP connected */ + bool usb; /* USB connected */ + bool cable; /* Activ/Passive Cable */ + bool polarity; /* polarity of connected device */ + bool hpd_lvl; /* HPD Level assert */ + bool hpd_irq; /* HPD IRQ assert */ + bool ufp; + bool acc; + uint8_t dp_mode; /* DP Operation Mode */ + uint8_t usb3_port; /* USB2 Port Number */ + uint8_t usb2_port; /* USB3 Port Number */ +}; + +void early_tcss_enable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a Gerrit-Change-Number: 42079 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 64

Change in coreboot[master]: soc/intel/common/block/smbus: Add config to use ACPI
by Maxim Polyakov (Code Review) 03 Mar '21

03 Mar '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44865 ) Change subject: soc/intel/common/block/smbus: Add config to use ACPI ...................................................................... soc/intel/common/block/smbus: Add config to use ACPI Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/smbus/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44865/1 diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index fe940cc..818200e 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -3,6 +3,13 @@ help Intel Processor common SMBus support +config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_SMBUS + help + Intel Processor SMBus ACPI driver support + config SOC_INTEL_COMMON_BLOCK_TCO bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/44865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Gerrit-Change-Number: 44865 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/alderlake: Log internal device wake events
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47399 ) Change subject: soc/intel/alderlake: Log internal device wake events ...................................................................... soc/intel/alderlake: Log internal device wake events Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/elog.c 3 files changed, 77 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..68c33c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,8 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..f1d7b65 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += xhci.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 88760b9..c3509df 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> @@ -56,6 +57,77 @@ } } +static void pch_log_add_elog_event(const struct pme_map *ipme_map) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((ipme_map->devfn == PCH_DEVFN_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(ipme_map->wake_source, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + bool dev_found = false; + + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + { SA_DEVFN_TCSS_DMA0, ELOG_WAKE_SOURCE_PME_TCSS_DMA0 }, + { SA_DEVFN_TCSS_DMA1, ELOG_WAKE_SOURCE_PME_TCSS_DMA1 }, + }; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + pch_log_add_elog_event(&ipme_map[i]); + dev_found = true; + } + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + /* Check Thunderbolt ports */ + if (!dev_found) { + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + } + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -74,9 +146,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Gerrit-Change-Number: 47399 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/alderlake: Add some helper macros for accessing TCSS DMA de...
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47413 ) Change subject: soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices ...................................................................... soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/pci_devs.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47413/1 diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index d86e81d..fd9823e 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -50,6 +50,8 @@ #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, (x + 2)) #define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) #define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) #define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/47413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Gerrit-Change-Number: 47413 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: soc/intel/alderlake: Add PCIe root port wake sources to elog
by Tim Wawrzynczak (Code Review) 03 Mar '21

03 Mar '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47398 ) Change subject: soc/intel/alderlake: Add PCIe root port wake sources to elog ...................................................................... soc/intel/alderlake: Add PCIe root port wake sources to elog Log PCIe root port wake events in the elog. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 --- M src/soc/intel/alderlake/elog.c 1 file changed, 39 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47398/1 diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84f0a7e..88760b9 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -2,11 +2,18 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> +#include <types.h> + +struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; +}; static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +27,35 @@ } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +66,9 @@ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 Gerrit-Change-Number: 47398 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate lock bit write
by Angel Pons (Code Review) 03 Mar '21

03 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47036 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate lock bit write ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate lock bit write This lock bit can be set later, and should also be set for Lynxpoint-H. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47036/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b47b8a..10e498a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -364,9 +364,6 @@ if (RCBA32(FD) & PCH_DISABLE_ADSPD) RCBA32_OR(0x2b1c, (1 << 29)); - /* Lock */ - RCBA32_OR(0x3a6c, 0x00000001); - /* Set RCBA 0x33D4 after other setup */ RCBA32_OR(0x33d4, 0x2fff2fb1); @@ -772,6 +769,9 @@ { spi_finalize_ops(); + /* Lock */ + RCBA32_OR(0x3a6c, 0x00000001); + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) apm_control(APM_CNT_FINALIZE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Gerrit-Change-Number: 47036 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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