coreboot-gerrit November 2020

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Change in coreboot[master]: soc/mediatek/mt8192: fix impedance tracking channel number
by Yidi Lin (Code Review) 11 Mar '21

11 Mar '21

Hello Xi Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46399 to review the following change. Change subject: soc/mediatek/mt8192: fix impedance tracking channel number ...................................................................... soc/mediatek/mt8192: fix impedance tracking channel number Update impedance tracking CH1 setting. Signed-off-by: mtk11206 <xixi.chen(a)mediatek.com> Change-Id: Iafec2e14a4b0b318e30493ee49c07af5aad5f1e8 --- M src/soc/mediatek/mt8192/dramc_tracking.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46399/1 diff --git a/src/soc/mediatek/mt8192/dramc_tracking.c b/src/soc/mediatek/mt8192/dramc_tracking.c old mode 100644 new mode 100755 index 3b0b8d6..382675e --- a/src/soc/mediatek/mt8192/dramc_tracking.c +++ b/src/soc/mediatek/mt8192/dramc_tracking.c @@ -526,7 +526,7 @@ MISC_IMPCAL_DIS_SUS_CH1_DRV, 1, MISC_IMPCAL_IMPSRCEXT, 0, MISC_IMPCAL_IMPCAL_ECO_OPT, 1); - SET32_BITFIELDS(&ch[0].phy_ao.misc_impcal, + SET32_BITFIELDS(&ch[1].phy_ao.misc_impcal, MISC_IMPCAL_DIS_SUS_CH0_DRV, 1, MISC_IMPCAL_DIS_SUS_CH1_DRV, 0, MISC_IMPCAL_IMPSRCEXT, 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/46399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafec2e14a4b0b318e30493ee49c07af5aad5f1e8 Gerrit-Change-Number: 46399 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: DO-NOT-SUBMIT: Asurada ToT - Coreboot
by Yidi Lin (Code Review) 09 Mar '21

09 Mar '21

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46413 to review the following change. Change subject: DO-NOT-SUBMIT: Asurada ToT - Coreboot ...................................................................... DO-NOT-SUBMIT: Asurada ToT - Coreboot Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: If23898ebc6a1a0bcec910873a07b7470f9aa3dd6 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46413/1 diff --git a/README.md b/README.md index 14879c1..d2b1bc8 100644 --- a/README.md +++ b/README.md @@ -102,3 +102,4 @@ Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2. + -- To view, visit https://review.coreboot.org/c/coreboot/+/46413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If23898ebc6a1a0bcec910873a07b7470f9aa3dd6 Gerrit-Change-Number: 46413 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Do rx dqs gating training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44718 to review the following change. Change subject: soc/mediatek/mt8192: Do rx dqs gating training ...................................................................... soc/mediatek/mt8192: Do rx dqs gating training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I141abc1fdd283f4898d0772736bc777e87017561 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 323 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44718/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index e531de0..8d65a67 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -18,6 +18,15 @@ }, }; +struct rxdqs_gating_best_win { + u8 dqsien_dly_mck[DQS_NUMBER]; + u8 dqsien_dly_ui[DQS_NUMBER]; + u8 dqsien_dly_pi[DQS_NUMBER]; + u8 dqsien_dly_mck_p1[DQS_NUMBER]; + u8 dqsien_dly_ui_p1[DQS_NUMBER]; + u8 dqsien_dly_pi_p1[DQS_NUMBER]; +}; + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -1378,3 +1387,311 @@ dramc_set_broadcast(bc_bak); } + +static u8 rxdqs_gating_get_tx_dly_min(dram_freq_grp freq_group, + struct rxdqs_gating_best_win *rxdqs_best_win) +{ + u8 tx_dly_dqs_gated = 0, tx_dly_min = 0xff; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs, + rxdqs_best_win->dqsien_dly_mck[dqs], + rxdqs_best_win->dqsien_dly_ui[dqs], + rxdqs_best_win->dqsien_dly_pi[dqs]); + + tx_dly_dqs_gated = (rxdqs_best_win->dqsien_dly_mck[dqs] << 4) + + rxdqs_best_win->dqsien_dly_ui[dqs]; + + if (freq_group != DDRFREQ_400) + tx_dly_dqs_gated >>= 3; + else + tx_dly_dqs_gated >>= 2; + + if (tx_dly_dqs_gated < tx_dly_min) + tx_dly_min = tx_dly_dqs_gated; + } + return tx_dly_min; +} + +static u8 rxdqs_gating_get_tx_dly_max(dram_freq_grp freq_group, + struct rxdqs_gating_best_win *rxdqs_best_win) +{ + u8 tx_dly_dqs_gated = 0, tx_dly_max = 0; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs, + rxdqs_best_win->dqsien_dly_mck_p1[dqs], + rxdqs_best_win->dqsien_dly_ui_p1[dqs], + rxdqs_best_win->dqsien_dly_pi_p1[dqs]); + + tx_dly_dqs_gated = (rxdqs_best_win->dqsien_dly_mck_p1[dqs] << 4) + + rxdqs_best_win->dqsien_dly_ui_p1[dqs]; + + if (freq_group != DDRFREQ_400) + tx_dly_dqs_gated >>= 3; + else + tx_dly_dqs_gated >>= 2; + + if (tx_dly_dqs_gated > tx_dly_max) + tx_dly_max = tx_dly_dqs_gated; + } + return tx_dly_max; +} + +void dramc_rx_dqs_gating_cal(const struct ddr_cali* cali, + u8 *tx_dly_min, u8 *tx_dly_max) +{ + u8 chn, rank; + u8 pi_per_ui, ui_per_mck, freq_div; + dram_freq_grp freq_group; + struct rxdqs_gating_best_win best_win = {0}; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + freq_group = get_freq_group(cali); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy_ao.dvs_b[0].b0_dq6}, + {&ch[chn].phy_ao.dvs_b[1].b0_dq6}, + {&ch[chn].phy_ao.misc_stbcal1}, + {&ch[chn].phy_ao.misc_stbcal2}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + pi_per_ui = 32; + ui_per_mck = 16; + if (get_div_mode(cali) == DIV4_MODE) + freq_div = 2; + else + freq_div = 4; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + best_win.dqsien_dly_mck[dqs] = params->gating_MCK[chn][rank][dqs]; + best_win.dqsien_dly_ui[dqs] = params->gating_UI[chn][rank][dqs]; + best_win.dqsien_dly_pi[dqs] = params->gating_PI[chn][rank][dqs]; + + /* Calculate P1 */ + best_win.dqsien_dly_ui_p1[dqs] = + best_win.dqsien_dly_mck[dqs] * ui_per_mck + + best_win.dqsien_dly_ui[dqs] + freq_div; + best_win.dqsien_dly_mck_p1[dqs] = + best_win.dqsien_dly_ui_p1[dqs] / ui_per_mck; + best_win.dqsien_dly_ui_p1[dqs] = + best_win.dqsien_dly_ui_p1[dqs] % ui_per_mck; + dramc_dbg("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", + chn, rank, dqs, best_win.dqsien_dly_mck[dqs], + best_win.dqsien_dly_ui[dqs], + best_win.dqsien_dly_pi[dqs]); + dramc_dbg("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", + chn, rank, dqs, best_win.dqsien_dly_mck_p1[dqs], + best_win.dqsien_dly_ui_p1[dqs], + best_win.dqsien_dly_pi_p1[dqs]); + } + + *tx_dly_min = rxdqs_gating_get_tx_dly_min(freq_group, &best_win); + *tx_dly_max = rxdqs_gating_get_tx_dly_max(freq_group, &best_win); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, best_win.dqsien_dly_mck[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, best_win.dqsien_dly_ui[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, best_win.dqsien_dly_mck_p1[0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, best_win.dqsien_dly_ui_p1[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, best_win.dqsien_dly_mck[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, best_win.dqsien_dly_ui[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, best_win.dqsien_dly_mck_p1[1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, best_win.dqsien_dly_ui_p1[1]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, best_win.dqsien_dly_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, best_win.dqsien_dly_pi[1]); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + dramc_phy_reset(chn); +} + +static void dramc_rx_dqs_gating_post_process_find_best_coarse( + const struct ddr_cali* cali, s8 change_dqs_inctl, u8 mck2ui_shift) +{ + u8 chn, rk; + u8 best_coarse_mck[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_ui[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_mck_P1[RANK_MAX][DQS_NUMBER]; + u8 best_coarse_ui_P1[RANK_MAX][DQS_NUMBER]; + u32 rank_sel_mck_p0[2], rank_sel_mck_p1[2]; + + chn = cali->chn; + for (rk = 0; rk < cali->support_ranks; rk++) { + best_coarse_mck[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + best_coarse_ui[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + best_coarse_mck_P1[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + best_coarse_ui_P1[rk][0] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + + best_coarse_mck[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + best_coarse_ui[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + best_coarse_mck_P1[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + best_coarse_ui_P1[rk][1] = + READ32_BITFIELD(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + } + + if (change_dqs_inctl != 0) { + for (rk = 0; rk < cali->support_ranks; rk++) { + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + u8 total_ui, total_ui_P1; + total_ui = (best_coarse_mck[rk][dqs] << 4) + + best_coarse_ui[rk][dqs]; + total_ui_P1 = (best_coarse_mck_P1[rk][dqs] << 4) + + best_coarse_ui_P1[rk][dqs]; + + total_ui += (change_dqs_inctl << mck2ui_shift); + total_ui_P1 += (change_dqs_inctl << mck2ui_shift); + + best_coarse_mck[rk][dqs] = (total_ui >> 4); + best_coarse_ui[rk][dqs] = total_ui & 0xf; + + best_coarse_mck_P1[rk][dqs] = (total_ui_P1 >> 4); + best_coarse_ui_P1[rk][dqs] = total_ui_P1 & 0xf; + dramc_dbg("best DQS%d dly(2T, 0.5T) = (%d, %d)\n", + dqs, best_coarse_mck[rk][dqs], + best_coarse_ui[rk][dqs]); + } + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_dbg("best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", + dqs, best_coarse_mck_P1[rk][dqs], + best_coarse_ui_P1[rk][dqs]); + } + + for (rk = 0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, + best_coarse_mck[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, + best_coarse_ui[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, + best_coarse_mck_P1[rk][0], + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, + best_coarse_ui_P1[rk][0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, + best_coarse_mck[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, + best_coarse_ui[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, + best_coarse_mck_P1[rk][1], + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, + best_coarse_ui_P1[rk][1]); + } + } + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + if (best_coarse_mck[RANK_0][dqs] > best_coarse_mck[RANK_1][dqs]) { + rank_sel_mck_p0[dqs] = (best_coarse_mck[RANK_0][dqs] > 0) ? + (best_coarse_mck[RANK_0][dqs] - 1) : 0; + rank_sel_mck_p1[dqs] = (best_coarse_mck_P1[RANK_0][dqs] > 0) ? + (best_coarse_mck_P1[RANK_0][dqs] - 1) : 0; + } else { + rank_sel_mck_p0[dqs] = (best_coarse_mck[RANK_1][dqs] > 0) ? + (best_coarse_mck[RANK_1][dqs] - 1) : 0; + rank_sel_mck_p1[dqs] = (best_coarse_mck_P1[RANK_1][dqs] > 0) ? + (best_coarse_mck_P1[RANK_1][dqs] - 1) : 0; + } + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_rank_selph_ui_dly, + SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, rank_sel_mck_p0[0], + SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, rank_sel_mck_p1[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_rank_selph_ui_dly, + SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, rank_sel_mck_p0[1], + SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, rank_sel_mck_p1[1]); +} + +void dramc_rx_dqs_gating_post_process(const struct ddr_cali* cali, + u8 tx_dly_min, u8 tx_dly_max) +{ + u8 chn, rank; + dram_freq_grp freq_group; + + u8 mck2ui_shift; + s8 change_dqs_inctl; + u16 phs_inctl = 0; + u32 read_dqs_inctl, rank_inctl_root, xrtr2r, tx_dly_dqs_gate_min = 0; + u32 rank_inctl_stb; + + chn = cali->chn; + rank = cali->rank; + freq_group = get_freq_group(cali); + + if (get_div_mode(cali) == DIV8_MODE) { + if (freq_group > DDRFREQ_1200) + tx_dly_dqs_gate_min = 2; + else + tx_dly_dqs_gate_min = 1; + mck2ui_shift = 3; + } else { + tx_dly_dqs_gate_min = 2; + mck2ui_shift = 2; + } + + change_dqs_inctl = tx_dly_dqs_gate_min - tx_dly_min; + dramc_dbg("[RxdqsGatingPostProcess] freq %d\n" + "ChangeDQSINCTL %d, tx_dly_dqs_gate_min %d, tx_dly_min %d\n", + get_frequency(cali), + change_dqs_inctl, tx_dly_dqs_gate_min, tx_dly_min); + + dramc_rx_dqs_gating_post_process_find_best_coarse(cali, change_dqs_inctl, mck2ui_shift); + + read_dqs_inctl = READ32_BITFIELD(&ch[chn].phy_ao.misc_rk[rank].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL); + read_dqs_inctl -= change_dqs_inctl; + rank_inctl_stb = (read_dqs_inctl > 2) ? (read_dqs_inctl - 2) : 0; + phs_inctl = (read_dqs_inctl == 0) ? 0 : (read_dqs_inctl - 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_STB, rank_inctl_stb); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + + if (read_dqs_inctl >= 2) + rank_inctl_root = read_dqs_inctl - 2; + else + rank_inctl_root = 0; + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, read_dqs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl_root); + xrtr2r = READ32_BITFIELD(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R); + dramc_dbg("TX_dly_DQSgated check: min %d max %d, ChangeDQSINCTL=%d\n", + tx_dly_min, tx_dly_max, change_dqs_inctl); + dramc_dbg("DQSINCTL=%d, RANKINCTL=%d, xrtr2r=%d\n", + read_dqs_inctl, rank_inctl_root, xrtr2r); +} + diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 2be3962..4b77c85 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -220,6 +220,7 @@ static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn) { + u8 txdly_min, txdly_max; u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]; cali->chn = chn; @@ -243,7 +244,12 @@ /* should disable the auto refresh before do write leveling */ dramc_auto_refresh_switch(chn, false); dramc_write_leveling(cali, dqs_final_delay); + + /* should enable the auto refresh before do RX and TX calibration */ + dramc_auto_refresh_switch(chn, true); + dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); } + dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I141abc1fdd283f4898d0772736bc777e87017561 Gerrit-Change-Number: 44718 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc rx window training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44719 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc rx window training ...................................................................... soc/mediatek/mt8192: Do dramc rx window training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I584db990a9777551bcf3d4d59cdd3fd64d6e52cc --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 264 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44719/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 8d65a67..363a3bd 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -27,6 +27,15 @@ u8 dqsien_dly_pi_p1[DQS_NUMBER]; }; +typedef struct { + s16 first_pass; + s16 last_pass; + s16 win_center; + u16 win_size; + u16 best_dqdly; +} pass_win_data_t; + + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -1695,3 +1704,255 @@ read_dqs_inctl, rank_inctl_root, xrtr2r); } + +static void dramc_set_rank_engin2(u8 chn, u8 rank) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a3, TEST2_A3_ADRDECEN_TARKMODE, 1); + SET32_BITFIELDS(&ch[chn].ao.test2_a4, TEST2_A4_TESTAGENTRKSEL, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a4, TEST2_A4_TESTAGENTRK, rank); +} + +static void dramc_engin2_set_ui_shift(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a0, + TEST2_A0_TA2_LOOP_EN, 1, + TEST2_A0_LOOP_CNT_INDEX, 3); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2_PAT_SHIFT, 1, + TEST2_A3_PAT_SHIFT_SW_EN, 0); +} + +static void dramc_engin2_set_pat(u8 chn, u8 rank, u8 loop_cnt) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a4, + TEST2_A4_TEST_REQ_LEN1, 1, + TEST2_A4_TESTAUDINIT, 0, + TEST2_A4_TESTAUDINC, 0, + TEST2_A4_TESTXTALKPAT, 0, + TEST2_A4_TESTSSOPAT, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TESTAUDPAT, 0, + TEST2_A3_AUTO_GEN_PAT, 1, + TEST2_A3_HFIDPAT, 1, + TEST2_A3_TEST_AID_EN, 1, + TEST2_A3_TESTCNT, loop_cnt); + SET32_BITFIELDS(&ch[chn].ao.test2_a2, TEST2_A2_TEST2_OFF, 0x56); + dramc_engin2_set_ui_shift(chn); +} + +static void dramc_engine2_init(u8 chn, u8 rank) +{ + u32 test2_1 = 0x55000000; + u32 test2_2 = 0xaa000100; + + dramc_set_rank_engin2(chn, rank); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, + DUMMY_RD_DQSG_DMYRD_EN, 0, + DUMMY_RD_DQSG_DMYWR_EN, 0, + DUMMY_RD_DUMMY_RD_EN, 0, + DUMMY_RD_SREF_DMYRD_EN, 0, + DUMMY_RD_DMY_RD_DBG, 0, + DUMMY_RD_DMY_WR_DBG, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + SET32_BITFIELDS(&ch[chn].ao.test2_a0, + TEST2_A0_TEST2_PAT0, test2_1 >> 24, + TEST2_A0_TEST2_PAT1, test2_2 >> 24); + SET32_BITFIELDS(&ch[chn].ao.rk[rank].rk_test2_a1, + RK_TEST2_A1_TEST2_BASE, (test2_1 + 0x10000) & 0x00ffffff); + SET32_BITFIELDS(&ch[chn].ao.test2_a2, TEST2_A2_TEST2_OFF, test2_2 & 0x00ffffff); + + dramc_engin2_set_pat(chn, rank, 0); +} + +static const u8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = +{ + [PINMUX_DSC] = { + [CHANNEL_A] = { 0, 1, 6, 7, 4, 5, 3, 2, 9, 8, 11, 10, 15, 14, 12, 13}, + [CHANNEL_B] = { 1, 0, 5, 4, 7, 2, 3, 6, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5, 8, 9, 10, 12, 15, 14, 11, 13}, + [CHANNEL_B] = {0, 1, 7, 4, 2, 5, 6, 3, 9, 8, 10, 12, 11, 14, 13, 15}, + } +}; + +static void rddqc_pinmux_set(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 pinmux = get_pinmux_type(cali); + + const u8 *pinmux_map = uiLPDDR4_RDDQC_Mapping_POP[pinmux][chn]; + + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, pinmux_map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, pinmux_map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, pinmux_map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, pinmux_map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, pinmux_map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, pinmux_map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, pinmux_map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, pinmux_map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, pinmux_map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, pinmux_map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, pinmux_map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, pinmux_map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, pinmux_map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, pinmux_map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, pinmux_map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, pinmux_map[15]); +} + +static void dramc_rx_rddqc_init(const struct ddr_cali* cali) +{ + u8 rddqc_bit_ctrl_lower = 0x55; + u8 rddqc_bit_ctrl_upper = 0x55; + u8 rddqc_patternA = 0x5A; + u8 rddqc_patternB = 0x3C; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0); + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + rddqc_pinmux_set(cali); + dramc_mode_reg_write_by_rank(cali, chn, rank, 15, rddqc_bit_ctrl_lower); + dramc_mode_reg_write_by_rank(cali, chn, rank, 20, rddqc_bit_ctrl_upper); + dramc_mode_reg_write_by_rank(cali, chn, rank, 32, rddqc_patternA); + dramc_mode_reg_write_by_rank(cali, chn, rank, 40, rddqc_patternB); + + SET32_BITFIELDS(&ch[chn].ao.rddqcgolden, + RDDQCGOLDEN_MR15_GOLDEN, rddqc_bit_ctrl_lower, + RDDQCGOLDEN_MR20_GOLDEN, rddqc_bit_ctrl_upper, + RDDQCGOLDEN_MR32_GOLDEN, rddqc_patternA, + RDDQCGOLDEN_MR40_GOLDEN, rddqc_patternB); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1); +} +void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type cali_type) +{ + u8 chn, rank, fsp; + dram_odt_state odt; + dram_freq_grp freq_group = cali->freq_group; + const struct sdram_params *params = cali->params; + + u8 bit, byte; + bool enable_vref_scan = false; + u16 final_vref[DQS_NUMBER] = {0xe, 0xe}; + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH]; + s32 dqs_dly_perbyte[DQS_NUMBER] = {0x0}, dqm_dly_perbyte[DQS_NUMBER] = {0x0}; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + odt = get_odt_state(cali); + dramc_dbg("RX window ch:%d, rank:%d, freq_group:%d, type:%d\n", + chn, rank, freq_group, cali_type); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.mrr_bit_mux1}, + {&ch[chn].ao.mrr_bit_mux2}, + {&ch[chn].ao.mrr_bit_mux3}, + {&ch[chn].ao.mrr_bit_mux4}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + dramc_auto_refresh_switch(chn, false); + + if (cali_type == RX_WIN_TEST_ENG) { + dramc_engine2_init(chn, rank); + + if ((rank == RANK_0) || (freq_group == DDRFREQ_2133)) + enable_vref_scan = true; + } else { + dramc_rx_rddqc_init(cali); + } + + if (enable_vref_scan) { + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + } + + for (byte = 0; byte < BYTE_NUM; byte++) { + if (enable_vref_scan) + final_vref[byte] = params->rx_best_vref[chn][rank][byte]; + + dqs_dly_perbyte[byte] = params->rx_perbit_dqs[chn][rank][byte]; + dqm_dly_perbyte[byte] = params->rx_perbit_dqm[chn][rank][byte]; + } + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) + final_win_perbit[bit].best_dqdly = params->rx_perbit_dq[chn][rank][bit]; + + if (enable_vref_scan) { + for (u8 rk = rank; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, final_vref[0], + RG_RX_ARDQ_VREF_SEL_UB_B0, final_vref[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, final_vref[1], + RG_RX_ARDQ_VREF_SEL_UB_B1, final_vref[1]); + + for (byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg("Final RX Vref Byte %d = %d to rank%d\n", + byte, final_vref[byte], rk); + } + } + } + + /* set dqs delay, (dqm delay) */ + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, dqs_dly_perbyte[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, dqm_dly_perbyte[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, dqs_dly_perbyte[1]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, dqm_dly_perbyte[1]); + + /* set dq delay */ + for (bit = 0; bit < DQS_BIT_NUMBER; bit += 2) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_rxdly0 + bit / 2, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, final_win_perbit[bit].best_dqdly, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, final_win_perbit[bit + 1].best_dqdly); + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_rxdly0 + bit / 2, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, final_win_perbit[bit + 8].best_dqdly, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, final_win_perbit[bit + 9].best_dqdly); + } + + dramc_phy_reset(chn); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + dramc_dbg("DQS Delay:\nDQS0 = %d, DQS1 = %d\n" + "DQM Delay:\nDQM0 = %d, DQM1 = %d\n", + dqs_dly_perbyte[0], dqs_dly_perbyte[1], + dqm_dly_perbyte[0], dqm_dly_perbyte[1]); + + dramc_dbg("DQ Delay:\n"); + for (bit = 0; bit < DQ_DATA_WIDTH; bit = bit + 4) + dramc_dbg("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", + bit, final_win_perbit[bit].best_dqdly, + bit + 1, final_win_perbit[bit + 1].best_dqdly, + bit + 2, final_win_perbit[bit + 2].best_dqdly, + bit + 3, final_win_perbit[bit + 3].best_dqdly); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 4b77c85..41d85a2 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -248,6 +248,9 @@ /* should enable the auto refresh before do RX and TX calibration */ dramc_auto_refresh_switch(chn, true); dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); + + dramc_rx_window_perbit_cal(cali, RX_WIN_RD_DQC); + dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584db990a9777551bcf3d4d59cdd3fd64d6e52cc Gerrit-Change-Number: 44719 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc command bus training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44716 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc command bus training ...................................................................... soc/mediatek/mt8192: Do dramc command bus training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I06ee26e3b82811bffa09ab5e3e535b3174c3e3a6 --- M src/soc/mediatek/mt8192/dramc_dvfs.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 4 files changed, 761 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44716/1 diff --git a/src/soc/mediatek/mt8192/dramc_dvfs.c b/src/soc/mediatek/mt8192/dramc_dvfs.c index 67e2340..c51c261 100644 --- a/src/soc/mediatek/mt8192/dramc_dvfs.c +++ b/src/soc/mediatek/mt8192/dramc_dvfs.c @@ -193,3 +193,19 @@ MISC_SRAM_DMA0_SW_MODE, 0); } } + +void shuffle_dfs_to_fsp1(const struct ddr_cali* cali) +{ + u8 operating_fsp = cali->fsp; + struct mr_values *mr_value = cali->mr_value; + + /* Double confirm PLL switched from CLRPLL to PHYPLL */ + if (operating_fsp == FSP_1) { + for (u8 rk = 0; rk < cali->support_ranks; rk++) { + u8 mr13 = mr_value->mr13[rk]; + mr13 |= (BIT(6) | BIT(7)); + mr_value->mr13[rk] = mr13; + } + cbt_switch_freq(cali, CBT_HIGH_FREQ); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 8362c05..84acb3e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -111,6 +111,26 @@ set_dqO1_pinmux_mapping(cali); } +u8 get_cbt_vref_pinmux_value(const struct ddr_cali* cali, u8 range, u8 vref_lev) +{ + u8 chn = cali->chn; + u8 vref_bit, vref_org; + u8 vref_new = 0; + const u8 *map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + return ((range & 0x1) << 6) | (vref_lev & 0x3f); + + vref_org = ((range & 0x1) << 6) | (vref_lev & 0x3f); + + for (vref_bit = 0; vref_bit < 8; vref_bit++) + if (vref_org & (1 << vref_bit)) + vref_new |= (1 << map[vref_bit]); + + dramc_dbg("=== vref_new: 0x%x --> 0x%x\n", vref_org, vref_new); + return vref_new; +} + static void dramc_init_default_mr_value(const struct ddr_cali *cali) { struct mr_values *mr_value = cali->mr_value; diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index e1f3d67..e531de0 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -5,6 +5,19 @@ #include <soc/dramc_register.h> #include <timer.h> +static const u8 ca_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][CA_NUM_LP4] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {1, 4, 5, 3, 2, 0}, + [CHANNEL_B] = {3, 5, 0, 2, 4, 1}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {2, 4, 3, 5, 1, 0}, + [CHANNEL_B] = {4, 5, 2, 0, 3, 1} + }, +}; + static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, @@ -580,6 +593,710 @@ write32(regs_bak[i].addr, regs_bak[i].value); } +static void ca_training_set_perbit_delay_cell(const struct ddr_cali* cali, + u8 chn, u8 rank, u8 *ca_center) +{ + u8 ca_prebit_delay[DQS_BIT_NUMBER] = {0}; + const u8 *ca_mapping = ca_pinmux_mapping[get_pinmux_type(cali)][chn]; + + for (u8 u1CA = 0;u1CA < CA_NUM_LP4;u1CA++) { + ca_prebit_delay[ca_mapping[u1CA]] = ca_center[u1CA]; + dramc_dbg("CA_PerBit_DelayLine[%d]= %d\n", + ca_mapping[u1CA], ca_prebit_delay[ca_mapping[u1CA]]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, ca_prebit_delay[0], + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, ca_prebit_delay[1], + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, ca_prebit_delay[2], + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, ca_prebit_delay[3]); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rank].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, ca_prebit_delay[4], + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, ca_prebit_delay[5], + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, ca_prebit_delay[6], + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, ca_prebit_delay[7]); +} + +static u32 get_ca_ui(u8 chn) +{ + u32 dly = read32(&ch[chn].ao.shu_selph_ca7); + return dly & 0x0FFFFFFFU; +} + +static void put_ca_ui(u8 chn, u32 ca_ui) +{ + u32 dly; + + dly = read32(&ch[chn].ao.shu_selph_ca7); + dly &= 0xF0000000U; + ca_ui &= 0x0FFFFFFFU; + dly |= ca_ui; + + write32(&ch[chn].ao.shu_selph_ca7, dly); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CKE, ca_ui & 0xF); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, SHU_SELPH_CA6_DLY_CKE1, ca_ui & 0xF); +} + +static void put_ca_mck(u8 chn, u32 ca_mck) +{ + u32 dly; + + dly = read32(&ch[chn].ao.shu_selph_ca3); + dly &= 0xF0000000U; + ca_mck &= 0x0FFFFFFFU; + dly |= ca_mck; + + write32(&ch[chn].ao.shu_selph_ca3, dly); +} + +static u32 get_cs_ui(u8 chn, u8 rank) +{ + if (rank == RANK_1) + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS1); + else + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS); +} + +static u32 get_cs_mck(u8 chn, u8 rank) +{ + if (rank == RANK_1) + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS1); + else + return READ32_BITFIELD(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS); +} + +static int get_capi_max(dram_freq_grp freq_group) +{ + if (freq_group == DDRFREQ_400) + return 32; + + return 64; +} + +static u8 get_ca_pi_per_ui(void) +{ + return 32; +} + +static u8 get_mck_ck_ratio(u8 chn) +{ + u32 ratio = READ32_BITFIELD(&ch[chn].ao.shu_lp5_cmd, SHU_LP5_CMD_LP5_CMD1TO2EN); + + dramc_dbg("MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2"); + return ratio; +} + +static u8 get_cbtui_adjustable_maxvalue(u8 chn) +{ + u8 ratio = get_mck_ck_ratio(chn); + return ratio == 1 ? 1 : 3; +} + +static void put_cs_ui(u8 chn, u8 rank, u32 cs_ui) +{ + if (rank == RANK_1) + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS1, cs_ui); + else + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, SHU_SELPH_CA5_DLY_CS, cs_ui); +} + +static void put_cs_mck(u8 chn, u8 rank, u32 cs_ui) +{ + if (rank == RANK_1) + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS1, cs_ui); + else + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca1, SHU_SELPH_CA1_TXDLY_CS, cs_ui); +} + +static u32 get_ca_mck(u8 chn) +{ + u32 dly = read32(&ch[chn].ao.shu_selph_ca3); + return dly & 0x0FFFFFFFU; +} + +static void xlate_ca_mck_ui(u8 chn, u32 ui_delta, + u32 mck_old, u32 ui_old, u32 *mck_new, u32 *ui_new) +{ + u8 i; + u32 mask, max; + u32 bit_ui, bit_mck; + u32 ui_tmp = 0, mck_tmp = 0; + + max = get_cbtui_adjustable_maxvalue(chn); + mask = max; + + for (i = 0; i < 7; i++) { + bit_mck = 0; + bit_ui = ((ui_old >> (i * 4)) & mask) + ui_delta; + if (bit_ui > max) { + bit_mck = bit_ui / (max + 1); + bit_ui = bit_ui % (max + 1); + } + + mck_tmp += (bit_mck << (i * 4)); + ui_tmp += (bit_ui << (i * 4)); + } + + if (ui_new) + *ui_new = ui_tmp; + + if (mck_new) + *mck_new = mck_old + mck_tmp; +} + +static s16 adjust_cs_ui(const struct ddr_cali* cali, u32 cs_mck, u32 cs_ui, s16 pi_dly) +{ + u8 ratio; + s16 p2u,ui = 0, pi = 0; + u32 ui_max, cs_bit_mask, cs_ui_tmp, cs_mck_tmp; + dram_freq_grp freq_group = get_freq_group(cali); + + u8 chn = cali->chn; + u8 rank = cali->rank; + dramc_dbg("pi_dly:%d, get_capi_max:%d\n", pi_dly, get_capi_max(freq_group)); + + if (pi_dly < get_capi_max(freq_group)) + return pi_dly; + + p2u = get_ca_pi_per_ui(); + + ui = pi_dly / p2u; + pi = pi_dly % p2u; + + ratio = get_mck_ck_ratio(chn); + if (ratio) + /* 1:1 */ + cs_bit_mask = 1; + else + /* 1:2 */ + cs_bit_mask = 3; + + ui_max = get_cbtui_adjustable_maxvalue(chn); + cs_ui_tmp = (cs_ui & cs_bit_mask) + ui; + cs_mck_tmp = 0; + if (cs_ui_tmp > ui_max) { + cs_mck_tmp = cs_ui_tmp / (ui_max + 1); + cs_ui_tmp = cs_ui_tmp % (ui_max + 1); + } + + cs_mck_tmp += cs_mck; + put_cs_ui(chn, rank, cs_ui_tmp); + put_cs_mck(chn, rank, cs_mck_tmp); + + return pi; +} + +static s8 adjust_ca_ui(const struct ddr_cali* cali, u32 ca_mck, u32 ca_ui, s16 pi_dly) +{ + s16 p2u; + s16 ui, pi; + u32 ui_new = 0, mck_new = 0; + dram_freq_grp freq_group = get_freq_group(cali); + + u8 chn = cali->chn; + if (pi_dly < get_capi_max(freq_group)) + return pi_dly; + + p2u = get_ca_pi_per_ui(); + ui = pi_dly / p2u; + pi = pi_dly % p2u; + xlate_ca_mck_ui(chn, ui, ca_mck, ca_ui, &mck_new, &ui_new); + + put_ca_ui(chn, ui_new); + put_ca_mck(chn, mck_new); + dramc_dbg("mck_new: %#x, ui_new: %#x, pi:%d\n", mck_new, ui_new, pi); + + return pi; +} + +static void cbt_set_ca_clk_result(const struct ddr_cali* cali, u32 mck, u32 ui) +{ + s8 final_ca_clk; + u8 chn, rank; + u8 ca_center[DQS_BIT_NUMBER] = {0}; + + chn = cali->chn; + rank = cali->rank; + const struct sdram_params *params = cali->params; + s8 cmd_dly = params->cbt_cmd_dly[chn][rank]; + + for (u8 ca = 0; ca < CA_NUM_LP4; ca++) { + ca_center[ca] = params->cbt_ca_prebit_dly[chn][rank][ca]; + dramc_dbg("ca_center[%d]= %d\n", ca, ca_center[ca]); + } + + final_ca_clk = cmd_dly; + dramc_dbg("CA Dly = %d\n", final_ca_clk); + + final_ca_clk = adjust_ca_ui(cali, mck, ui, final_ca_clk); + dramc_dbg("after adjust, CA Dly = %d\n", final_ca_clk); + for (u8 rk = RANK_0; rk <= rank; rk++) { + cbt_delay_ca_clk(chn, rk, final_ca_clk); + ca_training_set_perbit_delay_cell(cali, chn, rk, ca_center); + } +} + +static void cbt_adjust_cs(const struct ddr_cali* cali) +{ + u8 chn, rank, cs_dly[RANK_MAX]; + u8 cs_final_delay; + u32 pi_dly; + u32 cs_ui, cs_mck; + + const struct sdram_params *params = cali->params; + chn = cali->chn; + rank = cali->rank; + cs_dly[RANK_0] = params->cbt_cs_dly[chn][RANK_0]; + cs_dly[RANK_1] = params->cbt_cs_dly[chn][RANK_1]; + + cs_ui = get_cs_ui(chn, rank); + cs_mck = get_cs_mck(chn, rank); + + if (rank == RANK_0) + cs_final_delay = cs_dly[RANK_0]; + else + cs_final_delay = (cs_dly[RANK_0] + cs_dly[RANK_1]) >> 1; + + for (u8 rk = RANK_0; rk <= rank; rk++) { + pi_dly = adjust_cs_ui(cali, cs_mck, cs_ui, cs_final_delay); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_ARPI_CS, pi_dly); + } + + dramc_dbg("CS Dly: %d\n", cs_final_delay); +} + +static void set_dram_mr_cbt_on_off(const struct ddr_cali* cali, o1_state o1) +{ + u8 chn, rank, fsp; + struct mr_values *mr_value = cali->mr_value; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + u8 mr13 = mr_value->mr13[rank] & (~ BIT(0)) & (~ BIT(6)) & (~ BIT(7)) ; + + if (o1 == O1_ON) { + if (fsp == FSP_1) + mr13 |= BIT(0) | BIT(6); + else + mr13 |= BIT(0) | BIT(7); + + if (get_cbt_mode(cali) == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_BYTEMODECBTEN, 1, + CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 1); + } else { + if (fsp == FSP_1) + mr13 |= BIT(6); + } + + dramc_mode_reg_write_by_rank(cali, chn, rank, 13, mr13); + mr_value->mr13[rank] = mr13; +} + +void o1_path_on_off(const struct ddr_cali* cali, o1_state o1) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 vref_sel = 0x37; + + if (o1 == O1_ON) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_vref, + SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_vref, + SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B0, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B0, vref_sel); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel, + RG_RX_ARDQ_VREF_SEL_LB_B1, vref_sel, + RG_RX_ARDQ_VREF_SEL_UB_B1, vref_sel); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, o1, + B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, o1, + B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_phy3, + B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_phy3, + B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, o1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, (o1 << 1) | o1); + + udelay(1); +} + +static void dramc_mode_reg_ca_term(const struct ddr_cali* cali, u8 do_term) +{ + + u8 chn = cali->chn; + u8 fsp = get_fsp(cali); + u8 mr11, mr13, mr22; + struct mr_values *mr_value = cali->mr_value; + static u8 state_do_term[CHANNEL_MAX] = {0}; + + if (state_do_term[chn] == do_term) + return; + + state_do_term[chn] = do_term; + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + mr11 = 0x3; + if (get_cbt_mode(cali) == CBT_NORMAL_MODE) + mr11 |= 0x40; + else + mr11 |= 0x20; + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + mr13 = mr_value->mr13[rk] & (~ BIT(6)) & (~ BIT(7)); + mr13 |= BIT(6); + dramc_mode_reg_write_by_rank(cali, chn, rk, 13, mr13); + mr_value->mr13[rk] = mr13; + + dramc_mode_reg_write_by_rank(cali, chn, rk, 11, mr11); + mr_value->mr11[fsp] = mr11; + + if (do_term) { + mr22 = 0x4; + } else { + if (rk == RANK_0) + mr22 = 0x4; + else + mr22 = 0x2c; + } + + dramc_mode_reg_write_by_rank(cali, chn, rk, 22, mr22); + mr_value->mr22[fsp] = mr22; + } + + dramc_set_broadcast(bc_bak); +} + +static void cbt_entry(const struct ddr_cali* cali) +{ + u8 chn, rank, fsp; + u8 mr13, dram_dq_b0 = 0; + struct mr_values *mr_value = cali->mr_value; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + mr13 = mr_value->mr13[rank]; + + if (fsp == FSP_1) + dramc_mode_reg_ca_term(cali, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0); + + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + + set_dram_mr_cbt_on_off(cali, true); + + if (get_cbt_mode(cali) == CBT_NORMAL_MODE) { + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_DQSOEAOEN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 1 << dram_dq_b0); + } + + udelay(1); + cke_fix_onoff(cali, chn, rank, CKE_FIXOFF); + + if (fsp == FSP_1) + mr13 |= BIT(7); + else + mr13 &= (~ BIT(7)); + mr_value->mr13[rank] = mr13; + + o1_path_on_off(cali, O1_ON); + + udelay(1); +} + +static void cbt_exit(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 cbt_mode = get_cbt_mode(cali); + + if (cbt_mode == CBT_NORMAL_MODE || cbt_mode == CBT_BYTE_MODE1) { + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + udelay(1); + set_dram_mr_cbt_on_off(cali, false); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 0); + } + + o1_path_on_off(cali, O1_OFF); + if (cbt_mode == CBT_BYTE_MODE1) + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_BYTEMODECBTEN, 0, + CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 0); + + udelay(1); +} + +static void cbt_entry_top(const struct ddr_cali* cali) +{ + u8 chn, fsp; + + chn = cali->chn; + fsp = get_fsp(cali); + + if(fsp == FSP_1) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + cbt_switch_freq(cali, CBT_LOW_FREQ); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + } + cbt_entry(cali); + + if(fsp == FSP_1) + cbt_switch_freq(cali, CBT_HIGH_FREQ); +} + +static void cbt_exit_top(const struct ddr_cali* cali, cbt_state state) +{ + if (state == OUT_CBT || get_cbt_mode(cali) == CBT_BYTE_MODE1){ + if (get_fsp(cali) == FSP_1) + cbt_switch_freq(cali, CBT_LOW_FREQ); + cbt_exit(cali); + } +} + +static void cbt_set_vref(const struct ddr_cali* cali, cbt_state state) +{ + u8 chn, rank, fsp, range; + u8 dram_dq_b0 = 0; + u8 vref_value_pinmux; + u8 ca_vref, mr12, mr13; + struct mr_values *mr_value = cali->mr_value; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + ca_vref = params->cbt_final_vref[chn][rank]; + mr12 = mr_value->mr12[chn][rank][fsp]; + range = mr12 >> 6; + + if (state == IN_CBT && get_cbt_mode(cali) == CBT_NORMAL_MODE) { + vref_value_pinmux = get_cbt_vref_pinmux_value(cali, range, ca_vref); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl4, + CBT_WLEV_CTRL4_CBT_TXDQ_B0, vref_value_pinmux); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 0x1 << dram_dq_b0); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl3, + CBT_WLEV_CTRL3_DQSBX_G, 0xa); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 0); + } else { + if (fsp == FSP_1) { + mr13 = mr_value->mr13[rank] | (0x1 << 6); + dramc_mode_reg_write_by_rank(cali, chn, rank, 13, mr13); + mr_value->mr13[rank] = mr13; + } + + dramc_dbg("CmdBusTraining Vref(ca) range %d: %d\n", range, ca_vref); + + ca_vref = ((range & 0x1) << 6) | (ca_vref & 0x3f); + dramc_mode_reg_write_by_rank(cali, chn, rank, 12, ca_vref); + mr_value->mr12[chn][rank][fsp] = ca_vref; + } + udelay(1); +} + +static void cbt_set_best_vref(const struct ddr_cali* cali, cbt_state state) +{ + u8 fsp = get_fsp(cali); + + if (state == IN_CBT && get_cbt_mode(cali) == CBT_BYTE_MODE1) { + if (fsp == FSP_1) + cbt_switch_freq(cali, CBT_LOW_FREQ); + + cbt_exit(cali); + cbt_set_vref(cali, state); + cbt_entry(cali); + if (fsp == FSP_1) + cbt_switch_freq(cali, CBT_HIGH_FREQ); + } else { + cbt_set_vref(cali, state); + } +} + +static void set_cbt_wlev_intv(u8 chn, dram_freq_grp freq_group) +{ + u8 tcmdo1lat; + u8 catrain_intv; + u8 new_cbt_pat_intv; + u8 wlev_dqspat_lat; + + switch (freq_group) { + case DDRFREQ_400: + tcmdo1lat = 12; + catrain_intv = 13; + new_cbt_pat_intv = 12; + wlev_dqspat_lat = 12; + break; + case DDRFREQ_600: + tcmdo1lat = 9; + catrain_intv = 8; + new_cbt_pat_intv = 11; + wlev_dqspat_lat = 11; + break; + case DDRFREQ_800: + tcmdo1lat = 10; + catrain_intv = 8; + new_cbt_pat_intv = 12; + wlev_dqspat_lat = 12; + break; + case DDRFREQ_933: + tcmdo1lat = 11; + catrain_intv = 9; + new_cbt_pat_intv = 13; + wlev_dqspat_lat = 13; + break; + case DDRFREQ_1200: + tcmdo1lat = 12; + catrain_intv = 9; + new_cbt_pat_intv = 14; + wlev_dqspat_lat = 14; + break; + case DDRFREQ_1600: + tcmdo1lat = 14; + catrain_intv = 11; + new_cbt_pat_intv = 16; + wlev_dqspat_lat = 16; + break; + case DDRFREQ_2133: + tcmdo1lat = 17; + catrain_intv = 14; + new_cbt_pat_intv = 19; + wlev_dqspat_lat = 19; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl1, + CBT_WLEV_CTRL1_TCMDO1LAT, tcmdo1lat, + CBT_WLEV_CTRL1_CATRAIN_INTV, catrain_intv); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl5, + CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, new_cbt_pat_intv); + SET32_BITFIELDS(&ch[chn].ao.cbt_wlev_ctrl0, + CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, wlev_dqspat_lat); +} + +static void dramc_cmd_ui_delay_setting(u8 chn, u8 value) +{ + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca7, + SHU_SELPH_CA7_DLY_RA0, value, + SHU_SELPH_CA7_DLY_RA1, value, + SHU_SELPH_CA7_DLY_RA2, value, + SHU_SELPH_CA7_DLY_RA3, value, + SHU_SELPH_CA7_DLY_RA4, value, + SHU_SELPH_CA7_DLY_RA5, value, + SHU_SELPH_CA7_DLY_RA6, value); + + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca5, + SHU_SELPH_CA5_DLY_CKE, value); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_ca6, + SHU_SELPH_CA6_DLY_CKE1, value); +} + +void dramc_cmd_bus_training(const struct ddr_cali* cali) +{ + u8 chn, rank, fsp; + u32 ca_ui, ca_mck; + u8 ca_final_center[CA_NUM_LP4] = {0}; + + chn = cali->chn; + rank = cali->rank; + fsp = get_fsp(cali); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].phy_ao.misc_stbcal}, + {&ch[chn].ao.ckectrl}, + {&ch[chn].phy_ao.dvs_b[0].b0_dq2}, + {&ch[chn].phy_ao.dvs_b[1].b0_dq2}, + {&ch[chn].ao.cbt_wlev_ctrl0}, + {&ch[chn].ao.cbt_wlev_ctrl1}, + {&ch[chn].ao.cbt_wlev_ctrl2}, + {&ch[chn].ao.cbt_wlev_ctrl3}, + {&ch[chn].ao.cbt_wlev_ctrl4}, + {&ch[chn].ao.swcmd_ctrl0}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy_ao.byte[0].shu_b0_vref}, + {&ch[chn].phy_ao.byte[1].shu_b0_vref}, + {&ch[chn].phy_ao.byte[0].rk[rank].shu_b0_phy_vref_sel}, + {&ch[chn].phy_ao.byte[1].rk[rank].shu_b0_phy_vref_sel}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + ca_training_set_perbit_delay_cell(cali, chn, rank, ca_final_center); + dramc_cmd_ui_delay_setting(chn, 1); + cbt_delay_ca_clk(chn, rank, 0); + + ca_mck = get_ca_mck(chn); + dramc_auto_refresh_switch(chn, false); + + set_cbt_wlev_intv(chn, get_freq_group(cali)); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, rank); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_DCMEN2, 0, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 1, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0, + DRAMC_PD_CTRL_COMBCLKCTRL, 0, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1, + DRAMC_PD_CTRL_TCKFIXON, 1); + + cbt_entry_top(cali); + cbt_set_best_vref(cali, IN_CBT); + dramc_cmd_UI_delay_setting(chn, 0); + ca_ui = get_ca_ui(chn); + + put_ca_ui(chn, ca_ui); + cbt_set_ca_clk_result(cali, ca_mck, ca_ui); + udelay(1); + + cbt_adjust_cs(cali); + cbt_exit_top(cali, OUT_CBT); + cbt_set_best_vref(cali, OUT_CBT); + + if (fsp == FSP_1) + dramc_mode_reg_ca_term(cali, 0); + + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANK, 0); + SET32_BITFIELDS(&ch[chn].ao.tx_set0, TX_SET0_TXRANKFIX, 0); + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + +} + static void duty_delay_reg_convert(s8 duty_delay, u8 *delay) { u8 delay_tmp; @@ -615,7 +1332,6 @@ } } - static void dramc_duty_set_wck_delay_cell(u8 chn, const s8* duty_delay) { u8 dqs; diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 11ec636..214bf55 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -225,6 +225,14 @@ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) { + cali->rank = rank; + dramc_auto_refresh_switch(chn, false); + dramc_cmd_bus_training(cali); + } + + shuffle_dfs_to_fsp1(cali); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ee26e3b82811bffa09ab5e3e535b3174c3e3a6 Gerrit-Change-Number: 44716 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc rx datlat training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44721 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc rx datlat training ...................................................................... soc/mediatek/mt8192: Do dramc rx datlat training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I9a426e1273dceae3a739bbbfc36db44d3ba9140d --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44721/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 602e61d..9ccedf1 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -1408,6 +1408,36 @@ dramc_set_broadcast(bc_bak); } +static void dramc_dle_factor_handler(u8 chn, u8 value) +{ + u8 datlat_dsel = 0, dlecg_ext1 = 0, dlecg_ext2 = 0, dlecg_ext3 = 0; + + if (READ32_BITFIELD(&ch[chn].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = value; + else + datlat_dsel = (value < 1) ? value : value - 1; + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, value, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + + dlecg_ext1 = (value >= 8) ? 1 : 0; + dlecg_ext2 = (value >= 14) ? 1 : 0; + dlecg_ext3 = (value >= 19) ? 1 : 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_READ_START_EXTEND1, dlecg_ext1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, dlecg_ext1, + SHU_RX_CG_SET0_READ_START_EXTEND2, dlecg_ext2, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, dlecg_ext2, + SHU_RX_CG_SET0_READ_START_EXTEND3, dlecg_ext3, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, dlecg_ext3); + + dramc_phy_reset(chn); +} + static u8 rxdqs_gating_get_tx_dly_min(dram_freq_grp freq_group, struct rxdqs_gating_best_win *rxdqs_best_win) { @@ -2713,3 +2743,25 @@ update_tx_tracking(chn, rk, cali_type, dq_pi, dqm_pi); } } + +void dramc_rx_datlat_cal(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 datlat = cali->params->rx_datlat[chn][rank]; + dramc_dbg("best_step = %d\n", datlat); + + dramc_engine2_init(chn, rank); + dramc_dle_factor_handler(chn, datlat); +} + +void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 datlat_1 = cali->params->rx_datlat[chn][0]; + u8 datlat_2 = cali->params->rx_datlat[chn][1]; + u8 final_datlat = MAX(datlat_1, datlat_2); + + dramc_dle_factor_handler(chn, final_datlat); +} + diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index f724e54..9df4285 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -287,9 +287,11 @@ switch_write_dbi_settings(cali, DBI_OFF); } + dramc_rx_datlat_cal(cali); dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); + dramc_dual_rank_rx_datlat_cal(cali); } static void dramc_calibration_all_channels(struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a426e1273dceae3a739bbbfc36db44d3ba9140d Gerrit-Change-Number: 44721 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc txoe training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44722 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc txoe training ...................................................................... soc/mediatek/mt8192: Do dramc txoe training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I72ae272d145f3b4aaa1076f1fec3b8b1384d4293 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44722/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 9ccedf1..ce03db4 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -2744,6 +2744,35 @@ } } +void dramc_tx_oe_calibration(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + const struct sdram_params *params = cali->params; + u8 large[DQS_NUMBER], small[DQS_NUMBER]; + + if (cali->freq_group < DDRFREQ_1600) + return; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + large[byte] = params->tx_oe_dq_mck[chn][rank][byte]; + small[byte] = params->tx_oe_dq_ui[chn][rank][byte]; + } + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, large[0], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, large[1]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, large[0], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, large[1]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, small[0], + SHURK_SELPH_DQ2_DLY_OEN_DQ1, small[1]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, small[0], + SHURK_SELPH_DQ3_DLY_OEN_DQM1, small[1]); +} + void dramc_rx_datlat_cal(const struct ddr_cali* cali) { u8 chn = cali->chn; diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 9df4285..052b320 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -30,7 +30,7 @@ dramc_write_shift_mck_write_DBI(cali, tx_shift); mr03 = (mr03 & ~(0x1 << 7)) | (dbi_state << 7); - dramc_mode_reg_write_by_rank(chn, rank, 3, mr03); + dramc_mode_reg_write_by_rank(cali, chn, rank, 3, mr03); mr_value->mr03[get_fsp(cali)] = mr03; dramc_write_dbi_onoff(dbi_state); @@ -289,6 +289,7 @@ dramc_rx_datlat_cal(cali); dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); + dramc_tx_oe_calibration(cali); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); dramc_dual_rank_rx_datlat_cal(cali); -- To view, visit https://review.coreboot.org/c/coreboot/+/44722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72ae272d145f3b4aaa1076f1fec3b8b1384d4293 Gerrit-Change-Number: 44722 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/mediatek/mt8192: set dramc dqsosc shuffle setting
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44723 to review the following change. Change subject: soc/mediatek/mt8192: set dramc dqsosc shuffle setting ...................................................................... soc/mediatek/mt8192: set dramc dqsosc shuffle setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Icf638f4d88a10ce451d63ea431facb2899b2be85 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 225 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44723/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index ce03db4..2082f4d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -2794,3 +2794,223 @@ dramc_dle_factor_handler(chn, final_datlat); } +static void dramc_start_dqsosc(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + const u32 timeout = 100; + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.swcmd_en}, + {&ch[chn].ao.swcmd_ctrl0}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, + }; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1); + + udelay(1); + cke_fix_onoff(cali, chn, RANK_MAX, CKE_FIXON); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_WCK2DQI_START_SWTRIG, 1); + + if (!wait_us(timeout, READ32_BITFIELD(&ch[chn].nao.spcmdresp3, + SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE))) { + dramc_err("ZQCAL Start fail (time out)\n"); + return; + } + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_WCK2DQI_START_SWTRIG, 0); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} + +static u16 dramc_dqsosc_auto(const struct ddr_cali* cali) +{ + u8 chn, rank; + u8 mr18, mr19, mr23; + u32 frequency; + + u16 dqs_cnt; + u16 dqsosc_cnt[RANK_MAX]; + u16 final_dqsosc; + + chn = cali->chn; + rank = cali->rank; + mr23 = cali->mr_value->mr23[chn][rank]; + frequency = get_frequency(cali); + + struct reg_bak regs_bak[] = { + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl} + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + dramc_mode_reg_write_by_rank(cali, chn, rank, 23, mr23); + SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0, SHU_DQSOSC_SET0_DQSOSCENDIS, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, DRAMC_PD_CTRL_TCKFIXON, 1); + + cke_fix_onoff(cali, chn, rank, CKE_FIXON); + dramc_start_dqsosc(cali); + udelay(1); + + mr18 = dramc_mode_reg_read_by_rank(chn, rank, 18); + mr19 = dramc_mode_reg_read_by_rank(chn, rank, 19); + + dqs_cnt = mr18 | (mr19 << 8); + if (dqs_cnt != 0) + dqsosc_cnt[0] = mr23 * 16 * 1000000 / (2 * dqs_cnt * frequency); + else + dqsosc_cnt[0] = 0; + + dqs_cnt = (mr18 >> 8) | (mr19 & 0xff00); + if (dqs_cnt != 0) + dqsosc_cnt[1] = mr23 * 16 * 1000000 / (2 * dqs_cnt * frequency); + else + dqsosc_cnt[1] = 0; + dramc_dbg("[DQSOSCAuto] RK%d, (LSB)MR18= %#x, (MSB)MR19= %#x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", + rank, mr18, mr19, dqsosc_cnt[0], dqsosc_cnt[1]); + + cali->mr_value->mr18[chn][rank] = mr18; + cali->mr_value->mr19[chn][rank] = mr19; + + if (dqsosc_cnt[1] != 0 && dqsosc_cnt[1] < dqsosc_cnt[0]) + final_dqsosc = dqsosc_cnt[1]; + else + final_dqsosc = dqsosc_cnt[0]; + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + + return final_dqsosc; +} + +void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali* cali, + u16 *dqsosc_thrd_inc, u16 *dqsosc_thrd_dec) +{ + u8 chn, rank; + u8 mr18, mr19, mr23; + u16 dqsosc_cnt[2], dqsosc; + u32 tCK; + + chn = cali->chn; + rank = cali->rank; + + dqsosc = dramc_dqsosc_auto(cali); + mr18 = cali->mr_value->mr18[chn][rank]; + mr19 = cali->mr_value->mr19[chn][rank]; + mr23 = cali->mr_value->mr23[chn][rank]; + + dqsosc_cnt[0] = mr18 | (mr19 << 8); + dqsosc_cnt[1] = (mr18 >> 8) | ((mr19 & 0xff00)); + + if ((get_cbt_mode(cali) == CBT_NORMAL_MODE) && (dqsosc_cnt[1] == 0)) + dqsosc_cnt[1] = dqsosc_cnt[0]; + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqsosc, + SHURK_DQSOSC_DQSOSC_BASE_RK0, dqsosc_cnt[0], + SHURK_DQSOSC_DQSOSC_BASE_RK0_B1, dqsosc_cnt[1]); + + tCK = 1000000 / get_frequency(cali); + if (dqsosc != 0) { + dqsosc_thrd_inc[rank] = (3 * mr23 * tCK * tCK) / (dqsosc * dqsosc * 20); + dqsosc_thrd_dec[rank] = (mr23 * tCK * tCK) / (dqsosc * dqsosc * 10); + } + + dramc_dbg("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", + chn, rank, mr19, mr18, dqsosc, mr23, + dqsosc_thrd_inc[rank], dqsosc_thrd_dec[rank]); +} + +void dqsosc_shu_settings(const struct ddr_cali* cali, + u16 *dqsosc_thrd_inc, u16 *dqsosc_thrd_dec) +{ + u8 prd_cnt_div = 4; + u8 filt_pi_thrd = 0; + u8 w2r_sel = 0; + u8 dqsosc_cr_cnt = 0, is_div4 = 0, round_up= 0; + u16 dqsosc_en_cnt = 0xfff; + u16 prd_cnt = 0x3ff, prd_cnt_tmp = 0x3ff; + + u8 chn = cali->chn; + u32 frequency = get_frequency(cali); + dram_freq_grp freq_group = cali->freq_group; + u8 mr23[RANK_MAX] = {cali->mr_value->mr23[chn][0], cali->mr_value->mr23[chn][1]}; + + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DQS2DQ_FILT_PITHRD, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_R_DMDQS2DQ_FILT_OPT, 0x0); + + switch (freq_group) { + case DDRFREQ_400: + filt_pi_thrd = 0x5; + w2r_sel = 0x2; + prd_cnt_div = 2; + is_div4 = 1; + break; + case DDRFREQ_600: + filt_pi_thrd = 0x6; + w2r_sel = 0x5; + break; + case DDRFREQ_800: + filt_pi_thrd = 0x6; + w2r_sel = 0x5; + break; + case DDRFREQ_933: + filt_pi_thrd = 0x9; + w2r_sel = 0x2; + break; + case DDRFREQ_1200: + filt_pi_thrd = 0xb; + w2r_sel = 0x2; + break; + case DDRFREQ_1600: + filt_pi_thrd = 0xE; + w2r_sel = 0x2; + break; + case DDRFREQ_2133: + filt_pi_thrd = 0x17; + w2r_sel = 0x2; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dqsosc_cr_cnt = ((frequency << is_div4)) / 100; + if ((frequency % 100) != 0) + dqsosc_cr_cnt++; + + if (mr23[RANK_1] > mr23[RANK_0]) + prd_cnt_tmp = ((mr23[RANK_1] * 100) / prd_cnt_div); + else + prd_cnt_tmp = ((mr23[RANK_0] * 100) / prd_cnt_div); + + prd_cnt = (prd_cnt_tmp + dqsosc_cr_cnt * 100 / 16) / 100; + round_up = (prd_cnt_tmp + dqsosc_cr_cnt *100 / 16) % 100; + if (round_up != 0) + prd_cnt++; + + SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0, + SHU_DQSOSC_SET0_DQSOSC_PRDCNT, prd_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_dqsoscr, + SHU_DQSOSCR_DQSOSCRCNT, dqsosc_cr_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, + SHU_TX_SET0_DQS2DQ_FILT_PITHRD, filt_pi_thrd); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, + SHU_TX_SET0_TXUPD_W2R_SEL, w2r_sel, + SHU_TX_SET0_TXUPD_SEL, 0x0); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_dqsosc_thrd, + SHURK_DQSOSC_THRD_DQSOSCTHRD_INC, dqsosc_thrd_inc[rk]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rk].shurk_dqsosc_thrd, + SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC, dqsosc_thrd_dec[rk]); + } + + SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0, + SHU_DQSOSC_SET0_DQSOSCENCNT, dqsosc_en_cnt); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 052b320..11c5d3a 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -242,6 +242,8 @@ { u8 txdly_min, txdly_max; u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]; + u16 dqsosc_thrd_inc[RANK_MAX]; + u16 dqsosc_thrd_dec[RANK_MAX]; cali->chn = chn; SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, @@ -290,7 +292,10 @@ dramc_rx_datlat_cal(cali); dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); dramc_tx_oe_calibration(cali); + dramc_auto_refresh_switch(chn, false); + dramc_dqsosc_set_mr18_mr19(cali, dqsosc_thrd_inc, dqsosc_thrd_dec); } + dqsosc_shu_settings(cali, dqsosc_thrd_inc, dqsosc_thrd_dec); dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); dramc_dual_rank_rx_datlat_cal(cali); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf638f4d88a10ce451d63ea431facb2899b2be85 Gerrit-Change-Number: 44723 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc tx window training
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44720 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc tx window training ...................................................................... soc/mediatek/mt8192: Do dramc tx window training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ica11573c1e0b657be0e8ddcbf81a9e3f2399e258 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 794 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/44720/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 363a3bd..602e61d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -5,6 +5,11 @@ #include <soc/dramc_register.h> #include <timer.h> +#define PASS_RANGE_NA 0x7fff +#define TX_VREF_RANGE_BEGIN 16 +#define TX_VREF_RANGE_END 50 +#define TX_VREF_RANGE_STEP 2 + static const u8 ca_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][CA_NUM_LP4] = { [PINMUX_DSC] = { [CHANNEL_A] = {1, 4, 5, 3, 2, 0}, @@ -35,6 +40,12 @@ u16 best_dqdly; } pass_win_data_t; +typedef struct { + u16 vref_used; + u16 winsum_by_vref; + u8 worse_bit_winsize; + u8 worse_bit_idx; +} pass_win_data_vref_t; static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ @@ -1704,6 +1715,19 @@ read_dqs_inctl, rank_inctl_root, xrtr2r); } +static void dramc_set_rw_ofoen(u8 chn, u8 onoff) +{ + u32 loop = 0, loop_cnt = 100000; + + while (READ32_BITFIELD(&ch[chn].nao.misc_statusa, MISC_STATUSA_REQQ_EMPTY) != 1) { + loop ++; + if (loop > loop_cnt) { + dramc_dbg("RWOFOEN timout! queue is not empty\n"); + break; + } + } + SET32_BITFIELDS(&ch[chn].ao.scheduler_com, SCHEDULER_COM_RWOFOEN, onoff); +} static void dramc_set_rank_engin2(u8 chn, u8 rank) { @@ -1767,6 +1791,94 @@ dramc_engin2_set_pat(chn, rank, 0); } +static void dramc_engine2_check_complete(u8 chn, u8 status) +{ + u32 loop = 0, loop_max = 100000; + u32 ta2_loop_cnt = 0; + + while ((read32(&ch[chn].nao.testrpt) & status) != status) { + udelay(1); + loop++; + if (loop > loop_max) { + dramc_dbg("testrpt time out, [22:20]=%#x\n", + READ32_BITFIELD(&ch[chn].nao.testrpt, TESTRPT_TESTSTAT)); + break; + } + } + + loop = 0; + if (READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TEST2_PAT_SHIFT)) { + while ((ta2_loop_cnt = read32(&ch[chn].nao.test_loop_cnt)) != 8) { + loop++; + if (loop > loop_max) { + dramc_dbg("test_loop_cnt time out, TEST_LOOP_CNT[%d]\n", + ta2_loop_cnt); + break; + } + } + } +} + +static u32 dramc_engine2_compare(u8 chn) +{ + u8 status = 1; + u32 result = 0xffffffff; + u32 loop_cnt; + u32 shift_ui_flag = 0; + + loop_cnt = READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TESTCNT); + if (loop_cnt == 1) + status = 3; + + shift_ui_flag = READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TEST2_PAT_SHIFT); + + if (!shift_ui_flag) { + dramc_engine2_check_complete(chn, status); + + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 1, + TEST2_A3_TEST1, 0); + } + + dramc_engine2_check_complete(chn, status); + result = (read32(&ch[chn].nao.testrpt) >> 4) & status; + + return result; +} + +static u32 dramc_engine2_run(u8 chn) +{ + u32 result = 0xffffffff; + + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 1, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + dramc_engine2_compare(chn); + udelay(1); + result = read32(&ch[chn].nao.cmp_err); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + + return result; +} + +static void dramc_engine2_end(u8 chn, u32 dummy_rd) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a4, + TEST2_A4_TEST_REQ_LEN1, 0); + dramc_set_rw_ofoen(chn, 1); + write32(&ch[chn].ao.dummy_rd, dummy_rd); +} + static const u8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { [PINMUX_DSC] = { @@ -1843,6 +1955,7 @@ SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1); } + void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type cali_type) { u8 chn, rank, fsp; @@ -1956,3 +2069,647 @@ bit + 2, final_win_perbit[bit + 2].best_dqdly, bit + 3, final_win_perbit[bit + 3].best_dqdly); } + +static void tx_perbit_calibarion_init(u8 chn, u8 rank, u8 cali_type) +{ + if (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY) { + write32(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly0, 0); + write32(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly1, 0); + write32(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly0, 0); + write32(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } +} + +static void tx_win_transfer_delay_to_uipi(const struct ddr_cali* cali, u16 delay, + u8 pi_to_center, u8 *p_ui_large_dq, u8 *p_ui_small_dq, u8 *p_pi, + u8 *p_ui_large_dqoe, u8 *p_ui_small_dqoe) +{ + dram_freq_grp freq_group = cali->freq_group; + bool is_freq_400 = freq_group == DDRFREQ_400; + + u8 small_ui_to_large, pi = 0, pi_to_ui, tx_dq_oe_shift = 0; + u8 pi_tap = is_freq_400 ? TX_PHASE_DQ_UI_TO_PI_TAP : TX_DQ_UI_TO_PI_TAP; + u16 tmp_val, dqoe_shift; + u8 mr03 = cali->mr_value->mr03[get_fsp(cali)]; + small_ui_to_large = get_mck2ui_div_shift(cali); + tx_dq_oe_shift = 3; + + if (p_pi != NULL) { + pi = delay & (pi_tap-1); + *p_pi =pi; + } + + if (is_freq_400) + pi_to_ui = 0; + else + pi_to_ui = 1; + + tmp_val = (delay /pi_tap) << pi_to_ui; + + if (pi_to_center && (p_pi != NULL) && (!is_freq_400)) { + if (pi < 10) { + pi += (pi_tap) >> 1; + tmp_val --; + } else if (pi > pi_tap - 10) { + pi -= (pi_tap) >> 1; + tmp_val ++; + } + + *p_pi = pi; + } + + *p_ui_small_dq = tmp_val - ((tmp_val >> small_ui_to_large) << small_ui_to_large); + *p_ui_large_dq = (tmp_val >> small_ui_to_large); + + tmp_val -= tx_dq_oe_shift; + + if (((mr03 & 0x80) >> 7) == 1) { + if (get_div_mode(cali) == DIV4_MODE) + dqoe_shift = 4; + else + dqoe_shift = 8; + + tmp_val += dqoe_shift; + } + + *p_ui_small_dqoe = tmp_val - ((tmp_val >> small_ui_to_large) << small_ui_to_large); + *p_ui_large_dqoe = (tmp_val >> small_ui_to_large); +} + +static void tx_set_delay_reg_dq(u8 chn, u8 rank, u8 update_reg_ui, u8 dq_ui_large[], + u8 dq_oen_ui_large[], u8 dq_ui_small[], u8 dq_oen_ui_small[], u8 dql_pi[]) +{ + if (update_reg_ui) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, dq_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_DQ1, dq_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_DQ2, dq_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_DQ3, dq_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, dq_oen_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, dq_oen_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, dq_oen_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, dq_oen_ui_large[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, dq_ui_small[0], + SHURK_SELPH_DQ2_DLY_DQ1, dq_ui_small[1], + SHURK_SELPH_DQ2_DLY_DQ2, dq_ui_small[0], + SHURK_SELPH_DQ2_DLY_DQ3, dq_ui_small[1], + SHURK_SELPH_DQ2_DLY_OEN_DQ0, dq_oen_ui_small[0], + SHURK_SELPH_DQ2_DLY_OEN_DQ1, dq_oen_ui_small[1], + SHURK_SELPH_DQ2_DLY_OEN_DQ2, dq_oen_ui_small[0], + SHURK_SELPH_DQ2_DLY_OEN_DQ3, dq_oen_ui_small[1]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, dql_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, dql_pi[1]); +} + +static void tx_set_delay_reg_dqm(u8 chn, u8 rank, u8 update_reg_ui, u8 dqm_ui_large[], + u8 dqm_oen_ui_large[], u8 dqm_ui_small[], u8 dqm_oen_ui_small[], u8 dqm_pi[]) +{ + if (update_reg_ui) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, dqm_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_DQM1, dqm_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_DQM2, dqm_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_DQM3, dqm_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, dqm_oen_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, dqm_oen_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, dqm_oen_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, dqm_oen_ui_large[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, dqm_ui_small[0], + SHURK_SELPH_DQ3_DLY_DQM1, dqm_ui_small[1], + SHURK_SELPH_DQ3_DLY_DQM2, dqm_ui_small[0], + SHURK_SELPH_DQ3_DLY_DQM3, dqm_ui_small[1], + SHURK_SELPH_DQ3_DLY_OEN_DQM0, dqm_oen_ui_small[0], + SHURK_SELPH_DQ3_DLY_OEN_DQM1, dqm_oen_ui_small[1], + SHURK_SELPH_DQ3_DLY_OEN_DQM2, dqm_oen_ui_small[0], + SHURK_SELPH_DQ3_DLY_OEN_DQM3, dqm_oen_ui_small[1]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, dqm_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, dqm_pi[1]); +} + +static void update_tx_tracking(u8 chn, u8 rank, tx_cali_type cali_type, u8 dq_pi[], u8 dqm_pi[]) +{ + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQM_ONLY) { + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B0, dq_pi[0], + SHURK_PI_RK0_ARPI_DQ_B1, dq_pi[1]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, dq_pi[1], + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, dq_pi[0]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, dq_pi[1], + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, dq_pi[0]); + } + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_pi, + SHURK_PI_RK0_ARPI_DQM_B0, dqm_pi[0], + SHURK_PI_RK0_ARPI_DQM_B1, dqm_pi[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, dqm_pi[1], + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, dqm_pi[0]); + } +} + +static void dramc_tx_set_vref(const struct ddr_cali* cali, u8 vref_range, u8 vref) +{ + u8 mr_value = (vref & 0x3f) | (vref_range << 6); + + dramc_mode_reg_write_by_rank(cali, cali->chn, cali->rank, 14, mr_value); +} + +static void tx_scan_range_PI(const struct ddr_cali* cali, tx_cali_type cali_type, + u16 *begin, u16 *end, const u8 dqs_final_delay[2][2]) +{ + u8 mck_to_ui, ui_to_pi, byte; + u8 dq_ui_large_bak[DQS_NUMBER], dq_ui_small_bak[DQS_NUMBER]; + u16 temp_virtual_delay, smallest_virtual_delay = 0xffff; + u16 delay_begin = 0, delay_end = 0; + u32 tx_dly, delay; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + tx_dly = read32(&ch[chn].ao.shu_selph_dqs0); + delay = read32(&ch[chn].ao.shu_selph_dqs1); + mck_to_ui = get_mck2ui_div_shift(cali); + ui_to_pi = 5; + + for (byte = 0; byte < BYTE_NUM; byte++) { + dq_ui_large_bak[byte] = (tx_dly >> (byte << 2)) & 0x7; + dq_ui_small_bak[byte] = (delay >> (byte << 2)) & 0x7; + temp_virtual_delay = (((dq_ui_large_bak[byte] << mck_to_ui) + + dq_ui_small_bak[byte]) << ui_to_pi) + dqs_final_delay[rank][byte]; + + if (temp_virtual_delay < smallest_virtual_delay) + smallest_virtual_delay = temp_virtual_delay; + } + + delay_begin = smallest_virtual_delay; + + if (cali_type == TX_DQ_DQS_MOVE_DQM_ONLY) + delay_begin -= (1 << (mck_to_ui + 5)); + delay_end = delay_begin + ((1 << mck_to_ui) << ui_to_pi); + + *begin = delay_begin; + *end = delay_end; +} + +static void tx_scan_range_vref(const struct ddr_cali* cali, bool enable_vref_scan, + u16 *range, u16 *begin, u16 *end, u16 *step) +{ + u16 vref_begin, vref_end; + u8 odt = get_odt_state(cali); + const struct sdram_params *params = cali->params; + + if (enable_vref_scan) { + vref_begin = params->tx_window_vref[cali->chn][cali->rank]; + vref_end = vref_begin + 1; + }else { + vref_begin = 0; + vref_end = 0; + } + + *range = (!odt); + *begin = vref_begin; + *end = vref_end; + *step = TX_VREF_RANGE_STEP; +} + +static u16 tx_choose_vref(pass_win_data_vref_t vref_info[], u8 vref_num) +{ + u8 vref, worse_bit = 0, win_size_worse_bit = 0; + u16 max_winsum = 0; + u16 final_vref = 0; + + for (vref = 0; vref < vref_num; vref++) + dramc_dbg("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n", + vref_info[vref].vref_used, + vref_info[vref].worse_bit_idx, + vref_info[vref].worse_bit_winsize, + vref_info[vref].winsum_by_vref); + + for (vref = 0; vref < vref_num; vref++) { + if ((vref_info[vref].worse_bit_winsize > win_size_worse_bit) || + ((vref_info[vref].worse_bit_winsize == win_size_worse_bit) && + (vref_info[vref].winsum_by_vref > max_winsum))) { + win_size_worse_bit = vref_info[vref].worse_bit_winsize; + worse_bit = vref_info[vref].worse_bit_idx; + max_winsum = vref_info[vref].winsum_by_vref; + final_vref = vref_info[vref].vref_used; + } + } + + dramc_dbg("Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", + worse_bit, win_size_worse_bit, max_winsum, final_vref); + + return final_vref; +} + +static void dramc_tx_window_perbit_cal_find_best_delay(const struct ddr_cali* cali, + tx_cali_type cali_type, bool enable_vref_scan, u16 delay_begin, u16 delay_end, + u16 delay_step, u32 *finish_count, u8 *ui_small_reg_value, + pass_win_data_t win_perbit[DQ_DATA_WIDTH], + pass_win_data_t vref_win_perbit[DQ_DATA_WIDTH]) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 pi, ui_small, ui_large, oen_ui_small, oen_ui_large; + u8 update_reg_ui; + u8 dq_ui_large[DQS_NUMBER] = {0}, dq_ui_small[DQS_NUMBER] = {0}; + u8 dq_oen_ui_large[DQS_NUMBER] = {0}, dq_oen_ui_small[DQS_NUMBER] = {0}; + u8 dqm_ui_large[DQS_NUMBER] = {0}, dqm_ui_small[DQS_NUMBER] = {0}; + u8 dqm_oen_ui_large[DQS_NUMBER] = {0}, dqm_oen_ui_small[DQS_NUMBER] = {0}; + u8 dq_pi[DQS_NUMBER] = {0}, dqm_pi[DQS_NUMBER] = {0}; + u16 perbit_winsum, vref_winsum; + u32 err_value, fail_bit; + + for (u16 delay = delay_begin; delay < delay_end; delay += delay_step) { + tx_win_transfer_delay_to_uipi(cali, delay, 0, &ui_large, + &ui_small, &pi, &oen_ui_large, &oen_ui_small); + + if (*ui_small_reg_value != ui_small) { + update_reg_ui = 1; + *ui_small_reg_value = ui_small; + } else + update_reg_ui = 0; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + if (update_reg_ui) { + dq_ui_large[byte] = ui_large; + dq_ui_small[byte] = ui_small; + dq_oen_ui_large[byte] = oen_ui_large; + dq_oen_ui_small[byte] = oen_ui_small; + + dqm_ui_large[byte] = ui_large; + dqm_ui_small[byte] = ui_small; + dqm_oen_ui_large[byte] = oen_ui_large; + dqm_oen_ui_small[byte] = oen_ui_small; + } + + dq_pi[byte] = pi; + dqm_pi[byte] = pi; + } + + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || + cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dq(chn, rank, update_reg_ui, dq_ui_large, + dq_oen_ui_large, dq_ui_small, dq_oen_ui_small, dq_pi); + + if (cali_type == TX_DQ_DQS_MOVE_DQM_ONLY || + cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dqm(chn, rank, update_reg_ui, + dqm_ui_large, dqm_oen_ui_large, dqm_ui_small, + dqm_oen_ui_small, dqm_pi); + + err_value = dramc_engine2_run(chn); + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) + if (err_value != 0) + dramc_dbg("%d |%d %d %d|[0]", delay, ui_large, ui_small, pi); + + for (u8 bit = 0; bit < DQ_DATA_WIDTH; bit++) { + fail_bit = err_value & BIT(bit); + + if (win_perbit[bit].first_pass == PASS_RANGE_NA) { + if (fail_bit == 0) + win_perbit[bit].first_pass = delay; + } else if (win_perbit[bit].last_pass == PASS_RANGE_NA) { + if (fail_bit != 0) + win_perbit[bit].last_pass = delay - delay_step; + else if (delay > (delay_end - delay_step)) + win_perbit[bit].last_pass = delay; + + if (win_perbit[bit].last_pass != PASS_RANGE_NA) { + perbit_winsum = win_perbit[bit].last_pass - + win_perbit[bit].first_pass; + vref_winsum = vref_win_perbit[bit].last_pass - + vref_win_perbit[bit].first_pass; + if (perbit_winsum >= vref_winsum) { + if ((vref_win_perbit[bit].last_pass != + PASS_RANGE_NA) && + vref_winsum > 0) + dramc_dbg("Bit[%d] Bigger window update %d > %d, window broken\n", + bit, perbit_winsum, + vref_winsum); + + if (perbit_winsum > TX_PASS_WIN_CRITERIA) + *finish_count |= BIT(bit); + + vref_win_perbit[bit].first_pass = + win_perbit[bit].first_pass; + vref_win_perbit[bit].last_pass = + win_perbit[bit].last_pass; + } + + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + } + } + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) { + if (err_value != 0) { + if (bit % DQS_BIT_NUMBER == 0) + dramc_dbg(" "); + + if (fail_bit == 0) + dramc_dbg("o"); + else + dramc_dbg("x"); + } + } + } + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) + if (err_value != 0) + dramc_dbg("[MSB]\n"); + + if (*finish_count == 0xffff) + break; + } +} + +static u16 dramc_tx_window_perbit_cal_find_best_vref(const struct ddr_cali* cali, + tx_cali_type cali_type, bool enable_vref_scan, u16 final_range, + u16 vref_begin, u16 vref_end, u16 vref_step, + u16 delay_begin, u16 delay_end, u16 delay_step, u8 *vref_tmp, + u16 center_min[DQS_NUMBER], u16 center_max[DQS_NUMBER], + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH], + pass_win_data_vref_t vref_info[LP4_TX_VREF_DATA_NUM]) +{ + u8 bit, byte, min_bit, min_winsize = 0, bit_tmp; + u8 ui_small_reg_value; + u16 vref_level; + u16 winsum, temp_winsum, max_window_sum = 0; + u32 finish_count; + u32 dummy_rd_bak = 0; + pass_win_data_t win_perbit[DQ_DATA_WIDTH], vref_win_perbit[DQ_DATA_WIDTH]; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + dummy_rd_bak = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank); + + for (vref_level = vref_begin; vref_level <= vref_end; vref_level += vref_step) { + if (enable_vref_scan) { + dramc_dbg("LP4 TX VrefRange %d, VrefLevel=%d\n", final_range, vref_level); + dramc_tx_set_vref(cali, final_range, vref_level); + } else { + dramc_dbg("TX Vref Scan disable\n"); + } + + finish_count = 0; + temp_winsum = 0; + ui_small_reg_value = 0xff; + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].first_pass = (s16)PASS_RANGE_NA; + win_perbit[bit].last_pass = (s16)PASS_RANGE_NA; + vref_win_perbit[bit].first_pass = (s16)PASS_RANGE_NA; + vref_win_perbit[bit].last_pass = (s16)PASS_RANGE_NA; + } + + dramc_tx_window_perbit_cal_find_best_delay(cali, cali_type,enable_vref_scan, + delay_begin, delay_end, delay_step, &finish_count, &ui_small_reg_value, + win_perbit, vref_win_perbit); + + min_winsize = 0xff; + min_bit = 0xff; + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + winsum = vref_win_perbit[bit].last_pass - + vref_win_perbit[bit].first_pass; + if (vref_win_perbit[bit].first_pass == PASS_RANGE_NA) + vref_win_perbit[bit].win_size = 0; + else + vref_win_perbit[bit].win_size = winsum + delay_step; + + if (vref_win_perbit[bit].win_size < min_winsize) { + min_bit = bit; + min_winsize = vref_win_perbit[bit].win_size; + } + + temp_winsum += vref_win_perbit[bit].win_size; + vref_win_perbit[bit].win_center = (vref_win_perbit[bit].first_pass + + vref_win_perbit[bit].last_pass) >> 1; + } + + if (enable_vref_scan) { + if (temp_winsum > max_window_sum) + max_window_sum = temp_winsum; + + vref_info[*vref_tmp].vref_used = vref_level; + vref_info[*vref_tmp].worse_bit_winsize = min_winsize; + vref_info[*vref_tmp].worse_bit_idx = min_bit; + vref_info[*vref_tmp].winsum_by_vref = temp_winsum; + *vref_tmp = *vref_tmp + 1; + } + + if (enable_vref_scan && + (temp_winsum < (max_window_sum * 95 / 100)) && + (min_winsize > TX_PASS_WIN_CRITERIA)) { + dramc_dbg("TX Vref early break, caculate TX vref\n"); + break; + } + } + + dramc_engine2_end(chn, dummy_rd_bak); + if (enable_vref_scan) + return vref_level; + + for (byte = 0; byte < (DQ_DATA_WIDTH / DQS_BIT_NUMBER); byte++) { + center_min[byte] = 0xffff; + center_max[byte] = 0; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + memcpy(final_win_perbit, vref_win_perbit, sizeof(vref_win_perbit)); + + if (final_win_perbit[bit_tmp].win_center < center_min[byte]) + center_min[byte] = final_win_perbit[bit_tmp].win_center; + + if (final_win_perbit[bit_tmp].win_center > center_max[byte]) + center_max[byte] = final_win_perbit[bit_tmp].win_center; + } + } + + return vref_level; +} + +void dramc_tx_window_perbit_cal(const struct ddr_cali* cali, + tx_cali_type cali_type, const u8 dqs_final_delay[2][2], bool enable_vref_scan) +{ + u8 chn, rank, fsp, odt; + u8 pi_diff; + u8 bit_tmp, bit, byte, rk; + u8 enable_delaycell = 0; + u8 vref_tmp = 0; + u8 dq_ui_large[DQS_NUMBER], dq_ui_small[DQS_NUMBER], dq_pi[DQS_NUMBER]; + u8 dq_oen_ui_large[DQS_NUMBER], dq_oen_ui_small[DQS_NUMBER]; + u8 dqm_ui_large[DQS_NUMBER] = {0}, dqm_ui_small[DQS_NUMBER] = {0}; + u8 dqm_oen_ui_large[DQS_NUMBER] = {0}, dqm_oen_ui_small[DQS_NUMBER] = {0}; + u8 dqm_pi[DQS_NUMBER] = {0}; + u16 delay, delay_step, dqm_delay; + u16 center_min[DQS_NUMBER] = {0}, center_max[DQS_NUMBER] = {0}; + u16 delaycell_offset[DQ_DATA_WIDTH] = {0}; + u16 final_range = 0, final_vref = 0; + u16 vref_begin, vref_end, vref_step; + u16 delay_begin, delay_end; + u32 frequency; + dram_freq_grp freq_group; + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH]; + pass_win_data_vref_t vref_info[LP4_TX_VREF_DATA_NUM]; + + fsp = get_fsp(cali); + odt = get_odt_state(cali); + bool bypass_cali = !fsp; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + freq_group = cali->freq_group; + frequency = get_frequency(cali); + + tx_perbit_calibarion_init(chn, rank, cali_type); + + tx_scan_range_PI(cali, cali_type, &delay_begin, &delay_end, dqs_final_delay); + tx_scan_range_vref(cali, enable_vref_scan, &final_range, &vref_begin, &vref_end, &vref_step); + dramc_dbg("delay_begin:%d, delay_end:%d,final_range:%d,vref_begin:%d, vref_end:%d,vref_step:%d\n", + delay_begin, delay_end, final_range, vref_begin, vref_end, vref_step); + + if (freq_group == DDRFREQ_400) + delay_step = 8; + else if (cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + delay_step = 2; + else + delay_step = 1; + + if (bypass_cali) { + for (byte = 0; byte < BYTE_NUM; byte++) { + center_min[byte] = params->tx_center_min[chn][rank][byte]; + center_max[byte] = params->tx_center_max[chn][rank][byte]; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + final_win_perbit[bit_tmp].win_center = + params->tx_win_center[chn][rank][bit_tmp]; + } + } + } else { + final_vref = dramc_tx_window_perbit_cal_find_best_vref(cali, cali_type, enable_vref_scan, + final_range, vref_begin, vref_end, vref_step, + delay_begin, delay_end, delay_step, &vref_tmp, + center_min, center_max, final_win_perbit, vref_info); + } + + if (enable_vref_scan) { + if (bypass_cali) + final_vref = params->tx_window_vref[chn][rank]; + else + final_vref = tx_choose_vref(vref_info, vref_tmp); + + dramc_tx_set_vref(cali, final_range, final_vref); + return; + } + + if ((cali_type == TX_DQ_DQS_MOVE_DQ_ONLY) && (freq_group > DDRFREQ_1200)) { + enable_delaycell = 1; + dramc_dbg("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", params->delay_cell_timex100); + } + + for (byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg(" == TX Byte %d ==\n", byte); + dqm_delay = ((center_min[byte] + center_max[byte]) >> 1); + + if (enable_delaycell == 0) { + delay = dqm_delay; + } else { + delay = center_min[byte]; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + pi_diff = final_win_perbit[bit_tmp].win_center - + center_min[byte]; + if (params->delay_cell_timex100 != 0) { + delaycell_offset[bit_tmp] = (pi_diff * 100000000 / + (frequency << 6)) / + params->delay_cell_timex100; + dramc_dbg("delaycell_offset[%d]=%d cells (%d PI)\n", + bit_tmp, delaycell_offset[bit_tmp], pi_diff); + if (delaycell_offset[bit_tmp] > 255) { + dramc_dbg("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", + bit, delaycell_offset[bit_tmp]); + delaycell_offset[bit_tmp] = 255; + } + } + } + } + + tx_win_transfer_delay_to_uipi(cali, delay, 1, &dq_ui_large[byte], + &dq_ui_small[byte], &dq_pi[byte], + &dq_oen_ui_large[byte], &dq_oen_ui_small[byte]); + tx_win_transfer_delay_to_uipi(cali, dqm_delay, 1, &dqm_ui_large[byte], + &dqm_ui_small[byte], &dqm_pi[byte], + &dqm_oen_ui_large[byte], &dqm_oen_ui_small[byte]); + + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQ_DQM) { + dramc_dbg("Update DQ dly =%d (%d ,%d, %d) DQ OEN =(%d ,%d)\n", + delay, dq_ui_large[byte], dq_ui_small[byte], dq_pi[byte], \ + dq_oen_ui_large[byte], dq_oen_ui_small[byte]); + } + + dramc_dbg("Update DQM dly =%d (%d ,%d, %d) DQM OEN =(%d ,%d)", + dqm_delay, dqm_ui_large[byte], dqm_ui_small[byte], dqm_pi[byte], + dqm_oen_ui_large[byte], dqm_oen_ui_small[byte]); + dramc_dbg("\n"); + } + + for (rk = rank; rk < RANK_MAX; rk++) { + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dq(chn, rk, true, dq_ui_large, dq_oen_ui_large, + dq_ui_small, dq_oen_ui_small, dq_pi); + tx_set_delay_reg_dqm(chn, rk, true, dqm_ui_large, dqm_oen_ui_large, + dqm_ui_small, dqm_oen_ui_small, dqm_pi); + + if (enable_delaycell) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, delaycell_offset[3], + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, delaycell_offset[2], + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, delaycell_offset[1], + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, delaycell_offset[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, delaycell_offset[7], + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, delaycell_offset[6], + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, delaycell_offset[5], + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, delaycell_offset[4]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, delaycell_offset[11], + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, delaycell_offset[10], + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, delaycell_offset[9], + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, delaycell_offset[8]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, delaycell_offset[15], + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, delaycell_offset[14], + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, delaycell_offset[13], + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, delaycell_offset[12]); + } + + update_tx_tracking(chn, rk, cali_type, dq_pi, dqm_pi); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 41d85a2..f724e54 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -16,6 +16,26 @@ shift_dq_ui(cali, cali->rank, ui_move); } +static void switch_write_dbi_settings(const struct ddr_cali *cali, dbi_mode dbi_state) +{ + s8 tx_shift; + u8 chn, rank; + struct mr_values *mr_value = cali->mr_value; + u8 mr03 = mr_value->mr03[get_fsp(cali)]; + + chn = cali->chn; + rank = cali->rank; + + tx_shift = dbi_state ? -1 : 1; + dramc_write_shift_mck_write_DBI(cali, tx_shift); + + mr03 = (mr03 & ~(0x1 << 7)) | (dbi_state << 7); + dramc_mode_reg_write_by_rank(chn, rank, 3, mr03); + mr_value->mr03[get_fsp(cali)] = mr03; + + dramc_write_dbi_onoff(dbi_state); +} + static void dramc_ac_timing_optimize(const struct ddr_cali* cali) { u8 rf_group = 0, cab_id = 0; @@ -250,6 +270,23 @@ dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); dramc_rx_window_perbit_cal(cali, RX_WIN_RD_DQC); + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_DQM, + dqs_final_delay, false); + if (get_vref_cali(cali) == VREF_CALI_ON) + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_ONLY, + dqs_final_delay, true); + + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_ONLY, + dqs_final_delay, false); + + if (get_write_dbi(cali) == DBI_ON) { + dramc_dbg("K DQM with DBI_ON\n"); + switch_write_dbi_settings(cali, DBI_ON); + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQM_ONLY, + dqs_final_delay, false); + switch_write_dbi_settings(cali, DBI_OFF); + } + dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); -- To view, visit https://review.coreboot.org/c/coreboot/+/44720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica11573c1e0b657be0e8ddcbf81a9e3f2399e258 Gerrit-Change-Number: 44720 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 39

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc runtime config settings
by CK HU (Code Review) 09 Mar '21

09 Mar '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44724 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc runtime config settings ...................................................................... soc/mediatek/mt8192: Do dramc runtime config settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Id7ccf0e2332f789f5ae50ec80479c4cd48bb9b40 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_tracking.c 3 files changed, 821 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44724/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index f42ae75..bfa3316 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 11c5d3a..c3c19bf 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -297,7 +297,12 @@ } dqsosc_shu_settings(cali, dqsosc_thrd_inc, dqsosc_thrd_dec); dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); + dramc_dqs_precalculation_preset(cali); dramc_dual_rank_rx_datlat_cal(cali); + + if (cali->support_ranks == DUAL_RANK_DDR) + xrtwtw_shu_setting(cali); + } static void dramc_calibration_all_channels(struct ddr_cali *cali) @@ -431,4 +436,6 @@ first_freq_k = false; dramc_info("frequency %d calibration finish\n", get_frequency(&cali)); } + + dramc_runtime_config(&cali); } diff --git a/src/soc/mediatek/mt8192/dramc_tracking.c b/src/soc/mediatek/mt8192/dramc_tracking.c new file mode 100644 index 0000000..3c13447 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_tracking.c @@ -0,0 +1,813 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static void dramc_dqs_precalculation_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_pre_tdqsck1, + MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 0x1); + } +} + +static void dramc_hw_gating_debug(bool enable) +{ + u8 dbg_en = enable ? 0x3 : 0x0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_DBG_EN, dbg_en, + MISC_STBCAL2_STB_PIDLYCG_IG, enable, + MISC_STBCAL2_STB_UIDLYCG_IG, enable, + MISC_STBCAL2_STB_GERRSTOP, enable, + MISC_STBCAL2_STB_DBG_CG_AO, 0, + MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 1); + } +} + +static void tx_picg_new_mode_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0, + MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0, + MISC_CTRL3_ARPI_CG_DQS_OPT, 0, + MISC_CTRL3_ARPI_CG_DQ_OPT, 0); + } +} + +static void enable_common_dcm_non_shuffle(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN3, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 0x0, + MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 0x0, + MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 0x1, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17, + MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 0x0, + MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 0x3, + MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 0x1, + MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 0x0, + MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 0x5); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi1, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dummy_rd, + DUMMY_RD_DUMMY_RD_PA_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_ARPI_CG_DQS_OPT, 0x0, + MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 0x0, + MISC_CTRL3_ARPI_CG_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_CMD_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 0x0, + MISC_CTRL3_ARPI_CG_CLK_OPT, 0x0, + MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 0x0, + MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 0x0); + } +} + +static void enable_common_dcm_shuffle(u8 shuffle) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd13 + shuffle * SHU_OFFSET, + SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl + shuffle * SHU_OFFSET, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1); + write32(&ch[chn].phy_ao.misc_shu_cg_ctrl0 + shuffle * SHU_OFFSET, + 0x33403000); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq7 + shuffle * SHU_OFFSET, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd7 + shuffle * SHU_OFFSET, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0x0, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq7 + shuffle * SHU_OFFSET, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0); + } +} + +void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle) +{ + u8 val = enable ? 0 : 1; + enable_common_dcm_shuffle(shuffle); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, val, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, val); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd8 + shuffle * SHU_OFFSET, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, val, + SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, val, + SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, val, + SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, val); + SET32_BITFIELDS(&ch[chn].ao.shu_aphy_tx_picg_ctrl + shuffle * SHU_OFFSET, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, enable); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8 + shuffle * SHU_OFFSET, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, val, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, val); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl + shuffle * SHU_OFFSET, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, val); + } +} + +void enable_phy_dcm_non_shuffle(dcm_state enable) +{ + enable_common_dcm_non_shuffle(); + + if (enable) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.tx_cg_set0, + TX_CG_SET0_DWCLKRUN, 0x0, + TX_CG_SET0_SELPH_CG_DIS, 0x0, + TX_CG_SET0_SELPH_4LCG_DIS, 0x0, + TX_CG_SET0_TX_ATK_CLKRUN, 0x0, + TX_CG_SET0_WDATA_CG_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl5, + MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x1, + MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x1, + MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x0, + MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x0, + MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x0, + MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_SREF_CG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.rx_cg_set0, + RX_CG_SET0_RDYCKAR, 0x0, + RX_CG_SET0_RDATCKAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN2, 0x0, + ACTIMING_CTRL_SEQCLKRUN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCARB_SM_CGAR, 0x0, + SCSMCTRL_CG_SCSM_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.cmd_dec_ctrl0, + CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x0); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUE_PACG_DIS, 0x0, + CLKAR_REQQUECLKRUN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x0); + SET32_BITFIELDS(&ch[chn].ao.ddrcommon0, + DDRCOMMON0_DISSTOP26M, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CG_OPT, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_ctrl0, DCM_CTRL0_BCLKAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x1, + DRAMC_PD_CTRL_DCMEN2, 0x1, + DRAMC_PD_CTRL_DCMEN, 0x1, + DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x0, + DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x0, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x0, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x0, + DRAMC_PD_CTRL_DCMENNOTRFC, 0x1, + DRAMC_PD_CTRL_COMBCLKCTRL, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x0, + MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_MCK, 0x1, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0x1, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x1, + MISC_CTRL4_R_OPT2_CG_DQ, 0x1, + MISC_CTRL4_R_OPT2_CG_DQS, 0x1, + MISC_CTRL4_R_OPT2_CG_DQM, 0x1, + MISC_CTRL4_R_OPT2_CG_CMD, 0x1, + MISC_CTRL4_R_OPT2_CG_CLK, 0x1, + MISC_CTRL4_R_OPT2_CG_CS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x0, + TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x0, + TX_TRACKING_SET0_HMRRSEL_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x0, + ZQ_SET0_ZQMASK_CGAR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x0); + } + } else { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.tx_cg_set0, + TX_CG_SET0_DWCLKRUN, 0x1, + TX_CG_SET0_SELPH_CG_DIS, 0x1, + TX_CG_SET0_SELPH_4LCG_DIS, 0x1, + TX_CG_SET0_TX_ATK_CLKRUN, 0x1, + TX_CG_SET0_WDATA_CG_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl5, + MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_CA_PI_DCM_EN, 0x0, + MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 0x0, + MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 0x1, + MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 0x1, + MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 0x1, + MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0); + SET32_BITFIELDS(&ch[chn].ao.misctl0, + MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_SREF_CG_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].ao.rx_cg_set0, + RX_CG_SET0_RDYCKAR, 0x1, + RX_CG_SET0_RDATCKAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, + ACTIMING_CTRL_SEQCLKRUN2, 0x1, + ACTIMING_CTRL_SEQCLKRUN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.scsmctrl_cg, + SCSMCTRL_CG_SCARB_SM_CGAR, 0x1, + SCSMCTRL_CG_SCSM_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.cmd_dec_ctrl0, + CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.clkar, + CLKAR_REQQUE_PACG_DIS, 0x7fff, + CLKAR_REQQUECLKRUN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 0x1); + SET32_BITFIELDS(&ch[chn].ao.ddrcommon0, + DDRCOMMON0_DISSTOP26M, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CG_OPT, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dcm_ctrl0, DCM_CTRL0_BCLKAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 0x0, + DRAMC_PD_CTRL_DCMEN2, 0x0, + DRAMC_PD_CTRL_DCMEN, 0x0, + DRAMC_PD_CTRL_PHYGLUECLKRUN, 0x1, + DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 0x1, + DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 0x1, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 0x1, + DRAMC_PD_CTRL_DCMENNOTRFC, 0x0, + DRAMC_PD_CTRL_COMBCLKCTRL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl3, + MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 0x1, + MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_CG_DQSIEN, 0x0, + MISC_CTRL4_R_OPT2_CG_CLK, 0x0, + MISC_CTRL4_R_OPT2_MPDIV_CG, 0x0, + MISC_CTRL4_R_OPT2_CG_DQM, 0x0, + MISC_CTRL4_R_OPT2_CG_CMD, 0x0, + MISC_CTRL4_R_OPT2_CG_DQS, 0x0, + MISC_CTRL4_R_OPT2_CG_MCK, 0x0, + MISC_CTRL4_R_OPT2_CG_CS, 0x0, + MISC_CTRL4_R_OPT2_CG_DQ, 0x0); + SET32_BITFIELDS(&ch[chn].ao.tx_tracking_set0, + TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 0x1, + TX_TRACKING_SET0_RDDQSOSC_CGAR, 0x1, + TX_TRACKING_SET0_HMRRSEL_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0x1, + ZQ_SET0_ZQMASK_CGAR, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rx_autok_cfg0, + MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 0x1); + } + } +} + +static void enable_tx_tracking(dram_freq_grp freq_group, u8 shuffle) +{ + u8 dqsosc_en = (freq_group <= DDRFREQ_400) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_dqsosc_set0 + shuffle * SHU_OFFSET, + SHU_DQSOSC_SET0_DQSOSCENDIS, dqsosc_en); +} + +static void enable_gating_tracking(dram_freq_grp freq_group, u8 shuffle) +{ + u8 stbcal = (freq_group <= DDRFREQ_400) ? 0 : 1; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal + shuffle * SHU_OFFSET, + MISC_SHU_STBCAL_STBCALEN, stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, stbcal); +} + +static void enable_rx_dcm_dphy(dram_freq_grp freq_group, u8 shuffle) +{ + u8 precal_cg_en = (freq_group <= DDRFREQ_400) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl + shuffle * SHU_OFFSET, + MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 0x1, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 0x0, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 0x1, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, precal_cg_en, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 0x2, + MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 0x0); +} + + +static void enable_clk_tx_rx_latch_en(u8 shuffle) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq10 + shuffle * SHU_OFFSET, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq10 + shuffle * SHU_OFFSET, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2 + shuffle * SHU_OFFSET, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2 + shuffle * SHU_OFFSET, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq11 + shuffle * SHU_OFFSET, + SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq11 + shuffle * SHU_OFFSET, + SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd11 + shuffle * SHU_OFFSET, + SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd10 + shuffle * SHU_OFFSET, + SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 1); + } + +} + +static void enable_tx_wdqs(u8 shuffle) +{ + u8 dqsb_read_base = 1; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, dqsb_read_base, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, + dqsb_read_base); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13 + shuffle * SHU_OFFSET, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, dqsb_read_base, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, + dqsb_read_base); + } +} + +static void set_mr13_vrcg_to_normal_operation_shuffle(u8 shuffle) +{ + u32 value = READ32_BITFIELD(&ch[0].ao.shu_hwset_vrcg + shuffle * SHU_OFFSET, + SHU_HWSET_VRCG_HWSET_VRCG_OP); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg + shuffle * SHU_OFFSET, + SHU_HWSET_VRCG_HWSET_VRCG_OP, value & ~ BIT(3)); +} + +static void dramc_shu_tracking_dcm_en_by_sram(const struct ddr_cali* cali) +{ + u8 shuffle, chn, shuffle_save; + dram_freq_grp freq_group = 0; + dram_freq_grp freq_group_bak = get_freq_group(cali); + + struct reg_bak regs_bak[] = { + {&ch[0].phy_ao.misc_sram_dma0}, + {&ch[1].phy_ao.misc_sram_dma0}, + {&ch[0].phy_ao.misc_sram_dma1}, + {&ch[1].phy_ao.misc_sram_dma1}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma1, + MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 0x1); + } + + for (shuffle = DRAM_DFS_SHU0; shuffle <= DRAM_DFS_SHU_MAX; shuffle++) { + if (shuffle < DRAM_DFS_SHU_MAX) { + /* save to shuffle */ + freq_group = get_freq_group_by_shu_save(shuffle); + for (chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma1, + MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, shuffle); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_APB_SLV_SEL, 0x1); + } + shuffle_save = DRAM_DFS_SHU1; + } else { + /* restore to SRAM */ + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); + shuffle_save = DRAM_DFS_SHU0; + freq_group = freq_group_bak; + } + + enable_tx_tracking(freq_group, shuffle_save); + enable_gating_tracking(freq_group, shuffle_save); + enable_rx_dcm_dphy(freq_group, shuffle_save); + enable_clk_tx_rx_latch_en(shuffle_save); + enable_tx_wdqs(shuffle_save); + enable_phy_dcm_shuffle(DCM_ON, shuffle_save); + set_mr13_vrcg_to_normal_operation_shuffle(shuffle_save); + } +} + +static void dramc_impedance_tracking_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IMPCAL_CHAB_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_HW, 1, + MISC_IMPCAL_IMPCAL_EN, 0, + MISC_IMPCAL_IMPCAL_SWVALUE_EN, 1, + MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 1, + MISC_IMPCAL_IMPCAL_DRVUPDOPT, 1, + MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 1, + MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 1, + MISC_IMPCAL_IMPBINARY, 1, + MISC_IMPCAL_DRV_ECO_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl0, + MISC_CTRL0_IMPCAL_LP_ECO_OPT, 0x1, + MISC_CTRL0_IMPCAL_TRACK_DISABLE, chn); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 1); + } + + SET32_BITFIELDS(&ch[0].phy_ao.misc_impcal, + MISC_IMPCAL_DIS_SUS_CH0_DRV, 0, + MISC_IMPCAL_DIS_SUS_CH1_DRV, 1, + MISC_IMPCAL_IMPSRCEXT, 0, + MISC_IMPCAL_IMPCAL_ECO_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_impcal, + MISC_IMPCAL_DIS_SUS_CH0_DRV, 1, + MISC_IMPCAL_DIS_SUS_CH1_DRV, 0, + MISC_IMPCAL_IMPSRCEXT, 1, + MISC_IMPCAL_IMPCAL_ECO_OPT, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_DRVCGWREF, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_DQDRVSWUPD, 1); + } +} + +static void dramc_impedance_hw_saving(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_HWSAVE_EN, 1); +} + +static void switch_hmr4(const struct ddr_cali* cali, bool en) +{ + u8 tog_opt = (en && cali->support_ranks == DUAL_RANK_DDR) ? 1 : 0; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.ref_bounce2, REF_BOUNCE2_PRE_MR4INT_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.refctrl2, REFCTRL2_MR4INT_TH, 5); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_HMR4_TOG_OPT, tog_opt); + SET32_BITFIELDS(&ch[chn].ao.hmr4, HMR4_REFRDIS, !en); + } +} + +static void dramc_refresh_rate_debounce_enable(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.ref_bounce1, + REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 0x4, + REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 5, + REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 0, + REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 0xff1f); +} + +static void enable_dfs_no_queue_flush(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_HWSET_WLRL, 0, + DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 0, + DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 1, + DVFS_CTRL0_R_DMDVFSMRW_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shuctrl1, + SHUCTRL1_FC_PRDCNT, 0, + SHUCTRL1_CKFSPE_PRDCNT, 0, + SHUCTRL1_VRCGEN_PRDCNT, 0, + SHUCTRL1_CKFSPX_PRDCNT, 0); + SET32_BITFIELDS(&ch[chn].ao.bypass_fspop, + BYPASS_FSPOP_BPFSP_OPT, 0); + } +} + +static void _dramc_dqs_precalculation_preset(u8 chn, u8 rk, u8 b) +{ + u8 mck, ui, pi, mck_p1, ui_p1, write_ui, write_pi; + const u8 mck2ui = 4; + + if (b == 0) { + mck = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0); + ui = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0); + mck_p1= READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0); + ui_p1 = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0); + pi = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0); + + write_ui = (mck << mck2ui) + ui; + write_pi = (mck_p1 << mck2ui) + ui_p1; + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, write_ui, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, pi); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, write_ui, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, write_pi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, pi); + } else { + mck = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1); + ui = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1); + mck_p1= READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1); + ui_p1 = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1); + pi = READ32_BITFIELD(&ch[chn].phy_ao.byte[b].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1); + + write_ui = (mck << mck2ui) +ui; + write_pi = (mck_p1 << mck2ui) + ui_p1; + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, write_ui, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, pi); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[b].rk[rk].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, write_ui, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, write_pi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, pi); + } +} + +void dramc_dqs_precalculation_preset(const struct ddr_cali* cali) +{ + u8 chn = cali->chn; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) + _dramc_dqs_precalculation_preset(chn, rank, byte); + + if (get_shu(cali) == DRAM_DFS_SHU6) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_pre_tdqsck, + SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x1); + } else { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_pre_tdqsck, + SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 0x0); + } +} + +void xrtwtw_shu_setting(const struct ddr_cali* cali) +{ + u8 byte, chn; + u16 tx_dly_oen_rk[2][2] = {0}, tx_pi_upd[2] = {0}; + u16 tx_rank_inctl, tx_dly_oen_rk_max, tx_pi_upd_max; + + dram_freq_grp freq_group = get_freq_group(cali); + chn = cali->chn; + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + tx_dly_oen_rk[rk][0] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0); + tx_dly_oen_rk[rk][1] = READ32_BITFIELD(&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1); + } + + for (byte = 0; byte < DQS_NUMBER; byte++) { + tx_dly_oen_rk_max = (tx_dly_oen_rk[0][byte] > tx_dly_oen_rk[1][byte]) ? + tx_dly_oen_rk[0][byte]: tx_dly_oen_rk[1][byte]; + if (freq_group >= DDRFREQ_1200) + tx_pi_upd[byte] = (tx_dly_oen_rk_max > 2) ? (tx_dly_oen_rk_max - 2) : 0; + else + tx_pi_upd[byte] = (tx_dly_oen_rk_max > 1) ? (tx_dly_oen_rk_max - 1) : 0; + } + + tx_pi_upd_max = (tx_pi_upd[0] > tx_pi_upd[1]) ? tx_pi_upd[0] : tx_pi_upd[1]; + tx_rank_inctl = (tx_pi_upd_max > 1) ? (tx_pi_upd_max - 1) : 0; + + SET32_BITFIELDS(&ch[chn].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, tx_pi_upd[0], + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, tx_pi_upd[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_rank_inctl); +} + +static void dpm_control_init(const struct ddr_cali *cali) +{ + u8 val, pll1_val, pll2_val; + u8 shu_sram = get_shu(cali); + u8 pll_mode = *(cali->pll_mode); + + + val = 0x3; + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_0, + LPIF_LOW_POWER_CFG_0_PHYPLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, val, + LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, val); + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_3, + LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, val, + LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, val, + LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, val); + + if (pll_mode == PHYPLL_MODE) { + dramc_dbg("PHYPLL\n"); + pll1_val = val; + pll2_val = 0; + } else { + dramc_dbg("CLRPLL\n"); + pll1_val = 0; + pll2_val = val; + } + + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_0, + LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, pll1_val, + LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, pll1_val, + LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, pll2_val, + LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, pll2_val); + SET32_BITFIELDS(&mtk_dpm->fsm_cfg_1, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 0x0, + LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 0x0, + LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 0x1, + LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 0x1, + LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 0x1, + LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 0x1); + SET32_BITFIELDS(&mtk_dpm->fsm_out_ctrl_0, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 0x1, + LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 0x1); + + shu_sram |= shu_sram << 4; + SET32_BITFIELDS(&mtk_dpm->low_power_cfg_1, + LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, shu_sram); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, + PHYPLL0_RG_RPHYPLL_EN, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, + CLRPLL0_RG_RCLRPLL_EN, 0x0); + } + SET32_BITFIELDS(&mtk_dpm->dfd_dbug_0, + LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0x1); +} + +void dramc_runtime_config(const struct ddr_cali* cali) +{ + dpm_control_init(cali); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.refctrl1, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 0x1); + dramc_dbg("REFRESH_OVERHEAD_REDUCTION: ON\n"); + + dramc_dqs_precalculation_enable(); + dramc_dbg("DQS Precalculation for DVFS: ON\n"); + + dramc_hw_gating_debug(true); + dramc_dbg("HW_GATING DBG: ON\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.zq_set1, ZQ_SET1_ZQCALDISB, 1); + dramc_dbg("ZQCS_ENABLE_LP4: ON\n"); + + tx_picg_new_mode_enable(); + dramc_dbg("TX_PICG_NEW_MODE: ON\n"); + + enable_phy_dcm_non_shuffle(DCM_ON); + dramc_dbg("LOWPOWER_GOLDEN_SETTINGS(DCM): ON\n"); + + dramc_shu_tracking_dcm_en_by_sram(cali); + + dramc_impedance_tracking_enable(); + dramc_dbg("IMPEDANCE_TRACKING: ON\n"); + dramc_impedance_hw_saving(); + + switch_hmr4(cali, true); + dramc_dbg("TEMP_SENSOR: ON\n"); + + dramc_dbg("Refresh Rate DeBounce: ON\n"); + dramc_refresh_rate_debounce_enable(); + + enable_dfs_no_queue_flush(); + dramc_dbg("DFS_NO_QUEUE_FLUSH: ON\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x0); + + dramc_dbg("DDR_RESERVE_NEW_MODE: ON\n"); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ddr_reserve, + MISC_DDR_RESERVE_WDT_LITE_EN, 1, + MISC_DDR_RESERVE_WDT_SM_CLR, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7ccf0e2332f789f5ae50ec80479c4cd48bb9b40 Gerrit-Change-Number: 44724 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020