coreboot-gerrit November 2020

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Change in coreboot[master]: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45917 ) Change subject: nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/pineview/memmap.c: Use `postcar_enable_tseg_cache` Also adjust the comments accordingly. Change-Id: I4cf11f205182fb18e92227e4d4dcdc8368a5598b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/memmap.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45917/1 diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index bebe3a5..d26ae01 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -126,12 +126,10 @@ { uintptr_t top_of_ram; - /* - * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both - * CBMEM and the TSEG region. - */ + /* Cache 8 MiB region below the top of RAM to cover CBMEM */ top_of_ram = (uintptr_t)cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), - MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf11f205182fb18e92227e4d4dcdc8368a5598b Gerrit-Change-Number: 45917 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45916 ) Change subject: nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/x4x/memmap.c: Use `postcar_enable_tseg_cache` Also correct comments and clean up cosmetics of the function. Change-Id: I99dfe339c46f1ab4f5bbbd8ae4368e43cd169fc4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/memmap.c 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45916/1 diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index aa737f3..0c62fdc 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -124,12 +124,10 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ + /* Cache 8 MiB region below the top of RAM to cover CBMEM */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99dfe339c46f1ab4f5bbbd8ae4368e43cd169fc4 Gerrit-Change-Number: 45916 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45/memmap.c: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45915 ) Change subject: nb/intel/gm45/memmap.c: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/gm45/memmap.c: Use `postcar_enable_tseg_cache` Also correct comments and clean up cosmetics of this function. Change-Id: I5f559d63bec15351b42b29ad97574ceb2c995039 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/memmap.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45915/1 diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 4fe3998..da5e0ed 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -119,13 +119,10 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ + /* Cache 8 MiB region below the top of RAM to cover CBMEM */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f559d63bec15351b42b29ad97574ceb2c995039 Gerrit-Change-Number: 45915 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945/memmap.c: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45914 ) Change subject: nb/intel/i945/memmap.c: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/i945/memmap.c: Use `postcar_enable_tseg_cache` Also correct comments and clean up cosmetics of this function. Change-Id: I5f3720c02875f546f9dad4bb5582e97d91d39c0d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/memmap.c 1 file changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45914/1 diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index c92e466..af32f39 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -85,11 +85,10 @@ { uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ + /* Cache 8 MiB region below the top of RAM to cover CBMEM */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f3720c02875f546f9dad4bb5582e97d91d39c0d Gerrit-Change-Number: 45914 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/memmap.c: Clean up includes
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45925 ) Change subject: nb/intel/sandybridge/memmap.c: Clean up includes ...................................................................... nb/intel/sandybridge/memmap.c: Clean up includes Drop unused includes and use <types.h> instead. Change-Id: I83d77c8da99567c004e96a15f485f338815036c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/memmap.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45925/1 diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 38fa6e9..eaf146d 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -5,13 +5,11 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <program_loading.h> +#include <types.h> + #include "sandybridge.h" -#include <stddef.h> -#include <stdint.h> static uintptr_t northbridge_get_tseg_base(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83d77c8da99567c004e96a15f485f338815036c1 Gerrit-Change-Number: 45925 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45670 ) Change subject: [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard ...................................................................... [DO NOT MERGE] {soc,mb}/intel/dehydratedlake: Add empty SoC/mainboard This lake got dried up. It contains a fraction of the code in other SoCs and is meant to be used as a base when adding support for new SoCs. It could be slimmed down even further, but this should be good enough. Change-Id: I5b1387b2826a7cad98c40d67cdc476c5d77ce0fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/intel/dehydratedlake_rvp/Kconfig A src/mainboard/intel/dehydratedlake_rvp/Kconfig.name A src/mainboard/intel/dehydratedlake_rvp/board_info.txt A src/mainboard/intel/dehydratedlake_rvp/devicetree.cb A src/mainboard/intel/dehydratedlake_rvp/dsdt.asl A src/soc/intel/dehydratedlake/Kconfig A src/soc/intel/dehydratedlake/Makefile.inc A src/soc/intel/dehydratedlake/acpi.c A src/soc/intel/dehydratedlake/bootblock/bootblock.c A src/soc/intel/dehydratedlake/chip.c A src/soc/intel/dehydratedlake/chip.h A src/soc/intel/dehydratedlake/espi.c A src/soc/intel/dehydratedlake/fsp_params.c A src/soc/intel/dehydratedlake/gpio.c A src/soc/intel/dehydratedlake/i2c.c A src/soc/intel/dehydratedlake/include/soc/cpu.h A src/soc/intel/dehydratedlake/include/soc/gpe.h A src/soc/intel/dehydratedlake/include/soc/gpio.h A src/soc/intel/dehydratedlake/include/soc/gpio_defs.h A src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h A src/soc/intel/dehydratedlake/include/soc/iomap.h A src/soc/intel/dehydratedlake/include/soc/irq.h A src/soc/intel/dehydratedlake/include/soc/itss.h A src/soc/intel/dehydratedlake/include/soc/me.h A src/soc/intel/dehydratedlake/include/soc/nvs.h A src/soc/intel/dehydratedlake/include/soc/p2sb.h A src/soc/intel/dehydratedlake/include/soc/pci_devs.h A src/soc/intel/dehydratedlake/include/soc/pcr_ids.h A src/soc/intel/dehydratedlake/include/soc/pm.h A src/soc/intel/dehydratedlake/include/soc/pmc.h A src/soc/intel/dehydratedlake/include/soc/ramstage.h A src/soc/intel/dehydratedlake/include/soc/smbus.h A src/soc/intel/dehydratedlake/include/soc/soc_chip.h A src/soc/intel/dehydratedlake/include/soc/systemagent.h A src/soc/intel/dehydratedlake/lockdown.c A src/soc/intel/dehydratedlake/p2sb.c A src/soc/intel/dehydratedlake/pmc.c A src/soc/intel/dehydratedlake/pmutil.c A src/soc/intel/dehydratedlake/reset.c A src/soc/intel/dehydratedlake/romstage/Makefile.inc A src/soc/intel/dehydratedlake/romstage/romstage.c A src/soc/intel/dehydratedlake/smihandler.c A src/soc/intel/dehydratedlake/smmrelocate.c A src/soc/intel/dehydratedlake/spi.c 44 files changed, 874 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45670/1 diff --git a/src/mainboard/intel/dehydratedlake_rvp/Kconfig b/src/mainboard/intel/dehydratedlake_rvp/Kconfig new file mode 100644 index 0000000..bab01c9 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/Kconfig @@ -0,0 +1,29 @@ +if BOARD_INTEL_DEHYDRATEDLAKE_RVP + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_DEHYDRATEDLAKE + +config MAINBOARD_DIR + string + default "intel/dehydratedlake_rvp" + +config MAINBOARD_PART_NUMBER + string + default "Dehydrated Lake RVP" + +config MAINBOARD_FAMILY + string + default "Intel_dehydratedlake_rvp" + +config MAX_CPUS + int + default 8 + +config DIMM_SPD_SIZE + int + default 512 +endif diff --git a/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name b/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name new file mode 100644 index 0000000..b2ece12 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DEHYDRATEDLAKE_RVP + bool "Dehydrated Lake RVP" diff --git a/src/mainboard/intel/dehydratedlake_rvp/board_info.txt b/src/mainboard/intel/dehydratedlake_rvp/board_info.txt new file mode 100644 index 0000000..3be4e3e --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Dehydrated Lake RVP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb b/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb new file mode 100644 index 0000000..44c02ff --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/devicetree.cb @@ -0,0 +1,10 @@ +chip soc/intel/dehydratedlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + end +end diff --git a/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl b/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl new file mode 100644 index 0000000..8bb2332 --- /dev/null +++ b/src/mainboard/intel/dehydratedlake_rvp/dsdt.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/soc/intel/dehydratedlake/Kconfig b/src/soc/intel/dehydratedlake/Kconfig new file mode 100644 index 0000000..cad5286 --- /dev/null +++ b/src/soc/intel/dehydratedlake/Kconfig @@ -0,0 +1,119 @@ +config SOC_INTEL_DEHYDRATEDLAKE + bool + help + Intel Dehydrated Lake support + +if SOC_INTEL_DEHYDRATEDLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP + select GENERIC_GPIO_LIB + select HAVE_FSP_GOP + select HAVE_INTEL_FSP_REPO + select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_SMI_HANDLER + select IDT_IN_EVERY_STAGE + select INTEL_GMA_ACPI + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select IOAPIC + select MRC_SETTINGS_PROTECT + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select MICROCODE_BLOB_UNDISCLOSED + select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE + select REG_SCRIPT + select PMC_GLOBAL_RESET_ENABLE_LOCK + select CPU_INTEL_COMMON_SMM + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_THERMAL + select SOC_INTEL_COMMON_PCH_BASE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_CAR + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select UDK_2017_BINDING + select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + select USE_CAR_NEM_ENHANCED_V1 + +config DCACHE_RAM_BASE + default 0xdead0000 + +config DCACHE_RAM_SIZE + default 0x8000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config MAX_ROOT_PORTS + int + default 1 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config PCR_BASE_ADDRESS + hex + default 0xdeadbeef + help + This option allows you to select MMIO Base Address of sideband bus. + +config MMCONF_BASE_ADDRESS + hex + default 0xdeadbeef + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config FSP_HEADER_PATH + default "3rdparty/fsp/IceLakeFspBinPkg/Include" + +config FSP_FD_PATH + default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" + +config CONSOLE_UART_BASE_ADDRESS + hex + default 0xfe032000 + depends on INTEL_LPSS_UART_FOR_CONSOLE + +# Clock divider parameters for 115200 baud rate +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 + +endif diff --git a/src/soc/intel/dehydratedlake/Makefile.inc b/src/soc/intel/dehydratedlake/Makefile.inc new file mode 100644 index 0000000..be8b70e --- /dev/null +++ b/src/soc/intel/dehydratedlake/Makefile.inc @@ -0,0 +1,44 @@ +ifeq ($(CONFIG_SOC_INTEL_DEHYDRATEDLAKE),y) + +subdirs-y += romstage +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += i2c.c +all-y += pmutil.c + +bootblock-y += bootblock/bootblock.c +bootblock-y += espi.c +bootblock-y += gpio.c +bootblock-y += p2sb.c + +romstage-y += espi.c +romstage-y += gpio.c +romstage-y += reset.c + +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += espi.c +ramstage-y += fsp_params.c +ramstage-y += gpio.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += smmrelocate.c +ramstage-y += spi.c + +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmc.c +smm-y += pmutil.c +smm-y += smihandler.c + +CPPFLAGS_common += -I$(src)/soc/intel/dehydratedlake/include + +endif diff --git a/src/soc/intel/dehydratedlake/acpi.c b/src/soc/intel/dehydratedlake/acpi.c new file mode 100644 index 0000000..6e0ec29 --- /dev/null +++ b/src/soc/intel/dehydratedlake/acpi.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <intelblocks/acpi.h> + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + entries = 0; + return NULL; +} + +void soc_power_states_generation(int core_id, int cores_per_package) +{ +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ +} + +uint32_t soc_read_sci_irq_select(void) +{ + return 0; +} + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, const struct chipset_power_state *ps) +{ + return 0; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + return 0; +} diff --git a/src/soc/intel/dehydratedlake/bootblock/bootblock.c b/src/soc/intel/dehydratedlake/bootblock/bootblock.c new file mode 100644 index 0000000..9780e3b --- /dev/null +++ b/src/soc/intel/dehydratedlake/bootblock/bootblock.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ +} + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/chip.c b/src/soc/intel/dehydratedlake/chip.c new file mode 100644 index 0000000..b93498d --- /dev/null +++ b/src/soc/intel/dehydratedlake/chip.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/acpi.h> + +#if CONFIG(HAVE_ACPI_TABLES) +const char *soc_acpi_name(const struct device *dev) +{ + return NULL; +} +#endif + +struct chip_operations soc_intel_dehydratedlake_ops = { + CHIP_NAME("Intel Dehydrated Lake") +}; diff --git a/src/soc/intel/dehydratedlake/chip.h b/src/soc/intel/dehydratedlake/chip.h new file mode 100644 index 0000000..09f5249 --- /dev/null +++ b/src/soc/intel/dehydratedlake/chip.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <intelblocks/cfg.h> +#include <stdint.h> + +struct soc_intel_dehydratedlake_config { + + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /* TCC activation offset */ + uint32_t tcc_offset; +}; + +typedef struct soc_intel_dehydratedlake_config config_t; + +#endif diff --git a/src/soc/intel/dehydratedlake/espi.c b/src/soc/intel/dehydratedlake/espi.c new file mode 100644 index 0000000..969d314 --- /dev/null +++ b/src/soc/intel/dehydratedlake/espi.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <intelblocks/lpc_lib.h> + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges() +{ + return NULL; +} + +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ +} diff --git a/src/soc/intel/dehydratedlake/fsp_params.c b/src/soc/intel/dehydratedlake/fsp_params.c new file mode 100644 index 0000000..d12cf8f --- /dev/null +++ b/src/soc/intel/dehydratedlake/fsp_params.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <intelblocks/lpss.h> + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = 0; + return NULL; +} diff --git a/src/soc/intel/dehydratedlake/gpio.c b/src/soc/intel/dehydratedlake/gpio.c new file mode 100644 index 0000000..e375d9f --- /dev/null +++ b/src/soc/intel/dehydratedlake/gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <stddef.h> + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = 0; + return NULL; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/soc/intel/dehydratedlake/i2c.c b/src/soc/intel/dehydratedlake/i2c.c new file mode 100644 index 0000000..54ec270 --- /dev/null +++ b/src/soc/intel/dehydratedlake/i2c.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/i2c/designware/dw_i2c.h> + +int dw_i2c_soc_devfn_to_bus(unsigned int devfn) +{ + return -1; +} + +int dw_i2c_soc_bus_to_devfn(unsigned int bus) +{ + return -1; +} diff --git a/src/soc/intel/dehydratedlake/include/soc/cpu.h b/src/soc/intel/dehydratedlake/include/soc/cpu.h new file mode 100644 index 0000000..5826e55 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/cpu.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_CPU_H_ +#define _SOC_DEHYDRATEDLAKE_CPU_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpe.h b/src/soc/intel/dehydratedlake/include/soc/gpe.h new file mode 100644 index 0000000..925af18 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpe.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +#define GPE_MAX 0 + +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio.h b/src/soc/intel/dehydratedlake/include/soc/gpio.h new file mode 100644 index 0000000..cffe631 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h b/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..a542edf --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio_defs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_DEFS_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 2 + +#define NUM_GPI_STATUS_REGS 1 + +#define GPIO_MISCCFG 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h b/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..2233cc6 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_DEHYDRATEDLAKE_GPIO_SOC_DEFS_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/iomap.h b/src/soc/intel/dehydratedlake/include/soc/iomap.h new file mode 100644 index 0000000..dd97f42 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/iomap.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_IOMAP_H_ +#define _SOC_DEHYDRATEDLAKE_IOMAP_H_ + +#define EARLY_I2C_BASE(x) 0 + +#define MCH_BASE_ADDRESS 0 + +#define HECI1_BASE_ADDRESS 0 + +#define ACPI_BASE_ADDRESS 0 + +#define TCO_BASE_ADDRESS 0 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS +#define P2SB_SIZE (-4 * MiB) + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/irq.h b/src/soc/intel/dehydratedlake/include/soc/irq.h new file mode 100644 index 0000000..7dfb121 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/irq.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define LPSS_UART0_IRQ -2 +#define LPSS_UART1_IRQ -4 +#define LPSS_UART2_IRQ -6 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/itss.h b/src/soc/intel/dehydratedlake/include/soc/itss.h new file mode 100644 index 0000000..f29e1c3 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/itss.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ITSS_H_ +#define _SOC_ITSS_H_ + +#define ITSS_MAX_IRQ 0 +#define IRQS_PER_IPC 1 +#define NUM_IPC_REGS 0 + +#endif /* _SOC_ITSS_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/me.h b/src/soc/intel/dehydratedlake/include/soc/me.h new file mode 100644 index 0000000..9be7b67 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/me.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DEHYDRATEDLAKE_ME_H_ +#define _DEHYDRATEDLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 reserved1: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +/* ME Host Firmware Status Register 3 */ +union me_hfsts3 { + u32 data; + struct { + u32 reserved_0: 4; + u32 fw_sku: 3; + u32 reserved_7: 2; + u32 reserved_9: 2; + u32 resered_11: 3; + u32 resered_14: 16; + u32 reserved_30: 2; + } __packed fields; +}; + +#endif /* _DEHYDRATEDLAKE_ME_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/nvs.h b/src/soc/intel/dehydratedlake/include/soc/nvs.h new file mode 100644 index 0000000..5129458 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/nvs.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include <intelblocks/nvs.h> + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/p2sb.h b/src/soc/intel/dehydratedlake/include/soc/p2sb.h new file mode 100644 index 0000000..0114693 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/p2sb.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_P2SB_H_ +#define _SOC_DEHYDRATEDLAKE_P2SB_H_ + +#define HPTC_OFFSET 0 +#define HPTC_ADDR_ENABLE_BIT 0 + +#define PCH_P2SB_EPMASK0 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pci_devs.h b/src/soc/intel/dehydratedlake/include/soc/pci_devs.h new file mode 100644 index 0000000..5c929b6 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pci_devs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_PCI_DEVS_H_ +#define _SOC_DEHYDRATEDLAKE_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#else +#define _PCH_DEV(slot, func) PCI_DEV(-98, PCH_DEV_SLOT_ ## slot, func) +#endif + +/* System Agent Devices */ +#define SA_DEV_SLOT_ROOT 0x54 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, -45) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(-117, SA_DEV_SLOT_ROOT, -103) +#endif + +#define SA_DEV_SLOT_IGD -2 +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, -39) +#define SA_DEV_IGD PCI_DEV(42, SA_DEV_SLOT_IGD, 67) + +/* PCH Devices */ +#define PCH_DEV_SLOT_THERMAL 93 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 121) +#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, -78) + +#define PCH_DEV_SLOT_XHCI 0xf3 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 88) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 97) + +#define PCH_DEV_SLOT_CSE 0xe2 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, -3) +#define PCH_DEV_CSE _PCH_DEV(CSE, -5) + +#define PCH_DEV_SLOT_SIO2 0x66 +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, -62) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, -32) + +#define PCH_DEV_SLOT_SIO3 0x99 +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 50) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, -1) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 45) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, -37) + +#define PCH_DEV_SLOT_ESPI 0xaa +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, -1) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, -4) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, -9) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, -2) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, -6) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, -7) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, -3) +#define PCH_DEV_SPI _PCH_DEV(ESPI, -8) + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h b/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h new file mode 100644 index 0000000..ae4f939 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pcr_ids.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_DEHYDRATEDLAKE_PCR_H +#define SOC_DEHYDRATEDLAKE_PCR_H + +#define PID_DMI 0 +#define PID_PSTH 0 +#define PID_CSME0 0 +#define PID_RTC 0 +#define PID_ITSS 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pm.h b/src/soc/intel/dehydratedlake/include/soc/pm.h new file mode 100644 index 0000000..c5685c4 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pm.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#define PM1_STS 0 +#define WAK_STS 0 +#define PWRBTN_STS 0 +#define PM1_EN 0 +#define PWRBTN_EN 0 +#define GBL_EN 0 +#define PM1_CNT 0 +#define SCI_EN 0 +#define SMI_EN 0 +#define ESPI_SMI_EN 0 +#define PERIODIC_EN 0 +#define TCO_SMI_EN 0 +#define MCSMI_EN 0 +#define APMC_EN 0 +#define SLP_SMI_EN 0 +#define EOS 0 +#define SMI_STS 0 +#define APM_STS_BIT 0 +#define SMI_ON_SLP_EN_STS_BIT 0 + +#define GPE0_REG_MAX 0 +#define GPE0_STS(x) 0 +#define GPE_STD 0 +#define GPE0_EN(x) 0 +#define PME_B0_EN 0 + +#define EN_BLOCK 0 + +#define ENABLE_SMI_PARAMS 0 + +#define PSS_RATIO_STEP 0 +#define PSS_MAX_ENTRIES 0 +#define PSS_LATENCY_TRANSITION 0 +#define PSS_LATENCY_BUSMASTER 0 + +#if !defined(__ACPI__) + +#include <acpi/acpi.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/pmc.h> + +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __packed; + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +#endif /* !defined(__ACPI__) */ +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/pmc.h b/src/soc/intel/dehydratedlake/include/soc/pmc.h new file mode 100644 index 0000000..f6d203e --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/pmc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_PMC_H_ +#define _SOC_DEHYDRATEDLAKE_PMC_H_ + +#define ETR 0 +#define CF9_LOCK 0 +#define CF9_GLB_RST 0 + +#define PRSTS 0 + +#define GPIO_GPE_CFG 0 +#define GPE0_DWX_MASK 0 +#define GPE0_DW_SHIFT(x) 0 + +#define SCI_IRQ_ADJUST 0 +#define SCI_IRQ_SEL 0 + +#define SCIS_IRQ9 -8 +#define SCIS_IRQ10 -1 +#define SCIS_IRQ11 -2 +#define SCIS_IRQ20 -4 +#define SCIS_IRQ21 -5 +#define SCIS_IRQ22 -6 +#define SCIS_IRQ23 -7 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/ramstage.h b/src/soc/intel/dehydratedlake/include/soc/ramstage.h new file mode 100644 index 0000000..258a672 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/ramstage.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/smbus.h b/src/soc/intel/dehydratedlake/include/soc/smbus.h new file mode 100644 index 0000000..41f0d0a --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/smbus.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_SMBUS_H_ +#define _SOC_DEHYDRATEDLAKE_SMBUS_H_ + +#define TCO1_STS 0 +#define TCO_TIMEOUT 0 +#define TCO2_STS 0 +#define TCO_STS_SECOND_TO 0 +#define TCO_INTRD_DET 0 +#define TCO1_CNT 0 +#define TCO_LOCK 0 +#define TCO_TMR_HLT 0 +#define TCO2_CNT 0 +#define TCO_INTRD_SEL_MASK 0 +#define TCO_INTRD_SEL_SMI 0 +#define TCO_INTRD_SEL_INT 0 + +#define SMBUS_SLAVE_ADDR 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/include/soc/soc_chip.h b/src/soc/intel/dehydratedlake/include/soc/soc_chip.h new file mode 100644 index 0000000..9676c46 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ +#define _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ + +#include "../../chip.h" + +#endif /* _SOC_DEHYDRATEDLAKE_SOC_CHIP_H_ */ diff --git a/src/soc/intel/dehydratedlake/include/soc/systemagent.h b/src/soc/intel/dehydratedlake/include/soc/systemagent.h new file mode 100644 index 0000000..a6e6402 --- /dev/null +++ b/src/soc/intel/dehydratedlake/include/soc/systemagent.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_DEHYDRATEDLAKE_SYSTEMAGENT_H +#define SOC_DEHYDRATEDLAKE_SYSTEMAGENT_H + +#define CAPID0_A 0 + +#define BIOS_RESET_CPL 0 + +#endif diff --git a/src/soc/intel/dehydratedlake/lockdown.c b/src/soc/intel/dehydratedlake/lockdown.c new file mode 100644 index 0000000..f5012f5 --- /dev/null +++ b/src/soc/intel/dehydratedlake/lockdown.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelpch/lockdown.h> + +void soc_lockdown_config(int chipset_lockdown) +{ +} diff --git a/src/soc/intel/dehydratedlake/p2sb.c b/src/soc/intel/dehydratedlake/p2sb.c new file mode 100644 index 0000000..5ce4990 --- /dev/null +++ b/src/soc/intel/dehydratedlake/p2sb.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/p2sb.h> + +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count) +{ +} diff --git a/src/soc/intel/dehydratedlake/pmc.c b/src/soc/intel/dehydratedlake/pmc.c new file mode 100644 index 0000000..4cebc30 --- /dev/null +++ b/src/soc/intel/dehydratedlake/pmc.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pmclib.h> +#include <stdbool.h> + +void pmc_soc_set_afterg3_en(const bool on) +{ +} diff --git a/src/soc/intel/dehydratedlake/pmutil.c b/src/soc/intel/dehydratedlake/pmutil.c new file mode 100644 index 0000000..bec6841 --- /dev/null +++ b/src/soc/intel/dehydratedlake/pmutil.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <soc/pm.h> + +const char *const *soc_smi_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +const char *const *soc_tco_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +const char *const *soc_std_gpe_sts_array(size_t *a) +{ + *a = 0; + return NULL; +} + +uint8_t *pmc_mmio_regs(void) +{ + return NULL; +} + +uintptr_t soc_read_pmc_base(void) +{ + return 0; +} + +uint32_t *soc_pmc_etr_addr(void) +{ + return NULL; +} + +void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ +} + +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) +{ + return ACPI_S5; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ +} diff --git a/src/soc/intel/dehydratedlake/reset.c b/src/soc/intel/dehydratedlake/reset.c new file mode 100644 index 0000000..ed8a30e --- /dev/null +++ b/src/soc/intel/dehydratedlake/reset.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/util.h> +#include <soc/intel/common/reset.h> + +void do_global_reset(void) +{ +} + +void chipset_handle_reset(uint32_t status) +{ +} diff --git a/src/soc/intel/dehydratedlake/romstage/Makefile.inc b/src/soc/intel/dehydratedlake/romstage/Makefile.inc new file mode 100644 index 0000000..da933d5 --- /dev/null +++ b/src/soc/intel/dehydratedlake/romstage/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c diff --git a/src/soc/intel/dehydratedlake/romstage/romstage.c b/src/soc/intel/dehydratedlake/romstage/romstage.c new file mode 100644 index 0000000..056da92 --- /dev/null +++ b/src/soc/intel/dehydratedlake/romstage/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/romstage.h> + +void mainboard_romstage_entry(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/smihandler.c b/src/soc/intel/dehydratedlake/smihandler.c new file mode 100644 index 0000000..c0e91f9 --- /dev/null +++ b/src/soc/intel/dehydratedlake/smihandler.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/smihandler.h> + +const smi_handler_t southbridge_smi[32] = {}; diff --git a/src/soc/intel/dehydratedlake/smmrelocate.c b/src/soc/intel/dehydratedlake/smmrelocate.c new file mode 100644 index 0000000..e15e70f --- /dev/null +++ b/src/soc/intel/dehydratedlake/smmrelocate.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/intel/smm_reloc.h> +#include <types.h> + +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +{ +} + +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) +{ +} + +void smm_initialize(void) +{ +} + +void smm_relocate(void) +{ +} diff --git a/src/soc/intel/dehydratedlake/spi.c b/src/soc/intel/dehydratedlake/spi.c new file mode 100644 index 0000000..a95be42 --- /dev/null +++ b/src/soc/intel/dehydratedlake/spi.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/spi.h> + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + return -1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b1387b2826a7cad98c40d67cdc476c5d77ce0fd Gerrit-Change-Number: 45670 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45425 ) Change subject: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files ...................................................................... nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/x4x/registers/dmibar.h A src/northbridge/intel/x4x/registers/epbar.h A src/northbridge/intel/x4x/registers/mchbar.h M src/northbridge/intel/x4x/x4x.h 4 files changed, 113 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45425/1 diff --git a/src/northbridge/intel/x4x/registers/dmibar.h b/src/northbridge/intel/x4x/registers/dmibar.h new file mode 100644 index 0000000..6fef8d3 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/dmibar.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_DMIBAR_H__ +#define __X4X_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#endif /* __X4X_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/epbar.h b/src/northbridge/intel/x4x/registers/epbar.h new file mode 100644 index 0000000..14ba313 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/epbar.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_EPBAR_H__ +#define __X4X_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + +#endif /* __X4X_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/mchbar.h b/src/northbridge/intel/x4x/registers/mchbar.h new file mode 100644 index 0000000..e44078c --- /dev/null +++ b/src/northbridge/intel/x4x/registers/mchbar.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_MCHBAR_H__ +#define __X4X_REGISTERS_MCHBAR_H__ + +#define CHDECMISC 0x111 +#define STACKED_MEM (1 << 1) + +#define C0DRB0 0x200 +#define C0DRB1 0x202 +#define C0DRB2 0x204 +#define C0DRB3 0x206 +#define C0DRA01 0x208 +#define C0DRA23 0x20a +#define C0CKECTRL 0x260 + +#define C1DRB0 0x600 +#define C1DRB1 0x602 +#define C1DRB2 0x604 +#define C1DRB3 0x606 +#define C1DRA01 0x608 +#define C1DRA23 0x60a +#define C1CKECTRL 0x660 + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ + +#endif /* __X4X_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index ea34fe0..948f5f8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -57,37 +57,7 @@ #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define CHDECMISC 0x111 -#define STACKED_MEM (1 << 1) - -#define C0DRB0 0x200 -#define C0DRB1 0x202 -#define C0DRB2 0x204 -#define C0DRB3 0x206 -#define C0DRA01 0x208 -#define C0DRA23 0x20a -#define C0CKECTRL 0x260 - -#define C1DRB0 0x600 -#define C1DRB1 0x602 -#define C1DRB2 0x604 -#define C1DRB3 0x606 -#define C1DRA01 0x608 -#define C1DRA23 0x60a -#define C1CKECTRL 0x660 - -#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 8) -#define PMSTS_BOTH_SELFREFRESH (3 << 0) - -#define CLKCFG_MCHBAR 0x0c00 -#define CLKCFG_FSBCLK_SHIFT 0 -#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) -#define CLKCFG_MEMCLK_SHIFT 4 -#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) -#define CLKCFG_UPDATE (1 << 12) - -#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ +#include "registers/mchbar.h" /* * DMIBAR @@ -97,42 +67,7 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIVCPRCAP 0x028 /* 32bit */ -#define DMIVCPRCTL 0x02c /* 32bit */ -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP (1 << 1) - -#define DMIVCMRCAP 0x034 /* 32bit */ -#define DMIVCMRCTL 0x038 /* 32bit */ -#define DMIVCMRSTS 0x03e /* 16bit */ -#define VCMNP (1 << 1) - -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMIUESTS 0x1c4 /* 32bit */ -#define DMICESTS 0x1d0 /* 32bit */ +#include "registers/dmibar.h" /* * EPBAR @@ -142,28 +77,7 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCTL 0x00c /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1ITC 0x02c /* 32bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ +#include "registers/epbar.h" void x4x_early_init(void); void x4x_late_init(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/45425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Gerrit-Change-Number: 45425 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: nb/intel/gm45: Put register definitions into separate files
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45450 ) Change subject: nb/intel/gm45: Put register definitions into separate files ...................................................................... nb/intel/gm45: Put register definitions into separate files MCHBAR registers are scattered throughout raminit, and located next to the code using them. Therefore, they have not been moved in this patch. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I9bb3c907565ef2a278b748b1b7771dbd11d42df9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h A src/northbridge/intel/gm45/registers/dmibar.h A src/northbridge/intel/gm45/registers/epbar.h A src/northbridge/intel/gm45/registers/host_bridge.h 4 files changed, 93 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45450/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 4c16abf..061bf2d 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -184,27 +184,8 @@ /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 + +#include "registers/host_bridge.h" /* * D1:F0 PEG @@ -361,29 +342,7 @@ #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) -#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ +#include "registers/dmibar.h" /* * EPBAR @@ -393,30 +352,7 @@ #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) -#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCTL 0x00c /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1ITC 0x02c /* 32bit */ - -#define EPVC1IST 0x038 /* 64bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ +#include "registers/epbar.h" #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/registers/dmibar.h b/src/northbridge/intel/gm45/registers/dmibar.h new file mode 100644 index 0000000..2ece871 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/dmibar.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_DMIBAR_H__ +#define __GM45_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#endif /* __GM45_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/gm45/registers/epbar.h b/src/northbridge/intel/gm45/registers/epbar.h new file mode 100644 index 0000000..6342844 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/epbar.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_EPBAR_H__ +#define __GM45_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + +#endif /* __GM45_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/gm45/registers/host_bridge.h b/src/northbridge/intel/gm45/registers/host_bridge.h new file mode 100644 index 0000000..4d50d39 --- /dev/null +++ b/src/northbridge/intel/gm45/registers/host_bridge.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __GM45_REGISTERS_HOST_BRIDGE_H__ +#define __GM45_REGISTERS_HOST_BRIDGE_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +#endif /* __GM45_REGISTERS_HOST_BRIDGE_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bb3c907565ef2a278b748b1b7771dbd11d42df9 Gerrit-Change-Number: 45450 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: pcm_suspend_v1.45_20201028_mtcmosapi
by Roger Lu (Code Review) 11 Mar '21

11 Mar '21

Hello Roger Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46876 to review the following change. Change subject: pcm_suspend_v1.45_20201028_mtcmosapi ...................................................................... pcm_suspend_v1.45_20201028_mtcmosapi Change-Id: Iabd48e9ad8e79027d46f4a4a658a69d9b8a9797c --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 330 insertions(+), 330 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46876/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 578a637..5613027 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -12,12 +12,12 @@ 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, 0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e, - 0x3a03001e, 0x0002001e, 0x3609001e, 0xfa01001e, 0xf601001e, 0xf201001e, + 0x3a03001e, 0x0002001e, 0x3c09001e, 0xfa01001e, 0xf601001e, 0xf201001e, 0xee01001e, 0x000f0f98, 0x300d0e00, 0x000fee00, 0x380d0100, 0x000f1160, 0x380d0200, 0x001c22d8, 0x01041218, 0x1c0423e1, 0x000c3262, 0x801c3303, 0xf0064014, 0x00090104, 0x831d2201, 0x801c40f8, 0xd0066010, 0x00090101, 0x831d3301, 0x150460f8, 0x000d0140, 0x18041101, 0x03931020, 0x001f0493, - 0x1393b912, 0x0400001f, 0x0000001e, 0xc0051198, 0x3fa02000, 0x00008005, + 0x1393bf12, 0x0400001f, 0x0000001e, 0xc0051198, 0x3fa02000, 0x00008005, 0x0000a005, 0x0000a005, 0x0000a005, 0xe1a70292, 0x0300f2a7, 0x82ac018c, 0x84ad03ad, 0x86ae05ae, 0x02ace2a5, 0x018b0300, 0x000802a8, 0x02ac2201, 0xf2a5e1a5, 0xa005ee97, 0x00000000, 0x01200000, 0x31060013, 0x0621500f, @@ -40,8 +40,8 @@ 0x21ac1144, 0x80c921a8, 0x31a821ac, 0x31b408c9, 0x2fa031a8, 0x31b680c9, 0x31681e04, 0x0600300f, 0x668c6908, 0x2fa008c9, 0x50ac51ac, 0x08c921a8, 0x21a821b4, 0x21b480c9, 0x20c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, - 0x21b698c9, 0x0f0d21a8, 0x21b41100, 0x08c921a8, 0x21a821b4, 0x21b420c9, - 0x80c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, 0x21b698c9, 0x81860300, + 0x21b698c9, 0x40c921a8, 0x21a821b4, 0x21b408c9, 0x20c921a8, 0x21a821b4, + 0x21b480c9, 0x90c921a8, 0x21a821b4, 0x98c92fa0, 0x008021b6, 0x81860300, 0x000c01a8, 0x31bc1104, 0x3f200040, 0x0100300f, 0x1120640d, 0x9dc906a8, 0x02202fa0, 0x06b66633, 0x28c921a8, 0x21a821b4, 0x21b4b0c9, 0x2fa021a8, 0x21b6c8c9, 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, @@ -91,10 +91,10 @@ 0x7700660d, 0x52650007, 0x50c961a8, 0x61aa61b6, 0xffa571ac, 0xfe972fa0, 0x00800080, 0x38f00049, 0xffa704f0, 0x00c971a8, 0xe3050000, 0x71a871b4, 0xff0188c9, 0x1f17f700, 0x71b495fe, 0x178a71a8, 0xffa577b6, 0xfe972fa0, - 0x00800080, 0x37f00049, 0x61a8ffa7, 0xd1b94080, 0xc014ffa5, 0x00800812, - 0x00a0204c, 0x880466a8, 0x11866601, 0x049366ac, 0x78fe1f17, 0xc3090000, + 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80154080, 0xffa5213a, 0x0810c014, + 0x41980080, 0x880466a8, 0x11866601, 0x049366ac, 0x78fe1f17, 0xc3090000, 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, - 0xfe972fa0, 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80144080, 0xffa5204e, + 0xfe972fa0, 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80154080, 0xffa5214e, 0x0810c014, 0x41980080, 0x880466a8, 0x11866601, 0x000066ac, 0xc0f30180, 0x1130000c, 0x200c8414, 0xc3090000, 0x00a0a14d, 0x48fe1f17, 0x00208249, 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, @@ -103,338 +103,338 @@ 0x00001130, 0x841cc309, 0x439b2006, 0x1afe1f17, 0x00208249, 0x30c961a8, 0x61a861b4, 0x61b6a8c9, 0x2fa0ffa5, 0x0080fe97, 0x006d8014, 0x07140000, 0x0700300f, 0x7780690d, 0x112061a8, 0x61ac61c0, 0x890461a8, 0x890411bd, - 0x61ac119c, 0x17844d06, 0x1102000c, 0xfd0881bb, 0x300f7184, 0x680d0800, - 0x00a08850, 0x890466a8, 0x76bc66fe, 0x890476a8, 0xc349629c, 0x52b60020, - 0x000c06a8, 0x831c6602, 0x00a0c0e6, 0x890461a8, 0x004011bc, 0x89042f20, - 0x61b6119d, 0xaef246f3, 0x418a21a8, 0x51fe7f1d, 0x46f32fa0, 0x07620007, + 0x61ac119c, 0x17844d06, 0x1102000c, 0xfd0821bb, 0x300f7184, 0x680d0800, + 0x00a08850, 0x890466a8, 0xf6be66fe, 0x000c06a8, 0x831c6602, 0x00a0c0f2, + 0x890461a8, 0x004011bc, 0x89042f20, 0x61b6119d, 0x890476a8, 0x8693629c, + 0x52b66ea1, 0xaef246f3, 0x418a21a8, 0x51fe7f1d, 0x46f32fa0, 0x07620007, 0x4670ac49, 0x0200300f, 0x2204670d, 0x07003000, 0x718a11a8, 0x20fc8315, 0x0100300f, 0x12006708, 0x124c2498, 0x670d13ac, 0x1f161304, 0x100fabff, 0x00800700, 0x300f0192, 0x600d0100, 0x93bb11dc, 0x8949ffa7, 0x049908f0, 0x21a8824c, 0x080f18c9, 0x21ac0700, 0x96ff1f17, 0x46920000, 0x13744706, 0x770668c9, 0xffa51374, 0xfe972fa0, 0x00200040, 0x05f08949, 0x0870824c, 0xcc6421a8, 0x040f0020, 0x21ac0700, 0x7eff1f17, 0x46920000, 0x13744706, - 0x770670c9, 0xffa51374, 0xfe972fa0, 0x00800080, 0x300f0192, 0x600d0b00, - 0xf000b934, 0x0b0f0100, 0x000d0616, 0xffa76a08, 0x1910f006, 0xa904f006, - 0xa9ecff06, 0x19084106, 0x51b84080, 0x2fa0ffa5, 0x0080fe97, 0x0d800000, - 0x300f019a, 0x6a0d0600, 0x00076624, 0x56a81d61, 0x000066b9, 0x00070710, - 0x300f1d62, 0x680d0100, 0x06a81150, 0x04003dc9, 0xf1068800, 0xf20661dc, - 0x08ac71d4, 0x2fa0ffa5, 0x0080fe97, 0x8c890300, 0x1c004006, 0x1140000c, - 0x20c88114, 0xb7a86408, 0x1c004006, 0x1100200c, 0x1f1741be, 0x139859fc, - 0x1c004006, 0x1100200c, 0x4006a1be, 0x080c1c00, 0x51be1100, 0x74ff1f17, - 0x00a08149, 0x1c004006, 0x1100200c, 0x4006a1bc, 0x400c1c00, 0x81151100, - 0x67082006, 0x00a0bb08, 0x1c004006, 0x1100200c, 0x030061b9, 0x01a88186, - 0x1100040c, 0x059301bb, 0x44100000, 0x3aff1f17, 0x00a0294c, 0x0100300f, - 0x1150680d, 0x890406a8, 0x06b66691, 0x0200300f, 0x224c680d, 0x11a81398, - 0x00208464, 0x04100000, 0xe8fb1f17, 0x12e0f106, 0x1c004006, 0x11bc8904, - 0xf50f0000, 0x96fb1f17, 0x1c007006, 0x3204f306, 0x890483f3, 0x83f211b6, - 0x400615ac, 0x200c1c00, 0x80151100, 0x0000206a, 0x20000880, 0x02000100, - 0x00070200, 0x04931864, 0xccfc1f17, 0x00a0a14c, 0x0700300f, 0x7720610d, - 0x28640007, 0x61287b4e, 0x87870300, 0x61ac1298, 0x1d430007, 0x20c9618a, - 0x0710000f, 0x0000c7f2, 0x00070104, 0x04002d61, 0x00070280, 0x00077d61, - 0x00071865, 0x00072865, 0x0b451d43, 0x000d0020, 0xc7f26130, 0xf006f19f, - 0xf0061910, 0x7006a904, 0xffa5a900, 0xfe972fa0, 0x00200040, 0xf1050000, - 0x44100000, 0x1b007006, 0xc4fe1f17, 0x05f0514c, 0x00000593, 0x1f174410, - 0xb398bdfe, 0x00000593, 0x1f174410, 0x9398b7fe, 0xf1040000, 0x70060593, - 0x00001b00, 0x1f174410, 0xa398adfe, 0x00000593, 0x1f174410, 0xb398a7fe, - 0x00000593, 0x1f174410, 0x7398a1fe, 0x00000593, 0x1f174410, 0x93989bfe, - 0x31080000, 0x1b48f106, 0x1b004006, 0x11958904, 0x48ff1f16, 0x1b007006, - 0x04f0084c, 0x0020444c, 0x17a8f306, 0x52fc1f17, 0xe3040000, 0x8d610007, - 0x78c961a8, 0x12ff1f16, 0x008061ac, 0x300f0192, 0x60080d00, 0xf000d134, - 0x0b0f0600, 0x000d0716, 0xffa77908, 0x6110f006, 0x8a890300, 0x09ac89b4, - 0x1a004006, 0x1100200c, 0x20848015, 0x41880300, 0x1f170493, 0x03a82bfc, - 0x0100300f, 0x113c610d, 0x890406a8, 0x831466f3, 0x0000c0fa, 0x00000780, - 0x000f0604, 0x00070110, 0x86f26764, 0x16fc1f17, 0x43100000, 0x02000200, - 0x00071198, 0x784e2765, 0xeef386f2, 0x20c9618a, 0x0600300f, 0x6620610d, - 0xc506c6f2, 0x03001618, 0x0300028a, 0x11ac8887, 0x78a811a8, 0x03008189, - 0x20000888, 0x71ac0200, 0x71a853a8, 0x51ac3188, 0x27650007, 0x1a004006, - 0x1100200c, 0x030061b9, 0x01a88186, 0x1100040c, 0x059301bb, 0x44100000, - 0x14fe1f17, 0x00a0214c, 0x0100300f, 0x1150680d, 0x890406a8, 0x06b66692, - 0x1a004006, 0x1100200c, 0x4006a1bc, 0x400c1a00, 0x80151100, 0x670820c6, - 0x00a0dc08, 0x00208249, 0xc4fb1f17, 0x43100000, 0x1a004006, 0x1100200c, - 0x4006a1be, 0x080c1a00, 0x51be1100, 0x04fe1f17, 0x00a0094c, 0x1a004006, - 0x1100200c, 0x1f1741be, 0x0393d3fa, 0x1a004006, 0x1140000c, 0x000021bb, - 0x434c0180, 0x64080470, 0xa8f2d7a8, 0x07a8f306, 0x9cfb1f17, 0xe3040000, - 0x890461a8, 0x61ac1190, 0x01800000, 0x0370034d, 0x0400300f, 0x444c680d, - 0xa872f94f, 0x806431a8, 0x1f170020, 0x31ac7ffa, 0x1a004006, 0x119c8904, - 0x30fa1f17, 0x1af0ff06, 0x14e0c106, 0x580c218c, 0x000d1100, 0xf8061106, - 0x7e061400, 0x7e062408, 0x7e069418, 0xffa5941c, 0xfe972fa0, 0x00200040, - 0xfb050000, 0x70060593, 0x0000bc00, 0x1f174410, 0x839895fd, 0xf1040000, - 0x70060593, 0x00001c00, 0x1f174410, 0x83988bfd, 0xbc007006, 0x05708249, - 0x50fb1f17, 0x43100000, 0x44100000, 0x7efd1f17, 0x00a0694c, 0x00000593, - 0x1f174410, 0xc39877fd, 0xf1040000, 0x70060593, 0x00001c00, 0x1f174410, - 0x63986dfd, 0x00000593, 0x1f174410, 0xd39867fd, 0x3b080000, 0x00000593, - 0x1f174410, 0xc3985ffd, 0xbc48f106, 0x1c004006, 0x11968904, 0x62ff1f16, - 0x1c007006, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1710c9, 0x61b417fb, - 0x8c6461a8, 0x1f170020, 0x61b411fb, 0xa0c961a8, 0x61a861b4, 0x61b488c9, - 0x00c961a8, 0x61a861b4, 0x1f17c0c9, 0x61b403fb, 0xe46461a8, 0x1f170020, - 0x61b4fdfa, 0xe86461a8, 0x1f170020, 0x61b4f7fa, 0xd8c961a8, 0xffa561b6, - 0xf0fa1f16, 0x0080fe97, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1718c9, - 0x61b4e5fa, 0x886461a8, 0x1f170020, 0x61b4dffa, 0x88c961a8, 0x61a861b4, - 0x61b4a0c9, 0x00c961a8, 0xffa561b6, 0xfe972fa0, 0x00800080, 0x80150192, - 0xffa76822, 0x0100300f, 0x11a4640d, 0x801501a8, 0x500f2112, 0x08000600, - 0x61880103, 0x06ac1698, 0x61108014, 0x0100800f, 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0x07ac6128, + 0x09800000, 0x00a00049, 0x0700300f, 0x77a0640d, 0x19400007, 0x8904ffa7, + 0x61a81afe, 0xc6ff1f17, 0x13082120, 0x0800040f, 0x0200100f, 0x0400080f, + 0x200fcab8, 0x00070500, 0x00078962, 0x00072962, 0x0ba14961, 0x59610007, + 0x89610007, 0x29610007, 0x49620007, 0x59620007, 0x1c0d61a8, 0x05001100, + 0x61b606bc, 0x619d8904, 0xff017188, 0x07a8b67f, 0xff0f768a, 0x86b407ef, + 0x76fff70d, 0x768a07a8, 0xffa506b6, 0xfe972fa0, 0x00800080, 0xcfa70492, + 0x72ef1f1f, 0xb6ff1f1f, 0xa6ff1f1f, 0x81890300, 0x0300f1a7, 0xe1a78186, + 0x01800000, 0x06200000, 0x61640007, 0x01100000, 0x0694010f, 0x61650007, + 0x01160b0f, 0x0600300f, 0x110c000d, 0x66446008, 0x400651ac, 0x831576dc, + 0x010fe0fa, 0x300f0794, 0x60080600, 0x51ac6648, 0x01100000, 0x71640007, + 0x16b84506, 0x61acf7a5, 0x16c04506, 0x51b4e6a5, 0x66a8d6a7, 0x0100f80f, + 0x1f17618b, 0x61acb7ed, 0x01a8f1a5, 0x1100040c, 0x00a041be, 0x48fc1f1f, + 0x01a8f1a5, 0x1100040c, 0xf1a581b8, 0x000c01a8, 0x31be1120, 0x60ee1f1f, + 0x01a8d1a5, 0x1140000c, 0x20688314, 0x0600800f, 0x07800000, 0xcfa58049, + 0x67670007, 0x3f20e74b, 0x01000100, 0x01000201, 0x02010201, 0x01000402, + 0x02010402, 0x04020402, 0x01000803, 0x02010803, 0x04020803, 0x01001004, + 0x02011004, 0x04021004, 0x08031004, 0x01002005, 0x02012005, 0x04022005, + 0x08032005, 0x01004006, 0x02014006, 0x04024006, 0x08034006 }; static struct spm_desc spm_firmware = { - .version = "pcm_suspend_v1.43_no_GPU_WAYEN", - .pmem_words = 0x9bf, - .total_words = 0x9d4, + .version = "pcm_suspend_v1.45_20201028_mtcmosapi", + .pmem_words = 0x9c2, + .total_words = 0x9d7, .pmem_start = 0x10000000, .dmem_start = 0x10003800 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd48e9ad8e79027d46f4a4a658a69d9b8a9797c Gerrit-Change-Number: 46876 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add multi freq calibration
by Yidi Lin (Code Review) 11 Mar '21

11 Mar '21

Hello Xi Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46398 to review the following change. Change subject: soc/mediatek/mt8192: Add multi freq calibration ...................................................................... soc/mediatek/mt8192: Add multi freq calibration For calibration highest freq. Signed-off-by: mtk11206 <xixi.chen(a)mediatek.com> Change-Id: Iddab4dd1a331c668b967207e7f1542ea29424b68 --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/dramc_pi_main.c M src/soc/mediatek/mt8192/include/soc/dramc_param.h 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/46398/1 diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig index ea82a8b..6723cc5 100644 --- a/src/soc/mediatek/mt8192/Kconfig +++ b/src/soc/mediatek/mt8192/Kconfig @@ -38,7 +38,7 @@ config MT8192_DRAM_DVFS_LIMIT_FREQ_CNT bool - default n + default y select MT8192_DRAM_DVFS help This options limit DRAM frequency calibration count from total 7 to 3, diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c old mode 100644 new mode 100755 index e4772c2..e7c6ecb --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -480,7 +480,7 @@ after_calib(&cali); enable_dfs_hw_mode_clk(); - if (CONFIG(MT8192_DRAM_DVFS)) { + if (CONFIG(MT8192_DRAM_DVFS) || CONFIG(MT8192_DRAM_DVFS_LIMIT_FREQ_CNT)) { dram_cali_seq bootup_cali_seq = CALI_SEQ5; dram_dfs_shu bootup_shu = get_shu_save_by_k_shu(bootup_cali_seq); diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h old mode 100644 new mode 100755 index b4e982f..2d4f2ca --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -8,7 +8,7 @@ #include <soc/dramc_common_mt8192.h> enum { - DRAMC_PARAM_HEADER_VERSION = 3, + DRAMC_PARAM_HEADER_VERSION = 4, }; enum DRAMC_PARAM_STATUS_CODES { -- To view, visit https://review.coreboot.org/c/coreboot/+/46398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddab4dd1a331c668b967207e7f1542ea29424b68 Gerrit-Change-Number: 46398 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020