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Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Update as per newer reference code
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47032 ) Change subject: sb/intel/lynxpoint/sata.c: Update as per newer reference code ...................................................................... sb/intel/lynxpoint/sata.c: Update as per newer reference code Newer Lynxpoint reference code does some more stuff, which Broadwell already does. Also drop invalid register writes, which were copy-pasted from older southbridges and do not exist anymore on Lynxpoint. Change-Id: I0907905adfa9a21732f1918f143a1df1954275f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 69 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47032/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e..a1d504c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -215,51 +215,10 @@ /* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d8eb2a8..18dbb00 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/abar.h> #include "chip.h" #include "iobp.h" #include "pch.h" @@ -37,50 +38,35 @@ { u32 reg32; - u32 *abar; - /* Get the chip configuration */ config_t *config = dev->chip_info; - printk(BIOS_DEBUG, "SATA: Initializing...\n"); + printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } - /* SATA configuration */ - /* Enable memory space decoding for ABAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); + const uintptr_t abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", (void *)abar); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); + reg32 = pci_read_config32(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); @@ -93,7 +79,7 @@ if (pch_is_lp()) { reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ + reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ } pci_write_config32(dev, 0x98, reg32); @@ -107,31 +93,60 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS + + union abar_reg_cap abar_cap = { + .raw = abar_read32(abar, ABAR_REG_CAP), + }; + + abar_cap.external_sata = 0; /* Should be configurable */ + abar_cap.enclosure_management = 0; + abar_cap.port_multiplier = 0; + abar_cap.interlock_switch = 0; + + abar_cap.partial_state = 1; + abar_cap.slumber_state = 1; + abar_cap.pio_multiple_drq = 1; + abar_cap.cmd_list_override = 1; + abar_cap.interface_speed = 3; + abar_cap.aggressive_link_pm = 1; + abar_cap.staggered_spinup = 1; + if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ + abar_cap.ahci_mode_only = 1; + + abar_write32(abar, ABAR_REG_CAP, abar_cap.raw); + + abar_write_ports_implemented(abar, config->sata_port_map); + + union abar_reg_cap_2 abar_cap_2 = { + .raw = abar_read32(abar, ABAR_REG_CAP_2), + }; + if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; + if (config->sata_devslp_disable) { + abar_cap_2.supports_device_sleep = 0; + + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + } else { + abar_cap_2.auto_partial_to_slumber = 1; + abar_cap_2.supports_device_sleep = 1; + abar_cap_2.aggressive_devslp_mgmt = 1; + abar_cap_2.devslp_entry_slumber_only = 1; + + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + + for (int port = 0; port < 4; port++) { + if (!(config->sata_port_map & (1 << port))) + continue; + + union abar_reg_px_devslp px_devslp = { + .raw = abar_read32(abar, ABAR_REG_PxDEVSLP(port)), + }; + px_devslp.device_sleep_present = 1; + abar_write32(abar, ABAR_REG_PxDEVSLP(port), px_devslp.raw); + } + } } - write32(abar + 0x09, reg32); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) @@ -167,8 +182,9 @@ << SATA_DTLE_EDGE_SHIFT); } - /* Additional Programming Requirements */ - /* Power Optimizer */ + /* + * Additional Programming Requirements for Power Optimizer + */ /* Step 1 */ if (pch_is_lp()) @@ -196,9 +212,14 @@ } reg32 = pci_read_config32(dev, 0x300); - reg32 |= (1 << 17) | (1 << 16); + reg32 |= (1 << 17) | (1 << 16) | (1 << 19); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); + + pci_or_config32(dev, 0x98, 1 << 29); + + /* Register Lock */ + pci_or_config32(dev, 0x9c, 1 << 31); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/47032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0907905adfa9a21732f1918f143a1df1954275f8 Gerrit-Change-Number: 47032 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] common sb/intel fadt
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43470 ) Change subject: [WIP] common sb/intel fadt ...................................................................... [WIP] common sb/intel fadt Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/fadt.c A src/southbridge/intel/common/fadt.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43470/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 9356a2b..a3095bc 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -52,6 +52,9 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_PMBASE +config SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT + bool + config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa..77f0795 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -35,6 +35,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_FADT) += fadt.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c diff --git a/src/southbridge/intel/common/fadt.c b/src/southbridge/intel/common/fadt.c new file mode 100644 index 0000000..31feff6 --- /dev/null +++ b/src/southbridge/intel/common/fadt.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/common/fadt.h> +#include <southbridge/intel/common/pmbase.h> + +/* FIXME: pmutil.h definitions are a mess */ +#define PM1_STS 0x00 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define PM2_CNT 0x50 + +#define PM1A_EVT_BYTES 4 +#define PM1A_CNT_BYTES 2 +#define PM2_CNT_BYTES 1 +#define PM_TMR_BYTES 4 +#define GPE0_BYTES 16 + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const u16 pmbase = lpc_get_pmbase(); + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; +} diff --git a/src/southbridge/intel/common/fadt.h b/src/southbridge/intel/common/fadt.h new file mode 100644 index 0000000..48fe1cd --- /dev/null +++ b/src/southbridge/intel/common/fadt.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_FADT_H +#define SOUTHBRIDGE_INTEL_COMMON_FADT_H + +#endif /* SOUTHBRIDGE_INTEL_COMMON_FADT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b995d526d6781d1f53c017068ed83ea46a93f32 Gerrit-Change-Number: 43470 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Makefile.inc: Enable UBSAN on SMM, too
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43976 ) Change subject: lib/Makefile.inc: Enable UBSAN on SMM, too ...................................................................... lib/Makefile.inc: Enable UBSAN on SMM, too We don't want undefined behavior on such privileged code, do we? Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43976/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 72d4f24..c96aa90 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -4,7 +4,9 @@ ifeq ($(CONFIG_UBSAN),y) ramstage-y += ubsan.c +smm-y += ubsan.c CFLAGS_ramstage += -fsanitize=undefined +CFLAGS_smm += -fsanitize=undefined endif decompressor-y += decompressor.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f4c074ff90365cf96abf1f5bad3e2cde68547d Gerrit-Change-Number: 43976 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sandybridge boards: Drop gpio.c from bootblock
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45671 ) Change subject: sandybridge boards: Drop gpio.c from bootblock ...................................................................... sandybridge boards: Drop gpio.c from bootblock It is only used in romstage. Also update autoport. Change-Id: If6508997ce5b266d1fbf2aac56b22a8b542ae7b1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/Makefile.inc M src/mainboard/asrock/b75pro3-m/Makefile.inc M src/mainboard/asus/h61m-cs/Makefile.inc M src/mainboard/asus/maximus_iv_gene-z/Makefile.inc M src/mainboard/asus/p8h61-m_lx/Makefile.inc M src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc M src/mainboard/asus/p8h61-m_pro/Makefile.inc M src/mainboard/asus/p8z77-m_pro/Makefile.inc M src/mainboard/asus/p8z77-v_lx2/Makefile.inc M src/mainboard/biostar/th61-itx/Makefile.inc M src/mainboard/compulab/intense_pc/Makefile.inc M src/mainboard/dell/optiplex_9010/Makefile.inc M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc M src/mainboard/gigabyte/ga-h61m-series/Makefile.inc M src/mainboard/google/butterfly/Makefile.inc M src/mainboard/google/link/Makefile.inc M src/mainboard/google/parrot/Makefile.inc M src/mainboard/google/stout/Makefile.inc M src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc M src/mainboard/hp/snb_ivb_laptops/Makefile.inc M src/mainboard/hp/z220_sff_workstation/Makefile.inc M src/mainboard/intel/dcp847ske/Makefile.inc M src/mainboard/intel/emeraldlake2/Makefile.inc M src/mainboard/kontron/ktqm77/Makefile.inc M src/mainboard/lenovo/l520/Makefile.inc M src/mainboard/lenovo/s230u/Makefile.inc M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420s/Makefile.inc M src/mainboard/lenovo/t430/Makefile.inc M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t520/Makefile.inc M src/mainboard/lenovo/t530/Makefile.inc M src/mainboard/lenovo/x131e/Makefile.inc M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc M src/mainboard/lenovo/x220/Makefile.inc M src/mainboard/lenovo/x230/Makefile.inc M src/mainboard/msi/ms7707/Makefile.inc M src/mainboard/roda/rv11/Makefile.inc M src/mainboard/samsung/lumpy/Makefile.inc M src/mainboard/samsung/stumpy/Makefile.inc M src/mainboard/sapphire/pureplatinumh61/Makefile.inc M src/mainboard/supermicro/x9scl/Makefile.inc M util/autoport/bd82x6x.go 43 files changed, 0 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45671/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index 665a95f..ab64c56 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gnvs.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index e4b6fbf..a6025c2 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index e09d538..db6dc1d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index e09d538..db6dc1d 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc index 7167e10..45d063e 100644 --- a/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc index 26b20d7..b04939b 100644 --- a/src/mainboard/asus/p8z77-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc index 7167e10..45d063e 100644 --- a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc +++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc @@ -1,5 +1,4 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/src/mainboard/biostar/th61-itx/Makefile.inc b/src/mainboard/biostar/th61-itx/Makefile.inc index 549a84f..5d34b89 100644 --- a/src/mainboard/biostar/th61-itx/Makefile.inc +++ b/src/mainboard/biostar/th61-itx/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += hda_verb.c diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/optiplex_9010/Makefile.inc index 7a8a684..9c21731 100644 --- a/src/mainboard/dell/optiplex_9010/Makefile.inc +++ b/src/mainboard/dell/optiplex_9010/Makefile.inc @@ -2,7 +2,6 @@ smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 5dcf9e2..f1265f4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc index 9916927..0f0fd22 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-series/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 342c9f7..1ca07da 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -4,7 +4,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ee411c2..eec3fcc 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -13,7 +13,6 @@ SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 SPD_SOURCES += micron_4Gb_1600_1.35v_x16 -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index f2166e1..70c3922 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -4,7 +4,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 5c196f0..3f7ef94 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -9,7 +9,6 @@ smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc index c007bb6..c743a26 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Makefile.inc +++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/early_init.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index f0b34f9..3e0a0fa 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 28bc7c7..217f9d2 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,6 +1,5 @@ bootblock-y += early_southbridge.c romstage-y += early_southbridge.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-y += smihandler.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 151a3c3..43224bd 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -2,7 +2,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index e402ffa..ec8df11 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 0126a75..3a538f2 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index 12e7709..b6d9a57 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += ec.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 991eadb..7405a36 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 991eadb..7405a36 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 0f49600..2cf65ae 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 196a098..244cb6b 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index ab5aa4d..3c28088 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index ab5aa4d..3c28088 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index e4b6fbf..a6025c2 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index e9e74dd..5a1764b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += spd smm-y += smihandler.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index d870c4d..c316ad1 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only smm-y += smihandler.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 5316d24..6cd7764 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -2,7 +2,6 @@ smm-y += smihandler.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c -bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 2fa05da..b4f8b65 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1,4 +1,3 @@ -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index cb9c725..edafd79 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += variants/$(VARIANT_DIR)/early_init.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 1fd9498..18b38d8 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index 57ec1c5..63a1216 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -2,7 +2,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 1abca53..04b3798 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc index 3465dfe..38cf7f1 100644 --- a/src/mainboard/supermicro/x9scl/Makefile.inc +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += early_init.c -bootblock-y += gpio.c romstage-y += early_init.c romstage-y += gpio.c diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 5d943e4..55f22b9 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -288,7 +288,6 @@ File: "southbridge/intel/bd82x6x/acpi/pch.asl", }) - AddBootBlockFile("early_init.c", "") AddROMStageFile("early_init.c", "") sb := Create(ctx, "early_init.c") -- To view, visit https://review.coreboot.org/c/coreboot/+/45671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6508997ce5b266d1fbf2aac56b22a8b542ae7b1 Gerrit-Change-Number: 45671 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel: Factor out `select CPU_INTEL_COMMON`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45042 ) Change subject: soc/intel: Factor out `select CPU_INTEL_COMMON` ...................................................................... soc/intel: Factor out `select CPU_INTEL_COMMON` All affected platforms select `SOC_INTEL_COMMON_BLOCK_CPU` already. Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 10 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45042/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 96808cf..964e7d4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,7 +28,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..66030b1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..52896b9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -65,7 +65,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b24..094cf05 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_CPU bool default n + select CPU_INTEL_COMMON help This option selects Intel Common CPU Model support code which provides various CPU related APIs which are common diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e6d3237..3fce223 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -16,7 +16,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 2aeb6d6..8a98304 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index fd5648f..d172322 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..adb43ad 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,7 +26,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..de92090 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..a4274df 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,7 +31,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/45042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Gerrit-Change-Number: 45042 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: nb/intel/*/memmap.c: Use `postcar_frame_add_cbmem_top`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45927 ) Change subject: nb/intel/*/memmap.c: Use `postcar_frame_add_cbmem_top` ...................................................................... nb/intel/*/memmap.c: Use `postcar_frame_add_cbmem_top` Not all cases can be covered by this function. Change-Id: I15ab4b73adf6af3b870be8394aac017754238d8f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c 6 files changed, 6 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45927/1 diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index da5e0ed..acc4199 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -117,11 +117,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM to cover CBMEM */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 8 * MiB); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index af32f39..e2f64a8 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -83,11 +83,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM to cover CBMEM */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 8 * MiB); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 6771a20..e922c4e 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -35,10 +35,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); - /* Cache 8 MiB below the top of RAM */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 8 * MiB); /* Cache TSEG region */ postcar_enable_tseg_cache(pcf); diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index d26ae01..12366fa 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -124,11 +124,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM to cover CBMEM */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 8 * MiB); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index eaf146d..519fb95 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -46,7 +46,7 @@ * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 1); /* * Cache the TSEG region using regular MTRRs. This is only useful diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 0c62fdc..28d4eb3 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -122,11 +122,8 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM to cover CBMEM */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_cbmem_top(pcf, 8 * MiB, 8 * MiB); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/45927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ab4b73adf6af3b870be8394aac017754238d8f Gerrit-Change-Number: 45927 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: arch/x86: Define `postcar_frame_add_cbmem_top`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45926 ) Change subject: arch/x86: Define `postcar_frame_add_cbmem_top` ...................................................................... arch/x86: Define `postcar_frame_add_cbmem_top` This function is to be used to cache a region below cbmem_top(). Change-Id: I3eab4e55c3670094e32ba86550c3d602c0bbef07 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar_loader.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45926/1 diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 28d29bf..cb4aa73 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -33,6 +33,10 @@ */ void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type); +/* + * Add variable MTRR covering the given down-aligned size below cbmem_top(). + */ +void postcar_frame_add_cbmem_top(struct postcar_frame *pcf, size_t size, uintptr_t alignment); /* * Add variable MTRR covering the memory-mapped ROM with given MTRR type. diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 241ba8c..366f378 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -153,6 +153,13 @@ stage_cache_add(STAGE_POSTCAR, prog); } +void postcar_frame_add_cbmem_top(struct postcar_frame *pcf, size_t size, uintptr_t alignment) +{ + uintptr_t top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), alignment); + + postcar_frame_add_mtrr(pcf, top_of_ram - size, size, MTRR_TYPE_WRBACK); +} + /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. -- To view, visit https://review.coreboot.org/c/coreboot/+/45926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eab4e55c3670094e32ba86550c3d602c0bbef07 Gerrit-Change-Number: 45926 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/sandybridge: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45924 ) Change subject: nb/intel/sandybridge: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/sandybridge: Use `postcar_enable_tseg_cache` This may not be necessary at all if all CPUs using this code support SMRRs. Update the corresponding code to reflect that with a TODO. Change-Id: Ibf5a851a6684c9aa96d1c30a8f8dc068d00f3b81 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/memmap.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/45924/1 diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 7f46d66..38fa6e9 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -51,11 +51,9 @@ postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); /* - * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems - * is where the TSEG region resides. However, it is not restricted - * to SMM mode until SMM has been relocated. By setting the region - * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. + * Cache the TSEG region using regular MTRRs. This is only useful + * when SMRRs are not supported, however. TODO(hell__): Determine + * if all SNB/IVB CPUs support SMRRs, and if so remove this call. */ - postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf5a851a6684c9aa96d1c30a8f8dc068d00f3b81 Gerrit-Change-Number: 45924 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/ironlake: Clean up cosmetics of `fill_postcar_frame`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45922 ) Change subject: nb/intel/ironlake: Clean up cosmetics of `fill_postcar_frame` ...................................................................... nb/intel/ironlake: Clean up cosmetics of `fill_postcar_frame` Change-Id: Ic387d2783692344b7204899b0729998852c72f33 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/memmap.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/45922/1 diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 4ec8e3a..6771a20 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -35,11 +35,10 @@ void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; + uintptr_t top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); /* Cache 8 MiB below the top of RAM */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); /* Cache TSEG region */ postcar_enable_tseg_cache(pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/45922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic387d2783692344b7204899b0729998852c72f33 Gerrit-Change-Number: 45922 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache`
by Angel Pons (Code Review) 12 Mar '21

12 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45921 ) Change subject: nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache` ...................................................................... nb/intel/ironlake/memmap.c: Use `postcar_enable_tseg_cache` With SMM_TSEG_SIZE being fixed at 8 MiB, the code caches 8 MiB below TSEG and the TSEG region itself. Make the latter more obvious. Change-Id: I7ac7db0237f4b948eba06f728a16e3760708c016 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/memmap.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45921/1 diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 221ae92..4ec8e3a 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -37,11 +37,10 @@ { uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ + /* Cache 8 MiB below the top of RAM */ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Cache TSEG region */ + postcar_enable_tseg_cache(pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ac7db0237f4b948eba06f728a16e3760708c016 Gerrit-Change-Number: 45921 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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