coreboot-gerrit November 2020

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Change in coreboot[master]: drivers/analogix: improve the clock tolance from 0.1% to 2%
by jitao shi (Code Review) 27 Mar '21

27 Mar '21

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39025 ) Change subject: drivers/analogix: improve the clock tolance from 0.1% to 2% ...................................................................... drivers/analogix: improve the clock tolance from 0.1% to 2% Improve the input tolance to avoid panel scroll. BUG=b:149051882 BRANCH=kukui TEST=None Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39025/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9387a83b..d2d09d8 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -395,7 +395,7 @@ ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0, (n & 0xff)); /* diff */ - ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x37); + ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d); ret |= anx7625_odfc_config(bus, post_divider - 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/39025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4af96f58876932175b28fc0a8543720ebd7b5deb Gerrit-Change-Number: 39025 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: getac/p470: Let clang-format handle the coding style
by Patrick Georgi (Code Review) 26 Mar '21

26 Mar '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31652 Change subject: getac/p470: Let clang-format handle the coding style ...................................................................... getac/p470: Let clang-format handle the coding style Also make the format mandatory for the board. Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A .clang-format-scope M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/getac/p470/cstates.c M src/mainboard/getac/p470/ec_oem.c M src/mainboard/getac/p470/ec_oem.h M src/mainboard/getac/p470/gpio.c M src/mainboard/getac/p470/hda_verb.c M src/mainboard/getac/p470/irq_tables.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/mainboard.h M src/mainboard/getac/p470/mptable.c M src/mainboard/getac/p470/romstage.c M src/mainboard/getac/p470/smihandler.c 13 files changed, 179 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/1 diff --git a/.clang-format-scope b/.clang-format-scope new file mode 100644 index 0000000..96c588c --- /dev/null +++ b/.clang-format-scope @@ -0,0 +1 @@ +src/mainboard/getac diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 162c20a..460f345 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -33,7 +33,7 @@ gnvs->cmbp = 0x00; } -static long acpi_create_ecdt(acpi_ecdt_t * ecdt) +static long acpi_create_ecdt(acpi_ecdt_t *ecdt) { /* Attention: Make sure these match the values from * the DSDT's ec.asl @@ -43,7 +43,7 @@ acpi_header_t *header = &(ecdt->header); - memset((void *) ecdt, 0, ecdt_len); + memset((void *)ecdt, 0, ecdt_len); /* fill out header fields */ memcpy(header->signature, "ECDT", 4); @@ -61,7 +61,7 @@ ecdt->ec_control.addrl = 0x66; ecdt->ec_control.addrh = 0; - ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ + ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ ecdt->ec_data.bit_width = 8; ecdt->ec_data.bit_offset = 0; ecdt->ec_data.addrl = 0x62; @@ -73,14 +73,12 @@ strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id)); - header->checksum = - acpi_checksum((void *) ecdt, ecdt_len); + header->checksum = acpi_checksum((void *)ecdt, ecdt_len); return header->length; } -unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long start, +unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp) { unsigned long current; diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c index 38b0d30..2f1f815 100644 --- a/src/mainboard/getac/p470/cstates.c +++ b/src/mainboard/getac/p470/cstates.c @@ -16,21 +16,21 @@ #include <southbridge/intel/i82801gx/i82801gx.h> static acpi_cstate_t cst_entries[] = { - { - /* ACPI C1 / CPU C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* ACPI C2 / CPU C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } - }, - { - /* ACPI C3 / CPU C2 */ - 2, 0x11, 250, - { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } - }, + {/* ACPI C1 / CPU C1 */ + 1, + 0x01, + 1000, + {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}}, + {/* ACPI C2 / CPU C2 */ + 2, + 0x01, + 500, + {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}}, + {/* ACPI C3 / CPU C2 */ + 2, + 0x11, + 250, + {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, }; int get_cst_entries(acpi_cstate_t **entries) diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c index 8740167..49b7274 100644 --- a/src/mainboard/getac/p470/ec_oem.c +++ b/src/mainboard/getac/p470/ec_oem.c @@ -32,7 +32,7 @@ } if (!timeout) { printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n", - command); + command); // return -1; } @@ -51,8 +51,7 @@ printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", - data); + printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", data); // return -1; } @@ -112,12 +111,18 @@ { u8 ec_sc = inb(EC_OEM_SC); printk(BIOS_DEBUG, "Embedded Controller Status: "); - if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT "); - if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT "); - if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST "); - if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD "); - if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF "); - if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF "); + if (ec_sc & (1 << 6)) + printk(BIOS_DEBUG, "SMI_EVT "); + if (ec_sc & (1 << 5)) + printk(BIOS_DEBUG, "SCI_EVT "); + if (ec_sc & (1 << 4)) + printk(BIOS_DEBUG, "BURST "); + if (ec_sc & (1 << 3)) + printk(BIOS_DEBUG, "CMD "); + if (ec_sc & (1 << 1)) + printk(BIOS_DEBUG, "IBF "); + if (ec_sc & (1 << 0)) + printk(BIOS_DEBUG, "OBF "); printk(BIOS_DEBUG, "\n"); return ec_sc; diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 5d56107..ba42d7e 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -17,23 +17,35 @@ #ifndef _MAINBOARD_EC_OEM_H #define _MAINBOARD_EC_OEM_H -#define EC_OEM_DATA 0x68 -#define EC_OEM_SC 0x6c +#define EC_OEM_DATA 0x68 +#define EC_OEM_SC 0x6c /* EC_SC input */ -#define EC_SMI_EVT (1 << 6) // 1: SMI event pending -#define EC_SCI_EVT (1 << 5) // 1: SCI event pending -#define EC_BURST (1 << 4) // controller is in burst mode -#define EC_CMD (1 << 3) // 1: byte in data register is command - // 0: byte in data register is data -#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) +// 1: SMI event pending +#define EC_SMI_EVT (1 << 6) + +// 1: SCI event pending +#define EC_SCI_EVT (1 << 5) + +// controller is in burst mode +#define EC_BURST (1 << 4) + +// 1: byte in data register is command +// 0: byte in data register is data +#define EC_CMD (1 << 3) + +// 1: input buffer full (data ready for ec) +#define EC_IBF (1 << 1) + +// 1: output buffer full (data ready for host) +#define EC_OBF (1 << 0) + /* EC_SC output */ -#define RD_EC 0x80 // Read Embedded Controller -#define WR_EC 0x81 // Write Embedded Controller -#define BE_EC 0x82 // Burst Enable Embedded Controller -#define BD_EC 0x83 // Burst Disable Embedded Controller -#define QR_EC 0x84 // Query Embedded Controller +#define RD_EC 0x80 // Read Embedded Controller +#define WR_EC 0x81 // Write Embedded Controller +#define BE_EC 0x82 // Burst Enable Embedded Controller +#define BD_EC 0x83 // Burst Disable Embedded Controller +#define QR_EC 0x84 // Query Embedded Controller int send_ec_oem_command(u8 command); int send_ec_oem_data(u8 data); diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c index be52a86..2785bca 100644 --- a/src/mainboard/getac/p470/gpio.c +++ b/src/mainboard/getac/p470/gpio.c @@ -74,8 +74,7 @@ .gpio8 = GPIO_INVERT, }; -static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, @@ -100,16 +99,18 @@ }; const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, + .set1 = + { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = + { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, }; diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c index e858a35..1ec2205 100644 --- a/src/mainboard/getac/p470/hda_verb.c +++ b/src/mainboard/getac/p470/hda_verb.c @@ -17,9 +17,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 - 0x10714700, // Subsystem ID - 0x0000000d, // Number of jacks + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000d, // Number of jacks /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */ AZALIA_SUBVENDOR(0x0, 0x10EC0000), diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index 06d1492..fa491bf 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -17,18 +17,19 @@ #include <arch/pirq_routing.h> static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x27b0, /* Device */ - 0, /* miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xf, /* u8 checksum. */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ { + // clang-format off /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA @@ -48,8 +49,8 @@ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, - } -}; + // clang-format on + }}; unsigned long write_pirq_routing_table(unsigned long addr) { diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 5d271fd..0645424 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -25,7 +25,7 @@ #include "mainboard.h" -#define MAX_LCD_BRIGHTNESS 0xd8 +#define MAX_LCD_BRIGHTNESS 0xd8 static void ec_enable(void) { @@ -77,7 +77,8 @@ static void mainboard_init(struct device *dev) { ec_enable(); - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3); } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 0e6b24c..d074960 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -13,6 +13,5 @@ struct acpi_rsdp; -unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long start, +unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index c00102d..80c33df 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -41,28 +41,42 @@ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, + 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, + 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, + 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, + 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, + 0x11); /* Firewire 4:0.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, + 0x10); // riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, + 0x14); // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, + 0x15); // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, + 0x16); /* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, + 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3f80664..a591307 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -36,18 +36,18 @@ printk(BIOS_SPEW, "\n Initializing drive bay...\n"); gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 - gpios |= (1 << 0); // GPIO33 = ODD - gpios |= (1 << 1); // GPIO34 = IDE_RST# - outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + gpios |= (1 << 0); // GPIO33 = ODD + gpios |= (1 << 1); // GPIO34 = IDE_RST# + outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 13); // ?? - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + gpios &= ~(1 << 13); // ?? + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 24); // Enable LAN Power - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + gpios &= ~(1 << 24); // Enable LAN Power + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } static void ich7_enable_lpc(void) @@ -61,9 +61,10 @@ // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN + | COMA_LPC_EN); // Enable 0x02e0 - 0x2ff pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); // Enable 0x600 - 0x6ff @@ -93,7 +94,7 @@ { unsigned int port = dev >> 8; outb(reg, port); - outb(val, port+1); + outb(val, port + 1); } static void early_superio_config(void) @@ -103,15 +104,15 @@ dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x02, 0x0e); // UART power - pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base - pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_register(dev, 0x02, 0x0e); // UART power + pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ - pnp_write_register(dev, 0x1e, 1); // no 32khz clock - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ - pnp_write_register(dev, 0x2c, 0); // DMA0 FIR - pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + pnp_write_register(dev, 0x1e, 1); // no 32khz clock + pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_register(dev, 0x2c, 0); // DMA0 FIR + pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL @@ -144,8 +145,8 @@ static void rcba_config(void) { /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; + // RCBA32(0x0014) = 0x80000001; + // RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 5a82044..ca95447 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -115,7 +115,7 @@ case 0xde: printk(BIOS_DEBUG, "LAN power off\n"); reg32 = inl(DEFAULT_GPIOBASE + GP_LVL); - reg32 |= (1 << 24); // Disable LAN Power + reg32 |= (1 << 24); // Disable LAN Power outl(reg32, DEFAULT_GPIOBASE + GP_LVL); break; case 0xdf: @@ -151,27 +151,37 @@ u8 reg8; switch (hotkey) { - case 0x3b: break; // Fn+F1 - case 0x3c: break; // Fn+F2 - case 0x3d: break; // Fn+F3 - case 0x3e: break; // Fn+F4 - case 0x3f: break; // Fn+F5 - case 0x40: // Fn+F6 (Decrease Display Brightness) - reg8 = ec_read(0x17); - reg8 = (reg8 > 8) ? (reg8 - 8) : 0; - ec_write(0x17, reg8); - return; - case 0x41: // Fn+F7 (Increase Display Brightness) - reg8 = ec_read(0x17); - reg8 += 8; - reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; - ec_write(0x17, reg8); - return; - case 0x42: break; // Fn+F8 - case 0x43: break; // Fn+F9 - case 0x44: break; // Fn+F10 - case 0x57: break; // Fn+F11 - case 0x58: break; // Fn+F12 + case 0x3b: // Fn+F1 + break; + case 0x3c: // Fn+F2 + break; + case 0x3d: // Fn+F3 + break; + case 0x3e: // Fn+F4 + break; + case 0x3f: // Fn+F5 + break; + case 0x40: // Fn+F6 (Decrease Display Brightness) + reg8 = ec_read(0x17); + reg8 = (reg8 > 8) ? (reg8 - 8) : 0; + ec_write(0x17, reg8); + return; + case 0x41: // Fn+F7 (Increase Display Brightness) + reg8 = ec_read(0x17); + reg8 += 8; + reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; + ec_write(0x17, reg8); + return; + case 0x42: // Fn+F8 + break; + case 0x43: // Fn+F9 + break; + case 0x44: // Fn+F10 + break; + case 0x57: // Fn+F11 + break; + case 0x58: // Fn+F12 + break; } printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3 Gerrit-Change-Number: 31652 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
by Subrata Banik (Code Review) 24 Mar '21

24 Mar '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45571 ) Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ...................................................................... soc/intel/alderlake: Add GPIOs for Alder Lake SOC List of changes: 1. This implementation add the GPIO pins, communities and group mapping. 2. Add 5 GPIO community includes 16 GPIO groups GPIO COM 0 GPP_B, GPP_T, GPP_A GPIO COM 1 GPP_S, GPP_H, GPP_D, GPP_U, GPP_VGPIO GPIO COM 2 GPD GPIO COM 4 GPP_C, GPP_F, GPP_E, GPP_HVCMOD. GPP_JTAG GPIO COM 5 GPP_R, GPP_SPI 3. Add GPIO IRQ routing. 4. Add gpio.asl for ADL GPIO community. 5. Select SOC_INTEL_COMMON_BLOCK_ACPI for accessing common acpi code like gpio_op.asl Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h 7 files changed, 1,025 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 33acf43..550cfa3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -23,6 +23,7 @@ select PLATFORM_USES_FSP2_2 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a0b0e36..415da13 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -17,6 +17,10 @@ romstage-y += espi.c romstage-y += meminit.c romstage-y += reset.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include endif diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl new file mode 100644 index 0000000..f9d7f3d --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio.h> +#include <soc/gpio_defs.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c new file mode 100644 index 0000000..2466abf --- /dev/null +++ b/src/soc/intel/alderlake/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 630094 + * Chapter number: 27 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for ADL at: + * linux/drivers/pinctrl/intel/pinctrl-alderlake.c + */ +static const struct pad_group adl_community0_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64), /* GPP_A */ +}; + +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_THC_1, 224), /* GPP_VGPIO */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group adl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group adl_community4_groups[] = { + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ + INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ +}; + +static const struct pad_group adl_community5_groups[] = { + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +}; + +static const struct pad_community adl_communities[] = { + [COMM_0] = { /* GPP B, T, A */ + .port = PID_GPIOCOM0, + .first_pad = GPP_B0, + .last_pad = GPP_A24, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community0_groups, + .num_groups = ARRAY_SIZE(adl_community0_groups), + }, + [COMM_1] = { /* GPP S, D, H, U, VGPIO */ + .port = PID_GPIOCOM1, + .first_pad = GPP_S0, + .last_pad = GPP_VGPIO_THC_1, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDHU", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community1_groups, + .num_groups = ARRAY_SIZE(adl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPD_DRAM_RESETB, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = adl_community2_groups, + .num_groups = ARRAY_SIZE(adl_community2_groups), + }, + [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */ + .port = PID_GPIOCOM4, + .first_pad = GPP_C0, + .last_pad = GPP_DBG_PMODE, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community4_groups, + .num_groups = ARRAY_SIZE(adl_community4_groups), + }, + [COMM_5] = { /* GPP R, SPI */ + .port = PID_GPIOCOM5, + .first_pad = GPP_R0, + .last_pad = GPP_CLK_LOOPBK, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPU_VBPIO", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = adl_community5_groups, + .num_groups = ARRAY_SIZE(adl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(adl_communities); + return adl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_B, GPP_B }, + { PMC_GPP_T, GPP_T }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_R, GPP_R }, + { PMC_GPD, GPD }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_U, GPP_U }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_E, GPP_E }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h new file mode 100644 index 0000000..eec698a --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_H_ +#define _SOC_ALDERLAKE_GPIO_H_ + +#include <soc/gpio_defs.h> +#include <intelblocks/gpio.h> + +#define CROS_GPIO_NAME "INTC1055" +#define CROS_GPIO_DEVICE_NAME "INTC1055:00" + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..8d86473 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_DEFS_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + +/* Group VGPIO */ +#define GPP_VGPIO4_IRQ 0x54 +#define GPP_VGPIO_THC_0_IRQ 0x3d +#define GPP_VGPIO_THC_1_IRQ 0x3e + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..fb76265 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,385 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_ + +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define GPIO_COM0_START GPP_B0 +#define GPIO_COM0_END GPP_A24 +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define GPP_VGPIO_0 144 +#define GPP_VGPIO_4 145 +#define GPP_VGPIO_5 146 +#define GPP_VGPIO_6 147 +#define GPP_VGPIO_7 148 +#define GPP_VGPIO_8 149 +#define GPP_VGPIO_9 150 +#define GPP_VGPIO_10 151 +#define GPP_VGPIO_11 152 +#define GPP_VGPIO_12 153 +#define GPP_VGPIO_13 154 +#define GPP_VGPIO_18 155 +#define GPP_VGPIO_19 156 +#define GPP_VGPIO_20 157 +#define GPP_VGPIO_21 158 +#define GPP_VGPIO_22 159 +#define GPP_VGPIO_23 160 +#define GPP_VGPIO_24 161 +#define GPP_VGPIO_25 162 +#define GPP_VGPIO_30 163 +#define GPP_VGPIO_31 164 +#define GPP_VGPIO_32 165 +#define GPP_VGPIO_33 166 +#define GPP_VGPIO_34 167 +#define GPP_VGPIO_35 168 +#define GPP_VGPIO_36 169 +#define GPP_VGPIO_37 170 +#define GPP_VGPIO_THC_0 171 +#define GPP_VGPIO_THC_1 172 + +#define GPIO_COM1_START GPP_S0 +#define GPIO_COM1_END GPP_VGPIO_THC_1 +#define NUM_GPIO_COM1_PADS (GPP_VGPIO_THC_1 - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 173 +#define GPD1 174 +#define GPD2 175 +#define GPD3 176 +#define GPD4 177 +#define GPD5 178 +#define GPD6 179 +#define GPD7 180 +#define GPD8 181 +#define GPD9 182 +#define GPD10 183 +#define GPD11 184 +#define GPD_INPUT3VSEL 185 +#define GPD_SLP_LANB 186 +#define GPD__SLP_SUSB 187 +#define GPD_WAKEB 188 +#define GPD_DRAM_RESETB 189 + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 190 +#define GPP_C1 191 +#define GPP_C2 192 +#define GPP_C3 193 +#define GPP_C4 194 +#define GPP_C5 195 +#define GPP_C6 196 +#define GPP_C7 197 +#define GPP_C8 198 +#define GPP_C9 199 +#define GPP_C10 200 +#define GPP_C11 201 +#define GPP_C12 202 +#define GPP_C13 203 +#define GPP_C14 204 +#define GPP_C15 205 +#define GPP_C16 206 +#define GPP_C17 207 +#define GPP_C18 208 +#define GPP_C19 209 +#define GPP_C20 210 +#define GPP_C21 211 +#define GPP_C22 212 +#define GPP_C23 213 + +/* Group F */ +#define GPP_F0 214 +#define GPP_F1 215 +#define GPP_F2 216 +#define GPP_F3 217 +#define GPP_F4 218 +#define GPP_F5 219 +#define GPP_F6 220 +#define GPP_F7 221 +#define GPP_F8 222 +#define GPP_F9 223 +#define GPP_F10 224 +#define GPP_F11 225 +#define GPP_F12 226 +#define GPP_F13 227 +#define GPP_F14 228 +#define GPP_F15 229 +#define GPP_F16 230 +#define GPP_F17 231 +#define GPP_F18 232 +#define GPP_F19 233 +#define GPP_F20 234 +#define GPP_F21 235 +#define GPP_F22 236 +#define GPP_F23 237 +#define GPP_F_CLK_LOOPBK 238 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 239 +#define GPP_L_BKLTCTL 240 +#define GPP_L_VDDEN 241 +#define GPP_SYS_PWROK 242 +#define GPP_SYS_RESETB 243 +#define GPP_MLK_RSTB 244 + +/* Group E */ +#define GPP_E0 245 +#define GPP_E1 246 +#define GPP_E2 247 +#define GPP_E3 248 +#define GPP_E4 249 +#define GPP_E5 250 +#define GPP_E6 251 +#define GPP_E7 252 +#define GPP_E8 253 +#define GPP_E9 254 +#define GPP_E10 255 +#define GPP_E11 256 +#define GPP_E12 257 +#define GPP_E13 258 +#define GPP_E14 259 +#define GPP_E15 260 +#define GPP_E16 261 +#define GPP_E17 262 +#define GPP_E18 263 +#define GPP_E19 264 +#define GPP_E20 265 +#define GPP_E21 266 +#define GPP_E22 267 +#define GPP_E23 268 +#define GPP_E_CLK_LOOPBK 269 + +/* Group JTAG */ +#define GPP_JTAG_TDO 270 +#define GPP_JTAG_X 271 +#define GPP_JTAG_PRDYB 272 +#define GPP_JTAG_PREQB 273 +#define GPP_CPU_TRSTB 274 +#define GPP_JTAG_TDI 275 +#define GPP_JTAG_TMS 276 +#define GPP_JTAG_TCK 277 +#define GPP_DBG_PMODE 278 + +#define GPIO_COM4_START GPP_C0 +#define GPIO_COM4_END GPP_DBG_PMODE +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 279 +#define GPP_R1 280 +#define GPP_R2 281 +#define GPP_R3 282 +#define GPP_R4 283 +#define GPP_R5 284 +#define GPP_R6 285 +#define GPP_R7 286 + +/* Group SPI */ +#define GPP_SPI_IO_2 287 +#define GPP_SPI_IO_3 288 +#define GPP_SPI_MOSI_IO_0 289 +#define GPP_SPI_MOSI_IO_1 290 +#define GPP_SPI_TPM_CSB 291 +#define GPP_SPI_FLASH_0_CSB 292 +#define GPP_SPI_FLASH_1_CSB 293 +#define GPP_SPI_CLK 294 +#define GPP_CLK_LOOPBK 295 + +#define GPIO_COM5_START GPP_R0 +#define GPIO_COM5_END GPP_CLK_LOOPBK +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Gerrit-Change-Number: 45571 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 61

Change in coreboot[master]: ec/google/chromeec: add support to get SSFC from CBI EEPROM
by Sugnan Prabhu S (Code Review) 22 Mar '21

22 Mar '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45297 ) Change subject: ec/google/chromeec: add support to get SSFC from CBI EEPROM ...................................................................... ec/google/chromeec: add support to get SSFC from CBI EEPROM This change adds a support function to get the SSFC data from CBI. Change-Id: I52e2edc5b7fa6b5f82e88119355c99ff063a9a22 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45297/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 40285dc..d3c4209 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -856,6 +856,11 @@ return cbi_get_uint32(version, CBI_TAG_BOARD_VERSION); } +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc) +{ + return cbi_get_uint32(ssfc, CBI_TAG_SSFC); +} + static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag) { struct ec_params_get_cbi params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 9d4e588..de63648 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -80,6 +80,7 @@ /* version may be stored in CBI as a smaller integer width, but the EC code handles it correctly. */ int google_chromeec_cbi_get_board_version(uint32_t *version); +int google_chromeec_cbi_get_ssfc(uint32_t *ssfc); #define CROS_SKU_UNKNOWN 0xFFFFFFFF #define CROS_SKU_UNPROVISIONED 0x7FFFFFFF diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a2..86204b8 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5727,6 +5727,7 @@ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + CBI_TAG_SSFC = 8, /* uint32_t or smaller */ CBI_TAG_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52e2edc5b7fa6b5f82e88119355c99ff063a9a22 Gerrit-Change-Number: 45297 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/asus/p2b: Migrate southbridge ACPI stuff
by Keith Hui (Code Review) 22 Mar '21

22 Mar '21

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41050 ) Change subject: mb/asus/p2b: Migrate southbridge ACPI stuff ...................................................................... mb/asus/p2b: Migrate southbridge ACPI stuff Move (remaining) ACPI stuff for both southbridge main and PM functions into one file under sb/intel/i82371eb, that is simply included from the board's \_SB scope. Also, southbridge no longer claims I/O ports 0x2e-0x2f, following the p3b-f OEM scheme, and its PM device now reports its own I/O resources. Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/dsdt.asl M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 2 files changed, 85 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/41050/1 diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index c3a279d..b998ceb 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -159,79 +159,7 @@ #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> #include <southbridge/intel/i82371eb/acpi/isabridge.asl> - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x02) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) - Return (BUF1) - } - } - #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> #include <superio/winbond/w83977tf/acpi/superio.asl> } } diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index 57f347e..1e2818c 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -1,17 +1,60 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* - * Declares assorted devices that falls under this southbridge. - */ #include "southbridge/intel/i82371eb/i82371eb.h" +/* Declares assorted devices that falls under this southbridge. */ +Device (PX40) +{ + Name(_ADR, 0x00040000) + OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } + OperationRegion (S1XX, PCI_Config, 0xB2, 0x01) Field (S1XX, ByteAcc, NoLock, Preserve) { FXS1, 8 } + /* PNP Motherboard Resources */ + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PIIX4E ports */ + /* Aliased DMA ports */ + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) + /* Aliased PIC ports */ + /* Do not claim 0x2e-0x2f, per P3B-F vendor DSDT */ + IO (Decode16, 0x0022, 0x0022, 0x01, 0x0C, ) + IO (Decode16, 0x0030, 0x0030, 0x01, 0x10, ) + /* Aliased timer ports */ + /* Existing DSDT only reserves to 0x54 */ + IO (Decode16, 0x0044, 0x0044, 0x01, 0x10, ) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) + IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) + IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + /* W83977TF/EF Super I/O config ports */ + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) + }) + Return (BUF1) + } + } /* 8259-compatible Programmable Interrupt Controller */ Device (PIC) { @@ -79,3 +122,41 @@ IRQNoFlags () {13} }) } +} + +/* Power management functions allows ACPI reporting of PM and SMBus base ports. */ +Device (PX43) +{ + Name (_ADR, 0x00040003) // _ADR: Address + OperationRegion (IPMU, PCI_Config, PMBA, 0x02) + Field (IPMU, ByteAcc, NoLock, Preserve) + { + PM00, 16, + } + + OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) + Field (ISMB, ByteAcc, NoLock, Preserve) + { + SB00, 16, + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* PM register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) + /* SMBus register ports */ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) + }) + CreateWordField (BUF1, _Y06._MIN, PMLO) + CreateWordField (BUF1, _Y06._MAX, PMRL) + CreateWordField (BUF1, _Y07._MIN, SBLO) + CreateWordField (BUF1, _Y07._MAX, SBRL) + + And (PM00, 0xFFFE, PMLO) + And (SB00, 0xFFFE, SBLO) + Store (PMLO, PMRL) + Store (SBLO, SBRL) + Return (BUF1) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d Gerrit-Change-Number: 41050 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: drivers/generic/cbfs-serial: Update driver to read UUID from CBFS
by Name of user not set (Code Review) 21 Mar '21

21 Mar '21

Name of user not set #1002789 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44005 ) Change subject: drivers/generic/cbfs-serial: Update driver to read UUID from CBFS ...................................................................... drivers/generic/cbfs-serial: Update driver to read UUID from CBFS Modify the existing cbfs-serial driver to also read the UUID from a text file in CBFS, just as a serial number is done today. When driver is selected and a system_uuid exists in the CBFS the UUID is read from the file and populated in the SMBIOS table. Note that in order to work there must be no newline character at the end of the file, this is also true of the serial_number. Tested on a Google Tricky (Dell 3010 Chromebox). Change-Id: I140a61670cec1318c095e18815c6bc7c1bf78cd6 Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- M src/drivers/generic/cbfs-serial/Kconfig M src/drivers/generic/cbfs-serial/cbfs-serial.c 2 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44005/1 diff --git a/src/drivers/generic/cbfs-serial/Kconfig b/src/drivers/generic/cbfs-serial/Kconfig index 209c242..d0cce14 100644 --- a/src/drivers/generic/cbfs-serial/Kconfig +++ b/src/drivers/generic/cbfs-serial/Kconfig @@ -2,5 +2,8 @@ bool "Serial number in CBFS" default n help - Enable this option to read the board serial number from a - text file located in CBFS. + Enable this option to read the board serial number or + system UUID from a text file located in CBFS. The text + file should be named serial_number or system_uuid + respectively and include only the serial number or + UUID (with dashes) with no newline characters. diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 2e3e37d..6ee3c26 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -4,9 +4,10 @@ #include <device/device.h> #include <smbios.h> #include <string.h> - +#include <uuid.h> #define MAX_SERIAL_LENGTH 0x100 +#define UUID_LENGTH 0x128 const char *smbios_mainboard_serial_number(void) { @@ -37,3 +38,30 @@ return serial_number; } + +void smbios_system_set_uuid(u8 *uuid) +{ + static char system_uuid[UUID_LENGTH + 1] = {0}; + struct cbfsf file; + + if (system_uuid[0] != 0) + parse_uuid(uuid, system_uuid); + + if (cbfs_boot_locate(&file, "system_uuid", NULL) == 0) { + struct region_device cbfs_region; + size_t uuid_len; + + cbfs_file_data(&cbfs_region, &file); + + uuid_len = region_device_sz(&cbfs_region); + if (uuid_len <= UUID_LENGTH) { + if (rdev_readat(&cbfs_region, system_uuid, 0, + uuid_len) == uuid_len) { + system_uuid[uuid_len] = 0; + parse_uuid(uuid, system_uuid); + } + } + } + + parse_uuid(uuid, system_uuid); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I140a61670cec1318c095e18815c6bc7c1bf78cd6 Gerrit-Change-Number: 44005 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002789 Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [WIP] soc/intel/tigerlake: Configure top swap based on microcode version
by Jamie Ryu (Code Review) 17 Mar '21

17 Mar '21

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46647 ) Change subject: [WIP] soc/intel/tigerlake: Configure top swap based on microcode version ...................................................................... [WIP] soc/intel/tigerlake: Configure top swap based on microcode version In case of FIT based FW update feature is enabled, check that the microcode has been loaded via FIT, if not, then disable top-swap so that RO microcode is loaded on the next boot. This is to make sure that the system always boots up with a microcode loaded via FIT. BUG=b:149547271 TEST=Build and boot volteer2 to OS Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I25febfd946d5a82b92ba626e487eb183a0bd6286 --- M src/soc/intel/tigerlake/bootblock/report_platform.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46647/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 03d65a4..1662ba5 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -18,6 +18,9 @@ #include <soc/pch.h> #include <soc/pci_devs.h> #include <string.h> +#include <intelblocks/rtc.h> +#include <reset.h> +#include <halt.h> static struct { u32 cpuid; @@ -106,6 +109,7 @@ static const char *const mode[] = {"NOT ", ""}; const char *cpu_type = "Unknown"; u32 p[13]; + u32 microcode_ver; index = 0x80000000; cpuidr = cpuid(index); @@ -137,9 +141,20 @@ } } + microcode_ver = get_current_microcode_rev(); printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, get_current_microcode_rev()); + cpu_id, cpu_type, microcode_ver); + + if(microcode_ver == 0x0) { + printk(BIOS_DEBUG, "CPU: ucode is not loaded, Disable top swap\n"); + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) { + configure_rtc_buc_top_swap(TS_DISABLE); + printk(BIOS_DEBUG, "CPU: Booting with top swap disabled\n"); + do_board_reset(); + halt(); + } + } cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/46647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25febfd946d5a82b92ba626e487eb183a0bd6286 Gerrit-Change-Number: 46647 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: cbfs: Move stage header into a CBFS attribute
by Julius Werner (Code Review) 17 Mar '21

17 Mar '21

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46484 to review the following change. Change subject: cbfs: Move stage header into a CBFS attribute ...................................................................... cbfs: Move stage header into a CBFS attribute The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a --- M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M src/include/program_loading.h M src/lib/cbfs.c M src/lib/prog_loaders.c M src/lib/rmodule.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/pi/refcode_loader.c M util/cbfstool/cbfs-mkstage.c M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c M util/cbfstool/common.h 11 files changed, 210 insertions(+), 314 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46484/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index ac4b38f..c31d995 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -17,7 +17,8 @@ CBFS_TYPE_NULL = 0xffffffff, CBFS_TYPE_BOOTBLOCK = 0x01, CBFS_TYPE_CBFSHEADER = 0x02, - CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_LEGACY_STAGE = 0x10, + CBFS_TYPE_STAGE = 0x11, CBFS_TYPE_SELF = 0x20, CBFS_TYPE_FIT = 0x21, CBFS_TYPE_OPTIONROM = 0x30, @@ -125,6 +126,7 @@ CBFS_FILE_ATTR_TAG_ALIGNMENT = 0x42434c41, /* BE: 'BCLA' */ CBFS_FILE_ATTR_TAG_IBB = 0x32494242, /* BE: '2IBB' */ CBFS_FILE_ATTR_TAG_PADDING = 0x47444150, /* BE: 'GNDP' */ + CBFS_FILE_ATTR_TAG_STAGEHEADER = 0x53746748, /* BE: 'StgH' */ }; struct cbfs_file_attr_compression { @@ -154,22 +156,20 @@ uint32_t alignment; } __packed; +struct cbfs_file_attr_stageheader { + uint32_t tag; + uint32_t len; + uint64_t loadaddr; /* Memory address to load the code to. */ + uint32_t entry_offset; /* Offset of entry point from loadaddr. */ + uint32_t memlen; /* Total length (including BSS) in memory. */ +} __packed; + + /*** Component sub-headers ***/ /* Following are component sub-headers for the "standard" component types */ -/** This is the sub-header for stage components. Stages are - loaded by coreboot during the normal boot process */ - -struct cbfs_stage { - uint32_t compression; /** Compression type */ - uint64_t entry; /** entry point */ - uint64_t load; /** Where to load in memory */ - uint32_t len; /** length of data to load */ - uint32_t memlen; /** total length of object in memory */ -} __packed; - /** this is the sub-header for payload components. Payloads are loaded by coreboot at the end of the boot process */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e26792e..57efd7b 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -4,6 +4,7 @@ #include <assert.h> #include <bootmem.h> +#include <commonlib/bsd/cbfs_serialized.h> #include <commonlib/region.h> #include <types.h> @@ -41,7 +42,8 @@ /* Representation of a program. */ struct prog { enum prog_type type; - uint32_t cbfs_type; + enum cbfs_type cbfs_type; + enum cbfs_compression compression; /* Only used for CBFS_TYPE_STAGE. */ const char *name; struct region_device load_rdev; /* Source for loading (e.g. flash). */ void *start; /* Program start in memory after loading. */ @@ -66,11 +68,16 @@ return prog->type; } -static inline uint32_t prog_cbfs_type(const struct prog *prog) +static inline enum cbfs_type prog_cbfs_type(const struct prog *prog) { return prog->cbfs_type; } +static inline enum cbfs_compression prog_compression(const struct prog *prog) +{ + return prog->compression; +} + static inline struct region_device *prog_rdev(struct prog *prog) { return &prog->load_rdev; @@ -118,6 +125,8 @@ static inline void prog_set_entry(struct prog *prog, void *e, void *arg) { + if (prog->cbfs_type == CBFS_TYPE_STAGE) + assert(e >= prog->start && e - prog->start < prog->size); prog->entry = e; prog->arg = arg; } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a6f0e69..452dce4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -338,57 +338,30 @@ int cbfs_prog_stage_load(struct prog *pstage) { - struct cbfs_stage stage; - uint8_t *load; - void *entry; + struct region_device *rdev = prog_rdev(pstage); size_t fsize; - size_t foffset; - const struct region_device *fh = prog_rdev(pstage); - - if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) - return -1; - - fsize = region_device_sz(fh); - fsize -= sizeof(stage); - foffset = 0; - foffset += sizeof(stage); - - /* cbfs_stage fields are written in little endian despite the other - cbfs data types being encoded in big endian. */ - stage.compression = read_le32(&stage.compression); - stage.entry = read_le64(&stage.entry); - stage.load = read_le64(&stage.load); - stage.len = read_le32(&stage.len); - stage.memlen = read_le32(&stage.memlen); - - assert(fsize == stage.len); - - load = (void *)(uintptr_t)stage.load; - entry = (void *)(uintptr_t)stage.entry; /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { - void *mapping = rdev_mmap(fh, foffset, fsize); - rdev_munmap(fh, mapping); - if (mapping == load) - goto out; + void *mapping = rdev_mmap_full(rdev); + rdev_munmap(rdev, mapping); + if (mapping == prog_start(pstage)) + return 0; } - fsize = cbfs_stage_load_and_decompress(fh, foffset, fsize, load, - stage.memlen, stage.compression); + fsize = cbfs_stage_load_and_decompress(rdev, 0, region_device_sz(rdev), + prog_start(pstage), prog_size(pstage), + prog_compression(pstage)); if (!fsize) return -1; /* Clear area not covered by file. */ - memset(&load[fsize], 0, stage.memlen - fsize); + memset(prog_start(pstage) + fsize, 0, prog_size(pstage) - fsize); - prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); - -out: - prog_set_area(pstage, load, stage.memlen); - prog_set_entry(pstage, entry, NULL); + prog_segment_loaded((uintptr_t)prog_start(pstage), prog_size(pstage), + SEG_FINAL); return 0; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 4fae5d2..f75f2ee 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -36,6 +36,26 @@ return err; prog->cbfs_type = be32toh(mdata.h.type); + + const struct cbfs_file_attr_compression *compr = cbfs_find_attr(&mdata, + CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*compr)); + if (compr) + prog->compression = be32toh(compr->compression); + else + prog->compression = CBFS_COMPRESS_NONE; + + if (prog->cbfs_type == CBFS_TYPE_STAGE) { + const struct cbfs_file_attr_stageheader *stgh = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_STAGEHEADER, + sizeof(*stgh)); + if (!stgh) + return CB_ERR; + prog_set_area(prog, (void *)(uintptr_t)be64toh(stgh->loadaddr), + be32toh(stgh->memlen)); + prog_set_entry(prog, prog_start(prog) + + be32toh(stgh->entry_offset), NULL); + } + return CB_SUCCESS; } diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 7944535..c68fe20 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -242,21 +242,15 @@ char *stage_region; int rmodule_offset; int load_offset; - struct cbfs_stage stage; void *rmod_loc; - struct region_device *fh; - if (rsl->prog == NULL || prog_name(rsl->prog) == NULL) - return -1; - - fh = prog_rdev(rsl->prog); - - if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + struct prog *prog = rsl->prog; + if (prog == NULL || prog_name(prog) == NULL) return -1; rmodule_offset = - rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, - stage.memlen, &region_size, &load_offset); + rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, prog_size(prog), + &region_size, &load_offset); stage_region = cbmem_add(rsl->cbmem_id, region_size); @@ -266,10 +260,11 @@ rmod_loc = &stage_region[rmodule_offset]; printk(BIOS_INFO, "Decompressing stage %s @ %p (%d bytes)\n", - prog_name(rsl->prog), rmod_loc, stage.memlen); + prog_name(rsl->prog), rmod_loc, prog_size(prog)); - if (!cbfs_load_and_decompress(fh, sizeof(stage), stage.len, rmod_loc, - stage.memlen, stage.compression)) + if (!cbfs_load_and_decompress(prog_rdev(prog), 0, + region_device_sz(prog_rdev(prog)), rmod_loc, + prog_size(prog), prog_compression(prog))) return -1; if (rmodule_parse(rmod_loc, &rmod_stage)) @@ -278,13 +273,13 @@ if (rmodule_load(&stage_region[load_offset], &rmod_stage)) return -1; - prog_set_area(rsl->prog, rmod_stage.location, + prog_set_area(prog, rmod_stage.location, rmodule_memory_size(&rmod_stage)); /* Allow caller to pick up parameters, if available. */ rsl->params = rmodule_parameters(&rmod_stage); - prog_set_entry(rsl->prog, rmodule_entry(&rmod_stage), rsl->params); + prog_set_entry(prog, rmodule_entry(&rmod_stage), rsl->params); return 0; } diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 56a0664..d8b42f8 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -45,7 +45,6 @@ verstage_main(); after_verstage(); } else if (verstage_should_load()) { - struct cbfsf file; struct prog verstage = PROG_INIT(PROG_VERSTAGE, CONFIG_CBFS_PREFIX "/verstage"); @@ -53,10 +52,8 @@ printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n"); /* load verstage from RO */ - if (cbfs_boot_locate(&file, prog_name(&verstage), NULL)) - die("failed to load verstage"); - - cbfs_file_data(prog_rdev(&verstage), &file); + if (prog_locate(&verstage)) + die("failed to locate verstage"); if (cbfs_prog_stage_load(&verstage)) die("failed to load verstage"); diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index bedd847..9be2079 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -29,14 +29,8 @@ static int agesa_locate_stage_file_early(const char *name, struct region_device *rdev) { - const size_t metadata_sz = sizeof(struct cbfs_stage); - if (agesa_locate_file(name, rdev, CBFS_TYPE_STAGE)) return -1; - - /* Peel off the cbfs stage metadata. */ - return rdev_chain(rdev, rdev, metadata_sz, - region_device_sz(rdev) - metadata_sz); } static int agesa_locate_stage_file_ramstage(const char *name, diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index bfe7bf8..935bca0 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -10,8 +10,6 @@ #include "cbfs.h" #include "rmodule.h" -#include <commonlib/bsd/compression.h> - /* Checks if program segment contains the ignored section */ static int is_phdr_ignored(Elf64_Phdr *phdr, Elf64_Shdr *shdr) { @@ -73,19 +71,20 @@ return NULL; } -static void fill_cbfs_stage(struct buffer *outheader, enum cbfs_compression algo, - uint64_t entry, uint64_t loadaddr, - uint32_t filesize, uint32_t memsize) +static int fill_cbfs_stageheader(struct cbfs_file_attr_stageheader *stageheader, + uint64_t entry, uint64_t loadaddr, + uint32_t memsize) { - /* N.B. The original plan was that SELF data was B.E. - * but: this is all L.E. - * Maybe we should just change the spec. - */ - xdr_le.put32(outheader, algo); - xdr_le.put64(outheader, entry); - xdr_le.put64(outheader, loadaddr); - xdr_le.put32(outheader, filesize); - xdr_le.put32(outheader, memsize); + if (entry - loadaddr >= memsize) { + ERROR("stage entry point out of bounds!\n"); + return -1; + } + + stageheader->loadaddr = htonll(loadaddr); + stageheader->memlen = htonl(memsize); + stageheader->entry_offset = htonl(entry - loadaddr); + + return 0; } /* returns size of result, or -1 if error. @@ -93,26 +92,20 @@ * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum cbfs_compression algo, uint32_t *location, - const char *ignore_section) + uint32_t *location, const char *ignore_section, + struct cbfs_file_attr_stageheader *stageheader) { struct parsed_elf pelf; Elf64_Phdr *phdr; Elf64_Ehdr *ehdr; Elf64_Shdr *shdr_ignored; Elf64_Addr virt_to_phys; - char *buffer; - struct buffer outheader; int ret = -1; int headers; - int i, outlen; + int i; uint64_t data_start, data_end, mem_end; - comp_func_ptr compress = compression_function(algo); - if (!compress) - return -1; - DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location); int flags = ELF_PARSE_PHDR | ELF_PARSE_SHDR | ELF_PARSE_STRTAB; @@ -185,15 +178,13 @@ exit(1); } - /* allocate an intermediate buffer for the data */ - buffer = calloc(data_end - data_start, 1); - - if (buffer == NULL) { + if (buffer_create(output, data_end - data_start, input->name) != 0) { ERROR("Unable to allocate memory: %m\n"); goto err; } + memset(output->data, 0, output->size); - /* Copy the file data into the buffer */ + /* Copy the file data into the output buffer */ for (i = 0; i < headers; i++) { uint64_t l_start, l_offset = 0; @@ -222,92 +213,17 @@ ERROR("Underflow copying out the segment." "File has %zu bytes left, segment end is %zu\n", input->size, (size_t)(phdr[i].p_offset + phdr[i].p_filesz)); - free(buffer); goto err; } - memcpy(buffer + (l_start - data_start), + memcpy(&output->data[l_start - data_start], &input->data[phdr[i].p_offset + l_offset], phdr[i].p_filesz - l_offset); } - /* Now make the output buffer */ - if (buffer_create(output, sizeof(struct cbfs_stage) + data_end - data_start, - input->name) != 0) { - ERROR("Unable to allocate memory: %m\n"); - free(buffer); - goto err; - } - memset(output->data, 0, output->size); - - /* Compress the data, at which point we'll know information - * to fill out the header. This seems backward but it works because - * - the output header is a known size (not always true in many xdr's) - * - we do need to know the compressed output size first - * If compression fails or makes the data bigger, we'll warn about it - * and use the original data. - */ - if (compress(buffer, data_end - data_start, - (output->data + sizeof(struct cbfs_stage)), - &outlen) < 0 || (unsigned)outlen > data_end - data_start) { - WARN("Compression failed or would make the data bigger " - "- disabled.\n"); - memcpy(output->data + sizeof(struct cbfs_stage), - buffer, data_end - data_start); - outlen = data_end - data_start; - algo = CBFS_COMPRESS_NONE; - } - - /* Check for enough BSS scratch space to decompress LZ4 in-place. */ - if (algo == CBFS_COMPRESS_LZ4) { - size_t result; - size_t memlen = mem_end - data_start; - size_t compressed_size = outlen; - char *compare_buffer = malloc(memlen); - char *start = compare_buffer + memlen - compressed_size; - - if (compare_buffer == NULL) { - ERROR("Can't allocate memory!\n"); - free(buffer); - goto err; - } - - memcpy(start, output->data + sizeof(struct cbfs_stage), - compressed_size); - result = ulz4fn(start, compressed_size, compare_buffer, memlen); - - if (result == 0) { - ERROR("Not enough scratch space to decompress LZ4 in-place -- increase BSS size or disable compression!\n"); - free(compare_buffer); - free(buffer); - goto err; - } - if (result != data_end - data_start || - memcmp(compare_buffer, buffer, data_end - data_start)) { - ERROR("LZ4 compression BUG! Report to mailing list.\n"); - free(compare_buffer); - free(buffer); - goto err; - } - free(compare_buffer); - } - - free(buffer); - - /* Set up for output marshaling. */ - outheader.data = output->data; - outheader.size = 0; - /* coreboot expects entry point to be physical address. Thus, adjust the - * entry point accordingly. - */ - fill_cbfs_stage(&outheader, algo, ehdr->e_entry + virt_to_phys, - data_start, outlen, mem_end - data_start); - - if (*location) - *location -= sizeof(struct cbfs_stage); - output->size = sizeof(struct cbfs_stage) + outlen; - ret = 0; - + entry point accordingly. */ + ret = fill_cbfs_stageheader(stageheader, ehdr->e_entry + virt_to_phys, + data_start, mem_end - data_start); err: parsed_elf_destroy(&pelf); return ret; @@ -358,13 +274,13 @@ } int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output, - uint32_t *location, const char *ignore_section) + uint32_t *location, const char *ignore_section, + struct cbfs_file_attr_stageheader *stageheader) { struct xip_context xipctx; struct rmod_context *rmodctx; struct reloc_filter filter; struct parsed_elf *pelf; - size_t output_sz; uint32_t adjustment; struct buffer binput; struct buffer boutput; @@ -398,13 +314,12 @@ if (rmodule_collect_relocations(rmodctx, &filter)) goto out; - output_sz = sizeof(struct cbfs_stage) + pelf->phdr->p_filesz; - if (buffer_create(output, output_sz, input->name) != 0) { + if (buffer_create(output, pelf->phdr->p_filesz, input->name) != 0) { ERROR("Unable to allocate memory: %m\n"); goto out; } buffer_clone(&boutput, output); - memset(buffer_get(&boutput), 0, output_sz); + memset(buffer_get(&boutput), 0, pelf->phdr->p_filesz); buffer_set_size(&boutput, 0); /* Single loadable segment. The entire segment moves to final @@ -412,17 +327,16 @@ adjustment = *location - pelf->phdr->p_vaddr; DEBUG("Relocation adjustment: %08x\n", adjustment); - fill_cbfs_stage(&boutput, CBFS_COMPRESS_NONE, - (uint32_t)pelf->ehdr.e_entry + adjustment, - (uint32_t)pelf->phdr->p_vaddr + adjustment, - pelf->phdr->p_filesz, pelf->phdr->p_memsz); + fill_cbfs_stageheader(stageheader, + (uint32_t)pelf->ehdr.e_entry + adjustment, + (uint32_t)pelf->phdr->p_vaddr + adjustment, + pelf->phdr->p_memsz); /* Need an adjustable buffer. */ buffer_clone(&binput, input); buffer_seek(&binput, pelf->phdr->p_offset); bputs(&boutput, buffer_get(&binput), pelf->phdr->p_filesz); buffer_clone(&boutput, output); - buffer_seek(&boutput, sizeof(struct cbfs_stage)); /* Make adjustments to all the relocations within the program. */ for (i = 0; i < rmodctx->nrelocs; i++) { @@ -448,8 +362,6 @@ xdr_le.put32(&out, val + adjustment); } - /* Need to back up the location to include cbfs stage metadata. */ - *location -= sizeof(struct cbfs_stage); ret = 0; out: diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 05fdc8a..a51f941 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -823,69 +823,6 @@ return NULL; } -static int cbfs_stage_decompress(struct cbfs_stage *stage, struct buffer *buff) -{ - struct buffer reader; - char *orig_buffer; - char *new_buffer; - size_t new_buff_sz; - decomp_func_ptr decompress; - - buffer_clone(&reader, buff); - - /* The stage metadata is in little endian. */ - stage->compression = xdr_le.get32(&reader); - stage->entry = xdr_le.get64(&reader); - stage->load = xdr_le.get64(&reader); - stage->len = xdr_le.get32(&reader); - stage->memlen = xdr_le.get32(&reader); - - /* Create a buffer just with the uncompressed program now that the - * struct cbfs_stage has been peeled off. */ - if (stage->compression == CBFS_COMPRESS_NONE) { - new_buff_sz = buffer_size(buff) - sizeof(struct cbfs_stage); - - orig_buffer = buffer_get(buff); - new_buffer = calloc(1, new_buff_sz); - memcpy(new_buffer, orig_buffer + sizeof(struct cbfs_stage), - new_buff_sz); - buffer_init(buff, buff->name, new_buffer, new_buff_sz); - free(orig_buffer); - return 0; - } - - decompress = decompression_function(stage->compression); - if (decompress == NULL) - return -1; - - orig_buffer = buffer_get(buff); - - /* This can be too big of a buffer needed, but there's no current - * field indicating decompressed size of data. */ - new_buff_sz = stage->memlen; - new_buffer = calloc(1, new_buff_sz); - - if (decompress(orig_buffer + sizeof(struct cbfs_stage), - (int)(buffer_size(buff) - sizeof(struct cbfs_stage)), - new_buffer, (int)new_buff_sz, &new_buff_sz)) { - ERROR("Couldn't decompress stage.\n"); - free(new_buffer); - return -1; - } - - /* Include correct size for full stage info. */ - buffer_init(buff, buff->name, new_buffer, new_buff_sz); - - /* True decompressed size is just the data size -- no metadata. */ - stage->len = new_buff_sz; - /* Stage is not compressed. */ - stage->compression = CBFS_COMPRESS_NONE; - - free(orig_buffer); - - return 0; -} - static int cbfs_payload_decompress(struct cbfs_payload_segment *segments, struct buffer *buff, int num_seg) { @@ -1019,11 +956,11 @@ return 0; } -static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch) +static int cbfs_stage_make_elf(struct buffer *buff, uint32_t arch, + struct cbfs_file *entry) { Elf64_Ehdr ehdr; Elf64_Shdr shdr; - struct cbfs_stage stage; struct elf_writer *ew; struct buffer elf_out; size_t empty_sz; @@ -1034,16 +971,23 @@ return -1; } - if (cbfs_stage_decompress(&stage, buff)) { - ERROR("Failed to decompress stage.\n"); + struct cbfs_file_attr_stageheader *stage = NULL; + for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry); + attr != NULL; attr = cbfs_file_next_attr(entry, attr)) { + if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { + stage = (struct cbfs_file_attr_stageheader *)attr; + break; + } + } + + if (stage == NULL) { + ERROR("Stage header not found for %s\n", entry->filename); return -1; } if (init_elf_from_arch(&ehdr, arch)) return -1; - ehdr.e_entry = stage.entry; - /* Attempt rmodule translation first. */ rmod_ret = rmodule_stage_to_elf(&ehdr, buff); @@ -1055,6 +999,8 @@ /* Rmodule couldn't do anything with the data. Continue on with SELF. */ + ehdr.e_entry = ntohll(stage->loadaddr) + ntohl(stage->entry_offset); + ew = elf_writer_init(&ehdr); if (ew == NULL) { ERROR("Unable to init ELF writer.\n"); @@ -1064,9 +1010,9 @@ memset(&shdr, 0, sizeof(shdr)); shdr.sh_type = SHT_PROGBITS; shdr.sh_flags = SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR; - shdr.sh_addr = stage.load; - shdr.sh_size = stage.len; - empty_sz = stage.memlen - stage.len; + shdr.sh_addr = ntohll(stage->loadaddr); + shdr.sh_size = buffer_size(buff); + empty_sz = ntohl(stage->memlen) - buffer_size(buff); if (elf_writer_add_section(ew, &shdr, buff, ".program")) { ERROR("Unable to add ELF section: .program\n"); @@ -1081,7 +1027,7 @@ memset(&shdr, 0, sizeof(shdr)); shdr.sh_type = SHT_NOBITS; shdr.sh_flags = SHF_WRITE | SHF_ALLOC; - shdr.sh_addr = stage.load + stage.len; + shdr.sh_addr = ntohl(stage->loadaddr) + buffer_size(buff); shdr.sh_size = empty_sz; if (elf_writer_add_section(ew, &shdr, &b, ".empty")) { ERROR("Unable to add ELF section: .empty\n"); @@ -1105,7 +1051,8 @@ return 0; } -static int cbfs_payload_make_elf(struct buffer *buff, uint32_t arch) +static int cbfs_payload_make_elf(struct buffer *buff, uint32_t arch, + unused struct cbfs_file *entry) { Elf64_Ehdr ehdr; Elf64_Shdr shdr; @@ -1257,7 +1204,7 @@ } if (elf_writer_serialize(ew, &elf_out)) { - ERROR("Unable to create ELF file from stage.\n"); + ERROR("Unable to create ELF file from payload.\n"); goto out; } @@ -1319,13 +1266,13 @@ } /* - * The stage metadata is never compressed proper for cbfs_stage - * files. The contents of the stage data can be though. Therefore - * one has to do a second pass for stages to potentially decompress - * the stage data to make it more meaningful. + * We want to export stages and payloads as ELFs, not with coreboot's + * custom stage/SELF binary formats, so we need to do extra processing + * to turn them back into an ELF. */ if (do_processing) { - int (*make_elf)(struct buffer *, uint32_t) = NULL; + int (*make_elf)(struct buffer *, uint32_t, + struct cbfs_file *) = NULL; switch (ntohl(entry->type)) { case CBFS_TYPE_STAGE: make_elf = cbfs_stage_make_elf; @@ -1334,7 +1281,7 @@ make_elf = cbfs_payload_make_elf; break; } - if (make_elf && make_elf(&buffer, arch)) { + if (make_elf && make_elf(&buffer, arch, entry)) { ERROR("Failed to write %s into %s.\n", entry_name, filename); buffer_delete(&buffer); @@ -1386,17 +1333,29 @@ return 0; } -static int cbfs_print_stage_info(struct cbfs_stage *stage, FILE* fp) +static int cbfs_print_stage_info(struct cbfs_file *entry, FILE* fp) { + + struct cbfs_file_attr_stageheader *stage = NULL; + for (struct cbfs_file_attribute *attr = cbfs_file_first_attr(entry); + attr != NULL; attr = cbfs_file_next_attr(entry, attr)) { + if (ntohl(attr->tag) == CBFS_FILE_ATTR_TAG_STAGEHEADER) { + stage = (struct cbfs_file_attr_stageheader *)attr; + break; + } + } + + if (stage == NULL) { + fprintf(fp, " ERROR: stage header not found!\n"); + return -1; + } + fprintf(fp, - " %s compression, entry: 0x%" PRIx64 ", load: 0x%" PRIx64 ", " - "length: %d/%d\n", - lookup_name_by_type(types_cbfs_compression, - stage->compression, "(unknown)"), - stage->entry, - stage->load, - stage->len, - stage->memlen); + " entry: 0x%" PRIx64 ", load: 0x%" PRIx64 ", " + "memlen: %d\n", + ntohll(stage->loadaddr) + ntohl(stage->entry_offset), + ntohll(stage->loadaddr), + ntohl(stage->memlen)); return 0; } @@ -1518,8 +1477,7 @@ /* note the components of the subheader may be in host order ... */ switch (ntohl(entry->type)) { case CBFS_TYPE_STAGE: - cbfs_print_stage_info((struct cbfs_stage *) - CBFS_SUBHEADER(entry), fp); + cbfs_print_stage_info(entry, fp); break; case CBFS_TYPE_SELF: diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 454aff9..d4d9829 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -14,7 +14,9 @@ #include "cbfs_sections.h" #include "elfparsing.h" #include "partitioned_file.h" +#include "lz4/lib/xxhash.h" #include <commonlib/bsd/cbfs_private.h> +#include <commonlib/bsd/compression.h> #include <commonlib/bsd/metadata_hash.h> #include <commonlib/fsp.h> #include <commonlib/endian.h> @@ -681,18 +683,7 @@ sizeof(struct cbfs_file_attr_position)); if (attrs == NULL) return -1; - /* If we add a stage or a payload, we need to take */ - /* care about the additional metadata that is added */ - /* to the cbfs file and therefore set the position */ - /* the real beginning of the data. */ - if (type == CBFS_TYPE_STAGE) - attrs->position = htonl(offset + - sizeof(struct cbfs_stage)); - else if (type == CBFS_TYPE_SELF) - attrs->position = htonl(offset + - sizeof(struct cbfs_payload)); - else - attrs->position = htonl(offset); + attrs->position = htonl(offset); } /* Add alignment attribute if used */ if (param.alignment) { @@ -872,6 +863,12 @@ struct buffer output; int ret; + struct cbfs_file_attr_stageheader *stageheader = (void *) + cbfs_add_file_attr(header, CBFS_FILE_ATTR_TAG_STAGEHEADER, + sizeof(struct cbfs_file_attr_stageheader)); + if (!stageheader) + return -1; + if (param.stage_xip) { int32_t address; size_t data_size; @@ -881,8 +878,9 @@ return 1; } - if (do_cbfs_locate(&address, sizeof(struct cbfs_stage), - data_size)) { + if (do_cbfs_locate(&address, + sizeof(struct cbfs_file_attr_stageheader), + data_size)) { ERROR("Could not find location for XIP stage.\n"); return 1; } @@ -897,18 +895,57 @@ *offset = address; ret = parse_elf_to_xip_stage(buffer, &output, offset, - param.ignore_section); - } else - ret = parse_elf_to_stage(buffer, &output, param.compression, - offset, param.ignore_section); - + param.ignore_section, + stageheader); + } else { + ret = parse_elf_to_stage(buffer, &output, offset, + param.ignore_section, stageheader); + } if (ret != 0) return -1; + + /* Store a hash of original uncompressed stage to compare later. */ + size_t decmp_size = buffer_size(&output); + uint32_t decmp_hash = XXH32(buffer_get(&output), decmp_size, 0); + + /* Chain to base conversion routine to handle compression. */ + ret = cbfstool_convert_raw(&output, offset, header); + if (ret != 0) + goto fail; + + /* Special care must be taken for LZ4-compressed stages that the BSS is + large enough to provide scratch space for in-place decompression. */ + if (!param.precompression && param.compression == CBFS_COMPRESS_LZ4) { + size_t memlen = ntohl(stageheader->memlen); + size_t compressed_size = buffer_size(&output); + uint8_t *compare_buffer = malloc(memlen); + uint8_t *start = compare_buffer + memlen - compressed_size; + if (!compare_buffer) { + ERROR("Out of memory\n"); + goto fail; + } + memcpy(start, buffer_get(&output), compressed_size); + ret = ulz4fn(start, compressed_size, compare_buffer, memlen); + if (ret == 0) { + ERROR("Not enough scratch space to decompress LZ4 in-place -- increase BSS size or disable compression!\n"); + free(compare_buffer); + goto fail; + } else if (ret != (int)decmp_size || + decmp_hash != XXH32(compare_buffer, decmp_size, 0)) { + ERROR("LZ4 compression BUG! Report to mailing list.\n"); + free(compare_buffer); + goto fail; + } + free(compare_buffer); + } + buffer_delete(buffer); - // Direct assign, no dupe. - memcpy(buffer, &output, sizeof(*buffer)); - header->len = htonl(output.size); + buffer_clone(buffer, &output); return 0; + +fail: + buffer_delete(&output); + return -1; } static int cbfstool_convert_mkpayload(struct buffer *buffer, diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index f1287e2..7c3539a 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -169,11 +169,12 @@ enum cbfs_compression algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum cbfs_compression algo, uint32_t *location, - const char *ignore_section); + uint32_t *location, const char *ignore_section, + struct cbfs_file_attr_stageheader *stageheader); /* location is TOP aligned. */ int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output, - uint32_t *location, const char *ignore_section); + uint32_t *location, const char *ignore_section, + struct cbfs_file_attr_stageheader *stageheader); void print_supported_architectures(void); void print_supported_filetypes(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/46484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Gerrit-Change-Number: 46484 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

5 38

Change in coreboot[master]: program_loading: Split source rdev and loaded memory region concepts
by Julius Werner (Code Review) 17 Mar '21

17 Mar '21

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46483 to review the following change. Change subject: program_loading: Split source rdev and loaded memory region concepts ...................................................................... program_loading: Split source rdev and loaded memory region concepts In the current struct prog API, prog_rdev() can refer to either the program binary on the storage media or the loaded program in memory, depending on at what time it was called. This context-dependent double meaning is a bit confusing, and it also makes it impossible to define the memory area the program should be loaded into before actually loading it (which will become necessary with the new stage header format). Therefore this patch splits the two so that the rdev will always only refer to the program binary on storage, and a new start pointer and size variable will represent the program in memory. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 --- M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c M src/include/program_loading.h M src/soc/amd/common/block/pi/refcode_loader.c 4 files changed, 29 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46483/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0b6540e..3c745d4 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -200,7 +200,10 @@ if (s3wake && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, fsps); - if (fsp_validate_component(&fsps_hdr, prog_rdev(fsps)) != CB_SUCCESS) + + struct region_device mem_rdev; + prog_chain_mem_rdev(fsps, &mem_rdev); + if (fsp_validate_component(&fsps_hdr, &mem_rdev) != CB_SUCCESS) die("On resume fsps header is invalid\n"); load_done = 1; return; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index acc3f4b..62bcc5c 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -177,7 +177,7 @@ uint32_t compression_algo; size_t output_size; void *dest; - struct region_device source_rdev; + struct region_device source_rdev, mem_rdev; struct prog *fsp_prog = &fspld->fsp_prog; if (fspld->get_destination == NULL) @@ -198,7 +198,8 @@ prog_set_area(fsp_prog, dest, output_size); - if (fsp_validate_component(hdr, prog_rdev(fsp_prog)) != CB_SUCCESS) { + prog_chain_mem_rdev(fsp_prog, &mem_rdev); + if (fsp_validate_component(hdr, &mem_rdev) != CB_SUCCESS) { printk(BIOS_ERR, "Invalid FSP header after load!\n"); return CB_ERR; } diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e5a2931..e26792e 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -2,6 +2,7 @@ #ifndef PROGRAM_LOADING_H #define PROGRAM_LOADING_H +#include <assert.h> #include <bootmem.h> #include <commonlib/region.h> #include <types.h> @@ -39,18 +40,14 @@ /* Representation of a program. */ struct prog { - /* The region_device is the source of program content to load. After - * loading program it represents the memory region of the stages and - * payload. For architectures that use a bounce buffer - * then it would represent the bounce buffer. */ enum prog_type type; uint32_t cbfs_type; const char *name; - struct region_device rdev; - /* Entry to program with optional argument. It's up to the architecture - * to decide if argument is passed. */ - void (*entry)(void *); - void *arg; + struct region_device load_rdev; /* Source for loading (e.g. flash). */ + void *start; /* Program start in memory after loading. */ + size_t size; /* Program size in memory (including BSS). */ + void (*entry)(void *); /* Function pointer to entry point. */ + void *arg; /* Optional argument (only valid for some archs). */ }; #define PROG_INIT(type_, name_) \ @@ -76,19 +73,19 @@ static inline struct region_device *prog_rdev(struct prog *prog) { - return &prog->rdev; + return &prog->load_rdev; } -/* Only valid for loaded programs. */ static inline size_t prog_size(const struct prog *prog) { - return region_device_sz(&prog->rdev); + assert(prog->size); + return prog->size; } -/* Only valid for loaded programs. */ static inline void *prog_start(const struct prog *prog) { - return rdev_mmap_full(&prog->rdev); + assert(prog->size); + return prog->start; } static inline void *prog_entry(const struct prog *prog) @@ -104,15 +101,19 @@ /* region_device representing the 32-bit flat address space. */ extern const struct mem_region_device addrspace_32bit; -static inline void prog_memory_init(struct prog *prog, uintptr_t ptr, - size_t size) +/* Can be used to get an rdev representation of program area in memory. */ +static inline void prog_chain_mem_rdev(const struct prog *prog, + struct region_device *rdev_out) { - rdev_chain(&prog->rdev, &addrspace_32bit.rdev, ptr, size); + assert(prog->size); + rdev_chain(rdev_out, &addrspace_32bit.rdev, + (uintptr_t)prog->start, prog->size); } static inline void prog_set_area(struct prog *prog, void *start, size_t size) { - prog_memory_init(prog, (uintptr_t)start, size); + prog->start = start; + prog->size = size; } static inline void prog_set_entry(struct prog *prog, void *e, void *arg) diff --git a/src/soc/amd/common/block/pi/refcode_loader.c b/src/soc/amd/common/block/pi/refcode_loader.c index 2fdbe83..bedd847 100644 --- a/src/soc/amd/common/block/pi/refcode_loader.c +++ b/src/soc/amd/common/block/pi/refcode_loader.c @@ -65,8 +65,9 @@ } } - return rdev_chain(rdev, prog_rdev(&prog), 0, - region_device_sz(prog_rdev(&prog))); + prog_chain_mem_rdev(&prog, rdev); + + return 0; } static int agesa_locate_stage_file(const char *name, struct region_device *rdev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Gerrit-Change-Number: 46483 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 33

Change in coreboot[master]: cbfstool: Move alignment/baseaddress handling into cbfs_add_component()
by Julius Werner (Code Review) 16 Mar '21

16 Mar '21

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47823 ) Change subject: cbfstool: Move alignment/baseaddress handling into cbfs_add_component() ...................................................................... cbfstool: Move alignment/baseaddress handling into cbfs_add_component() The --alignment flag is currently only handled by cbfstool add, but there seems little reason to not handle it for all file-adding commands (the help text actually mentions it for add-stage as well but it doesn't currently work there). This patch moves the related code (and the related baseaddress handling) into cbfs_add_component(). As a nice side effect this allows us to rearrange cbfs_add_component() such that we can conclusively determine whether we need a hash attribute before trying to align the file, allowing that code to correctly infer the final header size even when a hash attribute was implicitly added (for an image built with CBFS verification enabled). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 --- M util/cbfstool/cbfstool.c 1 file changed, 37 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47823/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 878db22..68c2c22 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -301,7 +301,7 @@ return convert_to_from_absolute_top_aligned(region, offset); } -static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size, +static int do_cbfs_locate(uint32_t *cbfs_addr, size_t metadata_size, size_t data_size) { if (!param.filename) { @@ -363,7 +363,7 @@ int32_t address = cbfs_locate_entry(&image, data_size, param.pagesize, param.alignment, metadata_size); - if (address == -1) { + if (address < 0) { ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", param.name, param.pagesize, param.alignment); return 1; @@ -616,11 +616,16 @@ static int cbfs_add_component(const char *filename, const char *name, uint32_t type, - uint32_t offset, uint32_t headeroffset, convert_buffer_t convert) { size_t len_align = 0; + uint32_t offset = param.baseaddress_assigned ? param.baseaddress : 0; + + if (param.alignment && param.baseaddress_assigned) { + ERROR("Cannot specify both alignment and base address\n"); + return 1; + } if (!filename) { ERROR("You need to specify -f/--filename.\n"); @@ -652,22 +657,9 @@ return 1; } - /* - * Check if Intel CPU topswap is specified this will require a - * second bootblock to be added. - */ - if (type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) - if (add_topswap_bootblock(&buffer, &offset)) - return 1; - struct cbfs_file *header = cbfs_create_file_header(type, buffer.size, name); - if (convert && convert(&buffer, &offset, header) != 0) { - ERROR("Failed to parse file '%s'.\n", filename); - goto error; - } - /* Bootblock and CBFS header should never have file hashes. When adding the bootblock it is important that we *don't* look up the metadata hash yet (before it is added) or we'll cache an outdated result. */ @@ -683,12 +675,31 @@ goto error; } } + } - if (param.hash != VB2_HASH_INVALID && - cbfs_add_file_hash(header, &buffer, param.hash) == -1) { - ERROR("couldn't add hash for '%s'\n", name); + /* This needs to run after potentially updating param.hash above. */ + if (param.alignment) + if (do_cbfs_locate(&offset, 0, 0)) goto error; - } + + /* + * Check if Intel CPU topswap is specified this will require a + * second bootblock to be added. + */ + if (type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) + if (add_topswap_bootblock(&buffer, &offset)) + goto error; + + if (convert && convert(&buffer, &offset, header) != 0) { + ERROR("Failed to parse file '%s'.\n", filename); + goto error; + } + + /* This needs to run after convert(). */ + if (param.hash != VB2_HASH_INVALID && + cbfs_add_file_hash(header, &buffer, param.hash) == -1) { + ERROR("couldn't add hash for '%s'\n", name); + goto error; } if (param.autogen_attr) { @@ -700,7 +711,7 @@ CBFS_FILE_ATTR_TAG_POSITION, sizeof(struct cbfs_file_attr_position)); if (attrs == NULL) - return -1; + goto error; attrs->position = htonl(offset); } /* Add alignment attribute if used */ @@ -711,7 +722,7 @@ CBFS_FILE_ATTR_TAG_ALIGNMENT, sizeof(struct cbfs_file_attr_align)); if (attrs == NULL) - return -1; + goto error; attrs->alignment = htonl(param.alignment); } } @@ -722,7 +733,7 @@ CBFS_FILE_ATTR_TAG_IBB, sizeof(struct cbfs_file_attribute)); if (attrs == NULL) - return -1; + goto error; /* For Intel TXT minimum align is 16 */ len_align = 16; } @@ -736,7 +747,7 @@ header, CBFS_FILE_ATTR_TAG_PADDING, size); if (attr == NULL) - return -1; + goto error; } if (IS_TOP_ALIGNED_ADDRESS(offset)) @@ -892,7 +903,7 @@ return -1; if (param.stage_xip) { - int32_t address; + uint32_t address; size_t data_size; if (elf_program_file_size(buffer, &data_size) < 0) { @@ -1027,16 +1038,7 @@ static int cbfs_add(void) { - int32_t address; - convert_buffer_t convert; - uint32_t local_baseaddress = param.baseaddress; - - if (param.alignment && param.baseaddress) { - ERROR("Cannot specify both alignment and base address\n"); - return 1; - } - - convert = cbfstool_convert_raw; + convert_buffer_t convert = cbfstool_convert_raw; /* Set the alignment to 4KiB minimum for FSP blobs when no base address * is provided so that relocation can occur. */ @@ -1049,18 +1051,9 @@ return 1; } - if (param.alignment) { - /* CBFS compression file attribute is unconditionally added. */ - size_t metadata_sz = sizeof(struct cbfs_file_attr_compression); - if (do_cbfs_locate(&address, metadata_sz, 0)) - return 1; - local_baseaddress = address; - } - return cbfs_add_component(param.filename, param.name, param.type, - local_baseaddress, param.headeroffset, convert); } @@ -1082,7 +1075,6 @@ return cbfs_add_component(param.filename, param.name, CBFS_TYPE_STAGE, - param.baseaddress, param.headeroffset, cbfstool_convert_mkstage); } @@ -1092,7 +1084,6 @@ return cbfs_add_component(param.filename, param.name, CBFS_TYPE_SELF, - param.baseaddress, param.headeroffset, cbfstool_convert_mkpayload); } @@ -1112,7 +1103,6 @@ return cbfs_add_component(param.filename, param.name, CBFS_TYPE_SELF, - param.baseaddress, param.headeroffset, cbfstool_convert_mkflatpayload); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 Gerrit-Change-Number: 47823 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020