coreboot-gerrit November 2020

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Change in coreboot[master]: cpu/intel/haswell: Align cosmetics with Broadwell
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46913 ) Change subject: cpu/intel/haswell: Align cosmetics with Broadwell ...................................................................... cpu/intel/haswell: Align cosmetics with Broadwell Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 33 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/46913/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 15dcff5..86a9053 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -304,14 +304,15 @@ wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ - if (haswell_is_ult()) { - msr = rdmsr(MSR_VR_MISC_CONFIG2); - msr.lo &= ~0xffff; - /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; - wrmsr(MSR_VR_MISC_CONFIG2, msr); - } + if (!haswell_is_ult()) + return; + + msr = rdmsr(MSR_VR_MISC_CONFIG2); + msr.lo &= ~0xffff; + /* Allow CPU to control minimum voltage completely (15:8) and + * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ + msr.lo |= 0x006f; + wrmsr(MSR_VR_MISC_CONFIG2, msr); } static void configure_pch_power_sharing(void) @@ -382,8 +383,7 @@ u8 power_limit_1_val; if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - - 1; + power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; if (!(msr.lo & PLATFORM_INFO_SET_TDP)) return; @@ -491,26 +491,24 @@ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - /* Haswell ULT only supoprts the 3-5 latency response registers.*/ - if (haswell_is_ult()) { - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + /* Only Haswell ULT supports the 3-5 latency response registers */ + if (!haswell_is_ult()) + return; - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); - } + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } static void configure_thermal_target(void) @@ -595,7 +593,7 @@ } /* All CPUs including BSP will run the following function. */ -static void haswell_init(struct device *cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -640,10 +638,11 @@ initialize_vr_config(); - if (haswell_is_ult()) { - calibrate_24mhz_bclk(); - configure_pch_power_sharing(); - } + if (!haswell_is_ult()) + return; + + calibrate_24mhz_bclk(); + configure_pch_power_sharing(); } static int get_cpu_count(void) @@ -705,7 +704,7 @@ } static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = cpu_core_init, }; static const struct cpu_device_id cpu_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa Gerrit-Change-Number: 46913 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Top align bootblock program
by Kyösti Mälkki (Code Review) 07 Jan '21

07 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47599 ) Change subject: arch/x86: Top align bootblock program ...................................................................... arch/x86: Top align bootblock program Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_crt0.S M src/arch/x86/memlayout.ld M src/arch/x86/walkcbfs.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 12 files changed, 62 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47599/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3f41464..20262eb 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@ #include <cpu/x86/cr.h> -.section .text +.section ".init", "ax", @progbits /* * Include the old code for reset vector and protected mode entry. That code has @@ -53,3 +53,5 @@ /* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry + +.previous diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index b487e48..a68dac5 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,8 +28,6 @@ #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, - CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index b8d4fb9..66b97e3b 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -21,7 +21,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) .code32 -.section .text +.section ".init" .global walkcbfs_asm /* @@ -121,3 +121,5 @@ filemagic: .ascii "LARCHIVE" + +.previous diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..40cd60d 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +.section ".init" .global bootblock_pre_c_entry .code32 @@ -190,3 +191,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cde1ca3..1846408 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -7,6 +7,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e +.section ".init" .global bootblock_pre_c_entry #include <cpu/intel/car/cache_as_ram_symbols.inc> @@ -257,3 +258,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e3447..b48afac 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +.section ".init" .global bootblock_pre_c_entry .code32 @@ -179,3 +180,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538..b02fced 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,6 +8,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +.section ".init" .global bootblock_pre_c_entry .code32 @@ -390,3 +391,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..8bef63d 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,7 +43,7 @@ * if the revision of the update is newer than what is installed */ -.section .text +.section ".init" .global update_bsp_microcode update_bsp_microcode: @@ -151,3 +151,5 @@ .string "cpu_microcode_blob.bin" _update_bsp_microcode_end: + +.previous diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12be..e9ebac6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -28,10 +28,9 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. +/* Symbol _start16bit must reachable from the reset vector, and be aligned to + * 4kB to start AP CPUs with Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index d356034..be1209a 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -11,14 +11,28 @@ ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; #endif -/* - * _ROMTOP : The top of the ROM used where we - * need to put the reset vector. - */ - SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + . = BOOTBLOCK_TOP - PROGRAM_SZ; + . = ALIGN(16); + + _bootblock = .; + + INCLUDE "bootblock/lib/program.ld" + + . = ID_SECTION - EARLYASM_SZ; + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16); + BOOTBLOCK_TOP = .; + .init . : { + *(.init); + } + + /* + * Allocation reserves extra space here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + PROGRAM_SZ = SIZEOF(.text) + 32; + EARLYASM_SZ = SIZEOF(.init) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16); . = ID_SECTION; .id (.): { @@ -40,4 +54,9 @@ . = 15; BYTE(0x00); } + _ebootblock = .; } + +_bogus1 = ASSERT(_bootblock & 0x80000000, "Invalid linker script"); +_bogus2 = ASSERT(_start16bit & 0x80000000, "Invalid linker script"); +_bogus3 = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29..9235008 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +.section ".init" + .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -73,3 +76,4 @@ jmp stop _cache_as_ram_setup_end: +.previous diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 3eb7670..9d35d5c 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,9 +8,17 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/post_code.h> +.section ".init" + +.code32 +.globl _cache_as_ram_setup, _cache_as_ram_setup_end + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -43,3 +51,6 @@ post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: +.previous -- To view, visit https://review.coreboot.org/c/coreboot/+/47599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32518b1c19d08935727330314904b52a246af3c Gerrit-Change-Number: 47599 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK`
by Angel Pons (Code Review) 07 Jan '21

07 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46910 ) Change subject: cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK` ...................................................................... cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK` This is just to ease merging with Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46910/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index f44d304..d257d86 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -173,7 +173,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * HASWELL_BCLK; + clock_max = ratio_max * CPU_BCLK; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -237,7 +237,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * HASWELL_BCLK; + clock = ratio * CPU_BCLK; acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 9349a3d..0701332 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -18,7 +18,7 @@ #define HASWELL_STEPPING_ULT_C0 1 /* Haswell bus clock is fixed at 100MHz */ -#define HASWELL_BCLK 100 +#define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 32b6a9d..4b73c6a 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -596,7 +596,7 @@ wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); } static void configure_mca(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/46910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024 Gerrit-Change-Number: 46910 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAIL
by Martin Roth (Code Review) 07 Jan '21

07 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47671 ) Change subject: mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAIL ...................................................................... mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAIL The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in cb:29680. The default is currently to keep power off after a power failure. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308 --- M src/mainboard/asrock/h110m/Kconfig 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/47671/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index d923c30..a88f6c7 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -45,9 +45,4 @@ int default 512 #DDR4 -# This is overridden if CMOS is used for configuration values. -config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308 Gerrit-Change-Number: 47671 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Modify Shuboz variant to support proto
by Kane Chen (Code Review) 07 Jan '21

07 Jan '21

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48001 ) Change subject: mb/google/zork: Modify Shuboz variant to support proto ...................................................................... mb/google/zork: Modify Shuboz variant to support proto 1. Add ELAN touchscreen/touchpad to overridetree.cb 2. Follow Dalboz setting to add variant.c BUG=b:none BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb --- M src/mainboard/google/zork/variants/shuboz/Makefile.inc M src/mainboard/google/zork/variants/shuboz/overridetree.cb A src/mainboard/google/zork/variants/shuboz/variant.c 3 files changed, 53 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48001/1 diff --git a/src/mainboard/google/zork/variants/shuboz/Makefile.inc b/src/mainboard/google/zork/variants/shuboz/Makefile.inc index 295acd2..001ab6b 100644 --- a/src/mainboard/google/zork/variants/shuboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/shuboz/Makefile.inc @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./spd +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 1cc2364..d79997e 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -37,6 +37,23 @@ end # domain device mmio 0xfedc4000 on # APU_I2C2_BASE - end # device - + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + end end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c new file mode 100644 index 0000000..cbc160e --- /dev/null +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> + +static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb Gerrit-Change-Number: 48001 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/razer/blade_stealth_kbl: Remove comments with pad functions
by Maxim Polyakov (Code Review) 07 Jan '21

07 Jan '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45370 ) Change subject: mb/razer/blade_stealth_kbl: Remove comments with pad functions ...................................................................... mb/razer/blade_stealth_kbl: Remove comments with pad functions Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have. Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45370/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 495c905..5dc1da4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -22,158 +22,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), -/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), -/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), -/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), -/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B8, NONE), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B10, NONE), -/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), -/* GPIO */ PAD_NC(GPP_B16, NONE), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), -/* GPIO */ PAD_NC(GPP_B19, NONE), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), -/* GPP_C6 - RESERVED */ -/* GPP_C7 - RESERVED */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), -/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), -/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), -/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), -/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), -/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), -/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), -/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), -/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), -/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), -/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), -/* GPIO */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), -/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), -/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), -/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), -/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), -/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), -/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), -/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), -/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), -/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), + PAD_CFG_GPO(GPP_A12, 1, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_CFG_GPO(GPP_B15, 0, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E9, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; #endif /* __ACPI__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Gerrit-Change-Number: 45370 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8
by Angel Pons (Code Review) 06 Jan '21

06 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46952 ) Change subject: mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 ...................................................................... mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8 Haswell and Broadwell have at most 8 threads. Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/wtm2/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46952/1 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 61d7657..bb0fdf4 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -29,7 +29,7 @@ config MAX_CPUS int - default 16 + default 8 config VGA_BIOS_FILE string -- To view, visit https://review.coreboot.org/c/coreboot/+/46952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Gerrit-Change-Number: 46952 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: util/testing: Build test more of our tools
by Patrick Georgi (Code Review) 06 Jan '21

06 Jan '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47446 ) Change subject: util/testing: Build test more of our tools ...................................................................... util/testing: Build test more of our tools https://qa.coreboot.org/job/untested-coreboot-files reports a bunch of untouched Makefiles, so we never even attempt to build those tools. Change-Id: I70ca658d9642b84fa8388c72ecb83327a6a74291 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/testing/Makefile.inc 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47446/1 diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc index d094196..20f19d9 100644 --- a/util/testing/Makefile.inc +++ b/util/testing/Makefile.inc @@ -54,10 +54,15 @@ cbmem \ ectool \ futility \ +genprof \ +intelmetool \ inteltool \ intelvbttool \ nvramtool \ -superiotool +post \ +superiotool \ +uio_usbdebug \ +vgabios TEST_PAYLOADLIST_INTERNAL= \ coreinfo \ -- To view, visit https://review.coreboot.org/c/coreboot/+/47446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70ca658d9642b84fa8388c72ecb83327a6a74291 Gerrit-Change-Number: 47446 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/mediatek/mt8192: add pmif driver
by CK HU (Code Review) 06 Jan '21

06 Jan '21

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45398 to review the following change. Change subject: soc/mediatek/mt8192: add pmif driver ...................................................................... soc/mediatek/mt8192: add pmif driver MT8192 uses power management interface(PMIF) to access pmics by spmi and spi, so we add pmif driver to control pmics. TEST=Boots correctly on MT8192EVB. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/include/soc/addressmap.h M src/soc/mediatek/mt8192/include/soc/pll.h A src/soc/mediatek/mt8192/include/soc/pmif.h A src/soc/mediatek/mt8192/include/soc/pmif_spi.h A src/soc/mediatek/mt8192/include/soc/pmif_spmi.h A src/soc/mediatek/mt8192/include/soc/pmif_sw.h A src/soc/mediatek/mt8192/include/soc/spmi.h A src/soc/mediatek/mt8192/pmif.c A src/soc/mediatek/mt8192/pmif_clk.c A src/soc/mediatek/mt8192/pmif_spi.c A src/soc/mediatek/mt8192/pmif_spmi.c 13 files changed, 1,550 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45398/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 533eae2..0fc47c4 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 8dffe56..0852f0e 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/pmif.h> #include <soc/wdt.h> void bootblock_soc_init(void) @@ -10,4 +11,5 @@ mtk_mmu_init(); mtk_wdt_init(); mt_pll_init(); + mtk_pmif_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd536..e9cb788 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -21,7 +21,11 @@ GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, - PWRAP_BASE = IO_PHYS + 0x0000D000, + MODEM_TEMP_SHARE_BASE = IO_PHYS + 0x00018000, + PMIF_SPI_BASE = IO_PHYS + 0x00026000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + PMICSPI_MST_BASE = IO_PHYS + 0x00028000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 442aa30..c83436e 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -178,7 +178,11 @@ u32 mfgpll_con2; u32 mfgpll_con3; u32 ap_pllgp1_con2; - u32 reserved2[33]; + u32 reserved2[13]; + u32 ulposc1_con0; + u32 ulposc1_con1; + u32 ulposc1_con2; + u32 reserved3[17]; u32 ap_pllgp2_con0; /* 0x0300 */ u32 ap_pllgp2_con1; u32 univpll_con0; diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h new file mode 100644 index 0000000..6106a3d --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT8192_SOC_PMIF_H__ +#define __MT8192_SOC_PMIF_H__ + +#include <types.h> + +enum { + PMIF_CMD_REG_0, + PMIF_CMD_REG, + PMIF_CMD_EXT_REG, + PMIF_CMD_EXT_REG_LONG, +}; + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[5]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[502]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1DC); +check_member(mtk_pmif_regs, crc_ctrl, 0x398); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B4); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E0); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x400); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x40C); +check_member(mtk_pmif_regs, irq_event_en_0, 0x418); +check_member(mtk_pmif_regs, swinf_0_acc, 0xC00); + +struct pmif { + struct mtk_pmif_regs *mtk_pmif; + int swinf_ch_start; + int swinf_no; + int mstid; + int pmifid; + int (*read_cmd)(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int *rdata); + int (*write_cmd)(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata); + int (*is_pmif_init_done)(struct pmif *arb); +}; + +enum { + PMIF_SPI, + PMIF_SPMI, +}; + +enum { + E_IO = 1, /* I/O error */ + E_BUSY, /* Device or resource busy */ + E_NODEV, /* No such device */ + E_INVAL, /* Invalid argument */ + E_OPNOTSUPP, /* Operation not supported on transport endpoint */ + E_TIMEOUT, /* Wait for idle time out */ + E_READ_TEST_FAIL, /* SPI read fail */ + E_SPI_INIT_RESET_SPI, /* reset SPI fail */ + E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ +}; + +/* start external API */ +extern struct pmif *get_pmif_controller(int inf, int mstid); +extern int mtk_pmif_init(void); +#endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h new file mode 100644 index 0000000..606dbbd --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_pmicspi_mst_regs { + u32 reserved1[4]; + u32 other_busy_sta_0; + u32 wrap_en; + u32 reserved2[2]; + u32 man_en; + u32 man_acc; + u32 reserved3[3]; + u32 mux_sel; + u32 reserved4[3]; + u32 dio_en; + u32 rddmy; + u32 cslext_write; + u32 cslext_read; + u32 cshext_write; + u32 cshext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 si_sampling_ctrl; +}; + +check_member(mt8192_pmicspi_mst_regs, other_busy_sta_0, 0x10); +check_member(mt8192_pmicspi_mst_regs, man_en, 0x20); +check_member(mt8192_pmicspi_mst_regs, mux_sel, 0x34); +check_member(mt8192_pmicspi_mst_regs, dio_en, 0x44); + +static struct mt8192_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE; + +struct mtk_iocfg_tl_regs { + u32 drv_cfg0; + u32 drv_cfg0_set; + u32 drv_cfg0_clr; +}; +check_member(mtk_iocfg_tl_regs, drv_cfg0_set, 0x4); +check_member(mtk_iocfg_tl_regs, drv_cfg0_clr, 0x8); + +#define mtk_iocfg_tl ((struct mtk_iocfg_tl_regs *)IOCFG_TL_BASE) + +struct mtk_modem_temp_share_regs { + u32 ctrl; +}; + +#define mtk_modem_temp_share ((struct mtk_modem_temp_share_regs *)SPM_BASE) + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0032, + PMIC_DRV_CON1 = PMIC_BASE + 0x003a, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0042, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040c, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040e, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0424, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0426, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044a, + PMIC_INT_STA = PMIC_BASE + 0x0452, + PMIC_AUXADC_ADC7 = PMIC_BASE + 0x1096, + PMIC_AUXADC_ADC10 = PMIC_BASE + 0x109c, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, +}; + +#define PMIF_SPI_MD_SWINF_NO 0 +#define PMIF_SPI_AP_SECURE_SWINF_NO 1 +#define PMIF_SPI_AP_SWINF_NO 2 +#define PMIF_SPI_SWINF_0_CHAN_NO 8 +#define PMIF_SPI_MD_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_MD_SWINF_NO) +#define PMIF_SPI_AP_SECURE_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_AP_SECURE_SWINF_NO) +#define PMIF_SPI_AP_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_AP_SWINF_NO) + +#define DEFAULT_SLVID 0 + +#define GET_PMICSPI_BUSY(x) ((x>>9) & 0x00000001) +#define GET_CMDISSUE_BUSY(x) ((x>>2) & 0x00000001) + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO), + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = (IO_4_MA << SPI_CLK_SHIFT | IO_4_MA << SPI_CSN_SHIFT | + IO_4_MA << SPI_MOSI_SHIFT | IO_4_MA << SPI_MISO_SHIFT), +}; + +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a +}; + +enum { + DUMMY_READ_CYCLES = 0X8, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING +}; +extern int pmif_spi_init(struct pmif *arb); +#endif /* __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h new file mode 100644 index 0000000..5f89ddc --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SPMI_H__ +#define __PMIF_SPMI_H__ + +#include <soc/addressmap.h> + +#define DEFAULT_VALUE_READ_TEST (0x5a) +#define DEFAULT_VALUE_WRITE_TEST (0xa5) + +#define GET_REC_CMD(x) (x & 0x00000003) +#define GET_REC_W(x) ((x>>2) & 0x00000001) +#define GET_REC_OP_ST_NACK(x) ((x>>3) & 0x00000001) +#define GET_REC_PMIF_NACK(x) ((x>>4) & 0x00000001) +#define GET_REC_PMIF_PARITY_ERR(x) ((x>>5) & 0x00000001) +#define GET_REC_PMIF_BYTE_ERR(x) ((x>>6) & 0x00000001) +#define GET_REC_PMIF_GRP_RD_ERR(x) ((x>>7) & 0x00000001) +#define GET_REC_SLVID(x) ((x>>8) & 0x0000000f) +#define GET_REC_BYTECNT(x) ((x>>12) & 0x0000000f) +#define GET_REC_ADDR(x) ((x>>16) & 0x0000ffff) + +/* + * GPIO number for IO driving config, + * These can be look up by platform/<mtxxxx>/src/drivers/inc/gpio_cfg.h + * must check by platform + */ +#define SPMI_SCL_GPIO 89 +#define SPMI_SDA_GPIO 90 +#define SPMI_SCL_DRV_SHIFT (3) +#define SPMI_SDA_DRV_SHIFT (6) + +#define SPMIMST_RST_SHIFT 4 +#define WDT_UNLOCK_SHIFT 24 + +#define WDT_UNLOCK_KEY 0x85 + +struct mtk_rgu_regs { + u32 reserved[36]; + u32 wdt_swsysrst2; +}; +check_member(mtk_rgu_regs, wdt_swsysrst2, 0x0090); + +struct mtk_iocfg_bm_regs { + u32 reserved[9]; + u32 drv_cfg2_set; + u32 drv_cfg2_clr; +}; +check_member(mtk_iocfg_bm_regs, drv_cfg2_set, 0x0024); +check_member(mtk_iocfg_bm_regs, drv_cfg2_clr, 0x0028); + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 reserved[263]; + u32 ulposc_con; +}; +check_member(mtk_spm_regs, ulposc_con, 0x0420); + +struct mtk_spmi_mst_reg { + u32 op_st_ctrl; + u32 grp_id_en; + u32 op_st_sta; + u32 mst_sampl; + u32 mst_req_en; + u32 reserved1[11]; + u32 rec_ctrl; + u32 rec0; + u32 rec1; + u32 rec2; + u32 rec3; + u32 rec4; + u32 reserved2[41]; + u32 mst_dbg; +}; + +check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40); +check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc); + +#define mtk_rug ((struct mtk_rgu_regs *)RGU_BASE) +#define mtk_iocfg_bm ((struct mtk_iocfg_bm_regs *)IOCFG_BM_BASE) +#define mtk_spm ((struct mtk_spm_regs *)SPM_BASE) +#define mtk_spmi_mst ((struct mtk_spmi_mst_reg *)SPMI_MST_BASE) + +struct cali { + unsigned int dly; + unsigned int pol; +}; + +enum +{ + SPMI_CK_NO_DLY = 0, + SPMI_CK_DLY_1T +}; + +enum +{ + SPMI_CK_POL_NEG = 0, + SPMI_CK_POL_POS +}; + +enum +{ + SPMI_OP_ST_BUSY = 1, + SPMI_OP_ST_ACK = 0, + SPMI_OP_ST_NACK = 1 +}; + +enum +{ + SPMI_RCS_SR_BIT, + SPMI_RCS_A_BIT +}; + +enum +{ + SPMI_RCS_MST_W = 1, + SPMI_RCS_SLV_W = 3 +}; + +enum +{ + SPMI_RESET = 0, + SPMI_SLEEP, + SPMI_SHUTDOWN, + SPMI_WAKEUP +}; + +enum spmi_regs { + SPMI_OP_ST_CTRL, + SPMI_GRP_ID_EN, + SPMI_OP_ST_STA, + SPMI_MST_SAMPL, + SPMI_MST_REQ_EN, + SPMI_REC_CTRL, + SPMI_REC0, + SPMI_REC1, + SPMI_REC2, + SPMI_REC3, + SPMI_REC4, + SPMI_MST_DBG +}; + +extern int pmif_spmi_init(struct pmif *arb); +#endif /*__PMIF_SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_sw.h b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h new file mode 100644 index 0000000..1d250bf --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SW_H__ +#define __PMIF_SW_H__ + +/* Read/write byte limitation, by project */ +/* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ +#define PMIF_BYTECNT_MAX 1 + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE (0x00) +#define SWINF_FSM_REQ (0x02) +#define SWINF_FSM_WFDLE (0x04) +#define SWINF_FSM_WFVLDCLR (0x06) +#define SWINF_INIT_DONE (0x01) + +/* indicate which number SW channel start, by project */ +#define PMIF_SWINF_0_CHAN_NO 4 + +/* MD: 0, security domain: 1, AP: 2 */ +#define PMIF_AP_SWINF_NO 2 + +#define GET_SWINF_0_FSM(x) ((x >> 1) & 0x7) + +struct pmif_mpu { + unsigned int rgn_slvid; + unsigned short rgn_s_addr; + unsigned short rgn_e_addr; + unsigned int rgn_domain_per; +}; + +enum { + PMIF_READ_US = 1000, + PMIF_WAIT_IDLE_US = 1000, +}; +extern int pmif_clk_init(void); +#endif /*__PMIF_SW_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/spmi.h b/src/soc/mediatek/mt8192/include/soc/spmi.h new file mode 100644 index 0000000..61e49b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spmi.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPMI_H__ +#define __SPMI_H__ + +/* enum marco for cmd/channel */ +enum spmi_master +{ + SPMI_MASTER_0, + SPMI_MASTER_1, + SPMI_MASTER_2, + SPMI_MASTER_3 +}; + +enum spmi_slave +{ + SPMI_SLAVE_0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15 +}; + +enum slv_type +{ + BUCK_CPU, + BUCK_GPU, + BUCK_MD, + BUCK_RF, + MAIN_PMIC, + BUCK_VPU, + SUB_PMIC, + SLV_TYPE_MAX +}; + +enum slv_type_id +{ + BUCK_RF_ID = 1, + BUCK_MD_ID = 3, + MAIN_PMIC_ID = 5, + BUCK_CPU_ID = 6, + BUCK_GPU_ID = 7, + BUCK_VPU_ID, + SUB_PMIC_ID = 10, + SLV_TYPE_ID_MAX +}; + +struct spmi_device { + int slvid; + int grpiden; + enum slv_type type; + enum slv_type_id type_id; +}; +#endif /*__SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/pmif.c b/src/soc/mediatek/mt8192/pmif.c new file mode 100644 index 0000000..ca42d37 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pmif.h> +#include <soc/pmif_spi.h> +#include <soc/pmif_spmi.h> +#include <soc/pmif_sw.h> +#include <soc/spmi.h> +#include <string.h> +#include <timer.h> + +static unsigned int pmif_check_idle(struct pmif *arb, unsigned int timeout_us) { + unsigned int reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32(&arb->mtk_pmif->swinf_0_sta + 0x10 * arb->swinf_no); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_IDLE); + + return 0; +} + +static inline unsigned int pmif_check_vldclr(struct pmif *arb, unsigned int timeout_us) { + unsigned int reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32(&arb->mtk_pmif->swinf_0_sta + 0x10 * arb->swinf_no); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_WFVLDCLR); + + return 0; +} + +static int pmif_send_cmd(struct pmif *arb, unsigned int write, + unsigned int opc, unsigned int slvid, unsigned int addr, + unsigned int *rdata, unsigned int wdata, unsigned int len) +{ + unsigned int ret = 0, data = 0; + unsigned int bc = len - 1; + + bc = 0; + /* Wait for Software Interface FSM state to be IDLE. */ + ret = pmif_check_idle(arb, PMIF_WAIT_IDLE_US); + if(ret) + return ret; + + /* Set the write data */ + if (write == 1) { + /* Set the write data. */ + write32(&arb->mtk_pmif->swinf_0_wdata_31_0 + 0x10 * arb->swinf_no, wdata); + } + + /* Send the command. */ + write32(&arb->mtk_pmif->swinf_0_acc + 0x10 * arb->swinf_no, + (opc << 30) | (write << 29) | (slvid << 24) | (bc << 16) | addr); + + if (write == 0) { + /* Wait for Software Interface FSM state to be WFVLDCLR, + * + * read the data and clear the valid flag. + */ + ret = pmif_check_vldclr(arb, PMIF_READ_US); + if(ret) + return ret; + + data = read32(&arb->mtk_pmif->swinf_0_rdata_31_0 + 0x10 * arb->swinf_no); + *rdata = data; + write32(&arb->mtk_pmif->swinf_0_vld_clr + 0x10 * arb->swinf_no, 0x1); + } + + return 0; +} + +static int pmif_spmi_read_cmd(struct pmif *arb,unsigned int slvid, + unsigned int addr, unsigned int *rdata) +{ + + return pmif_send_cmd(arb, 0, PMIF_CMD_EXT_REG_LONG, slvid, addr, rdata, 0, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spmi_write_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata) +{ + return pmif_send_cmd(arb, 1, PMIF_CMD_EXT_REG_LONG, slvid, addr, NULL, wdata, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spi_read_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int *rdata) +{ + + return pmif_send_cmd(arb, 0, PMIF_CMD_REG_0, slvid, addr, rdata, 0, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spi_write_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata) +{ + return pmif_send_cmd(arb, 1, PMIF_CMD_REG_0, slvid, addr, NULL, wdata, (PMIF_BYTECNT_MAX - 1)); +} + +static int is_pmif_init_done(struct pmif *arb) +{ + if ((read32(&arb->mtk_pmif->init_done) & 0x1)) + return 0; + + return -E_NODEV; +} + +static struct pmif pmif_spmi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_BASE, + .swinf_ch_start = PMIF_SWINF_0_CHAN_NO, + .swinf_no = PMIF_AP_SWINF_NO, + .mstid = SPMI_MASTER_0, + .pmifid = PMIF_SPMI, + .write_cmd = pmif_spmi_write_cmd, + .read_cmd = pmif_spmi_read_cmd, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +static struct pmif pmif_spi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, + .swinf_no = PMIF_AP_SWINF_NO, + .pmifid = PMIF_SPI, + .write_cmd = pmif_spi_write_cmd, + .read_cmd = pmif_spi_read_cmd, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +struct pmif *get_pmif_controller(int inf, int mstid) +{ + if (inf == PMIF_SPMI) + return &pmif_spmi_arb[mstid]; + else if (inf == PMIF_SPI) + return &pmif_spi_arb[0]; + + return NULL; +} + +int mtk_pmif_init(void) +{ + int ret = 1; + + ret = pmif_clk_init(); + if (ret) + goto FAIL; + + ret = pmif_spmi_init(&pmif_spmi_arb[SPMI_MASTER_0]); + if (ret) + goto FAIL; + + ret = pmif_spi_init(&pmif_spi_arb[0]); + if (ret) + goto FAIL; + + return 0; + +FAIL: + /* assert(0); */ + return ret; +} diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c new file mode 100644 index 0000000..96dfe0e --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_clk.c @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/pmif.h> +#include <soc/pmif_sw.h> +#include <soc/pmif_spmi.h> + +#define FREQ_260MHZ 260 +/* calibation miss rate, unit: 0.1% */ +#define CAL_MIS_RATE 40 +/* + * FREQ METER ID + * Ask clkmgr owner to find this information + * at clock table[fmeter]. + */ +#define FREQ_METER_ABIST_AD_OSC_CK 37 +#define CAL_MAX_VAL 0x7f + +static unsigned int mt_get_abist_freq(unsigned int ID) +{ + int output = 0, i = 0; + unsigned int temp, clk26cali_0, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1; + + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + /* sel abist_cksw and enable freq meter sel abist */ + write32(&mtk_topckgen->clk_dbg_cfg, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16)); + + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + /* select divider, div 4 */ + write32(&mtk_topckgen->clk_misc_cfg_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24)); + + clk26cali_0 = read32(&mtk_topckgen->clk26cali_0); + clk26cali_1 = read32(&mtk_topckgen->clk26cali_1); + write32(&mtk_topckgen->clk26cali_0, 0x1000); + write32(&mtk_topckgen->clk26cali_0, 0x1010); + + /* wait frequency meter finish */ + while (read32(&mtk_topckgen->clk26cali_0) & 0x10) + { + udelay(10); + i++; + if(i > 100) + break; + } + + temp = read32(&mtk_topckgen->clk26cali_1) & 0xFFFF; + output = ((temp * 26000) ) / 1024; /* Khz */ + + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + write32(&mtk_topckgen->clk26cali_0, clk26cali_0); + write32(&mtk_topckgen->clk26cali_1, clk26cali_1); + + return output * 4; +} + +static void pmif_ulposc_config(void) +{ + /* Config ULPOSC_CON0 */ + /* OSC_CP_EN = 0 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x1 << 24)); + + /* OSC_DIV = 1110 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x3f << 18)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0xe << 18)); + + /* OSC_FBAND = 0010 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0xf << 14)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0x2 << 14)); + + /* OSC_IBAND = 1010010 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f << 7)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0x52 << 7)); + + /* OSC_CALI = 1000000 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | 0x40); + + /* + **** Config ULPOSC_CON1 *** + */ + + /* OSC_DIV2_EN= 1b'0 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0x1 << 26)); + + /* OSC_MOD = 00 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0x3 << 24)); + + /* OSC_RSV2= 8b'00000000 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff << 16)); + + /* OSC_RSV1= 8b'00101001 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff << 8)); + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) | (0x29 << 8)); + + /* OSC_32KCALI = 8b'00000000 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff)); + + /* + **** Config ULPOSC_CON2 *** + */ + + /* OSC_BIAS= 8b'01000010 */ + write32(&mtk_apmixed->ulposc1_con2, read32(&mtk_apmixed->ulposc1_con2) &~(0xff)); + write32(&mtk_apmixed->ulposc1_con2, read32(&mtk_apmixed->ulposc1_con2) | (0x40)); + +} + +static u32 pmif_get_ulposc_freq(u32 cali_val) +{ + u32 result = 0; + + /* set calibration value */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | cali_val); + + udelay(50); + + result = mt_get_abist_freq(FREQ_METER_ABIST_AD_OSC_CK); + + return result / 1000; +} + +static int pmif_ulposc_cali(void) +{ + u32 current_val = 0, min = 0, max = CAL_MAX_VAL, middle; + u32 diff_by_min = 0, diff_by_max = 0xffff, cal_result; + int ret = 0; + + do { + middle = (min + max) / 2; + if (middle == min) + break; + + current_val = pmif_get_ulposc_freq(middle); + + if (current_val > FREQ_260MHZ) + max = middle; + else + min = middle; + } while (min <= max); + + current_val = pmif_get_ulposc_freq(min); + if (current_val > FREQ_260MHZ) + diff_by_min = current_val - FREQ_260MHZ; + else + diff_by_min = FREQ_260MHZ - current_val; + + current_val = pmif_get_ulposc_freq(max); + if (current_val > FREQ_260MHZ) + diff_by_max = current_val - FREQ_260MHZ; + else + diff_by_max = FREQ_260MHZ - current_val; + + if (diff_by_min < diff_by_max) { + cal_result = min; + current_val = pmif_get_ulposc_freq(min); + } else { + cal_result = max; + current_val = pmif_get_ulposc_freq(max); + } + + /* check if calibrated value is in the range of target value +- 15% */ + if (current_val < (FREQ_260MHZ * (1000 - CAL_MIS_RATE) / 1000) + || current_val > (FREQ_260MHZ * (1000 + CAL_MIS_RATE) / 1000)) { + printk(BIOS_ERR, "[%s]calibration fail: %dM\n", __func__, current_val); + ret = 1; + } + + return ret; +} + +static int pmif_init_ulposc(void) +{ + int ret = 1; + + /* calibrate ULPOSC1 */ + pmif_ulposc_config(); + + /* enable spm swinf */ + if ((read32(&mtk_spm->poweron_config_en) & 0x1) != 0x1) + write32(&mtk_spm->poweron_config_en, (0xb16 << 16) | 0x1); + + /* turn on ulposc */ + write32(&mtk_spm->ulposc_con, read32(&mtk_spm->ulposc_con) | 0x1); + udelay(100); + write32(&mtk_spm->ulposc_con, read32(&mtk_spm->ulposc_con) | 0x1 << 2); + + ret = pmif_ulposc_cali(); + return ret; +} + +int pmif_clk_init(void) +{ + int ret = 1; + + ret = pmif_init_ulposc(); + if(ret) + return -E_NODEV; + + /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + write32(&mt8192_infracfg->module_sw_cg_0_set, 0xf); + /* Use MTS: modem_temp_share_cg need to enable + * DRV_WriteReg32(MODULE_SW_CG_2_SET, 0x00000020); + * Use TIA: modem_temp_share_cg not need + */ + write32(&mtk_topckgen->clk_cfg_8_clr, (0x1 << 15) | (0x1 << 12) | (0x7 << 8)); + write32(&mtk_topckgen->clk_cfg_update1, 0x1 << 2); + + /* use ULPOSC1 clock */ + write32(&mt8192_infracfg->pmicw_clock_ctrl_clr, 0xf); + + /* toggle SPMI sw reset */ + write32(&mt8192_infracfg->infra_globalcon_rst2_set, 0x1 << 14); + write32(&mt8192_infracfg->infra_globalcon_rst2_clr, 0x1 << 14); + + /* toggle SPI sw reset */ + write32(&mt8192_infracfg->infra_globalcon_rst2_set, 0x1); + write32(&mt8192_infracfg->infra_globalcon_rst2_clr, 0x1); + + /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + write32(&mt8192_infracfg->module_sw_cg_0_clr, 0xf); + /* Use MTS: modem_temp_share_cg need to enable + * DRV_WriteReg32(MODULE_SW_CG_2_CLR, 0x00000020); + * Use TIA: modem_temp_share_cg not need + */ + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spi.c b/src/soc/mediatek/mt8192/pmif_spi.c new file mode 100644 index 0000000..e1d77aa --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spi.c @@ -0,0 +1,319 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pmif.h> +#include <soc/pmif_spi.h> +#include <soc/pmif_sw.h> +#include <timer.h> + +/* PMIF, SPI_MODE_CTRL */ +DEFINE_BIT(SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 5) +DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9) +DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10) +DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11) + +/* PMIF, SLEEP_PROTECTION_CTRL */ +DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) + +/* PMIF, STAUPD_CTRL */ +DEFINE_BITFIELD(STAUPD_CTRL_PRD, 3, 0) +DEFINE_BIT(STAUPD_CTRL_PMIC0_SIG_STA, 4) +DEFINE_BIT(STAUPD_CTRL_PMIC0_EINT_STA, 6) + +/* SPIMST, Manual_Mode_Access */ +DEFINE_BIT(SPI_RW, 13) +DEFINE_BITFIELD(SPI_OP, 12, 8) + +static void pmif_spi_config(struct pmif *arb) +{ + /* Set srclk_en always valid regardless of ulposc_sel_for_scp */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 0); + + + /* Set SPI mode controlled by srclk_en and srvol_en instead of pmif_rdy */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_SRCLK_EN, 1, SPI_MODE_CTRL_SRVOL_EN, 1); + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_PMIF_RDY, 0); + + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0); + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SCP_SLEEP_REQ_SEL, 0); + + /* Enable SWINF for AP */ + write32(&arb->mtk_pmif->inf_en, PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable arbitration for SWINF for AP */ + write32(&arb->mtk_pmif->arb_en, PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable PMIF_SPI Command Issue */ + write32(&arb->mtk_pmif->cmdissue_en, 1); +} + +static signed int reset_spislv(void) +{ + unsigned int pmicspi_mst_dio_en_backup, rdata; + struct stopwatch sw; + + write32(&mtk_pmicspi_mst->wrap_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 1); + write32(&mtk_pmicspi_mst->man_en, 1); + pmicspi_mst_dio_en_backup = read32(&mtk_pmicspi_mst->dio_en); + write32(&mtk_pmicspi_mst->dio_en, 0); + + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_CSL); + /* Reset counter */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_CSH); + /* + * In order to pull CSN signal to PMIC, + * PMIC will count it then reset spi slave + */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + + /* Wait for PMIC SPI Master to be idle */ + stopwatch_init_usecs_expire(&sw, PMIF_WAIT_IDLE_US); + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + write32(&mtk_pmicspi_mst->man_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 0); + write32(&mtk_pmicspi_mst->wrap_en, 1); + write32(&mtk_pmicspi_mst->dio_en, pmicspi_mst_dio_en_backup); + + return 0; +} + +static void init_reg_clock(struct pmif *arb) +{ + unsigned int rdata; + + /* Set SoC SPI IO driving strength to 4 mA */ + write32(&mtk_iocfg_tl->drv_cfg0_clr, 0x7 << 21); + write32(&mtk_iocfg_tl->drv_cfg0_set, 0x1 << 21); + + /* Configure SPI protocol */ + write32(&mtk_pmicspi_mst->ext_ck_write, 1); + write32(&mtk_pmicspi_mst->ext_ck_read, 0); + write32(&mtk_pmicspi_mst->cshext_write, 0); + write32(&mtk_pmicspi_mst->cshext_read, 0); + write32(&mtk_pmicspi_mst->cslext_write, 0); + write32(&mtk_pmicspi_mst->cslext_read, 0x100); + + /* Set Read Dummy Cycle Number (Slave Clock is 18MHz) */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + write32(&mtk_pmicspi_mst->rddmy, DUMMY_READ_CYCLES); + + /* Enable DIO mode */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_DIO_EN, 0x1); + + /* Wait for completion of sending the commands */ + do { + rdata = read32(&arb->mtk_pmif->inf_busy_sta); + } while ((rdata & PMIF_SPI_AP_SWINF_CHAN_NO) != 0x0); + + do { + rdata = read32(&arb->mtk_pmif->other_busy_sta_0); + } while (GET_CMDISSUE_BUSY(rdata) != 0x0); + + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + write32(&mtk_pmicspi_mst->dio_en, 1); +} + +static void init_spislv(struct pmif *arb) +{ + /* Turn on SPI IO filter function */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_FILTER_CON0, SPI_FILTER); + /* Turn on SPI IO SMT function to improve noise immunity */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SMT_CON1, SPI_SMT); + /* Turn off SPI IO pull function for power saving */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + /* Enable SPI access in SODI-3.0 and Suspend modes */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON0, 0x2); + /* Set SPI IO driving strength to 4 mA */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DRV_CON1, SPI_DRIVING); +} + +static s32 init_sistrobe(struct pmif *arb) +{ + unsigned int rdata = 0; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pmicspi_mst->si_sampling_ctrl, si_sample_ctrl << 5); + + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + /* + * Add the delay time of SPI data from PMIC to align the start boundary + * to current sampling clock edge. + */ + for (int si_dly = 0; si_dly < 10; si_dly++) { + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON2, si_dly); + + int start_boundary_found = 0; + for (size_t i = 0; i < 30; i++) { + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, test_data[i]); + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + start_boundary_found = 1; + break; + } + } + if (start_boundary_found == 1) + break; + } + + /* + * Change the sampling clock edge to the next one which is the middle + * of SPI data window. + */ + write32(&mtk_pmicspi_mst->si_sampling_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + printk(BIOS_ERR, "[%s] rdata = %#x, exp = %#x\n", + __func__, rdata, DEFAULT_VALUE_READ_TEST); + return E_READ_TEST_FAIL; + } + + return 0; +} + +static void initstaupd(struct pmif *arb) +{ + unsigned int rdata; + + /* Unlock SPI Slave registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0xbade); + + /* Enable CRC of PMIC 0 */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_CRC_EN, 0x1); + + /* Wait for completion of sending the commands */ + do { + rdata = read32(&arb->mtk_pmif->inf_busy_sta); + } while ((rdata & PMIF_SPI_AP_SWINF_CHAN_NO) != 0x0); + + do { + rdata = read32(&arb->mtk_pmif->other_busy_sta_0); + } while (GET_CMDISSUE_BUSY(rdata) != 0x0); + + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + /* Configure CRC of PMIC Interface */ + write32(&arb->mtk_pmif->crc_ctrl, 0x1); + write32(&arb->mtk_pmif->sig_mode, 0x0); + + /* Lock SPI Slave registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* Setup PMIC Siganature */ + write32(&arb->mtk_pmif->pmic_sig_addr, PMIC_DEW_CRC_VAL); + + /* Setup PMIC EINT */ + write32(&arb->mtk_pmif->pmic_eint_sta_addr, PMIC_INT_STA); + + SET32_BITFIELDS(&arb->mtk_pmif->staupd_ctrl, STAUPD_CTRL_PRD, 5, + STAUPD_CTRL_PMIC0_SIG_STA, 1, STAUPD_CTRL_PMIC0_EINT_STA, 1); +} + +int pmif_spi_init(struct pmif *arb) +{ + int sub_return = 0; + + pmif_spi_config(arb); + + /* Reset spislv */ + sub_return = reset_spislv(); + if (sub_return != 0) + return E_SPI_INIT_RESET_SPI; + + /* Enable WRAP */ + write32(&mtk_pmicspi_mst->wrap_en, 0x1); + + /* SPI Waveform Configuration */ + init_reg_clock(arb); + + /* SPI Slave Configuration */ + init_spislv(arb); + + /* Input data calibration flow; */ + sub_return = init_sistrobe(arb); + if (sub_return != 0) { + printk(BIOS_ERR, "[%s] data calibration fail,ret=%d\n", + __func__, sub_return); + return E_SPI_INIT_SIDLY; + } + + /* Lock SPISLV Registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + initstaupd(arb); + + /* Configure PMIF Timer */ + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + + /* Enable interfaces and arbitration */ + write32(&arb->mtk_pmif->inf_en, 0x307f | + PMIF_SPI_MD_SWINF_CHAN_NO | + PMIF_SPI_AP_SECURE_SWINF_CHAN_NO | + PMIF_SPI_AP_SWINF_CHAN_NO); + + write32(&arb->mtk_pmif->arb_en, 0x707f | + PMIF_SPI_MD_SWINF_CHAN_NO | + PMIF_SPI_AP_SECURE_SWINF_CHAN_NO | + PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable GPS AUXADC HW 0 and 1 */ + write32(&arb->mtk_pmif->arb_en, read32(&arb->mtk_pmif->arb_en) | (0x3 << 19)); + write32(&arb->mtk_pmif->other_inf_en, read32(&arb->mtk_pmif->other_inf_en) | (0x3 << 4)); + + /* Set INIT_DONE */ + write32(&arb->mtk_pmif->init_done, 0x1); + + /* Configure MD ADC Interface */ + udelay(100); + + /* write MODEM_TEMP_SHARE_CTRL start */ + write32(&mtk_modem_temp_share->ctrl, 0xf0); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c new file mode 100644 index 0000000..4a9af68 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pmif.h> +#include <soc/spmi.h> +#include <soc/pmif_sw.h> +#include <soc/pmif_spmi.h> +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <string.h> +#include <console/console.h> +#include <soc/pll.h> +#include <soc/pll_common.h> + +#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) +#define PMIF_CMD_PER_1_3 \ + ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) +#define PMIF_CMD_PER_2_3 \ + ((0x1 << PMIF_CMD_EXT_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) + +/* spmi master setting */ +struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_6, + .grpiden = 0x800, + .type = BUCK_CPU, + .type_id = BUCK_CPU_ID, + }, { + .slvid = SPMI_SLAVE_7, + .grpiden = 0x800, + .type = BUCK_GPU, + .type_id = BUCK_GPU_ID, + }, +}; + +static int spmi_config_io(void) +{ + /* 0'b010 SPMI_SCL[5:3]; */ + write32(&mtk_iocfg_bm->drv_cfg2_set, 0x2 << SPMI_SCL_DRV_SHIFT); + write32(&mtk_iocfg_bm->drv_cfg2_clr, 0x5 << SPMI_SCL_DRV_SHIFT); + /* 0'b010 SPMI_SDA[6:8] */ + write32(&mtk_iocfg_bm->drv_cfg2_set, 0x2 << SPMI_SDA_DRV_SHIFT); + write32(&mtk_iocfg_bm->drv_cfg2_clr, 0x5 << SPMI_SDA_DRV_SHIFT); + + return 0; +} + +static int spmi_config_master(void) +{ + /* Software reset */ + write32(&mtk_rug->wdt_swsysrst2, + (WDT_UNLOCK_KEY << WDT_UNLOCK_SHIFT) | \ + (0x1 << SPMIMST_RST_SHIFT)); + + write32(&mtk_topckgen->clk_cfg_15_clr, (0x700) | (0x1 << 12) | (0x1 << 15)); + write32(&mtk_topckgen->clk_cfg_update2, (0x1 << 30)); + + /* Software reset */ + write32(&mtk_rug->wdt_swsysrst2, (WDT_UNLOCK_KEY << WDT_UNLOCK_SHIFT)); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + + return 0; +} + +static int spmi_read_check(struct pmif *pmif_arb, int slvid) +{ + unsigned int rdata = 0; + + + /* MT6315_PMIC_HWCID_H_ADDR/MT6315_HWCID_H 0x9 */ + pmif_arb->read_cmd(pmif_arb, slvid, 0x9, &rdata); + if (rdata != 0x15) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_IO; + } + + /*MT6315_PMIC_SWCID_H_ADDR/MT6315_SWCID_H 0xb*/ + pmif_arb->read_cmd(pmif_arb, slvid, 0xb, &rdata); + if (rdata != 0x15) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_IO; + } + + return 0; +} + +static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb, struct spmi_device *dev) +{ + unsigned int i = 0; + struct cali cali_data[] = { + {SPMI_CK_DLY_1T, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_NEG} + }; + + /* Indicate sampling clock polarity, 1: Positive 0: Negative */ + for (i = 0;i < 3; i++) { + write32(&mtk_spmi_mst->mst_sampl, (cali_data[i].dly << 0x1) | cali_data[i].pol); + if (spmi_read_check(pmif_arb, dev->slvid) == 0) + break; + } + + if (i == 3) { + printk(BIOS_ERR, "FATAL ERROR"); + /* ASSERT(0); */ + } + + return 0; +} + +static int spmi_mst_init(struct pmif *pmif_arb) +{ + int i; + unsigned char spmi_device_cnt; + + if (pmif_arb == NULL) { + printk(BIOS_ERR, "arguments err\n"); + return -E_INVAL; + } + + /* config IOCFG */ + spmi_config_io(); + spmi_config_master(); + + spmi_device_cnt = sizeof(spmi_dev)/sizeof(spmi_dev[0]); + for (i = 0; i < spmi_device_cnt; i++) { + //spmi_dev[i].pmif_arb = pmif_spmi_arb_ctrl[pmif_arb->mstid]; + spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]); + } + + return 0; +} + +static void pmif_spmi_force_normal_mode(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + unsigned int value; + + /* listen srclken_0 only for entering normal or sleep mode */ + value = read32(&arb->mtk_pmif->spi_mode_ctrl) & (~(0x1 << 7)); + write32(&arb->mtk_pmif->spi_mode_ctrl, value); + + /* enable srclken_en or srvol_en(VREQ) control */ + value |= ((0x1 << 12) | (0x1 << 13)); + /* disable srclken_rc control */ + value &= (~(0x1 << 11)); + write32(&arb->mtk_pmif->spi_mode_ctrl, value); + + /* enable spm/scp sleep request */ + value = read32(&arb->mtk_pmif->sleep_protection_ctrl); + value &= (~0x3); + value &= (~(0x3 << 9)); + write32(&arb->mtk_pmif->sleep_protection_ctrl, value); +} + +static void pmif_spmi_enable_swinf(int mstid, unsigned int chan_no, + unsigned int swinf_no) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* Enable swinf chan_no = 4, swinf_no = 2*/ + write32(&arb->mtk_pmif->inf_en, 0x1 << (chan_no + swinf_no)); + + /* Enable arbitration */ + write32(&arb->mtk_pmif->arb_en, 0x1 << (chan_no + swinf_no)); +} + +static void pmif_spmi_enable_cmdIssue(int mstid, bool en) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* Enable cmdIssue */ + write32(&arb->mtk_pmif->cmdissue_en, en); +} + +static void pmif_spmi_enable(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + unsigned int bytecnt_per = 0, hw_bytecnt = 0; + unsigned int cmd_per = 0; + + /* clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); + + /* set bytecnt max limitation*/ + write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0); + + /* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ + hw_bytecnt = PMIF_BYTECNT_MAX -1; + if (hw_bytecnt > 0) { + bytecnt_per = hw_bytecnt << 28 | hw_bytecnt << 24 | + hw_bytecnt << 20 | hw_bytecnt << 16 | + hw_bytecnt << 12 | hw_bytecnt << 8 | + hw_bytecnt << 4 | hw_bytecnt << 0; + } + write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, bytecnt_per); + + /* Add latency limitation */ + write32(&arb->mtk_pmif->lat_cnter_en, 0x2F7); + write32(&arb->mtk_pmif->lat_limit_0, 0); + write32(&arb->mtk_pmif->lat_limit_1, 0x4); + write32(&arb->mtk_pmif->lat_limit_2, 0x8); + write32(&arb->mtk_pmif->lat_limit_4, 0x8); + write32(&arb->mtk_pmif->lat_limit_6, 0x3FF); + write32(&arb->mtk_pmif->lat_limit_9, 0x4); + write32(&arb->mtk_pmif->lat_limit_loading, 0x2F7); + + write32(&arb->mtk_pmif->inf_en, 0x2F7); + write32(&arb->mtk_pmif->arb_en, 0x2F7); + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + write32(&arb->mtk_pmif->init_done, 1); +} + +int pmif_spmi_init(struct pmif *arb) +{ + int ret = 0; + + if (arb->is_pmif_init_done(arb) != 0) { + pmif_spmi_force_normal_mode(arb->mstid); + pmif_spmi_enable_swinf(arb->mstid, PMIF_SWINF_0_CHAN_NO, arb->swinf_no); + pmif_spmi_enable_cmdIssue(arb->mstid, true); + pmif_spmi_enable(arb->mstid); + ret = arb->is_pmif_init_done(arb); + if(ret) + return -E_NODEV; + } + + ret = spmi_mst_init(arb); + if(ret) + return -E_NODEV; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c Gerrit-Change-Number: 45398 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

7 56

Change in coreboot[master]: mb/google/hatch: Configure IRQs as level triggered for HID over I2C
by Karthik Ramasubramanian (Code Review) 05 Jan '21

05 Jan '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47417 ) Change subject: mb/google/hatch: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/google/hatch: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb M src/mainboard/google/hatch/variants/dooly/overridetree.cb M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb M src/mainboard/google/hatch/variants/kindred/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb M src/mainboard/google/hatch/variants/mushu/overridetree.cb M src/mainboard/google/hatch/variants/nightfury/overridetree.cb M src/mainboard/google/hatch/variants/stryke/overridetree.cb 10 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47417/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 2d60271..8ae350c 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -172,7 +172,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -196,7 +196,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 8ced613..6e23448 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -315,7 +315,7 @@ chip drivers/i2c/hid register "generic.hid" = ""WDHT2002"" register "generic.desc" = ""WDT Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A20_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "100" diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index c5e2aeb..6ec1a48 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -83,7 +83,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -111,7 +111,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -127,7 +127,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 76f634f..e13270f 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -94,7 +94,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index f042401..750e068 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -107,7 +107,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" @@ -135,7 +135,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" @@ -151,7 +151,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index c75b7ba..c06f35b 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -117,7 +117,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" @@ -156,7 +156,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 1b91e8f..740a7d8 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -154,7 +154,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.probed" = "1" register "generic.wake" = "GPE0_DW0_21" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index 4e4d388..29b87e4 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -114,7 +114,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index d6be1fb..ff61d80 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -205,7 +205,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN902C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb index 536cd43..3611e58 100644 --- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb +++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb @@ -172,7 +172,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" -- To view, visit https://review.coreboot.org/c/coreboot/+/47417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320198d56131cf54e0f73227479f69968719b2a7 Gerrit-Change-Number: 47417 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020