coreboot-gerrit November 2020

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Change in coreboot[master]: cpu/intel/haswell: Raise PSI1 threshold to 20A
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46919 ) Change subject: cpu/intel/haswell: Raise PSI1 threshold to 20A ...................................................................... cpu/intel/haswell: Raise PSI1 threshold to 20A Haswell reference code version 1.9.0 uses the same value as Broadwell. Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46919/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b927d7..5e9b742 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -260,7 +260,7 @@ msr.hi &= 0xc0000000; msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ if (haswell_is_ult()) msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I979ea1b4ba2962bd0c55cfb9d0c291f32cf5fcad Gerrit-Change-Number: 46919 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Enable turbo ratio if available
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46918 ) Change subject: cpu/intel/haswell: Enable turbo ratio if available ...................................................................... cpu/intel/haswell: Enable turbo ratio if available Commit 7f28e4e (broadwell: Enable turbo ratio if available) is also applicable to Haswell, since the MSR definitions are the same for both. Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46918/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 6f483a5..4b927d7 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -547,7 +547,10 @@ perf_ctl.hi = 0; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; @@ -606,9 +609,6 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ - set_max_ratio(); - /* Enable Turbo */ enable_turbo(); } @@ -664,6 +664,9 @@ static void post_mp_init(void) { + /* Set Max Ratio */ + set_max_ratio(); + /* Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ global_smi_enable(); -- To view, visit https://review.coreboot.org/c/coreboot/+/46918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5f30a5b06301449253bbfb9ed58c6b35a767763 Gerrit-Change-Number: 46918 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46917 ) Change subject: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR ...................................................................... cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR This MSR only needs to be programmed when IO MWAIT is to be enabled. The code came from Sandy Bridge, which already showed this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46917/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 21f3f4a..6f483a5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -452,12 +452,6 @@ /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); - msr.lo &= ~0xffff; - msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address - /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/46917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Gerrit-Change-Number: 46917 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/lpgcc: Drop redundant linker path
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47632 ) Change subject: libpayload/lpgcc: Drop redundant linker path ...................................................................... libpayload/lpgcc: Drop redundant linker path It either doesn't exist (in-tree builds) or is the same as $_LIBDIR. Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47632/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index cff9fe0..b90c120 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -166,7 +166,7 @@ _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" -_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static" +_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static" if [ $DOLINK -eq 0 ]; then if [ $DEBUGME -eq 1 ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/47632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9551cbfc3295d86c22a3785be7cdc0f65eeb08c4 Gerrit-Change-Number: 47632 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/lpgcc: Set proper include paths for in-tree builds
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47631 ) Change subject: libpayload/lpgcc: Set proper include paths for in-tree builds ...................................................................... libpayload/lpgcc: Set proper include paths for in-tree builds Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47631/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index fa16149..cff9fe0 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -143,14 +143,19 @@ shift done -_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_OBJ -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" +_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1" -if [ "$CONFIG_LP_PDCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses" -fi +if [ $_LIBDIR = $_OBJ ]; then + _CFLAGS="$_CFLAGS -I$_OBJ" -if [ "$CONFIG_LP_TINYCURSES" = y ]; then - _CFLAGS="$_CFLAGS -I$BASE/../curses" + if [ "$CONFIG_LP_PDCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses -I$BASE/../curses/pdcurses-backend" + _CFLAGS="$_CFLAGS -I$BASE/../curses/form -I$BASE/../curses/menu" + fi + + if [ "$CONFIG_LP_TINYCURSES" = y ]; then + _CFLAGS="$_CFLAGS -I$BASE/../curses" + fi fi # Check for the -fno-stack-protector silliness -- To view, visit https://review.coreboot.org/c/coreboot/+/47631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29ef33065033e26ba61b09d412d8ca3566d643 Gerrit-Change-Number: 47631 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/lpgcc: Add more variables to support in-tree builds
by Nico Huber (Code Review) 11 Jan '21

11 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47630 ) Change subject: libpayload/lpgcc: Add more variables to support in-tree builds ...................................................................... libpayload/lpgcc: Add more variables to support in-tree builds Add $_DOTCONFIG and $_XCOMPILE pointing to the respective files and use them. Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/bin/lpgcc 1 file changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47630/1 diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 1e63d05..fa16149 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -57,11 +57,17 @@ # This will set the _LIBDIR and _INCDIR variables used below . $BASE/lp.functions +if [ $_LIBDIR != $_OBJ ]; then + _DOTCONFIG=$BASE/../libpayload.config + _XCOMPILE=$BASE/../libpayload.xcompile +else + _DOTCONFIG=$_OBJ/libpayload.config + _XCOMPILE=$BASE/../.xcompile +fi + # include libpayload config -if [ -f $BASE/../libpayload.config ]; then - . $BASE/../libpayload.config -elif [ -f $BASE/../.config ]; then - . $BASE/../.config +if [ -f $_DOTCONFIG ]; then + . $_DOTCONFIG else echo "Can't find config" exit 1 @@ -174,8 +180,8 @@ exit 1 fi - if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config && - grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then + if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] && + grep -q fix-cortex-a53-843419 $_XCOMPILE; then _LDFLAGS="$_LDFLAGS -Wl,--fix-cortex-a53-843419" fi -- To view, visit https://review.coreboot.org/c/coreboot/+/47630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I719b42d1c8abf055948daf5b000daa30cd249edd Gerrit-Change-Number: 47630 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Do not determine CPU type at runtime
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46912 ) Change subject: cpu/intel/haswell: Do not determine CPU type at runtime ...................................................................... cpu/intel/haswell: Do not determine CPU type at runtime It is already known at compile-time. Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46912/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 0701332..deadbc5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -145,8 +145,9 @@ int cpu_config_tdp_levels(void); /* CPU identification */ -int haswell_family_model(void); -int haswell_stepping(void); -int haswell_is_ult(void); +static inline int haswell_is_ult(void) +{ + return CONFIG(INTEL_LYNXPOINT_LP); +} #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 4b73c6a..15dcff5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -186,27 +186,6 @@ [0x11] = 128, }; -int haswell_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -int haswell_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int haswell_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) - ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); - - return ult; -} - /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9 Gerrit-Change-Number: 46912 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45: Guard macro parameters
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45435 ) Change subject: nb/intel/gm45: Guard macro parameters ...................................................................... nb/intel/gm45: Guard macro parameters Add brackets around the parameters to avoid operation order problems. The `CxDRBy_BOUND_SHIFT` macro has not been updated because it changes the resulting coreboot image. The reasons have not been determined. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I023bb116fa2bdcaa7cfdce2445513da3959e827d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/gm45.h 1 file changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45435/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index af42cf9..91e6326 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -233,9 +233,9 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + (x))) #define HPLLVCO_MCHBAR 0x0c0f @@ -267,46 +267,46 @@ #define DCC_SET_EREG_SHIFT 21 #define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT)) #define DCC_SET_EREGx(x) ((DCC_SET_EREG | \ - ((x - 1) << DCC_SET_EREG_SHIFT)) & \ + (((x) - 1) << DCC_SET_EREG_SHIFT)) & \ DCC_SET_EREG_MASK) /* Per channel DRAM Row Attribute registers (32-bit) */ -#define CxDRA_MCHBAR(x) (0x1208 + (x * 0x0100)) -#define CxDRA_PAGESIZE_SHIFT(r) (r * 4) /* Per rank r */ +#define CxDRA_MCHBAR(x) (0x1208 + ((x) * 0x0100)) +#define CxDRA_PAGESIZE_SHIFT(r) ((r) * 4) /* Per rank r */ #define CxDRA_PAGESIZE_MASKr(r) (0x7 << CxDRA_PAGESIZE_SHIFT(r)) #define CxDRA_PAGESIZE_MASK 0x0000ffff #define CxDRA_PAGESIZE(r, p) /* for log2(dimm page size in bytes) p */ \ - (((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r)) -#define CxDRA_BANKS_SHIFT(r) ((r * 3) + 16) + ((((p) - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r)) +#define CxDRA_BANKS_SHIFT(r) (((r) * 3) + 16) #define CxDRA_BANKS_MASKr(r) (0x3 << CxDRA_BANKS_SHIFT(r)) #define CxDRA_BANKS_MASK 0x07ff0000 #define CxDRA_BANKS(r, b) /* for number of banks b */ \ - ((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r)) + (((b) << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r)) /* * Per channel DRAM Row Boundary registers (32-bit) * Every two ranks share one register and must be programmed at the same time. * All registers (4 ranks per channel) have to be set. */ -#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4)) +#define CxDRBy_MCHBAR(x, r) (0x1200 + ((x) * 0x0100) + (((r) / 2) * 4)) #define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16) #define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r)) #define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \ - (((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) + ((((b) >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) -#define CxDRC0_MCHBAR(x) (0x1230 + (x * 0x0100)) +#define CxDRC0_MCHBAR(x) (0x1230 + ((x) * 0x0100)) #define CxDRC0_RANKEN0 (1 << 24) /* Rank Enable */ #define CxDRC0_RANKEN1 (1 << 25) #define CxDRC0_RANKEN2 (1 << 26) #define CxDRC0_RANKEN3 (1 << 27) -#define CxDRC0_RANKEN(r) (1 << (24 + r)) +#define CxDRC0_RANKEN(r) (1 << (24 + (r))) #define CxDRC0_RANKEN_MASK (0xf << 24) #define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */ #define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT) #define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT) #define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT) -#define CxDRC1_MCHBAR(x) (0x1234 + (x * 0x0100)) +#define CxDRC1_MCHBAR(x) (0x1234 + ((x) * 0x0100)) #define CxDRC1_SSDS_SHIFT 24 #define CxDRC1_SSDS_MASK (0xff << CxDRC1_SSDS_SHIFT) #define CxDRC1_DS (0x91 << CxDRC1_SSDS_SHIFT) @@ -315,51 +315,51 @@ #define CxDRC1_NOTPOP_MASK (0xf << 16) #define CxDRC1_MUSTWR (3 << 11) -#define CxDRC2_MCHBAR(x) (0x1238 + (x * 0x0100)) -#define CxDRC2_NOTPOP(r) (1 << (24 + r)) /* Write 1 for Not Populated */ +#define CxDRC2_MCHBAR(x) (0x1238 + ((x) * 0x0100)) +#define CxDRC2_NOTPOP(r) (1 << (24 + (r))) /* Write 1 for Not Populated */ #define CxDRC2_NOTPOP_MASK (0xf << 24) #define CxDRC2_MUSTWR (1 << 12) #define CxDRC2_CLK1067MT (1 << 0) /* DRAM Timing registers (32-bit each) */ -#define CxDRT0_MCHBAR(x) (0x1210 + (x * 0x0100)) +#define CxDRT0_MCHBAR(x) (0x1210 + ((x) * 0x0100)) #define CxDRT0_BtB_WtP_SHIFT 26 #define CxDRT0_BtB_WtP_MASK (0x1f << CxDRT0_BtB_WtP_SHIFT) #define CxDRT0_BtB_WtR_SHIFT 20 #define CxDRT0_BtB_WtR_MASK (0x1f << CxDRT0_BtB_WtR_SHIFT) -#define CxDRT1_MCHBAR(x) (0x1214 + (x * 0x0100)) -#define CxDRT2_MCHBAR(x) (0x1218 + (x * 0x0100)) -#define CxDRT3_MCHBAR(x) (0x121c + (x * 0x0100)) -#define CxDRT4_MCHBAR(x) (0x1220 + (x * 0x0100)) -#define CxDRT5_MCHBAR(x) (0x1224 + (x * 0x0100)) -#define CxDRT6_MCHBAR(x) (0x1228 + (x * 0x0100)) +#define CxDRT1_MCHBAR(x) (0x1214 + ((x) * 0x0100)) +#define CxDRT2_MCHBAR(x) (0x1218 + ((x) * 0x0100)) +#define CxDRT3_MCHBAR(x) (0x121c + ((x) * 0x0100)) +#define CxDRT4_MCHBAR(x) (0x1220 + ((x) * 0x0100)) +#define CxDRT5_MCHBAR(x) (0x1224 + ((x) * 0x0100)) +#define CxDRT6_MCHBAR(x) (0x1228 + ((x) * 0x0100)) /* Clock disable registers (32-bit each) */ -#define CxDCLKDIS_MCHBAR(x) (0x120c + (x * 0x0100)) +#define CxDCLKDIS_MCHBAR(x) (0x120c + ((x) * 0x0100)) #define CxDCLKDIS_MASK 3 #define CxDCLKDIS_ENABLE 3 /* Always enable both clock pairs. */ /* On-Die-Termination registers (2x 32-bit per channel) */ -#define CxODT_HIGH(x) (0x124c + (x * 0x0100)) -#define CxODT_LOW(x) (0x1248 + (x * 0x0100)) +#define CxODT_HIGH(x) (0x124c + ((x) * 0x0100)) +#define CxODT_LOW(x) (0x1248 + ((x) * 0x0100)) /* Write Training registers. */ -#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4)) +#define CxWRTy_MCHBAR(ch, s) (0x1470 + ((ch) * 0x0100) + ((3 - (s)) * 4)) -#define CxGTEW(x) (0x1270 + (x * 0x100)) -#define CxGTC(x) (0x1274 + (x * 0x100)) -#define CxDTPEW(x) (0x1278 + (x * 0x100)) -#define CxDTAEW(x) (0x1280 + (x * 0x100)) -#define CxDTC(x) (0x1288 + (x * 0x100)) +#define CxGTEW(x) (0x1270 + ((x) * 0x100)) +#define CxGTC(x) (0x1274 + ((x) * 0x100)) +#define CxDTPEW(x) (0x1278 + ((x) * 0x100)) +#define CxDTAEW(x) (0x1280 + ((x) * 0x100)) +#define CxDTC(x) (0x1288 + ((x) * 0x100)) /* * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x))) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x))) #define DMIVC0RCTL 0x14 #define DMIVC1RCTL 0x20 @@ -375,9 +375,9 @@ * EPBAR */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x))) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x))) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x))) #define EPESD 0x44 #define EPLE1D 0x50 -- To view, visit https://review.coreboot.org/c/coreboot/+/45435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I023bb116fa2bdcaa7cfdce2445513da3959e827d Gerrit-Change-Number: 45435 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/intel/broadwell: Use `mp_cpu_bus_init`
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46886 ) Change subject: soc/intel/broadwell: Use `mp_cpu_bus_init` ...................................................................... soc/intel/broadwell: Use `mp_cpu_bus_init` Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/cpu/cpu.c M src/soc/intel/broadwell/cpu/haswell.h M src/soc/intel/broadwell/northbridge.c 3 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46886/1 diff --git a/src/soc/intel/broadwell/cpu/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c index 9348439..10db364 100644 --- a/src/soc/intel/broadwell/cpu/cpu.c +++ b/src/soc/intel/broadwell/cpu/cpu.c @@ -614,10 +614,8 @@ .post_mp_init = post_mp_init, }; -void broadwell_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { - struct bus *cpu_bus = dev->link_list; - if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } diff --git a/src/soc/intel/broadwell/cpu/haswell.h b/src/soc/intel/broadwell/cpu/haswell.h index 399fc23..26077a7 100644 --- a/src/soc/intel/broadwell/cpu/haswell.h +++ b/src/soc/intel/broadwell/cpu/haswell.h @@ -120,8 +120,6 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void broadwell_init_cpus(struct device *dev); - void set_max_freq(void); /* CPU identification */ diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 980be4d..73c6e83 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -461,7 +461,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = &broadwell_init_cpus, + .init = &mp_cpu_bus_init, }; static void broadwell_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/46886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba Gerrit-Change-Number: 46886 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/intel/haswell/haswell.h: Align with Broadwell
by Angel Pons (Code Review) 10 Jan '21

10 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46914 ) Change subject: cpu/intel/haswell/haswell.h: Align with Broadwell ...................................................................... cpu/intel/haswell/haswell.h: Align with Broadwell Sort MSR definitions, move MCHBAR registers to northbridge and relocate C-state latency macros into the header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 3 files changed, 52 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46914/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index deadbc5..284ff01 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -21,22 +21,29 @@ #define CPU_BCLK 100 #define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 - #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 - +#define MSR_FEATURE_CONFIG 0x13c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 #define MSR_POWER_CTL 0x1fc +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b @@ -53,7 +60,7 @@ #define IRTL_33554432_NS (5 << 10) #define IRTL_RESPONSE_MASK (0x3ff) -/* long duration in low dword, short duration in high dword */ +/* Long duration in low dword, short duration in high dword */ #define MSR_PKG_POWER_LIMIT 0x610 #define PKG_POWER_LIMIT_MASK 0x7fff #define PKG_POWER_LIMIT_EN (1 << 15) @@ -76,18 +83,6 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) - -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 - -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 @@ -96,33 +91,26 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) +/* Intel suggested latency times in units of 1024ns. */ +#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 +#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 +#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 +#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 +#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 +#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef + +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ + (((1 << ((base) * 5)) * (limit)) / 1000) +#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ + C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ + (IRTL_1024_NS >> 10)) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -#define MAILBOX_BIOS_CMD_READ_PCS 1 -#define MAILBOX_BIOS_CMD_WRITE_PCS 2 -#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 -#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 -#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa -#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - /* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 86a9053..44bbbfd 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,20 +20,6 @@ #include "haswell.h" #include "chip.h" -/* Intel suggested latency times in units of 1024ns. */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef - -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - /* * List of supported C-states in this processor. Only the ULT parts support C8, * C9, and C10. diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 97ae433..4bdb49a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -34,6 +34,28 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define SSKPD 0x5d10 /* 64-bit scratchpad register */ + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29 Gerrit-Change-Number: 46914 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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