coreboot-gerrit November 2020

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Change in coreboot[master]: [WIP]lib/edid_fill_fb: Support multiple framebuffers
by Patrick Rudolph (Code Review) 13 Jan '21

13 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39002 ) Change subject: [WIP]lib/edid_fill_fb: Support multiple framebuffers ...................................................................... [WIP]lib/edid_fill_fb: Support multiple framebuffers Add an implementation that supports multiple framebuffers. This will allow to compile in multiple graphic drivers and select at runtime which one to choose. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/edid.h A src/include/framebuffer_info.h M src/lib/edid_fill_fb.c M src/mainboard/google/kukui/mainboard.c 4 files changed, 174 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39002/1 diff --git a/src/include/edid.h b/src/include/edid.h index a97b99b..7c3e9c8 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -104,11 +104,12 @@ EDID_ABSENT, }; +struct edid_fb_info; /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, int row_byte_alignment); -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); +struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr); void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation); int set_display_mode(struct edid *edid, enum edid_modes mode); diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h new file mode 100644 index 0000000..6d2f9a6 --- /dev/null +++ b/src/include/framebuffer_info.h @@ -0,0 +1,45 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FRAMEBUFFER_INFO_H_ +#define __FRAMEBUFFER_INFO_H_ + +#include <stdint.h> +#include <stdbool.h> +#include <commonlib/coreboot_tables.h> + +struct edid_fb_info; +struct edid_fb_info *fb_new_framebuffer_info(void); + +bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel, uint8_t reserved_mask_pos, + uint8_t reserved_mask_size, uint8_t red_mask_pos, + uint8_t red_mask_size, uint8_t green_mask_pos, + uint8_t green_mask_size, uint8_t blue_mask_pos, + uint8_t blue_mask_size); + +bool fb_fill_framebuffer_info(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel); + +void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, + enum lb_fb_orientation orientation); + +#endif /* __FRAMEBUFFER_INFO_H_ */ diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index 1b38ead..3abcdd0 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -23,75 +23,137 @@ #include <console/console.h> #include <edid.h> #include <boot/coreboot_tables.h> +#include <framebuffer_info.h> +#include <string.h> +#include <stdlib.h> -static int fb_valid; -static struct lb_framebuffer edid_fb; +struct edid_fb_info { + bool valid; + struct lb_framebuffer edid_fb; + struct edid_fb_info *next; +}; +static struct edid_fb_info *list; + +/* + * Allocate a new framebuffer info struct on heap. + * Returns NULL on error. + */ +struct edid_fb_info *fb_new_framebuffer_info(void) +{ + struct edid_fb_info *ret; + ret = malloc(sizeof(struct edid_fb_info)); + if (ret) { + memset(ret, 0, sizeof(struct edid_fb_info)); + ret->next = list; + list = ret; + } + return ret; +} + +/* + * Fills a provided framebuffer info struct and sets the valid bit to true. + * Returns false on error. + */ +bool fb_fill_framebuffer_info_ex(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel, uint8_t reserved_mask_pos, + uint8_t reserved_mask_size, uint8_t red_mask_pos, + uint8_t red_mask_size, uint8_t green_mask_pos, + uint8_t green_mask_size, uint8_t blue_mask_pos, + uint8_t blue_mask_size) +{ + /* Validate */ + if (!info) + return false; + + if (!x_resolution || !y_resolution || !bytes_per_line || !bits_per_pixel) { + printk(BIOS_ERR, "%s: Invalid framebuffer data provided\n", __func__); + return false; + } + + printk(BIOS_INFO, "framebuffer_info: bytes_per_line: %d, bits_per_pixel: %d\n " + " x_res x y_res: %d x %d, size: %d at %p\n", + bytes_per_line, bits_per_pixel, x_resolution, + y_resolution, (bytes_per_line * y_resolution), + (void *)fb_addr); + + /* Update */ + info->edid_fb.physical_address = fb_addr; + info->edid_fb.x_resolution = x_resolution; + info->edid_fb.y_resolution = y_resolution; + info->edid_fb.bytes_per_line = bytes_per_line; + info->edid_fb.bits_per_pixel = bits_per_pixel; + info->edid_fb.reserved_mask_pos = reserved_mask_pos; + info->edid_fb.reserved_mask_size = reserved_mask_size; + info->edid_fb.red_mask_pos = red_mask_pos; + info->edid_fb.red_mask_size = red_mask_size; + info->edid_fb.green_mask_pos = green_mask_pos; + info->edid_fb.green_mask_size = green_mask_size; + info->edid_fb.blue_mask_pos = blue_mask_pos; + info->edid_fb.blue_mask_size = blue_mask_size; + info->valid = true; + + return true; +} + +/* Fills a framebuffer into struct with common values for 32/24/16bpp framebuffers */ +bool fb_fill_framebuffer_info(struct edid_fb_info *info, + uintptr_t fb_addr, uint32_t x_resolution, + uint32_t y_resolution, uint32_t bytes_per_line, + uint8_t bits_per_pixel) +{ + if (!info) + return false; + + switch (bits_per_pixel) { + case 32: + case 24: + /* packed into 4-byte words */ + return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, + bytes_per_line, bits_per_pixel, 24, 8, 16, 8, 8, 8, 0, 8); + break; + case 16: + /* packed into 2-byte words */ + return fb_fill_framebuffer_info_ex(info, fb_addr, x_resolution, y_resolution, + bytes_per_line, bits_per_pixel, 0, 0, 11, 5, 5, 6, 0, 5); + break; + default: + printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, bits_per_pixel); + return false; + } + return true; +} + +void fb_fill_framebuffer_set_orientation(struct edid_fb_info *info, + enum lb_fb_orientation orientation) +{ + if (!info) + return; + + info->edid_fb.orientation = orientation; +} /* * Take an edid, and create a framebuffer. Set fb_valid to 1. */ -void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) +struct edid_fb_info *set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr) { - edid_fb.physical_address = fb_addr; - edid_fb.x_resolution = edid->x_resolution; - edid_fb.y_resolution = edid->y_resolution; - edid_fb.bytes_per_line = edid->bytes_per_line; - /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention - * nowadays seems to be to round it up to the nearest reasonable - * boundary, because otherwise the byte-packing is hideous. - * So, for example, in RGB with no alpha, the bytes are still - * packed into 32-bit words, the so-called 32bpp-no-alpha mode. - * Or, in 5:6:5 mode, the bytes are also packed into 32-bit words, - * and in 4:4:4 mode, they are packed into 16-bit words. - * Good call on the hardware guys part. - * It's not clear we're covering all cases here, but - * I'm not sure with grahpics you ever can. - */ - edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel; - edid_fb.reserved_mask_pos = 0; - edid_fb.reserved_mask_size = 0; - switch (edid->framebuffer_bits_per_pixel) { - case 32: - case 24: - /* packed into 4-byte words */ - edid_fb.reserved_mask_pos = 24; - edid_fb.reserved_mask_size = 8; - edid_fb.red_mask_pos = 16; - edid_fb.red_mask_size = 8; - edid_fb.green_mask_pos = 8; - edid_fb.green_mask_size = 8; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - edid_fb.red_mask_pos = 11; - edid_fb.red_mask_size = 5; - edid_fb.green_mask_pos = 5; - edid_fb.green_mask_size = 6; - edid_fb.blue_mask_pos = 0; - edid_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - edid->framebuffer_bits_per_pixel); - return; - } - - fb_valid = 1; -} - -void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation) -{ - edid_fb.orientation = orientation; + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return NULL; + fb_fill_framebuffer_info(info, fb_addr, edid->x_resolution, edid->y_resolution, + edid->bytes_per_line, edid->framebuffer_bits_per_pixel); + return info; } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { - if (!fb_valid) - return -1; - - *framebuffer = edid_fb; - - return 0; + for (struct edid_fb_info *i = list; i != NULL; i = i->next) { + if (i->valid) { + *framebuffer = i->edid_fb; + return 0; + } + } + return -1; } diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d..4033d51 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -172,8 +172,10 @@ return false; } mtk_ddp_mode_set(edid); - set_vbe_mode_info_valid(edid, 0); - set_vbe_framebuffer_orientation(panel->s->orientation); + struct edid_fb_info *info = set_vbe_mode_info_valid(edid, 0); + if (info) + fb_fill_framebuffer_set_orientation(info, panel->s->orientation); + return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Gerrit-Change-Number: 39002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 86

Change in coreboot[master]: nvramcui: Make local render_form() function static
by Nico Huber (Code Review) 13 Jan '21

13 Jan '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47635 ) Change subject: nvramcui: Make local render_form() function static ...................................................................... nvramcui: Make local render_form() function static Allows us to build with `-Wmissing-prototypes`. Change-Id: I722b41e515ee472697028a912b9136ce59611051 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/nvramcui/nvramcui.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47635/1 diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index ee3de1c..db3e522 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -37,7 +37,7 @@ return y; } -void render_form(FORM *form) +static void render_form(FORM *form) { int y, x, line; WINDOW *w = form_win(form); -- To view, visit https://review.coreboot.org/c/coreboot/+/47635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722b41e515ee472697028a912b9136ce59611051 Gerrit-Change-Number: 47635 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/sandybridge: Clean up program_timings
by Angel Pons (Code Review) 12 Jan '21

12 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47770 ) Change subject: nb/intel/sandybridge: Clean up program_timings ...................................................................... nb/intel/sandybridge: Clean up program_timings Clarify the clock, command and control programming sequence. Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 68 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/47770/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 399ba5a..e273c9b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -935,71 +935,89 @@ void program_timings(ramctr_timing *ctrl, int channel) { - u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; + u32 reg_roundtrip_latency, reg_io_latency; int lane; int slotrank, slot; - int full_shift = 0; - u16 pi_coding_ctrl[NUM_SLOTS]; + u32 ctl_delay[NUM_SLOTS] = { 0 }; + int cmd_delay = 0; + + /* Enable CLK XOVER */ + u32 clk_pi_coding = get_XOVER_CLK(ctrl->rankmap[channel]); + u32 clk_logic_dly = 0; + + /* + * Apply command delay if desired setting is negative. Find the + * most negative value: 'cmd_delay' will be the absolute value. + */ FOR_ALL_POPULATED_RANKS { - if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) - full_shift = -ctrl->timings[channel][slotrank].pi_coding; + if (cmd_delay < -ctrl->timings[channel][slotrank].pi_coding) + cmd_delay = -ctrl->timings[channel][slotrank].pi_coding; + } + if (cmd_delay < 0) { + printk(BIOS_ERR, "C%d command delay underflow: %d\n", channel, cmd_delay); + cmd_delay = 0; + } + if (cmd_delay >= 128) { + printk(BIOS_ERR, "C%d command delay overflow: %d\n", channel, cmd_delay); + cmd_delay = 127; } - for (slot = 0; slot < NUM_SLOTS; slot++) - switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { - case 0: - default: - pi_coding_ctrl[slot] = 0x7f; - break; - case 1: - pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; - break; - case 2: - pi_coding_ctrl[slot] = - ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; - break; - case 3: - pi_coding_ctrl[slot] = - (ctrl->timings[channel][2 * slot].pi_coding + - ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; - break; + /* Apply control and clock delay if desired setting is positive */ + if (cmd_delay == 0) { + for (slot = 0; slot < NUM_SLOTS; slot++) { + const int pi_coding_0 = ctrl->timings[channel][2 * slot + 0].pi_coding; + const int pi_coding_1 = ctrl->timings[channel][2 * slot + 1].pi_coding; + + const u8 slot_map = (ctrl->rankmap[channel] >> (2 * slot)) & 3; + + if (slot_map & 1) + ctl_delay[slot] += pi_coding_0 + cmd_delay; + + if (slot_map & 2) + ctl_delay[slot] += pi_coding_1 + cmd_delay; + + if (slot_map == 3) + ctl_delay[slot] /= 2; + + if (ctl_delay[slot] >= 128) { + printk(BIOS_ERR, "C%dS%d control delay overflow: %d\n", + channel, slot, ctl_delay[slot]); + ctl_delay[slot] = 127; + } } + FOR_ALL_POPULATED_RANKS { + const u32 pi_delay = + ctrl->timings[channel][slotrank].pi_coding + cmd_delay; + u32 logic_delay = pi_delay / 64; + + if (logic_delay > 1) { + printk(BIOS_ERR, "C%dR%d clock delay overflow: %d\n", + channel, slotrank, pi_delay); + logic_delay = 1; + } + + clk_pi_coding |= (pi_delay % 64) << (6 * slotrank); + clk_logic_dly |= logic_delay << slotrank; + } + } /* Enable CMD XOVER */ union gdcr_cmd_pi_coding_reg cmd_pi_coding = { .raw = get_XOVER_CMD(ctrl->rankmap[channel]), }; - cmd_pi_coding.cmd_pi_code = full_shift & 0x3f; - cmd_pi_coding.cmd_logic_delay = !!(full_shift & 0x40); + cmd_pi_coding.cmd_pi_code = cmd_delay % 64; + cmd_pi_coding.cmd_logic_delay = cmd_delay / 64; - cmd_pi_coding.ctl_pi_code_d0 = pi_coding_ctrl[0] & 0x3f; - cmd_pi_coding.ctl_pi_code_d1 = pi_coding_ctrl[1] & 0x3f; - cmd_pi_coding.ctl_logic_delay_d0 = !!(pi_coding_ctrl[0] & 0x40); - cmd_pi_coding.ctl_logic_delay_d1 = !!(pi_coding_ctrl[1] & 0x40); + cmd_pi_coding.ctl_pi_code_d0 = ctl_delay[0] % 64; + cmd_pi_coding.ctl_pi_code_d1 = ctl_delay[1] % 64; + cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / 64; + cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / 64; MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; - /* Enable CLK XOVER */ - reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); - reg_logic_delay = 0; - - FOR_ALL_POPULATED_RANKS { - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; - int offset_pi_code; - if (shift < 0) - shift = 0; - - offset_pi_code = ctrl->pi_code_offset + shift; - - /* Set CLK phase shift */ - reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); - reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; - } - - MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; - MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; + MCHBAR32(GDCRCKPICODE_ch(channel)) = clk_pi_coding; + MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = clk_logic_dly; reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); reg_io_latency &= ~0xffff; @@ -1010,7 +1028,7 @@ int post_timA_min_high = 7, pre_timA_min_high = 7; int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][slotrank].pi_coding + cmd_delay; if (shift < 0) shift = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Gerrit-Change-Number: 47770 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: Documentation: Add known bugs of x86_64 code on real hardware
by Patrick Rudolph (Code Review) 12 Jan '21

12 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44733 ) Change subject: Documentation: Add known bugs of x86_64 code on real hardware ...................................................................... Documentation: Add known bugs of x86_64 code on real hardware The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled. The bugs are so strange that no root cause could be found yet. Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 11d8a4f..a5406c0 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -65,3 +65,18 @@ * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +The `x86_64` reference code runs fine in qemu and on some real x86 platforms. +However some issues have been observed and no workaround or explanation could +be found. It either works fine or not at all. Here's a list of known issues: + +* After entering long mode the FPU doesn't work any more, including accessing + MMX register. It works fine before entering long mode. +* Reading from virtual memory where the lower twelve address bits are zero + returns a fixed constant. Writing to that memory location has no effect. + Depeding on the variables stored in heap and stack and where the code + resides, undefined behaviour happens whenever the lower twelve bits are zero. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU. -- To view, visit https://review.coreboot.org/c/coreboot/+/44733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Gerrit-Change-Number: 44733 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: cpu/x86/sipi_vector: Simplify loop getting unique CPU number
by Patrick Rudolph (Code Review) 12 Jan '21

12 Jan '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47714 ) Change subject: cpu/x86/sipi_vector: Simplify loop getting unique CPU number ...................................................................... cpu/x86/sipi_vector: Simplify loop getting unique CPU number Get rid of using eax and reload counter on race condition. Change-Id: Ie4b9957d8aa1f272ff1db5caf2c69d1e1f086a03 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/sipi_vector.S 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47714/1 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 394c03a..199a12b 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -89,10 +89,9 @@ mov idt_ptr, %ebx lidt (%ebx) - /* Obtain CPU number. */ - movl ap_count, %eax 1: - movl %eax, %ecx + /* Obtain CPU number. */ + movl ap_count, %ecx inc %ecx lock cmpxchg %ecx, ap_count jnz 1b -- To view, visit https://review.coreboot.org/c/coreboot/+/47714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4b9957d8aa1f272ff1db5caf2c69d1e1f086a03 Gerrit-Change-Number: 47714 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: util/superiotool: add IT8720F EC registers
by Michael Büchler (Code Review) 12 Jan '21

12 Jan '21

Michael Büchler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44985 ) Change subject: util/superiotool: add IT8720F EC registers ...................................................................... util/superiotool: add IT8720F EC registers Register and default values are from the publicly available datasheet. Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: I69987be4f5cb50b3c20f06733f30b308891d5ad0 --- M util/superiotool/ite.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44985/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 458250a..573475b 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1244,6 +1244,35 @@ 0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,EOT}}, {EOT}}}, + {0x8720, "IT8720F", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41, + 0x42,0x43,0x44,0x45,0x50,0x51,0x52,0x53,0x54,0x55, + 0x56,0x57,0x58,0x59,0x5b,0x5c,0x5d,0x5e,0x5f,0x60, + 0x61,0x62,0x63,0x64,0x65,0x68,0x69,0x6a,0x6b,0x6c, + 0x6d,0x70,0x71,0x72,0x73,0x74,0x75,0x80,0x81,0x82, + 0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,0x90,0x91, + 0x92,0x94,0x95,0x96,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80, + 0x58,0x09,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x07, + 0x50,MISC,MISC,MISC,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,0x00,0x00,0x7f,0x7f,0x7f,0x50, + 0x00,0x00,0x90,0x00,0x12,0x60,0x00,0x00,0x00,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00, + 0x7f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA, + 0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0xff,0x00, + 0x00,0xff,0x00,0x00,EOT}}, + {EOT}}}, {0x8783, "IT8783E/F", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, -- To view, visit https://review.coreboot.org/c/coreboot/+/44985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69987be4f5cb50b3c20f06733f30b308891d5ad0 Gerrit-Change-Number: 44985 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: prog_loaders: Switch prog_locate() to new CBFS API
by Julius Werner (Code Review) 12 Jan '21

12 Jan '21

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46482 to review the following change. Change subject: prog_loaders: Switch prog_locate() to new CBFS API ...................................................................... prog_loaders: Switch prog_locate() to new CBFS API This patch changes prog_locate() to use the new cbfs_boot_lookup() instead of cbfs_boot_locate(), in preparation for the following changes. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Iad80de16a9f5faae50d444b854b50a45166fb2e2 --- M src/include/program_loading.h M src/lib/prog_loaders.c 2 files changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46482/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index fae70ce..e5a2931 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -4,8 +4,7 @@ #include <bootmem.h> #include <commonlib/region.h> -#include <stdint.h> -#include <stddef.h> +#include <types.h> enum { /* Last segment of program. Can be used to take different actions for @@ -128,7 +127,7 @@ } /* Locate the identified program to run. Return 0 on success. < 0 on error. */ -int prog_locate(struct prog *prog); +cb_err_t prog_locate(struct prog *prog); /* The prog_locate_hook() is called prior to CBFS traversal. The hook can be * used to implement policy that allows or prohibits further progress through * prog_locate(). The type and name field within struct prog are the only valid diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 93efc0a..4fae5d2 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -3,6 +3,7 @@ #include <stdlib.h> #include <cbfs.h> +#include <cbfs_private.h> #include <cbmem.h> #include <console/console.h> #include <fallback.h> @@ -22,21 +23,20 @@ const struct mem_region_device addrspace_32bit = MEM_REGION_DEV_RO_INIT(0, ~0UL); -int prog_locate(struct prog *prog) +cb_err_t prog_locate(struct prog *prog) { - struct cbfsf file; + union cbfs_mdata mdata; + cb_err_t err; if (prog_locate_hook(prog)) - return -1; + return CB_ERR; - if (cbfs_boot_locate(&file, prog_name(prog), NULL)) - return -1; + err = cbfs_boot_lookup(prog_name(prog), false, &mdata, prog_rdev(prog)); + if (err != CB_SUCCESS) + return err; - cbfsf_file_type(&file, &prog->cbfs_type); - - cbfs_file_data(prog_rdev(prog), &file); - - return 0; + prog->cbfs_type = be32toh(mdata.h.type); + return CB_SUCCESS; } void run_romstage(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/46482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad80de16a9f5faae50d444b854b50a45166fb2e2 Gerrit-Change-Number: 46482 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/sandybridge: Shorten `slotrank` to `rank`
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47751 ) Change subject: nb/intel/sandybridge: Shorten `slotrank` to `rank` ...................................................................... nb/intel/sandybridge: Shorten `slotrank` to `rank` The longer name doesn't add any useful information. Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: Ie1fa6285c10cf12a0aecb0f0345ad7a55cd7e900 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 300 insertions(+), 300 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47751/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b3a59fc..d227472 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -534,7 +534,7 @@ static void write_reset(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; /* Choose a populated channel */ channel = (ctrl->rankmap[0]) ? 0 : 1; @@ -542,9 +542,9 @@ wait_for_iosav(channel); /* Choose a populated rank */ - slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; + rank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); + iosav_write_zqcs_sequence(channel, rank, 3, 8, 0); /* * Execute command queue - why is bit 22 set here?! @@ -618,11 +618,11 @@ *addr = (*addr & ~0x1f8) | ((*addr >> 1) & 0xa8) | ((*addr & 0xa8) << 1); } -static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) +static void write_mrreg(ramctr_timing *ctrl, int channel, int rank, int reg, u32 val) { wait_for_iosav(channel); - if (ctrl->rank_mirror[channel][slotrank]) + if (ctrl->rank_mirror[channel][rank]) ddr3_mirror_mrreg(&reg, &val); const struct iosav_ssq sequence[] = { @@ -641,7 +641,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command MRS */ @@ -660,7 +660,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command MRS */ @@ -678,7 +678,7 @@ .address = val, .rowbits = 6, .bank = reg, - .rank = slotrank, + .rank = rank, }, }, }; @@ -832,22 +832,22 @@ void dram_mrscommands(ramctr_timing *ctrl) { - u8 slotrank; + u8 rank; int channel; FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_RANKS { /* MR2 */ - dram_mr2(ctrl, slotrank, channel); + dram_mr2(ctrl, rank, channel); /* MR3 */ - dram_mr3(ctrl, slotrank, channel); + dram_mr3(ctrl, rank, channel); /* MR1 */ - dram_mr1(ctrl, slotrank, channel); + dram_mr1(ctrl, rank, channel); /* MR0 */ - dram_mr0(ctrl, slotrank, channel); + dram_mr0(ctrl, rank, channel); } } @@ -912,12 +912,12 @@ wait_for_iosav(channel); - slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; + rank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* Drain */ wait_for_iosav(channel); - iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); + iosav_write_zqcs_sequence(channel, rank, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -937,13 +937,13 @@ { u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; int lane; - int slotrank, slot; + int rank, slot; int full_shift = 0; u16 pi_coding_ctrl[NUM_SLOTS]; FOR_ALL_POPULATED_RANKS { - if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) - full_shift = -ctrl->timings[channel][slotrank].pi_coding; + if (full_shift < -ctrl->timings[channel][rank].pi_coding) + full_shift = -ctrl->timings[channel][rank].pi_coding; } for (slot = 0; slot < NUM_SLOTS; slot++) @@ -986,7 +986,7 @@ reg_logic_delay = 0; FOR_ALL_POPULATED_RANKS { - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][rank].pi_coding + full_shift; int offset_pi_code; if (shift < 0) shift = 0; @@ -994,8 +994,8 @@ offset_pi_code = ctrl->pi_code_offset + shift; /* Set CLK phase shift */ - reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); - reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; + reg_pi_code |= (offset_pi_code & 0x3f) << (6 * rank); + reg_logic_delay |= ((offset_pi_code >> 6) & 1) << rank; } MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; @@ -1010,23 +1010,23 @@ int post_timA_min_high = 7, pre_timA_min_high = 7; int post_timA_max_high = 0, pre_timA_max_high = 0; int shift_402x = 0; - int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; + int shift = ctrl->timings[channel][rank].pi_coding + full_shift; if (shift < 0) shift = 0; FOR_ALL_LANES { post_timA_min_high = MIN(post_timA_min_high, - (ctrl->timings[channel][slotrank].lanes[lane]. + (ctrl->timings[channel][rank].lanes[lane]. timA + shift) >> 6); pre_timA_min_high = MIN(pre_timA_min_high, - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. timA >> 6); post_timA_max_high = MAX(post_timA_max_high, - (ctrl->timings[channel][slotrank].lanes[lane]. + (ctrl->timings[channel][rank].lanes[lane]. timA + shift) >> 6); pre_timA_max_high = MAX(pre_timA_max_high, - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. timA >> 6); } @@ -1039,38 +1039,38 @@ shift_402x = -1; reg_io_latency |= - (ctrl->timings[channel][slotrank].io_latency + shift_402x - - post_timA_min_high) << (4 * slotrank); + (ctrl->timings[channel][rank].io_latency + shift_402x - + post_timA_min_high) << (4 * rank); reg_roundtrip_latency |= - (ctrl->timings[channel][slotrank].roundtrip_latency + - shift_402x) << (8 * slotrank); + (ctrl->timings[channel][rank].roundtrip_latency + + shift_402x) << (8 * rank); FOR_ALL_LANES { - MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. + MCHBAR32(lane_base[lane] + GDCRRX(channel, rank)) = + (((ctrl->timings[channel][rank].lanes[lane]. timA + shift) & 0x3f) | - ((ctrl->timings[channel][slotrank].lanes[lane]. + ((ctrl->timings[channel][rank].lanes[lane]. rising + shift) << 8) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timA + shift - (post_timA_min_high << 6)) & 0x1c0) << 10) - | ((ctrl->timings[channel][slotrank].lanes[lane]. + | ((ctrl->timings[channel][rank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = - (((ctrl->timings[channel][slotrank].lanes[lane]. + MCHBAR32(lane_base[lane] + GDCRTX(channel, rank)) = + (((ctrl->timings[channel][rank].lanes[lane]. timC + shift) & 0x3f) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timB + shift) & 0x3f) << 8) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timB + shift) & 0x1c0) << 9) | - (((ctrl->timings[channel][slotrank].lanes[lane]. + (((ctrl->timings[channel][rank].lanes[lane]. timC + shift) & 0x40) << 13)); } } @@ -1078,11 +1078,11 @@ MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; } -static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) +static void test_timA(ramctr_timing *ctrl, int channel, int rank) { wait_for_iosav(channel); - iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); + iosav_write_read_mpr_sequence(channel, rank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); /* Execute command queue */ iosav_run_once(channel); @@ -1090,9 +1090,9 @@ wait_for_iosav(channel); } -static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) +static int does_lane_work(ramctr_timing *ctrl, int channel, int rank, int lane) { - u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; + u32 timA = ctrl->timings[channel][rank].lanes[lane].timA; return (MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; @@ -1237,7 +1237,7 @@ return MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, idx)); } -static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void find_rcven_pi_coarse(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int timA; u32 statistics[NUM_LANES][4]; @@ -1246,12 +1246,12 @@ for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { for (timA = 0; timA < 64; timA++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA = + ctrl->timings[channel][rank].lanes[lane].timA = timA + logic_delay * 64; } program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); } FOR_ALL_LANES { statistics[lane][logic_delay * 2 + 0] = get_stats(channel, lane, 0); @@ -1265,17 +1265,17 @@ FOR_ALL_LANES { printk(BIOS_ERR, "Lane %d:\t", lane); struct run rn = get_passing_region(statistics[lane], 4); - ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; + ctrl->timings[channel][rank].lanes[lane].timA = rn.middle; upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } } -static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static void fine_tune_rcven_pi(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int timA_delta; int statistics[NUM_LANES][51]; @@ -1286,16 +1286,16 @@ for (timA_delta = -25; timA_delta <= 25; timA_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA + ctrl->timings[channel][rank].lanes[lane].timA = upperA[lane] + timA_delta + 0x40; } program_timings(ctrl, channel); for (i = 0; i < 100; i++) { - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, lane); + does_lane_work(ctrl, channel, rank, lane); } } } @@ -1324,15 +1324,15 @@ printram("lane %d: %d, %d\n", lane, last_zero, first_all); - ctrl->timings[channel][slotrank].lanes[lane].timA = + ctrl->timings[channel][rank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, rank, + lane, ctrl->timings[channel][rank].lanes[lane].timA); } } -static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) +static int find_roundtrip_latency(ramctr_timing *ctrl, int channel, int rank, int *upperA) { int works[NUM_LANES]; int lane; @@ -1341,10 +1341,10 @@ int all_works = 1, some_works = 0; program_timings(ctrl, channel); - test_timA(ctrl, channel, slotrank); + test_timA(ctrl, channel, rank); FOR_ALL_LANES { - works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); + works[lane] = !does_lane_work(ctrl, channel, rank, lane); if (works[lane]) some_works = 1; @@ -1355,40 +1355,40 @@ return 0; if (!some_works) { - if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { + if (ctrl->timings[channel][rank].roundtrip_latency < 2) { printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", - channel, slotrank); + channel, rank); return MAKE_ERR; } - ctrl->timings[channel][slotrank].roundtrip_latency -= 2; + ctrl->timings[channel][rank].roundtrip_latency -= 2; printram("4024 -= 2;\n"); continue; } - ctrl->timings[channel][slotrank].io_latency += 2; + ctrl->timings[channel][rank].io_latency += 2; printram("4028 += 2;\n"); - if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { + if (ctrl->timings[channel][rank].io_latency >= 0x10) { printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", - channel, slotrank); + channel, rank); return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { - ctrl->timings[channel][slotrank].lanes[lane].timA += 128; + ctrl->timings[channel][rank].lanes[lane].timA += 128; upperA[lane] += 128; - printram("increment %d, %d, %d\n", channel, slotrank, lane); + printram("increment %d, %d, %d\n", channel, rank, lane); } } return 0; } -static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int slotrank) +static int get_logic_delay_delta(ramctr_timing *ctrl, int channel, int rank) { int lane; u16 logic_delay_min = 7; u16 logic_delay_max = 0; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][rank].lanes[lane].timA >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); logic_delay_max = MAX(logic_delay_max, logic_delay); @@ -1396,7 +1396,7 @@ if (logic_delay_max < logic_delay_min) { printk(BIOS_EMERG, "Logic delay max < min (%u < %u): %d, %d\n", - logic_delay_max, logic_delay_min, channel, slotrank); + logic_delay_max, logic_delay_min, channel, rank); } assert(logic_delay_max >= logic_delay_min); @@ -1404,12 +1404,12 @@ return logic_delay_max - logic_delay_min; } -static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int slotrank, int prev) +static int align_rt_io_latency(ramctr_timing *ctrl, int channel, int rank, int prev) { int latency_offset = 0; /* Get changed maxima */ - const int post = get_logic_delay_delta(ctrl, channel, slotrank); + const int post = get_logic_delay_delta(ctrl, channel, rank); if (prev < post) latency_offset = +1; @@ -1420,40 +1420,40 @@ else latency_offset = 0; - ctrl->timings[channel][slotrank].io_latency += latency_offset; - ctrl->timings[channel][slotrank].roundtrip_latency += latency_offset; + ctrl->timings[channel][rank].io_latency += latency_offset; + ctrl->timings[channel][rank].roundtrip_latency += latency_offset; printram("4024 += %d;\n", latency_offset); printram("4028 += %d;\n", latency_offset); return post; } -static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slotrank) +static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int rank) { u16 logic_delay_min = 7; int lane; FOR_ALL_LANES { - const u16 logic_delay = ctrl->timings[channel][slotrank].lanes[lane].timA >> 6; + const u16 logic_delay = ctrl->timings[channel][rank].lanes[lane].timA >> 6; logic_delay_min = MIN(logic_delay_min, logic_delay); } if (logic_delay_min >= 2) { printk(BIOS_WARNING, "Logic delay %u greater than 1: %d %d\n", - logic_delay_min, channel, slotrank); + logic_delay_min, channel, rank); } FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= logic_delay_min << 6; + ctrl->timings[channel][rank].lanes[lane].timA -= logic_delay_min << 6; } - ctrl->timings[channel][slotrank].io_latency -= logic_delay_min; + ctrl->timings[channel][rank].io_latency -= logic_delay_min; printram("4028 -= %d;\n", logic_delay_min); } int receive_enable_calibration(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; int err; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -1463,74 +1463,74 @@ wait_for_iosav(channel); - iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); + iosav_write_prea_sequence(channel, rank, ctrl->tRP, 0); /* Execute command queue */ iosav_run_once(channel); const union gdcr_training_mod_reg training_mod = { .receive_enable_mode = 1, - .training_rank_sel = slotrank, + .training_rank_sel = rank, .odt_always_on = 1, }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; - ctrl->timings[channel][slotrank].io_latency = 4; - ctrl->timings[channel][slotrank].roundtrip_latency = 55; + ctrl->timings[channel][rank].io_latency = 4; + ctrl->timings[channel][rank].roundtrip_latency = 55; program_timings(ctrl, channel); - find_rcven_pi_coarse(ctrl, channel, slotrank, upperA); + find_rcven_pi_coarse(ctrl, channel, rank, upperA); all_high = 1; some_high = 0; FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) + if (ctrl->timings[channel][rank].lanes[lane].timA >= 0x40) some_high = 1; else all_high = 0; } if (all_high) { - ctrl->timings[channel][slotrank].io_latency--; + ctrl->timings[channel][rank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; + ctrl->timings[channel][rank].lanes[lane].timA -= 0x40; upperA[lane] -= 0x40; } } else if (some_high) { - ctrl->timings[channel][slotrank].roundtrip_latency++; - ctrl->timings[channel][slotrank].io_latency++; + ctrl->timings[channel][rank].roundtrip_latency++; + ctrl->timings[channel][rank].io_latency++; printram("4024++;\n"); printram("4028++;\n"); } program_timings(ctrl, channel); - prev = get_logic_delay_delta(ctrl, channel, slotrank); + prev = get_logic_delay_delta(ctrl, channel, rank); - err = find_roundtrip_latency(ctrl, channel, slotrank, upperA); + err = find_roundtrip_latency(ctrl, channel, rank, upperA); if (err) return err; - prev = align_rt_io_latency(ctrl, channel, slotrank, prev); + prev = align_rt_io_latency(ctrl, channel, rank, prev); - fine_tune_rcven_pi(ctrl, channel, slotrank, upperA); + fine_tune_rcven_pi(ctrl, channel, rank, upperA); - prev = align_rt_io_latency(ctrl, channel, slotrank, prev); + prev = align_rt_io_latency(ctrl, channel, rank, prev); - compute_final_logic_delay(ctrl, channel, slotrank); + compute_final_logic_delay(ctrl, channel, rank); - align_rt_io_latency(ctrl, channel, slotrank, prev); + align_rt_io_latency(ctrl, channel, rank, prev); - printram("4/8: %d, %d, %x, %x\n", channel, slotrank, - ctrl->timings[channel][slotrank].roundtrip_latency, - ctrl->timings[channel][slotrank].io_latency); + printram("4/8: %d, %d, %x, %x\n", channel, rank, + ctrl->timings[channel][rank].roundtrip_latency, + ctrl->timings[channel][rank].io_latency); printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, - ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, rank, lane, + ctrl->timings[channel][rank].lanes[lane].timA); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1544,7 +1544,7 @@ return 0; } -static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) +static void test_tx_dq(ramctr_timing *ctrl, int channel, int rank) { int lane; @@ -1555,7 +1555,7 @@ wait_for_iosav(channel); - iosav_write_misc_write_sequence(ctrl, channel, slotrank, + iosav_write_misc_write_sequence(ctrl, channel, rank, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); /* Execute command queue */ @@ -1563,7 +1563,7 @@ wait_for_iosav(channel); - iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); + iosav_write_prea_act_read_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -1590,7 +1590,7 @@ printram("threshold=%d min=%d max=%d\n", threshold, min, max); } -static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) +static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int rank) { int start[NUM_LANES]; int tx_dq; @@ -1599,23 +1599,23 @@ wait_for_iosav(channel); - iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); + iosav_write_prea_sequence(channel, rank, ctrl->tRP, 18); /* Execute command queue */ iosav_run_once(channel); FOR_ALL_LANES { /* 32 ticks for ideal centering */ - start[lane] = (ctrl->timings[channel][slotrank].lanes[lane].timB + 32) % 128; + start[lane] = (ctrl->timings[channel][rank].lanes[lane].timB + 32) % 128; } for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { FOR_ALL_LANES - ctrl->timings[channel][slotrank].lanes[lane].timC = + ctrl->timings[channel][rank].lanes[lane].timC = (start[lane] + tx_dq) % 128; program_timings(ctrl, channel); - test_tx_dq(ctrl, channel, slotrank); + test_tx_dq(ctrl, channel, rank); FOR_ALL_LANES { stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); @@ -1637,7 +1637,7 @@ if (rn.all || rn.length < 8) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); /* * With command training not being done yet, the lane can be erroneous. * Take the average as reference and try again to find a run. @@ -1653,10 +1653,10 @@ rn.start += start[lane]; rn.middle += start[lane]; rn.end += start[lane]; - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle % 128; + ctrl->timings[channel][rank].lanes[lane].timC = rn.middle % 128; printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1715,7 +1715,7 @@ program_wdb_pattern_length(channel, 16); } -static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) +static int write_level_rank(ramctr_timing *ctrl, int channel, int rank) { int timB; int statistics[NUM_LANES][128]; @@ -1723,26 +1723,26 @@ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, - .training_rank_sel = slotrank, + .training_rank_sel = rank, .enable_dqs_wl = 5, .odt_always_on = 1, .force_drive_enable = 1, }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + u32 mr1reg = make_mr1(ctrl, rank, channel) | 1 << 7; int bank = 1; - if (ctrl->rank_mirror[channel][slotrank]) + if (ctrl->rank_mirror[channel][rank]) ddr3_mirror_mrreg(&bank, &mr1reg); wait_for_iosav(channel); - iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); + iosav_write_jedec_write_leveling_sequence(ctrl, channel, rank, bank, mr1reg); for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timB = timB; + ctrl->timings[channel][rank].lanes[lane].timB = timB; } program_timings(ctrl, channel); @@ -1773,15 +1773,15 @@ else if ((rn.start & 0x3f) == 0x3f) rn.start += 1; - ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + ctrl->timings[channel][rank].lanes[lane].timB = rn.start; if (rn.all) { printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); return MAKE_ERR; } printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, rank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1808,7 +1808,7 @@ static void train_write_flyby(ramctr_timing *ctrl) { - int channel, slotrank, lane, old; + int channel, rank, lane, old; const union gdcr_training_mod_reg training_mod = { .dq_dqs_training_res = 1, @@ -1825,7 +1825,7 @@ wait_for_iosav(channel); - iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); + iosav_write_misc_write_sequence(ctrl, channel, rank, 3, 1, 3, 3, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1849,7 +1849,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -1871,7 +1871,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -1884,15 +1884,15 @@ .cmd_executions = 1, .cmd_delay_gap = 3, .post_ssq_wait = ctrl->tRP + - ctrl->timings[channel][slotrank].roundtrip_latency + - ctrl->timings[channel][slotrank].io_latency, + ctrl->timings[channel][rank].roundtrip_latency + + ctrl->timings[channel][rank].io_latency, .data_direction = SSQ_RD, }, .sp_cmd_addr = { .address = 8, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; @@ -1907,13 +1907,13 @@ res |= ((u64) MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += + old = ctrl->timings[channel][rank].lanes[lane].timB; + ctrl->timings[channel][rank].lanes[lane].timB += get_dqs_flyby_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, - old, ctrl->timings[channel][slotrank].lanes[lane].timB); + printram("Bval+: %d, %d, %d, %x -> %x\n", channel, rank, lane, + old, ctrl->timings[channel][rank].lanes[lane].timB); } } MCHBAR32(GDCRTRAININGMOD) = 0; @@ -1925,9 +1925,9 @@ FOR_ALL_POPULATED_CHANNELS { /* choose an existing rank */ - const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + const int rank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + iosav_write_zqcs_sequence(channel, rank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1962,7 +1962,7 @@ */ static int jedec_write_leveling(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; disable_refresh_machine(ctrl); @@ -1970,8 +1970,8 @@ Disable all DQ outputs Only NOP is allowed in this mode */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + write_mrreg(ctrl, channel, rank, 1, + make_mr1(ctrl, rank, channel) | 1 << 12 | 1 << 7); /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { @@ -1986,14 +1986,14 @@ /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - const int err = write_level_rank(ctrl, channel, slotrank); + const int err = write_level_rank(ctrl, channel, rank); if (err) return err; } /* Disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, rank, 1, make_mr1(ctrl, rank, channel)); MCHBAR32(GDCRTRAININGMOD) = 0; @@ -2023,7 +2023,7 @@ int write_training(ramctr_timing *ctrl) { - int channel, slotrank; + int channel, rank; int err; FOR_ALL_POPULATED_CHANNELS @@ -2042,7 +2042,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = tx_dq_write_leveling(ctrl, channel, slotrank); + err = tx_dq_write_leveling(ctrl, channel, rank); if (err) return err; } @@ -2059,9 +2059,9 @@ return 0; } -static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) +static int test_command_training(ramctr_timing *ctrl, int channel, int rank) { - struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; + struct ram_rank_timings saved_rt = ctrl->timings[channel][rank]; int timC_delta; int lanes_ok = 0; int ctr = 0; @@ -2069,7 +2069,7 @@ for (timC_delta = -5; timC_delta <= 5; timC_delta++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timC = + ctrl->timings[channel][rank].lanes[lane].timC = saved_rt.lanes[lane].timC + timC_delta; } program_timings(ctrl, channel); @@ -2082,7 +2082,7 @@ wait_for_iosav(channel); - iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); + iosav_write_command_training_sequence(ctrl, channel, rank, ctr); /* Program LFSR for the RD/WR subsequences */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; @@ -2103,7 +2103,7 @@ break; } - ctrl->timings[channel][slotrank] = saved_rt; + ctrl->timings[channel][rank] = saved_rt; return lanes_ok != ((1 << ctrl->lanes) - 1); } @@ -2162,7 +2162,7 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) { struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; - int slotrank; + int rank; int command_pi; int stat[NUM_SLOTRANKS][CT_PI_LENGTH]; int delta = 0; @@ -2170,7 +2170,7 @@ printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); FOR_ALL_POPULATED_RANKS { - saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; + saved_timings[channel][rank] = ctrl->timings[channel][rank]; } ctrl->cmd_stretch[channel] = cmd_stretch; @@ -2192,31 +2192,31 @@ delta = 4; FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank].roundtrip_latency -= delta; + ctrl->timings[channel][rank].roundtrip_latency -= delta; } for (command_pi = CT_MIN_PI; command_pi < CT_MAX_PI; command_pi++) { FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank].pi_coding = command_pi; + ctrl->timings[channel][rank].pi_coding = command_pi; } program_timings(ctrl, channel); reprogram_320c(ctrl); FOR_ALL_POPULATED_RANKS { - stat[slotrank][command_pi - CT_MIN_PI] = - test_command_training(ctrl, channel, slotrank); + stat[rank][command_pi - CT_MIN_PI] = + test_command_training(ctrl, channel, rank); } } FOR_ALL_POPULATED_RANKS { - struct run rn = get_longest_zero_run(stat[slotrank], CT_PI_LENGTH - 1); + struct run rn = get_longest_zero_run(stat[rank], CT_PI_LENGTH - 1); - ctrl->timings[channel][slotrank].pi_coding = rn.middle + CT_MIN_PI; + ctrl->timings[channel][rank].pi_coding = rn.middle + CT_MIN_PI; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, rn.start, rn.middle, rn.end); + channel, rank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { - ctrl->timings[channel][slotrank] = - saved_timings[channel][slotrank]; + ctrl->timings[channel][rank] = + saved_timings[channel][rank]; } return MAKE_ERR; } @@ -2279,7 +2279,7 @@ return 0; } -static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int rank, int *edges) { int dqs_pi; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; @@ -2287,8 +2287,8 @@ for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; - ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; + ctrl->timings[channel][rank].lanes[lane].rising = dqs_pi; + ctrl->timings[channel][rank].lanes[lane].falling = dqs_pi; } program_timings(ctrl, channel); @@ -2300,7 +2300,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2328,17 +2328,17 @@ if (rn.all) { printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, - slotrank, lane); + rank, lane); return MAKE_ERR; } - printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); + printram("eval %d, %d, %d: %02x\n", channel, rank, lane, edges[lane]); } return 0; } static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) { - int slotrank, lane; + int rank, lane; fill_pattern0(ctrl, channel, 0, 0); FOR_ALL_LANES { @@ -2347,8 +2347,8 @@ } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; + ctrl->timings[channel][rank].lanes[lane].falling = 16; + ctrl->timings[channel][rank].lanes[lane].rising = 16; } program_timings(ctrl, channel); @@ -2357,7 +2357,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2368,8 +2368,8 @@ /* XXX: check any measured value ? */ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; + ctrl->timings[channel][rank].lanes[lane].falling = 48; + ctrl->timings[channel][rank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -2378,7 +2378,7 @@ wait_for_iosav(channel); iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); + channel, rank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2398,7 +2398,7 @@ { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; + int channel, rank, lane; int err; MCHBAR32(GDCRTRAININGMOD) = 0; @@ -2419,8 +2419,8 @@ printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_read_mpr_margin(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + err = find_read_mpr_margin(ctrl, channel, rank, + falling_edges[channel][rank]); if (err) return err; } @@ -2429,8 +2429,8 @@ printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_read_mpr_margin(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + err = find_read_mpr_margin(ctrl, channel, rank, + rising_edges[channel][rank]); if (err) return err; } @@ -2438,10 +2438,10 @@ MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].falling = + falling_edges[channel][rank][lane]; + ctrl->timings[channel][rank].lanes[lane].rising = + rising_edges[channel][rank][lane]; } FOR_ALL_POPULATED_CHANNELS { @@ -2454,7 +2454,7 @@ return 0; } -static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int rank, int *edges) { const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; @@ -2492,13 +2492,13 @@ read_pi = MAX_EDGE_TIMING / 2; FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = read_pi; - ctrl->timings[channel][slotrank].lanes[lane].falling = read_pi; + ctrl->timings[channel][rank].lanes[lane].rising = read_pi; + ctrl->timings[channel][rank].lanes[lane].falling = read_pi; } program_timings(ctrl, channel); /* Write test pattern to memory */ - iosav_write_data_write_sequence(ctrl, channel, slotrank); + iosav_write_data_write_sequence(ctrl, channel, rank); iosav_run_once(channel); @@ -2506,9 +2506,9 @@ for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. rising = read_pi; - ctrl->timings[channel][slotrank].lanes[lane]. + ctrl->timings[channel][rank].lanes[lane]. falling = read_pi; } program_timings(ctrl, channel); @@ -2536,7 +2536,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 0, @@ -2559,7 +2559,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -2582,7 +2582,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; @@ -2624,7 +2624,7 @@ if (!sweep_vref) { printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, i, + "0x%02x-0x%02x\n", channel, rank, i, rn.start, rn.middle, rn.end, rn.start + edge_offset, rn.end - edge_offset); } @@ -2638,7 +2638,7 @@ if (!sweep_vref && (rn.all || lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: " - "%d, %d, %d, %d, %d, %d\n", channel, slotrank, + "%d, %d, %d, %d, %d, %d\n", channel, rank, lane, rn.all, lower[lane], upper[lane]); return MAKE_ERR; @@ -2660,7 +2660,7 @@ { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane, err; + int channel, rank, lane, err; /* * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will @@ -2670,8 +2670,8 @@ printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_agrsv_read_margin(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + err = find_agrsv_read_margin(ctrl, channel, rank, + falling_edges[channel][rank]); if (err) return err; } @@ -2680,8 +2680,8 @@ printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = find_agrsv_read_margin(ctrl, channel, slotrank, - rising_edges[channel][slotrank]); + err = find_agrsv_read_margin(ctrl, channel, rank, + rising_edges[channel][rank]); if (err) return err; } @@ -2689,11 +2689,11 @@ MCHBAR32(IOSAV_DC_MASK) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - falling_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].falling = + falling_edges[channel][rank][lane]; - ctrl->timings[channel][slotrank].lanes[lane].rising = - rising_edges[channel][slotrank][lane]; + ctrl->timings[channel][rank].lanes[lane].rising = + rising_edges[channel][rank][lane]; } FOR_ALL_POPULATED_CHANNELS @@ -2702,11 +2702,11 @@ return 0; } -static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank) +static void test_aggressive_write(ramctr_timing *ctrl, int channel, int rank) { wait_for_iosav(channel); - iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); + iosav_write_aggressive_write_read_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -2727,7 +2727,7 @@ int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; - int channel, slotrank, lane; + int channel, rank, lane; /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ if (!IS_IVY_CPU(ctrl->cpu)) @@ -2737,8 +2737,8 @@ return 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - lower[channel][slotrank][lane] = 0; - upper[channel][slotrank][lane] = MAX_TIMC; + lower[channel][rank][lane] = 0; + upper[channel][rank][lane] = MAX_TIMC; } /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ @@ -2766,12 +2766,12 @@ for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank] + ctrl->timings[channel][rank] .lanes[lane].timC = timC; } program_timings(ctrl, channel); - test_aggressive_write(ctrl, channel, slotrank); + test_aggressive_write(ctrl, channel, rank); raw_stats[timC] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); @@ -2788,24 +2788,24 @@ printk(BIOS_EMERG, "timC write discovery failed: " "%d, %d, %d\n", channel, - slotrank, lane); + rank, lane); return MAKE_ERR; } printram("timC: %d, %d, %d: " "0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, + "0x%02x-0x%02x\n", channel, rank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], rn.end - ctrl->timC_offset[i]); - lower[channel][slotrank][lane] = + lower[channel][rank][lane] = MAX(rn.start + ctrl->timC_offset[i], - lower[channel][slotrank][lane]); + lower[channel][rank][lane]); - upper[channel][slotrank][lane] = + upper[channel][rank][lane] = MIN(rn.end - ctrl->timC_offset[i], - upper[channel][slotrank][lane]); + upper[channel][rank][lane]); } } @@ -2825,13 +2825,13 @@ printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, - (lower[channel][slotrank][lane] + - upper[channel][slotrank][lane]) / 2); + printram("timC %d, %d, %d: %x\n", channel, rank, lane, + (lower[channel][rank][lane] + + upper[channel][rank][lane]) / 2); - ctrl->timings[channel][slotrank].lanes[lane].timC = - (lower[channel][slotrank][lane] + - upper[channel][slotrank][lane]) / 2; + ctrl->timings[channel][rank].lanes[lane].timC = + (lower[channel][rank][lane] + + upper[channel][rank][lane]) / 2; } FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); @@ -2841,23 +2841,23 @@ void normalize_training(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; int mat; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int delta; mat = 0; FOR_ALL_LANES mat = - MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); + MAX(ctrl->timings[channel][rank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n", - channel, slotrank, lane, mat); + channel, rank, lane, mat); - delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; + delta = (mat >> 6) - ctrl->timings[channel][rank].io_latency; printram("normalize %d, %d, %d: delta %d\n", - channel, slotrank, lane, delta); + channel, rank, lane, delta); - ctrl->timings[channel][slotrank].roundtrip_latency += delta; - ctrl->timings[channel][slotrank].io_latency += delta; + ctrl->timings[channel][rank].roundtrip_latency += delta; + ctrl->timings[channel][rank].io_latency += delta; } FOR_ALL_POPULATED_CHANNELS { @@ -2867,9 +2867,9 @@ int channel_test(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, rank, lane; - slotrank = 0; + rank = 0; FOR_ALL_POPULATED_CHANNELS if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); @@ -2879,16 +2879,16 @@ fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); } - for (slotrank = 0; slotrank < 4; slotrank++) + for (rank = 0; rank < 4; rank++) FOR_ALL_CHANNELS - if (ctrl->rankmap[channel] & (1 << slotrank)) { + if (ctrl->rankmap[channel] & (1 << rank)) { FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; } wait_for_iosav(channel); - iosav_write_memory_test_sequence(ctrl, channel, slotrank); + iosav_write_memory_test_sequence(ctrl, channel, rank); /* Execute command queue */ iosav_run_once(channel); @@ -2897,7 +2897,7 @@ FOR_ALL_LANES if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", - channel, slotrank, lane); + channel, rank, lane); return MAKE_ERR; } } @@ -2906,7 +2906,7 @@ void channel_scrub(ramctr_timing *ctrl) { - int channel, slotrank, row, rowsize; + int channel, rank, row, rowsize; u8 bank; FOR_ALL_POPULATED_CHANNELS { @@ -2925,7 +2925,7 @@ * and firmware running in x86_32. */ FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; + rowsize = 1 << ctrl->info.dimm[channel][rank >> 1].row_bits; for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { @@ -2950,7 +2950,7 @@ .address = row, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_1 = 1, @@ -2978,7 +2978,7 @@ .address = row, .rowbits = 0, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -3004,7 +3004,7 @@ .address = 0, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -3069,15 +3069,15 @@ /* Use a larger delay when running fast to improve stability */ const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; - int channel, slotrank; + int channel, rank; FOR_ALL_POPULATED_CHANNELS { int min_pi = 10000; int max_pi = -10000; FOR_ALL_POPULATED_RANKS { - max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); - min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); + max_pi = MAX(ctrl->timings[channel][rank].pi_coding, max_pi); + min_pi = MIN(ctrl->timings[channel][rank].pi_coding, min_pi); } const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index f2d0fb5..85553e1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -249,20 +249,20 @@ void iosav_run_once(const int ch); void wait_for_iosav(int channel); -void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); -void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); +void iosav_write_zqcs_sequence(int channel, int rank, u32 gap, u32 post, u32 wrap); +void iosav_write_prea_sequence(int channel, int rank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( - int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); -void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); + int channel, int rank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int rank); void iosav_write_jedec_write_leveling_sequence( - ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); -void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + ramctr_timing *ctrl, int channel, int rank, int bank, u32 mr1reg); +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int rank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( - ramctr_timing *ctrl, int channel, int slotrank, unsigned int address); -void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank); -void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); -void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank); + ramctr_timing *ctrl, int channel, int rank, unsigned int address); +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int rank); +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int rank); +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int rank); /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ @@ -294,10 +294,10 @@ /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ struct ram_rank_timings { - /* ROUNDT_LAT register: One byte per slotrank */ + /* ROUNDT_LAT register: One byte per rank */ u8 roundtrip_latency; - /* IO_LATENCY register: One nibble per slotrank */ + /* IO_LATENCY register: One nibble per rank */ u8 io_latency; /* Phase interpolator coding for command and control */ @@ -390,7 +390,7 @@ #define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++) #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) -#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) +#define FOR_ALL_POPULATED_RANKS for (rank = 0; rank < NUM_SLOTRANKS; rank++) if (ctrl->rankmap[channel] & (1 << rank)) #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) #define MAX_EDGE_TIMING 71 #define MAX_TIMC 127 @@ -399,7 +399,7 @@ #define MAX_CAS 18 #define MIN_CAS 4 -#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) +#define MAKE_ERR ((channel << 16) | (rank << 8) | 1) #define GET_ERR_CHANNEL(x) (x >> 16) void dram_mrscommands(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index d83dfd8..b230ee6 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -49,7 +49,7 @@ } } -void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) +void iosav_write_zqcs_sequence(int channel, int rank, u32 gap, u32 post, u32 wrap) { const struct iosav_ssq sequence[] = { /* DRAM command ZQCS */ @@ -67,7 +67,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = wrap, @@ -77,7 +77,7 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) +void iosav_write_prea_sequence(int channel, int rank, u32 post, u32 wrap) { const struct iosav_ssq sequence[] = { /* DRAM command PREA */ @@ -96,7 +96,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = wrap, @@ -107,7 +107,7 @@ } void iosav_write_read_mpr_sequence( - int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) + int channel, int rank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) { const struct iosav_ssq sequence[] = { /* @@ -131,7 +131,7 @@ .address = 4, .rowbits = 6, .bank = 3, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -150,7 +150,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command RD */ @@ -169,7 +169,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* @@ -192,14 +192,14 @@ .address = 0, .rowbits = 6, .bank = 3, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command PREA */ @@ -218,7 +218,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -240,7 +240,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -263,7 +263,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -286,7 +286,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -297,13 +297,13 @@ } void iosav_write_jedec_write_leveling_sequence( - ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) + ramctr_timing *ctrl, int channel, int rank, int bank, u32 mr1reg) { /* First DQS/DQS# rising edge after write leveling mode is programmed */ const u32 tWLMRD = 40; const struct iosav_ssq sequence[] = { - /* DRAM command MRS: enable DQs on this slotrank */ + /* DRAM command MRS: enable DQs on this rank */ [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, @@ -319,7 +319,7 @@ .address = mr1reg, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command NOP */ @@ -338,7 +338,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, /* DRAM command NOP */ @@ -357,10 +357,10 @@ .address = 4, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, - /* DRAM command MRS: disable DQs on this slotrank */ + /* DRAM command MRS: disable DQs on this rank */ [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, @@ -376,14 +376,14 @@ .address = mr1reg | 1 << 12, .rowbits = 6, .bank = bank, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int rank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) { const struct iosav_ssq sequence[] = { @@ -403,7 +403,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = loops0 == 1 ? 0 : 1, @@ -426,7 +426,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 31, @@ -448,7 +448,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -471,7 +471,7 @@ .address = 8, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 31, @@ -482,7 +482,7 @@ } void iosav_write_command_training_sequence( - ramctr_timing *ctrl, int channel, int slotrank, unsigned int address) + ramctr_timing *ctrl, int channel, int rank, unsigned int address) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -501,7 +501,7 @@ .address = address, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -524,7 +524,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -549,7 +549,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -574,7 +574,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, @@ -584,7 +584,7 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -603,7 +603,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 0, @@ -626,7 +626,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -649,7 +649,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -672,14 +672,14 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -698,7 +698,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -721,7 +721,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -744,7 +744,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -767,14 +767,14 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank) +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int rank) { const struct iosav_ssq sequence[] = { /* DRAM command ACT */ @@ -793,7 +793,7 @@ .address = 0, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_bank = 1, @@ -816,7 +816,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -839,7 +839,7 @@ .address = 0, .rowbits = 0, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .inc_addr_8 = 1, @@ -862,7 +862,7 @@ .address = 1024, .rowbits = 6, .bank = 0, - .rank = slotrank, + .rank = rank, }, .addr_update = { .addr_wrap = 18, -- To view, visit https://review.coreboot.org/c/coreboot/+/47751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1fa6285c10cf12a0aecb0f0345ad7a55cd7e900 Gerrit-Change-Number: 47751 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46941 ) Change subject: cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot ...................................................................... cpu/intel/haswell: Add delay for TPM before Flex Ratio reboot Commit 542307b (broadwell: Add small delay before Flex Ratio reboot) introduced a workaround for Broadwell. Implement it on Haswell as well. Since this is only necessary when a TPM is present on a system, only do the delay (which is not that small, to be honest) on TPM-enabled builds. Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/bootblock.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/46941/1 diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index c9e3f2a..7066637 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -4,6 +4,7 @@ #include <arch/bootblock.h> #include <cpu/x86/msr.h> #include <arch/io.h> +#include <delay.h> #include <halt.h> #include "haswell.h" @@ -50,6 +51,10 @@ /* Set soft reset control to use register value */ RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Delay before reset to avoid potential TPM lockout */ + if (CONFIG(TPM1) || CONFIG(TPM2)) + mdelay(30); + /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); outb(0x6, 0xcf9); -- To view, visit https://review.coreboot.org/c/coreboot/+/46941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596 Gerrit-Change-Number: 46941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Allow tuning VR for C-state operations
by Angel Pons (Code Review) 11 Jan '21

11 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46920 ) Change subject: cpu/intel/haswell: Allow tuning VR for C-state operations ...................................................................... cpu/intel/haswell: Allow tuning VR for C-state operations Apply commit ff0f460 (broadwell: Add configuration for tuning VR for C-state operations) to Haswell, in preparation for unification. Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 50 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46920/1 diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 9db1ad3..16f1079 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -3,6 +3,35 @@ /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC +#include <stdbool.h> +#include <stdint.h> + +struct cpu_vr_config { + /* + * Minimum voltage for C6/C7 state: + * 0x67 = 1.6V (full swing) + * ... + * 0x79 = 1.7V + * ... + * 0x83 = 1.8V (no swing) + */ + uint8_t cpu_min_vid; + + /* + * Set slow VR ramp rate on C-state exit: + * 0 = Fast VR ramp rate / 2 + * 1 = Fast VR ramp rate / 4 + * 2 = Fast VR ramp rate / 8 + * 3 = Fast VR ramp rate / 16 + */ + uint8_t slow_ramp_rate_set; + + /* Enable slow VR ramp rate */ + bool slow_ramp_rate_enable; +}; + struct cpu_intel_haswell_config { int tcc_offset; /* TCC Activation Offset */ + + struct cpu_vr_config vr_config; }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5e9b742..5838f1f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -249,8 +249,17 @@ static void initialize_vr_config(void) { + struct cpu_vr_config vr_config = { 0 }; msr_t msr; + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + + if (lapic && lapic->chip_info) { + const struct cpu_intel_haswell_config *conf = lapic->chip_info; + + vr_config = conf->vr_config; + } + printk(BIOS_DEBUG, "Initializing VR config.\n"); /* Configure VR_CURRENT_CONFIG. */ @@ -280,13 +289,23 @@ msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); + /* Set the slow ramp rate */ if (haswell_is_ult()) { - /* Set the slow ramp rate to be fast ramp rate / 4 */ msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); + /* Configure the C-state exit ramp rate. */ + if (vr_config.slow_ramp_rate_enable) { + /* Configured slow ramp rate. */ + msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); + /* Set exit ramp rate to slow. */ + msr.hi &= ~(1 << (50 - 32)); + } else { + /* Fast ramp rate / 4. */ + msr.hi |= (1 << (53 - 32)); + } } /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; + msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9 Gerrit-Change-Number: 46920 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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