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Change in coreboot[master]: soc/mediatek/mt8192: Get DDR base information after calibration
by CK HU (Code Review) 19 Jan '21

19 Jan '21

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44712 to review the following change. Change subject: soc/mediatek/mt8192: Get DDR base information after calibration ...................................................................... soc/mediatek/mt8192: Get DDR base information after calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index adabb80..31e8d0e 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3835,6 +3835,36 @@ write32(regs_bak[i].addr, regs_bak[i].value); } +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx) +{ + u8 value; + + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1); + + /* Wait until MRW command fired */ + while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) == 0) + udelay(1); + + value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG); + SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0); + dramc_dbg("Read MR%d =%#x\n", mr_idx, value); + + return value; +} + +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value = 0; + u8 rank_bak; + + rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak); + return value; +} + void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, u8 chn, u8 rank, u8 mr_idx, u8 value) { diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 355cc9d..cf199dc 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -14,6 +14,55 @@ mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); } +static void get_dram_info_after_cal(struct ddr_cali *cali) +{ + u8 vendor_id, density, max_density = 0; + u32 size_Gb, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff; + dramc_info("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff; + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + size_Gb = 4; + break; + case 0x1: + size_Gb = 6; + break; + case 0x2: + size_Gb = 8; + break; + case 0x3: + size_Gb = 12; + break; + case 0x4: + size_Gb = 16; + break; + case 0x5: + size_Gb = 24; + break; + case 0x6: + size_Gb = 32; + break; + default: + size_Gb = 0; + break; + } + if (size_Gb > max_size) { + max_size = size_Gb; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density); + } + + cali->density = max_density; +} + static void dramc_calibration_all_channels(struct ddr_cali *cali) { } @@ -91,6 +140,10 @@ dramc_calibration_all_channels(&cali); + /* only need do once for get DDR's base information */ + if (first_freq_k) + get_dram_info_after_cal(&cali); + first_freq_k= false; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Gerrit-Change-Number: 44712 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: tests: Add lib/imd_cbmem-test test case
by Name of user not set (Code Review) 18 Jan '21

18 Jan '21

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46458 ) Change subject: tests: Add lib/imd_cbmem-test test case ...................................................................... tests: Add lib/imd_cbmem-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie893b5e8fc91c230ff96a14146085de16d78b1c1 --- M tests/lib/Makefile.inc A tests/lib/imd_cbmem-test.c 2 files changed, 309 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46458/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..2f381fe 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += imd_cbmem-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,11 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +imd_cbmem-test-srcs += tests/lib/imd_cbmem-test.c +# imd_cbmem-test-srcs += src/lib/imd_cbmem.c +imd_cbmem-test-srcs += tests/stubs/console.c +imd_cbmem-test-srcs += src/lib/imd.c +imd_cbmem-test-srcs += src/lib/bootmem.c +imd_cbmem-test-srcs += src/lib/memrange.c diff --git a/tests/lib/imd_cbmem-test.c b/tests/lib/imd_cbmem-test.c new file mode 100644 index 0000000..2ad0941 --- /dev/null +++ b/tests/lib/imd_cbmem-test.c @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Include UUT source code directly instead of linking it. This will allow + * access to internal structures and data without having to extract them to + * another header file + */ +#include "../lib/imd_cbmem.c" + +#include <imd.h> +#include <cbmem.h> +#include <stdlib.h> +#include <tests/test.h> +#include <stdio.h> +#include <commonlib/bsd/helpers.h> +#include <imd_private.h> + +#define LIMIT_SZ (LIMIT_ALIGN + 1) + +#define CBMEM_ENTRY_ID 0xA001 +#define CBMEM_SM_ENTRY_ID 0xB001 + +#define CBMEM_SIZE (4 * MiB) + +void reset_imd(void) +{ + imd.lg.limit = (uintptr_t) NULL; + imd.lg.r = NULL; + imd.sm.limit = (uintptr_t) NULL; + imd.sm.r = NULL; +} + +void cbmem_run_init_hooks(int is_recovery) +{ + (void) is_recovery; +} + +static void test_cbmem_top(void **state) +{ + cbmem_top_init_once(); + + if (ENV_ROMSTAGE) + assert_ptr_equal(cbmem_top_chipset(), cbmem_top()); + + if (ENV_POSTCAR || ENV_RAMSTAGE) + assert_ptr_equal((void *)_cbmem_top_ptr, cbmem_top()); +} + +static void test_cbmem_initialize_empty(void **state) +{ + const struct cbmem_entry *found; + + cbmem_initialize_empty(); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_empty_id_size(void **state) +{ + const struct cbmem_entry *found_1, *found_2; + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_initialize(void **state) +{ + int res; + const struct cbmem_entry *found; + + res = cbmem_initialize(); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize(); + assert_int_equal(0, res); + + found = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found); +} + +static void test_cbmem_initialize_id_size(void **state) +{ + int res; + const struct cbmem_entry *found_1, *found_2; + + res = cbmem_initialize_id_size(0, 0); + assert_int_equal(0, res); + + cbmem_initialize_empty(); + + res = cbmem_initialize_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + assert_int_equal(0, res); + + found_1 = cbmem_entry_find(SMALL_REGION_ID); + assert_non_null(found_1); + + found_2 = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(found_2); +} + +static void test_cbmem_recovery(void **state) +{ + int is_wakeup = 1; + assert_int_equal(0, cbmem_recovery(is_wakeup)); + + is_wakeup = 0; + assert_int_equal(0, cbmem_recovery(is_wakeup)); +} + +static void test_cbmem_entry_add(void **state) +{ + int id1 = 0x1; + int id2 = 0x2; + + assert_null(cbmem_entry_find(id1)); + assert_null(cbmem_entry_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_entry_find(id1)); + assert_non_null(cbmem_entry_find(id2)); +} + +static void test_cbmem_add(void **state) +{ + int id1 = 0x3; + int id2 = 0x4; + + assert_null(cbmem_find(id1)); + assert_null(cbmem_find(id2)); + + cbmem_initialize_empty_id_size(id1, CBMEM_ROOT_SIZE); + cbmem_add(id2, CBMEM_ROOT_SIZE); + + assert_non_null(cbmem_find(id1)); + assert_non_null(cbmem_find(id2)); +} + +static void test_cbmem_entry_find(void **state) +{ + int id1 = 0x6; + int id2 = 0x7; + const struct cbmem_entry *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_entry_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_entry_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_entry_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_find(void **state) +{ + int id1 = 0x8; + int id2 = 0x9; + void *cbm_e1, *cbm_e2, *found_1, *found_2; + + assert_null(cbmem_find(id1)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_add(id2, CBMEM_ROOT_SIZE); + + found_1 = cbmem_find(id1); + assert_non_null(found_1); + assert_ptr_equal(cbm_e1, found_1); + + found_2 = cbmem_find(id2); + assert_non_null(found_2); + assert_ptr_equal(cbm_e2, found_2); +} + +static void test_cbmem_entry_remove(void **state) +{ + int id1 = 0x10; + int id2 = 0x11; + const struct cbmem_entry *cbm_e1, *cbm_e2; + + assert_int_equal(-1, cbmem_entry_remove(NULL)); + + cbmem_initialize_empty(); + cbm_e1 = cbmem_entry_add(id1, CBMEM_ROOT_SIZE); + cbm_e2 = cbmem_entry_add(id2, CBMEM_ROOT_SIZE); + + assert_int_equal(-1, cbmem_entry_remove(cbm_e1)); + assert_int_equal(0, cbmem_entry_remove(cbm_e2)); + assert_int_equal(0, cbmem_entry_remove(cbm_e1)); +} + +static void test_cbmem_entry_size(void **state) +{ + struct imd_entry i_e = { .size = CBMEM_ROOT_SIZE }; + const struct cbmem_entry *cbm_e = imd_to_cbmem(&i_e); + + assert_int_equal(CBMEM_ROOT_SIZE, cbmem_entry_size(cbm_e)); + + i_e.size = 0; + assert_int_equal(0, cbmem_entry_size(cbm_e)); +} + +static void test_cbmem_entry_start(void **state) +{ + const struct cbmem_entry *cbm_e = NULL; + + assert_null(cbmem_entry_start(cbm_e)); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + cbm_e = cbmem_entry_find(CBMEM_ENTRY_ID); + assert_non_null(cbmem_entry_start(cbm_e)); +} + +static void test_cbmem_add_bootmem(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_add_bootmem(); + + assert_non_null(&baseptr); + assert_int_not_equal(0, &size); +} + +static void test_cbmem_get_region(void **state) +{ + void *baseptr = NULL; + size_t size = 0; + + cbmem_get_region(&baseptr, &size); + assert_null(baseptr); + assert_int_equal(0, size); + + cbmem_initialize_empty_id_size(CBMEM_ENTRY_ID, CBMEM_ROOT_SIZE); + + cbmem_get_region(&baseptr, &size); + assert_non_null(&baseptr); + assert_int_not_equal(0, size); +} + +static int teardown_test_imd_cbmem(void **state) +{ + reset_imd(); + return 0; +} + +static int setup_group_imd_cbmem(void **status) +{ + _cbmem_top_ptr = (uintptr_t)malloc(CBMEM_SIZE) + CBMEM_SIZE; + return 0; +} + +static int teardown_group_imd_cbmem(void **status) +{ + free((void *)_cbmem_top_ptr - CBMEM_SIZE); + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_cbmem_top), + cmocka_unit_test_teardown(test_cbmem_initialize_empty, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_empty_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_initialize_id_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_recovery, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_find, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_remove, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_size, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_entry_start, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_add_bootmem, teardown_test_imd_cbmem), + cmocka_unit_test_teardown(test_cbmem_get_region, teardown_test_imd_cbmem), + }; + + return cmocka_run_group_tests(tests, setup_group_imd_cbmem, teardown_group_imd_cbmem); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie893b5e8fc91c230ff96a14146085de16d78b1c1 Gerrit-Change-Number: 46458 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

6 34

Change in coreboot[master]: nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 16 Jan '21

16 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46282 ) Change subject: nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/pineview: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I633d944b6171902e1c28de634341cd6001ba6f16 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 3 files changed, 326 insertions(+), 336 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46282/1 diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..13893f2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -67,10 +67,10 @@ if (config->use_crt) { /* Enable VGA */ - MCHBAR32_OR(DACGIOCTRL1, 1 << 15); + mchbar32_or(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); + mchbar32_unset(DACGIOCTRL1, (1 << 15)); } if (config->use_lvds) { @@ -79,17 +79,17 @@ reg32 &= ~0xf1000000; reg32 |= 0x90000000; MCHBAR32(LVDSICR2) = reg32; - MCHBAR32_OR(IOCKTRR1, 1 << 9); + mchbar32_or(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32_OR(DACGIOCTRL1, 3 << 25); + mchbar32_or(DACGIOCTRL1, 3 << 25); } MCHBAR32(CICTRL) = 0xc6db8b5f; MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); - MCHBAR32_OR(DACGIOCTRL1, 1 << 5); + mchbar32_unset(DACGIOCTRL1, 0x000000ff); + mchbar32_or(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ pci_write_config8(GMCH_IGD, 0xf4, 0x4c); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index ec4152f..025070a 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -33,16 +33,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 2248d03..67f0a29 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -501,7 +501,7 @@ if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32_OR(PMSTS, 1); + mchbar32_or(PMSTS, 1); reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -566,7 +566,7 @@ MCHBAR32(HMCCPEXT) = 0; MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; - MCHBAR32_OR(HMCCMC, 1 << 7); + mchbar32_or(HMCCMC, 1 << 7); if ((fsb_freq == 0) && (ddr_freq == 1)) { MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; @@ -616,8 +616,8 @@ u8 ddr_freq; u16 mpll_ctl; - MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); - MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); + mchbar16_unset(CSHRMISCCTL1, (1 << 8)); + mchbar8_unset(CSHRMISCCTL1, 0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { ddr_freq = 0; @@ -627,10 +627,10 @@ mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); + mchbar16_unset_and_set(MPLLCTL, 0x033f, mpll_ctl); MCHBAR32(C0GNT2LNCH1) = 0x58001117; - MCHBAR32_OR(C0STATRDCTRL, 1 << 23); + mchbar32_or(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ @@ -682,7 +682,7 @@ flag = 1; } - MCHBAR8_OR(C0PVCFG, 0x03); + mchbar8_or(C0PVCFG, 0x03); MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; @@ -699,7 +699,7 @@ /* FIXME: Only applies to DDR2 */ reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; - MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); + mchbar16_unset_and_set(SHCYCTRKCKEL, 0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; MCHBAR16(C0CYCTRKWR) = reg16; @@ -714,10 +714,10 @@ MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); - MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + mchbar16_unset_and_set(C0CKECTRL, 0x03fe, 100 << 1); + mchbar8_unset_and_set(C0CYCTRKPCHG2, 0x3f, s->selected_timings.tRAS); MCHBAR16(C0ARBCTRL) = 0x2310; - MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); + mchbar8_unset_and_set(C0ADDCSCTRL, 0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -730,7 +730,7 @@ reg2 = 5000; } reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); + mchbar16_unset_and_set(C0STATRDCTRL, 0x1f00, reg16); flag = 0; if (wl > 2) { @@ -739,13 +739,13 @@ reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); + mchbar16_unset_and_set(C0WRDATACTRL, 0x01ff, reg16); MCHBAR16(C0RDQCTRL) = 0x1585; - MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + mchbar8_unset(C0PWLRCTRL, 0x1f); /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ - MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); + mchbar16_unset_and_set(C0PWLRCTRL, 0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg16 = 0x0514; @@ -754,115 +754,115 @@ reg16 = 0x0618; reg32 = 0x0c30; } - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); + mchbar32_unset_and_set(C0REFRCTRL2, 0x0fffff00, (0x3f << 22) | (reg32 << 8)); /* FIXME: Is this weird access necessary? Reference code does it */ MCHBAR8(C0REFRCTRL + 3) = 0; - MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + mchbar16_unset_and_set(C0REFCTRL, 0x3fff, reg16); /* NPUT Static Mode */ - MCHBAR8_OR(C0DYNRDCTRL, 1); + mchbar8_or(C0DYNRDCTRL, 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); + mchbar32_unset_and_set(C0STATRDCTRL, 0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32_OR(C0STATRDCTRL, 1 << 24); + mchbar32_or(C0STATRDCTRL, 1 << 24); } - MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); - MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); + mchbar8_unset(C0RDFIFOCTRL, 0x3); + mchbar16_unset_and_set(C0WRDATACTRL, 0x7c00, (wl + 10) << 10); + mchbar32_unset_and_set(C0CKECTRL, 0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); + mchbar16_unset_and_set(C0REFRCTRL + 4, 0x7fff, reg16); reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); - MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); - MCHBAR8_AND(C0JEDEC, ~(1 << 7)); - MCHBAR8_AND(C0DYNRDCTRL, ~0x6); + mchbar32_unset_and_set(C0REFRCTRL2, 0x30000000, reg32 << 8); + mchbar8_unset_and_set(C0REFRCTRL + 3, 0xfa, reg32 >> 24); + mchbar8_unset(C0JEDEC, (1 << 7)); + mchbar8_unset(C0DYNRDCTRL, 0x6); /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; MCHBAR32(C0WRWMFLSH) = reg32; - MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); - MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + mchbar16_unset_and_set(C0WRWMFLSH + 4, 0x1ff, (8 << 3) | (6 >> 2)); + mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5)); /* FIXME: Why not do a single word write? */ - MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); - MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); - MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + mchbar8_unset_and_set(SHPAGECTRL, 0xff, 0x40); + mchbar8_unset_and_set(SHPAGECTRL + 1, 0x07, 0x05); + mchbar8_or(SHCMPLWRCMD, 0x1f); reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); - MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); - MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + mchbar8_unset_and_set(SHBONUSREG, 0xdf, reg8); + mchbar8_unset(CSHRWRIOMLNS, 0x02); + mchbar8_unset_and_set(C0MISCTM, 0x07, 0x02); + mchbar16_unset_and_set(C0BYPCTRL, 0x3fc, 4 << 2); /* [31..29] = 0b010 for kN = 2 (2N) */ reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + mchbar32_unset_and_set(WRWMCONFIG, 0xffb00000, reg32); reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); - MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + mchbar8_unset_and_set(BYPACTSF, 0xf0, reg8 << 4); reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); - MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + mchbar8_unset_and_set(BYPACTSF, 0x0f, reg8); /* FIXME: Why not clear everything at once? */ - MCHBAR8_AND(BYPKNRULE, ~0xfc); - MCHBAR8_AND(BYPKNRULE, ~0x03); - MCHBAR8_AND(SHBONUSREG, ~0x03); - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); + mchbar8_unset(BYPKNRULE, 0xfc); + mchbar8_unset(BYPKNRULE, 0x03); + mchbar8_unset(SHBONUSREG, 0x03); + mchbar8_or(C0BYPCTRL, 1); + mchbar16_or(CSHRMISCCTL1, 1 << 9); for (i = 0; i < 8; i++) { /* FIXME: Hardcoded for DDR2 SO-DIMMs */ - MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); + mchbar32_unset_and_set(C0DLLRCVCTLy(i), 0x3f3f3f3f, 0x0c0c0c0c); } /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, (s->selected_timings.CAS + 1) << 16); /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); - MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); + mchbar8_unset(C0RXRCVyDLL(i), 0x3f); + mchbar16_unset(C0RCVMISCCTL2, (u16) (3 << (i * 2))); + mchbar16_unset(C0RCVMISCCTL1, (u16) (3 << (i * 2))); + mchbar16_unset(C0COARSEDLY0, (u16) (3 << (i * 2))); } - MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ - MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ - MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ - MCHBAR32_OR(C0COREBONUS, 0x000c0400); - MCHBAR32_OR(C0CMDTX1, 1 << 31); + mchbar8_unset(C0DLLPIEN, 1); /* Power up receiver */ + mchbar8_or(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + mchbar8_or(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + mchbar32_or(C0COREBONUS, 0x000c0400); + mchbar32_or(C0CMDTX1, 1 << 31); } /* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16_AND_OR(C0CKTX, ~0xc440, + mchbar32_unset_and_set(0x400*ch + 0x59c, 0x3300000, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | (pll->dbsel[f][i] << 6)); - MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); + mchbar8_unset_and_set(C0TXCK0DLL, 0x3f, pll->pi[f][i]); } /* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { /* FIXME: This is actually a dword write! */ - MCHBAR16_AND_OR(C0CKTX, ~0x00030880, + mchbar32_unset_and_set(0x400*ch + 0x5a0, 0x30880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | (pll->dbsel[f][i] << 7)); - MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); + mchbar8_unset_and_set(C0TXCK1DLL, 0x3f, pll->pi[f][i]); } /* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -872,14 +872,14 @@ /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); + mchbar8_unset_and_set(C0CMDTX1, 0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); + mchbar8_unset_and_set(C0CMDTX2, 0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCMD0DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCMD1DLL, 0x3f, reg8); } /* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -895,11 +895,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); + mchbar32_unset_and_set(C0CTLTX2, 0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL0DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL1DLL, 0x3f, reg8); /* CTRL2 and CTRL3 */ reg32 = ((u32) pll->dbsel[f][i]) << 12; @@ -908,11 +908,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); + mchbar32_unset_and_set(C0CMDTX2, 0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL2DLL, 0x3f, reg8); + mchbar8_unset_and_set(C0TXCTL3DLL, 0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -934,11 +934,11 @@ & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + mchbar16_unset_and_set(0x400*i + 0x590, 0xffff, reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXDQS0R0DLL + j, 0x3f, reg8); } static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) @@ -960,10 +960,10 @@ & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); + mchbar32_unset_and_set(C0DQSDQRyTX3(rank), (1 << (dq * 2+1)) | (1 << (dq * 2)), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); + mchbar8_unset_and_set(C0TXDQ0R0DLL + j, 0x3f, reg8); } /* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ @@ -1054,8 +1054,8 @@ } /* Disable Dynamic DQS Slave Setting Per Rank */ - MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); - MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); + mchbar8_unset(CSHRDQSCMN, (1 << 7)); + mchbar16_unset_and_set(CSHRPDCTL4, 0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); @@ -1078,13 +1078,13 @@ s->async = 0; reg8 = 0; - MCHBAR16_OR(CSHRPDCTL, 1 << 15); - MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); - MCHBAR8_OR(CSHRPDCTL, 1 << 3); - MCHBAR8_OR(CSHRPDCTL, 1 << 2); + mchbar16_or(CSHRPDCTL, 1 << 15); + mchbar8_unset(CSHRPDCTL, (1 << 7)); + mchbar8_or(CSHRPDCTL, 1 << 3); + mchbar8_or(CSHRPDCTL, 1 << 2); /* Start hardware HMC calibration */ - MCHBAR8_OR(CSHRPDCTL, 1 << 7); + mchbar8_or(CSHRPDCTL, 1 << 7); /* Busy-wait until calibration is done */ while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) @@ -1109,80 +1109,80 @@ } else { reg32 = 0x00014221; } - MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); - MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); + mchbar32_unset_and_set(CSHRMSTRCTL1, 0x0fffffff, reg32); + mchbar32_or(CSHRMSTRCTL1, 1 << 23); + mchbar32_or(CSHRMSTRCTL1, 1 << 15); + mchbar32_unset(CSHRMSTRCTL1, (1 << 15)); if (s->nodll) { /* Disable the Master DLLs by setting these bits, IN ORDER! */ - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); + mchbar16_or(CSHRMSTRCTL0, 1 << 0); + mchbar16_or(CSHRMSTRCTL0, 1 << 2); + mchbar16_or(CSHRMSTRCTL0, 1 << 4); + mchbar16_or(CSHRMSTRCTL0, 1 << 8); + mchbar16_or(CSHRMSTRCTL0, 1 << 10); + mchbar16_or(CSHRMSTRCTL0, 1 << 12); + mchbar16_or(CSHRMSTRCTL0, 1 << 14); } else { /* Enable the Master DLLs by clearing these bits, IN ORDER! */ - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 0)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 2)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 4)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 8)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 10)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 12)); + mchbar16_unset(CSHRMSTRCTL0, (1 << 14)); } /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); + mchbar8_unset_and_set(CREFPI, 0x3f, 0x07); } else { - MCHBAR8_AND(CREFPI, ~0x3f); + mchbar8_unset(CREFPI, 0x3f); } sdram_calibratepll(s, 0); // XXX check /* Enable all modular Slave DLL */ - MCHBAR16_OR(C0DLLPIEN, 1 << 11); - MCHBAR16_OR(C0DLLPIEN, 1 << 12); + mchbar16_or(C0DLLPIEN, 1 << 11); + mchbar16_or(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); + mchbar16_or(C0DLLPIEN, (1 << 10) >> i); } /* Enable DQ/DQS output */ - MCHBAR8_OR(C0SLVDLLOUTEN, 1); + mchbar8_or(C0SLVDLLOUTEN, 1); MCHBAR16(CSPDSLVWT) = 0x5005; - MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); - MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); + mchbar16_unset_and_set(CSHRPDCTL2, 0x1f1f, 0x051a); + mchbar16_unset_and_set(CSHRPDCTL5, 0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); + mchbar8_unset_and_set(CSHRPDCTL3, 0x7f, 0x6b); } else { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); + mchbar8_unset_and_set(CSHRPDCTL3, 0x7f, 0x55); sdram_calibratehwpll(s); } /* Disable Dynamic Diff Amp */ - MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); + mchbar32_unset(C0STATRDCTRL, (1 << 22)); /* Now, start initializing the transmit FIFO */ - MCHBAR8_AND(C0MISCCTL, ~0x02); + mchbar8_unset(C0MISCCTL, 0x02); /* Disable (gate) mdclk and mdclkb */ - MCHBAR8_OR(CSHWRIOBONUS, 0xc0); + mchbar8_or(CSHWRIOBONUS, 0xc0); /* Select mdmclk */ - MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + mchbar8_unset(CSHWRIOBONUS, (1 << 5)); /* Ungate mdclk */ - MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); - MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + mchbar8_unset_and_set(CSHWRIOBONUS, 0xc0, 1 << 6); + mchbar8_unset_and_set(CSHRFIFOCTL, 0x3f, 0x1a); /* Enable the write pointer count */ - MCHBAR8_OR(CSHRFIFOCTL, 1); + mchbar8_or(CSHRFIFOCTL, 1); /* Set the DDR3 Reset Enable bit */ - MCHBAR8_OR(CSHRDDR3CTL, 1); + mchbar8_or(CSHRDDR3CTL, 1); /* Configure DQS-DQ Transmit */ MCHBAR32(CSHRDQSTXPGM) = 0x00551803; @@ -1190,10 +1190,10 @@ reg8 = 0; /* Switch all clocks on anyway */ /* Enable clock groups depending on rank population */ - MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + mchbar32_unset_and_set(C0CKTX, 0x3f000000, reg8 << 24); /* Enable DDR command output buffers from core */ - MCHBAR8_AND(0x594, ~1); + mchbar8_unset(0x594, 1); reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { @@ -1208,7 +1208,7 @@ if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16_OR(C0CTLTX2, reg16); + mchbar16_or(C0CTLTX2, reg16); } /* Define a shorter name for these to make the lines fit in 96 characters */ @@ -1343,54 +1343,54 @@ FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); - MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + mchbar8_unset_and_set(C0RCOMPCTRLx(i), 1, reg8); + mchbar8_unset(C0RCOMPCTRLx(i), 2); reg16 = rcompslew; - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_unset_and_set(C0RCOMPCTRLx(i), 0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); + mchbar8_unset_and_set(C0DCOMPx(i), 0x03, rcompdelay[i]); if (i == 2) { /* FIXME: Why are we rewriting this? */ - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_unset_and_set(C0RCOMPCTRLx(i), 0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); + mchbar8_unset_and_set(C0DCOMPx(i), 0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + mchbar16_unset(C0SLEWBASEx(i), 0x7f7f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + mchbar16_unset(C0SLEWPULUTx(i), 0x3f3f); + mchbar16_unset(C0SLEWPULUTx(i) + 2, 0x3f3f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); + mchbar16_unset(C0SLEWPDLUTx(i), 0x3f3f); + mchbar16_unset(C0SLEWPDLUTx(i) + 2, 0x3f3f); } /* FIXME: Hardcoded */ - MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); - MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); + mchbar8_unset_and_set(C0ODTRECORDX, 0x3f, 0x36); + mchbar8_unset_and_set(C0DQSODTRECORDX, 0x3f, 0x36); FOR_EACH_RCOMP_GROUP(i) { - MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); - MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); - MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); - MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); - MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); - MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); + mchbar8_unset(C0RCOMPCTRLx(i), 0x60); + mchbar16_unset(C0RCOMPCTRLx(i) + 2, 0x0706); + mchbar16_unset(C0RCOMPOSVx(i), 0x7f7f); + mchbar16_unset(C0SCOMPOFFx(i), 0x3f3f); + mchbar16_unset(C0DCOMPOFFx(i), 0x1f1f); + mchbar8_unset(C0DCOMPOFFx(i) + 2, 0x1f); } - MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); + mchbar16_unset(C0ODTRECORDX, 0xffc0); + mchbar16_unset(C0ODTRECORDX + 2, 0x000f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + mchbar16_unset(C0DQSODTRECORDX, 0xffc0); + mchbar16_unset(C0DQSODTRECORDX + 2, 0x000f); FOR_EACH_RCOMP_GROUP(i) { MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; @@ -1400,24 +1400,24 @@ MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); + mchbar32_unset_and_set(DCMEASBUFOVR, 0x001f1f1f, 0x000c1219); /* FIXME: Why not do a single word write? */ - MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); - MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + mchbar16_unset_and_set(XCOMPSDR0BNS, 0x1f00, 0x1200); + mchbar8_unset_and_set(XCOMPSDR0BNS, 0x1f, 0x12); MCHBAR32(COMPCTRL3) = 0x007C9007; MCHBAR32(OFREQDELSEL) = rcomp1; MCHBAR16(XCOMPCMNBNS) = 0x1f7f; MCHBAR32(COMPCTRL2) = rcomp2; - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + mchbar16_unset_and_set(XCOMPDFCTRL, 0x0f, 1); MCHBAR16(ZQCALCTRL) = 0x0134; MCHBAR32(COMPCTRL1) = 0x4C293600; /* FIXME: wtf did these MRC guys smoke */ - MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); - MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); - MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + mchbar8_unset_and_set(COMPCTRL1 + 3, 0x44, (1 << 6) | (1 << 2)); + mchbar16_unset(XCOMPSDR0BNS, (1 << 13)); + mchbar8_unset(XCOMPSDR0BNS, (1 << 5)); FOR_EACH_RCOMP_GROUP(i) { /* FIXME: This should be an _AND_OR */ @@ -1426,7 +1426,7 @@ if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { /* Start COMP */ - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); /* Wait until COMP is done */ while ((MCHBAR8(COMPCTRL1) & 1) != 0) @@ -1442,55 +1442,55 @@ /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + mchbar16_unset_and_set(C0SLEWBASEx(i), 0x7f00, reg16); reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); + mchbar8_unset_and_set(C0SLEWBASEx(i), 0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); + mchbar8_unset_and_set(C0SLEWPULUTx(0) + i, 0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); + mchbar8_unset_and_set(C0SLEWPULUTx(2) + i, 0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); - MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); + mchbar8_unset_and_set(C0SLEWPULUTx(3) + i, 0x3f, rcomplut[j][6]); + mchbar8_unset_and_set(C0SLEWPULUTx(4) + i, 0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); - MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); + mchbar8_unset_and_set(C0SLEWPULUTx(5) + i, 0x3f, rcomplut[j][8]); + mchbar8_unset_and_set(C0SLEWPULUTx(6) + i, 0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); + mchbar8_unset_and_set(C0SLEWPDLUTx(0) + i, 0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); + mchbar8_unset_and_set(C0SLEWPDLUTx(2) + i, 0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); + mchbar8_unset_and_set(C0SLEWPDLUTx(3) + i, 0x3f, rcomplut[j][7]); + mchbar8_unset_and_set(C0SLEWPDLUTx(4) + i, 0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); + mchbar8_unset_and_set(C0SLEWPDLUTx(5) + i, 0x3f, rcomplut[j][9]); + mchbar8_unset_and_set(C0SLEWPDLUTx(6) + i, 0x3f, rcomplut[j][9]); } } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); } /* FIXME: The ODT tables are for DDR2 only! */ @@ -1565,24 +1565,24 @@ if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x100001); MCHBAR32(C0DRA01) = 0x00000001; MCHBAR32(C0DRB0) = 0x00020002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_unset_and_set(C0CKECTRL, 1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + mchbar32_unset_and_set(C0CKECTRL, 1, w260[s->dimm_config[0]]); MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; @@ -1651,10 +1651,10 @@ u32 reg32a, reg32b; ok = 0; - MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); - MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); + mchbar8_unset(XCOMPDFCTRL, (1 << 3)); + mchbar8_unset(COMPCTRL1, (1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1667,7 +1667,7 @@ reg32a |= (1 << 31) | (1 << 15); MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1680,7 +1680,7 @@ reg32 = jval << 3; reg32 |= rank * (1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); + mchbar8_unset_and_set(C0JEDEC, 0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1689,10 +1689,10 @@ static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); - MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); + mchbar32_or(C0CKECTRL, 1 << 27); + mchbar8_unset_and_set(C0JEDEC, 0x0e, NORMAL_OP_CMD); + mchbar8_unset(C0JEDEC, 0x30); + mchbar32_unset_and_set(C0REFRCTRL2, (3 << 30), 3 << 30); } } @@ -1758,12 +1758,12 @@ reg32 = 0; reg32 |= (4 << 13); reg32 |= (6 << 8); - MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); - MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar32_unset_and_set(C0DYNRDCTRL, 0x3ff00, reg32); + mchbar8_unset(C0DYNRDCTRL, (1 << 7)); + mchbar8_or(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); + mchbar8_unset_and_set(C0JEDEC, 0x0e, NORMAL_OP_CMD); + mchbar8_unset(C0JEDEC, 0x30); } else { sdram_zqcl(s); } @@ -1860,10 +1860,10 @@ reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + mchbar8_unset_and_set(C0CKECTRL + 2, 0xf0, reg8); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_OR(C0CKECTRL, 1); + mchbar8_or(C0CKECTRL, 1); } addr = C0DRB0; @@ -1884,9 +1884,9 @@ { u8 dqsmatches = 1; while (count--) { - MCHBAR8_AND(C0RSTCTL, ~2); + mchbar8_unset(C0RSTCTL, 2); hpet_udelay(1); - MCHBAR8_OR(C0RSTCTL, 2); + mchbar8_or(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1905,12 +1905,12 @@ { if (*medium < 3) { (*medium)++; - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, *coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, *medium << (lane * 2)); } } @@ -1929,8 +1929,8 @@ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8_AND(C0RSTCTL, ~0x0c); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); + mchbar8_unset(C0RSTCTL, 0x0c); + mchbar8_unset(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 0\n"); for (lane = 0; lane < maxlane; lane++) { @@ -1942,10 +1942,10 @@ pi = 0; medium = 0; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, medium << (lane * 2)); - MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + mchbar8_unset(C0RXRCVyDLL(lane), 0x3f); savecoarse = coarse; savemedium = medium; @@ -1954,7 +1954,7 @@ PRINTK_DEBUG("rcven 0.1\n"); // XXX comment out - // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); + // mchbar16_unset_and_set(C0RCVMISCCTL1, 3 << lane * 2, 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); @@ -1985,8 +1985,8 @@ PRINTK_DEBUG("rcven 0.3\n"); coarse = savecoarse; medium = savemedium; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); + mchbar16_unset_and_set(C0RCVMISCCTL2, 3 << lane * 2, medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; @@ -1997,12 +1997,12 @@ break; // } } - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_unset_and_set(C0RXRCVyDLL(lane), 0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_unset_and_set(C0RXRCVyDLL(lane), 0x3f, pi << s->pioffset); rcvenclock(&coarse, &medium, lane); if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { @@ -2012,7 +2012,7 @@ PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { coarse--; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, coarse << 16); if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; @@ -2039,10 +2039,10 @@ do { lane--; offset = lanecoarse[lane] - minlanecoarse; - MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + mchbar16_unset_and_set(C0COARSEDLY0, 3 << lane * 2, offset << (lane * 2)); } while (lane != 0); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); + mchbar32_unset_and_set(C0STATRDCTRL, 0x000f0000, minlanecoarse << 16); s->coarsectrl = minlanecoarse; s->coarsedelay = MCHBAR16(C0COARSEDLY0); @@ -2050,14 +2050,14 @@ s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8_AND(C0RSTCTL, ~0x0e); - MCHBAR8_OR(C0RSTCTL, 0x02); - MCHBAR8_OR(C0RSTCTL, 0x04); - MCHBAR8_OR(C0RSTCTL, 0x08); + mchbar8_unset(C0RSTCTL, 0x0e); + mchbar8_or(C0RSTCTL, 0x02); + mchbar8_or(C0RSTCTL, 0x04); + mchbar8_or(C0RSTCTL, 0x08); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); - MCHBAR8_OR(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar8_unset(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } @@ -2137,20 +2137,20 @@ { u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8_OR(C0ADDCSCTRL, 1); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar8_or(C0ADDCSCTRL, 1); + mchbar8_or(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + mchbar32_unset_and_set(WRWMCONFIG, mask32, reg32); MCHBAR8(C0DITCTRL + 1) = 2; MCHBAR16(C0DITCTRL + 2) = 0x0804; MCHBAR16(C0DITCTRL + 4) = 0x2010; MCHBAR8(C0DITCTRL + 6) = 0x40; MCHBAR16(C0DITCTRL + 8) = 0x091c; MCHBAR8(C0DITCTRL + 10) = 0xf2; - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR8_OR(C0CWBCTRL, 1); - MCHBAR16_OR(C0ARBSPL, 0x0100); + mchbar8_or(C0BYPCTRL, 1); + mchbar8_or(C0CWBCTRL, 1); + mchbar16_or(C0ARBSPL, 0x0100); pci_or_config8(HOST_BRIDGE, 0xf0, 1); MCHBAR32(SBCTL) = 0x00000002; @@ -2208,14 +2208,14 @@ die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); - MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); + mchbar8_unset_and_set(CHDECMISC, 0xfc, reg8 & 0xfc); + mchbar32_unset(NOACFGBUSCTL, 0x80000000); MCHBAR32(HTBONUS0) = 0x0000000f; - MCHBAR8_OR(C0COREBONUS + 4, 1); + mchbar8_or(C0COREBONUS + 4, 1); - MCHBAR32_AND(HIT3, ~0x0e000000); - MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); + mchbar32_unset(HIT3, 0x0e000000); + mchbar32_unset_and_set(HIT4, 0x000c0000, 0x00040000); u32 clkcx[2][2][3] = { { @@ -2235,20 +2235,20 @@ MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; - MCHBAR8_AND(HIT4, ~0x02); + mchbar8_unset(HIT4, 0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8_AND(COMPCTRL1, ~0x02); + mchbar8_unset(COMPCTRL1, 0x02); while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16_AND(CSHRMISCCTL, ~0x3000); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); + mchbar16_unset(CSHRMISCCTL, 0x3000); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar16_unset_and_set(XCOMPDFCTRL, 0x0f, 0x09); - MCHBAR8_OR(COMPCTRL1, 0x82); + mchbar8_or(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2336,7 +2336,7 @@ } } - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); + mchbar16_unset_and_set(C0STATRDCTRL, 0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2346,26 +2346,26 @@ /* Thermal sensor */ MCHBAR8(TSC1) = 0x9b; - MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + mchbar32_unset_and_set(TSTTP, 0x00ffffff, 0x1d00); MCHBAR8(THERM1) = 0x08; MCHBAR8(TSC3) = 0x00; - MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); - MCHBAR8_AND_OR(THERM1, ~1, 1); - MCHBAR8_AND_OR(TCO, ~0x80, 0x80); + mchbar8_unset_and_set(TSC2, 0x0f, 0x04); + mchbar8_unset_and_set(THERM1, 1, 1); + mchbar8_unset_and_set(TCO, 0x80, 0x80); /* Clock gating */ - MCHBAR32_AND(PMMISC, ~0x00040001); - MCHBAR8_AND(SBCTL3 + 3, ~0x80); - MCHBAR8_AND(CISDCTRL + 3, ~0x80); - MCHBAR16_AND(CICGDIS, ~0x1fff); - MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); - MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); - MCHBAR8_AND(TSMISC, ~1); + mchbar32_unset(PMMISC, 0x00040001); + mchbar8_unset(SBCTL3 + 3, 0x80); + mchbar8_unset(CISDCTRL + 3, 0x80); + mchbar16_unset(CICGDIS, 0x1fff); + mchbar32_unset(SBCLKGATECTRL, 0x0001ffff); + mchbar16_unset(HICLKGTCTL, 0x03ff mchbar16_unset(HICLKGTCTL, 0x03ff mchbar16_unset(HICLKGTCTL, 0x03ff & 0x06); 0x06); 0x06); + mchbar32_unset_and_set(HTCLKGTCTL, 0xffffffff, 0x20); + mchbar8_unset(TSMISC, 1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + mchbar16_unset_and_set(CLOCKGATINGI, 0x07fc, 0x0040); + mchbar16_unset_and_set(CLOCKGATINGII, 0x0fff, 0x0d00); + mchbar16_unset(CLOCKGATINGIII, 0x0d80); MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ @@ -2378,15 +2378,15 @@ MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + mchbar16_unset_and_set(PMMSPMRES, 0x03ff, 0x00c8); else - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + mchbar16_unset_and_set(PMMSPMRES, 0x03ff, 0x0100); j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); - MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); - MCHBAR8_AND(PMBAK, ~0x02); + mchbar32_unset_and_set(PMCLKRC, 0x01fff37f, 0x10810700); + mchbar8_unset_and_set(PMPXPRC, 0x07, 1); + mchbar8_unset(PMBAK, 0x02); static const u16 ddr2lut[2][4][2] = { { @@ -2406,8 +2406,8 @@ MCHBAR16(C0C2REG) = 0x7a89; MCHBAR8(SHC2REGII) = 0xaa; MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + mchbar16_unset_and_set(SHC2REGI, 0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + mchbar16_unset_and_set(CLOCKGATINGIII, 0xf000, 0xf000); MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); reg32 = s->nodll ? 0x30000000 : 0; @@ -2415,72 +2415,72 @@ /* FIXME: Compacting this results in changes to the binary */ MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); - MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); - MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + mchbar32_unset_and_set(CLOCKGATINGI, 0x00f00000, 0x00f00000); + mchbar32_unset_and_set(CLOCKGATINGII - 1, 0x001ff000, 0xbf << 20); + mchbar16_unset_and_set(SHC3C4REG2, 0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); MCHBAR16(SHC3C4REG3) = 0x3264; - MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + mchbar16_unset_and_set(SHC3C4REG4, 0x3f3f, (0x14 << 8) | 0x0a); - MCHBAR32_OR(C1COREBONUS, 0x80002000); + mchbar32_or(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + mchbar16_unset_and_set(CLOCKGATINGII, 0x03ff, 0x0100); + mchbar16_unset_and_set(CLOCKGATINGIII, 0x003f, 0x0010); + mchbar16_unset_and_set(CLOCKGATINGI, 0x7000, 0x2000); - MCHBAR8_AND(CSHRPDCTL, ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); - MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + mchbar8_unset(CSHRPDCTL, 0x0e); + mchbar8_unset(CSHRWRIOMLNS, 0x0c); + mchbar8_unset(C0MISCCTLy(0), 0x0e); + mchbar8_unset(C0MISCCTLy(1), 0x0e); + mchbar8_unset(C0MISCCTLy(2), 0x0e); + mchbar8_unset(C0MISCCTLy(3), 0x0e); + mchbar8_unset(C0MISCCTLy(4), 0x0e); + mchbar8_unset(C0MISCCTLy(5), 0x0e); + mchbar8_unset(C0MISCCTLy(6), 0x0e); + mchbar8_unset(C0MISCCTLy(7), 0x0e); + mchbar8_unset(CSHRWRIOMLNS, 0x02); - MCHBAR16_AND(CSHRMISCCTL, ~0x0400); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); - MCHBAR8_AND(C0WRDPYN, ~0x80); - MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); - MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); - MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + mchbar16_unset(CSHRMISCCTL, 0x0400); + mchbar16_unset(CLOCKGATINGIII, 0x0dc0); + mchbar8_unset(C0WRDPYN, 0x80); + mchbar32_unset(C0COREBONUS, (1 << 22)); + mchbar16_unset(CLOCKGATINGI, 0x80fc); + mchbar16_unset(CLOCKGATINGII, 0x0c00); - MCHBAR8_AND(CSHRPDCTL, ~0x0d); - MCHBAR8_AND(C0MISCCTLy(0), ~1); - MCHBAR8_AND(C0MISCCTLy(1), ~1); - MCHBAR8_AND(C0MISCCTLy(2), ~1); - MCHBAR8_AND(C0MISCCTLy(3), ~1); - MCHBAR8_AND(C0MISCCTLy(4), ~1); - MCHBAR8_AND(C0MISCCTLy(5), ~1); - MCHBAR8_AND(C0MISCCTLy(6), ~1); - MCHBAR8_AND(C0MISCCTLy(7), ~1); + mchbar8_unset(CSHRPDCTL, 0x0d); + mchbar8_unset(C0MISCCTLy(0), 1); + mchbar8_unset(C0MISCCTLy(1), 1); + mchbar8_unset(C0MISCCTLy(2), 1); + mchbar8_unset(C0MISCCTLy(3), 1); + mchbar8_unset(C0MISCCTLy(4), 1); + mchbar8_unset(C0MISCCTLy(5), 1); + mchbar8_unset(C0MISCCTLy(6), 1); + mchbar8_unset(C0MISCCTLy(7), 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); - MCHBAR32_AND(C0COREBONUS, ~0x00100000); - MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); - MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); - MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); - MCHBAR16_OR(C0STATRDCTRL, 0x6000); - MCHBAR32_OR(C0CKECTRL, 0x00010000); - MCHBAR8_OR(C0COREBONUS, 0x10); - MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); - MCHBAR8_OR(CSHWRIOBONUS, 0x07); - MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); - MCHBAR8_OR(SHC2REGIII, 7); - MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); - MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); - MCHBAR16_OR(C0COREBONUS, 0x01e0); - MCHBAR8_OR(CSHWRIOBONUS, 0x18); - MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); - MCHBAR16_OR(SHC3C4REG1, 0x0a3f); - MCHBAR8_OR(C0STATRDCTRL, 3); - MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); - MCHBAR8_AND(C0COREBONUS + 4, ~0x60); - MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); + mchbar32_unset_and_set(C0STATRDCTRL, 0x00700000, 3 << 20); + mchbar32_unset(C0COREBONUS, 0x00100000); + mchbar8_or(C0DYNSLVDLLEN, 0x1e); + mchbar8_or(C0DYNSLVDLLEN2, 0x03); + mchbar32_unset_and_set(SHCYCTRKCKEL, 0x0c000000, 0x04000000); + mchbar16_or(C0STATRDCTRL, 0x6000); + mchbar32_or(C0CKECTRL, 0x00010000); + mchbar8_or(C0COREBONUS, 0x10); + mchbar32_or(CLOCKGATINGI - 1, 0xf << 24); + mchbar8_or(CSHWRIOBONUS, 0x07); + mchbar8_or(C0DYNSLVDLLEN, 0xc0); + mchbar8_or(SHC2REGIII, 7); + mchbar16_unset_and_set(SHC2MINTM, 0xffff, 0x0080); + mchbar8_unset_and_set(SHC2IDLETM, 0xff, 0x10); + mchbar16_or(C0COREBONUS, 0x01e0); + mchbar8_or(CSHWRIOBONUS, 0x18); + mchbar8_or(CSHRMSTDYNDLLENB, 0x0d); + mchbar16_or(SHC3C4REG1, 0x0a3f); + mchbar8_or(C0STATRDCTRL, 3); + mchbar8_unset_and_set(C0REFRCTRL2, 0xff, 0x4a); + mchbar8_unset(C0COREBONUS + 4, 0x60); + mchbar16_or(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2540,13 +2540,13 @@ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); + mchbar32_unset(C0COREBONUS, (1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32_OR(C0COREBONUS, 1 << 23); + mchbar32_or(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } @@ -2555,10 +2555,10 @@ MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8_OR(CLOCKGATINGI, 3); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); - MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); - MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); + mchbar8_or(CLOCKGATINGI, 3); + mchbar16_unset_and_set(CLOCKGATINGIII, 0xf000, pimdclk << 12); + mchbar8_unset_and_set(CSHWRIOBONUSX, 0x77, (push << 4) | push); + mchbar32_unset_and_set(C0COREBONUS, 0x0f000000, 0x03000000); } /** @@ -2591,7 +2591,7 @@ /* Enable HPET */ enable_hpet(); - MCHBAR16_OR(CPCTL, 1 << 15); + mchbar16_or(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2626,16 +2626,16 @@ PRINTK_DEBUG("Done mmap\n"); /* Enable DDR IO buffer */ - MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); - MCHBAR8_OR(C0RSTCTL, 1); + mchbar8_unset_and_set(C0IOBUFACTCTL, 0x3f, 0x08); + mchbar8_or(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8_OR(HIT4, 2); + mchbar8_or(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); + mchbar32_or(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2648,7 +2648,7 @@ PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0REFRCTRL2, 3 << 30); + mchbar32_or(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2679,7 +2679,7 @@ PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32_OR(C0REFRCTRL2, 1 << 30); + mchbar32_or(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633d944b6171902e1c28de634341cd6001ba6f16 Gerrit-Change-Number: 46282 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/intel/cannonlake: Add i915_gpu_controller_info
by Jeremy Soller (Code Review) 16 Jan '21

16 Jan '21

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43616 ) Change subject: soc/intel/cannonlake: Add i915_gpu_controller_info ...................................................................... soc/intel/cannonlake: Add i915_gpu_controller_info This adds the i915_gpu_controller_info struct to chip.h and implements intel_igd_get_controller_info. Due to conflicts with the GMA driver ACPI, gfx.asl had to be commented out. I believe gfx.asl should be removed, but would like to hear alternatives. Tested on system76/lemp9 - ACPI backlight control was verified. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/graphics.c 4 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43616/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 96f1f97..e6d330a 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += fsp_params.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 12269d3..9cdd3b5 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -17,7 +17,7 @@ #endif /* GFX 00:02.0 */ -#include "gfx.asl" +//TODO: fix inclusion when using gma ACPI #include "gfx.asl" /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2923efc..3457f4d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -5,6 +5,7 @@ #include <intelblocks/cfg.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -478,6 +479,9 @@ * Only override CPU flex ratio if don't want to boot with non-turbo max. */ uint8_t cpu_ratio_override; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c new file mode 100644 index 0000000..fda4998 --- /dev/null +++ b/src/soc/intel/cannonlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *device) +{ + struct soc_intel_cannonlake_config *chip = device->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027b5fc37527fbfcf985262c8a1a048e0363410e Gerrit-Change-Number: 43616 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz
by Kevin Chiu (Code Review) 15 Jan '21

15 Jan '21

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47857 to review the following change. Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz ...................................................................... mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz Enhance USB 2.0 M/B C0, DB C1 A1 port: HS DC Voltage Level(TXVREFTUNE0): 0x6 COMPDISTUNE(COMPDISTUNE0): 0x5 BUG=b:165209698 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47857/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index efd1dfc..7b63079 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -21,6 +21,45 @@ register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration + # USB 2.0 strength + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # USB 2.0 strength + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/47857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2 Gerrit-Change-Number: 47857 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/xeon_sp/acpi: Remove southcluster.asl
by Marc Jones (Code Review) 15 Jan '21

15 Jan '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45835 ) Change subject: soc/intel/xeon_sp/acpi: Remove southcluster.asl ...................................................................... soc/intel/xeon_sp/acpi: Remove southcluster.asl Remove the non-built southcluster.asl file. The asl is duplicated in iiostack.asl and uncore_irq.asl. Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- D src/soc/intel/xeon_sp/acpi/southcluster.asl 1 file changed, 0 insertions(+), 235 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45835/1 diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl deleted file mode 100644 index effed43..0000000 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ /dev/null @@ -1,235 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/iomap.h> - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -Name (MCRS, ResourceTemplate() { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfeafffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, - 0x6EB00000,,, PMEM) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, - 0x00100000,,, APIC) - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, - 0x00100000,,, PCHR) - - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000380000000000, // Range Minimum - 0x0000383FFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000004000000000, // Length - ,,, AddressRangeMemory, TypeStatic) -}) - -Method (_CRS, 0, Serialized) { - Return (MCRS) -} - -Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} - - -Name (AR00, Package() { - // [DMI0]: Legacy PCI Express Port 0 on PCI0 - Package() { 0x0000FFFF, 0, 0, 47 }, - // [BR1A]: PCI Express Port 1A on PCI0 - // [BR1B]: PCI Express Port 1B on PCI0 - Package() { 0x0001FFFF, 0, 0, 47 }, - // [BR2A]: PCI Express Port 2A on PCI0 - // [BR2B]: PCI Express Port 2B on PCI0 - // [BR2C]: PCI Express Port 2C on PCI0 - // [BR2D]: PCI Express Port 2D on PCI0 - Package() { 0x0002FFFF, 0, 0, 47 }, - // [BR3A]: PCI Express Port 3A on PCI0 - // [BR3B]: PCI Express Port 3B on PCI0 - // [BR3C]: PCI Express Port 3C on PCI0 - // [BR3D]: PCI Express Port 3D on PCI0 - Package() { 0x0003FFFF, 0, 0, 47 }, - // [CB0A]: CB3DMA on PCI0 - // [CB0E]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 0, 0, 31 }, - // [CB0B]: CB3DMA on PCI0 - // [CB0F]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 1, 0, 39 }, - // [CB0C]: CB3DMA on PCI0 - // [CB0G]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 2, 0, 31 }, - // [CB0D]: CB3DMA on PCI0 - // [CB0H]: CB3DMA on PCI0 - Package() { 0x0004FFFF, 3, 0, 39 }, - // [IIM0]: IIOMISC on PCI0 - Package() { 0x0005FFFF, 0, 0, 16 }, - Package() { 0x0005FFFF, 1, 0, 17 }, - Package() { 0x0005FFFF, 2, 0, 18 }, - Package() { 0x0005FFFF, 3, 0, 19 }, - // [IID0]: IIODFX0 on PCI0 - Package() { 0x0006FFFF, 0, 0, 16 }, - Package() { 0x0006FFFF, 1, 0, 17 }, - Package() { 0x0006FFFF, 2, 0, 18 }, - Package() { 0x0006FFFF, 3, 0, 19 }, - // [XHCI]: xHCI controller 1 on PCH - Package() { 0x0014FFFF, 3, 0, 19 }, - // [HECI]: ME HECI on PCH - // [IDER]: ME IDE redirect on PCH - Package() { 0x0016FFFF, 0, 0, 16 }, - // [HEC2]: ME HECI2 on PCH - // [MEKT]: MEKT on PCH - Package() { 0x0016FFFF, 1, 0, 17 }, - // [GBEM]: GbE Controller VPRO - Package() { 0x0019FFFF, 0, 0, 20 }, - // [EHC2]: EHCI controller #2 on PCH - Package() { 0x001AFFFF, 2, 0, 18 }, - // [ALZA]: High definition Audio Controller - Package() { 0x001BFFFF, 0, 0, 22 }, - // [RP01]: Pci Express Port 1 on PCH - // [RP05]: Pci Express Port 5 on PCH - Package() { 0x001CFFFF, 0, 0, 16 }, - // [RP02]: Pci Express Port 2 on PCH - // [RP06]: Pci Express Port 6 on PCH - Package() { 0x001CFFFF, 1, 0, 17 }, - // [RP03]: Pci Express Port 3 on PCH - // [RP07]: Pci Express Port 7 on PCH - Package() { 0x001CFFFF, 2, 0, 18 }, - // [RP04]: Pci Express Port 4 on PCH - // [RP08]: Pci Express Port 8 on ICH - Package() { 0x001CFFFF, 3, 0, 19 }, - // [EHC1]: EHCI controller #1 on PCH - Package() { 0x001DFFFF, 2, 0, 18 }, - // [SAT1]: SATA controller 1 on PCH - // [SAT2]: SATA Host controller 2 on PCH - Package() { 0x001FFFFF, 0, 0, 16 }, - // [SMBS]: SMBus controller on PCH - // [TERM]: Thermal Subsystem on ICH - Package() { 0x001FFFFF, 2, 0, 18 }, - Package() { 0x0017FFFF, 0, 0, 20 }, - Package() { 0x0011FFFF, 0, 0, 21 }, -}) - -// Socket 0 Root bridge -Method (_PRT, 0) { - Return (AR00) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/45835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d842880db03507adf7b2ba0e79c986c89584ca Gerrit-Change-Number: 45835 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: cpu/intel/haswell/acpi.c: Use C-state enum definitions
by Angel Pons (Code Review) 15 Jan '21

15 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46923 ) Change subject: cpu/intel/haswell/acpi.c: Use C-state enum definitions ...................................................................... cpu/intel/haswell/acpi.c: Use C-state enum definitions Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 3 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/46923/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index d257d86..7c99df3 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -15,15 +15,15 @@ #include <southbridge/intel/lynxpoint/pch.h> static int cstate_set_lp[3] = { - 2, - 3, - 9, + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT, }; static int cstate_set_trad[3] = { - 1, - 3, - 5, + C_STATE_C1, + C_STATE_C3, + C_STATE_C6_LONG_LAT, }; static int get_cores_per_package(void) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index d02cba6..e45acd5 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -140,6 +140,27 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif +/* + * List of supported C-states for Haswell and Broadwell. + * Only the ULT parts support C8, C9, and C10. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6_SHORT_LAT = 4, + C_STATE_C6_LONG_LAT = 5, + C_STATE_C7_SHORT_LAT = 6, + C_STATE_C7_LONG_LAT = 7, + C_STATE_C7S_SHORT_LAT = 8, + C_STATE_C7S_LONG_LAT = 9, + C_STATE_C8 = 10, + C_STATE_C9 = 11, + C_STATE_C10 = 12, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 1920350..04f5802 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -20,27 +20,6 @@ #include "haswell.h" #include "chip.h" -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - #define MWAIT_RES(state, sub_state) \ { \ .addrl = (((state) << 4) | (sub_state)), \ -- To view, visit https://review.coreboot.org/c/coreboot/+/46923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Gerrit-Change-Number: 46923 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: cpu/intel/haswell: Factor out ACPI C-state values
by Angel Pons (Code Review) 15 Jan '21

15 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46908 ) Change subject: cpu/intel/haswell: Factor out ACPI C-state values ...................................................................... cpu/intel/haswell: Factor out ACPI C-state values There's no need to have them in the devicetree. ACPI generation can now be simplified even further, and is done in subsequent commits. Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb 9 files changed, 26 insertions(+), 123 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46908/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 6dd8559..f44d304 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -14,6 +14,18 @@ #include <southbridge/intel/lynxpoint/pch.h> +static int cstate_set_lp[3] = { + 2, + 3, + 9, +}; + +static int cstate_set_trad[3] = { + 1, + 3, + 5, +}; + static int get_cores_per_package(void) { struct cpuinfo_x86 c; @@ -30,41 +42,6 @@ return cores; } -static void generate_cstate_entries(acpi_cstate_t *cstates, - int c1, int c2, int c3) -{ - int cstate_count = 0; - - /* Count number of active C-states */ - if (c1 > 0) - ++cstate_count; - if (c2 > 0) - ++cstate_count; - if (c3 > 0) - ++cstate_count; - if (!cstate_count) - return; - - acpigen_write_package(cstate_count + 1); - acpigen_write_byte(cstate_count); - - /* Add an entry if the level is enabled */ - if (c1 > 0) { - cstates[c1].ctype = 1; - acpigen_write_CST_package_entry(&cstates[c1]); - } - if (c2 > 0) { - cstates[c2].ctype = 2; - acpigen_write_CST_package_entry(&cstates[c2]); - } - if (c3 > 0) { - cstates[c3].ctype = 3; - acpigen_write_CST_package_entry(&cstates[c3]); - } - - acpigen_pop_len(); -} - static acpi_tstate_t tss_table_fine[] = { { 100, 1000, 0, 0x00, 0 }, { 94, 940, 0, 0x1f, 0 }, @@ -119,18 +96,12 @@ static void generate_C_state_entries(void) { + acpi_cstate_t map[3]; + int *set; + int i; + struct cpu_info *info; struct cpu_driver *cpu; - struct device *lapic; - struct cpu_intel_haswell_config *conf = NULL; - - /* Find the SpeedStep CPU in the device tree using magic APIC ID */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic) - return; - conf = lapic->chip_info; - if (!conf) - return; /* Find CPU map of supported C-states */ info = cpu_info(); @@ -140,25 +111,18 @@ if (!cpu || !cpu->cstates) return; - acpigen_emit_byte(0x14); /* MethodOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("_CST"); - acpigen_emit_byte(0x00); /* No Arguments */ + if (haswell_is_ult()) + set = cstate_set_lp; + else + set = cstate_set_trad; - /* If running on AC power */ - acpigen_emit_byte(0xa0); /* IfOp */ - acpigen_write_len_f(); /* PkgLength */ - acpigen_emit_namestring("PWRS"); - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_acpower, - conf->c2_acpower, conf->c3_acpower); - acpigen_pop_len(); + for (i = 0; i < ARRAY_SIZE(map); i++) { + map[i] = cpu->cstates[set[i]]; + map[i].ctype = i + 1; + } - /* Else on battery power */ - acpigen_emit_byte(0xa4); /* ReturnOp */ - generate_cstate_entries(cpu->cstates, conf->c1_battery, - conf->c2_battery, conf->c3_battery); - acpigen_pop_len(); + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 7d41461..9db1ad3 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -4,15 +4,5 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_haswell_config { - u8 disable_acpi; /* Do not generate CPU ACPI tables */ - - int c1_battery; /* ACPI C1 on Battery Power */ - int c2_battery; /* ACPI C2 on Battery Power */ - int c3_battery; /* ACPI C3 on Battery Power */ - - int c1_acpower; /* ACPI C1 on AC Power */ - int c2_acpower; /* ACPI C2 on AC Power */ - int c3_acpower; /* ACPI C3 on AC Power */ - int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index d257f18..e7dfa74 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,13 +5,6 @@ device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 8f36896..cf73e39 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -5,13 +5,6 @@ device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8fdfbd7..f9a56d7 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -18,14 +18,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 200721b..043ead6 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -23,14 +23,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) end end diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index ad3d35a..6d2342e 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -16,14 +16,6 @@ device lapic 0 on end # Magic APIC ID to locate this chip device lapic 0xACAC off end - - register "c1_battery" = "1" - register "c2_battery" = "3" - register "c3_battery" = "5" - - register "c1_acpower" = "1" - register "c2_acpower" = "3" - register "c3_acpower" = "5" end end diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 8c35681..33ff903 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -13,12 +13,6 @@ register "ec_present" = "true" device cpu_cluster 0x0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" device lapic 0x0 on end device lapic 0xacac off end end diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index ffcc56d..3a0dfbe 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -4,13 +4,6 @@ device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" - device lapic 0 on end device lapic 0xacac off end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7 Gerrit-Change-Number: 46908 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/baskingridge: Replace invalid C-state values
by Angel Pons (Code Review) 15 Jan '21

15 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46907 ) Change subject: mb/intel/baskingridge: Replace invalid C-state values ...................................................................... mb/intel/baskingridge: Replace invalid C-state values Basking Ridge is not ULT, thus does not support C-states deeper than C7. Replace them with the values used by all other Haswell non-ULT boards to allow subsequent commits to cleanly factor them out of the devicetree. Change-Id: Ife34f7828f9ef19c8fccb3ac7b60146960112a81 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/baskingridge/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46907/1 diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 6345090..ad3d35a 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -17,13 +17,13 @@ # Magic APIC ID to locate this chip device lapic 0xACAC off end - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/46907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife34f7828f9ef19c8fccb3ac7b60146960112a81 Gerrit-Change-Number: 46907 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/amd/picasso,stoneyridge: Refactor acpi_create_gnvs()
by Kyösti Mälkki (Code Review) 13 Jan '21

13 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44024 ) Change subject: soc/amd/picasso,stoneyridge: Refactor acpi_create_gnvs() ...................................................................... soc/amd/picasso,stoneyridge: Refactor acpi_create_gnvs() Add default_inject_dsdt(). Change-Id: I61010f64a4a935f238e6dcd0f8c1340a6cc68eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/acpi/acpi_gnvs.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c 4 files changed, 3 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44024/1 diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h index b8e2a37..08778ad 100644 --- a/src/include/acpi/acpi_gnvs.h +++ b/src/include/acpi/acpi_gnvs.h @@ -25,8 +25,6 @@ */ struct global_nvs; -void acpi_create_gnvs(struct global_nvs *gnvs); - void soc_fill_gnvs(struct global_nvs *gnvs); void mainboard_fill_gnvs(struct global_nvs *gnvs); diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 4a0ed85..6ce1f6b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -324,7 +324,7 @@ .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, .enable_resources = lpc_enable_resources, - .acpi_inject_dsdt = southbridge_inject_dsdt, + .acpi_inject_dsdt = default_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2cecd36..d57e924 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -13,7 +13,6 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> -#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <amdblocks/acpimmio.h> @@ -189,7 +188,7 @@ return acpi_write_hpet(device, current, rsdp); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = ~0ULL; @@ -199,22 +198,6 @@ gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) { /* diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index f6a5f8b..d5db81b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -12,7 +12,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <cpu/x86/smm.h> -#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <amdblocks/acpimmio.h> @@ -164,7 +163,7 @@ return acpi_write_hpet(device, current, rsdp); } -void acpi_create_gnvs(struct global_nvs *gnvs) +void soc_fill_gnvs(struct global_nvs *gnvs) { /* Set unknown wake source */ gnvs->pm1i = ~0ULL; @@ -174,22 +173,6 @@ gnvs->pcnt = dev_count_cpu(); } -void southbridge_inject_dsdt(const struct device *device) -{ - struct global_nvs *gnvs; - - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) { - acpi_create_gnvs(gnvs); - - /* Add it to DSDT */ - acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); - acpigen_pop_len(); - } -} - static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61010f64a4a935f238e6dcd0f8c1340a6cc68eb4 Gerrit-Change-Number: 44024 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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