coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/broadwell: Select INTEL_LYNXPOINT_LP
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46958 ) Change subject: soc/intel/broadwell: Select INTEL_LYNXPOINT_LP ...................................................................... soc/intel/broadwell: Select INTEL_LYNXPOINT_LP This allows the correct Haswell and Lynxpoint code to be used. Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46958/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 22173d2..02cd1c2 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -5,6 +5,10 @@ if SOC_INTEL_BROADWELL +config INTEL_LYNXPOINT_LP + bool + default y if SOC_INTEL_BROADWELL + config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES -- To view, visit https://review.coreboot.org/c/coreboot/+/46958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91 Gerrit-Change-Number: 46958 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/intel/haswell: Set C9/C10 vccmin
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46922 ) Change subject: cpu/intel/haswell: Set C9/C10 vccmin ...................................................................... cpu/intel/haswell: Set C9/C10 vccmin Backport commit ab7586f ( broadwell: Set C9/C10 vccmin) to Haswell. Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/registers/mchbar.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46922/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 7edb663..1920350 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -247,6 +247,26 @@ return MCHBAR32(BIOS_MAILBOX_DATA); } +static int pcode_mailbox_write(u32 command, u32 data) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return -1; + } + + MCHBAR32(BIOS_MAILBOX_DATA) = data; + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return -1; + } + + return 0; +} + static void initialize_vr_config(void) { struct cpu_vr_config vr_config = { 0 }; @@ -321,6 +341,9 @@ else msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); + + /* Set C9/C10 VCC Min */ + pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); } static void configure_pch_power_sharing(void) diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 4bdb49a..a61036a 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -46,6 +46,9 @@ #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 + /* Errors are returned back in bits 7:0 */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd Gerrit-Change-Number: 46922 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/intel/haswell: Add fast ramp voltage for Broadwell
by Angel Pons (Code Review) 24 Jan '21

24 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46921 ) Change subject: cpu/intel/haswell: Add fast ramp voltage for Broadwell ...................................................................... cpu/intel/haswell: Add fast ramp voltage for Broadwell Backport commit 55228ba (broadwell: Changes from 2.2.0 ref code) to Haswell, to eventually migrate Broadwell to use the same Haswell code. Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/46921/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 2352489..d02cba6 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -3,6 +3,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H +#include <arch/cpu.h> #include <stdint.h> /* CPU types without stepping */ @@ -147,6 +148,11 @@ int cpu_config_tdp_levels(void); /* CPU identification */ +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5838f1f..7edb663 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -315,8 +315,11 @@ msr = rdmsr(MSR_VR_MISC_CONFIG2); msr.lo &= ~0xffff; /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; + set the fast ramp voltage in 10mV steps. */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) + msr.lo |= 0x006a; /* 1.56V */ + else + msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9 Gerrit-Change-Number: 46921 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: ACPI S3: Remove stashed acpi_slp_typ value
by Kyösti Mälkki (Code Review) 23 Jan '21

23 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47694 ) Change subject: ACPI S3: Remove stashed acpi_slp_typ value ...................................................................... ACPI S3: Remove stashed acpi_slp_typ value Change-Id: Iff950d2bcf7eacbbdd40865abf62c35a2e8c3c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi_pm.c M src/include/acpi/acpi.h M src/lib/romstage_handoff.c 3 files changed, 11 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/47694/1 diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c index 540b6d2..c1e9996 100644 --- a/src/acpi/acpi_pm.c +++ b/src/acpi/acpi_pm.c @@ -1,32 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> -#include <romstage_handoff.h> #include <smbios.h> -/* This is filled with acpi_handoff_wakeup_s3() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_handoff_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - void __weak mainboard_suspend_resume(void) { } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index f6eb772..35c8bc9 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -49,6 +49,7 @@ #include <device/device.h> #include <uuid.h> #include <cper.h> +#include <romstage_handoff.h> #include <types.h> #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ @@ -1017,7 +1018,6 @@ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); -int acpi_handoff_wakeup_s3(void); /* ACPI_Sn assignments are defined to always equal the sleep state numbers */ enum { @@ -1073,7 +1073,7 @@ if (ENV_ROMSTAGE_OR_BEFORE) return (acpi_get_sleep_type() == ACPI_S3); - return acpi_handoff_wakeup_s3(); + return romstage_handoff_is_resume(); } static inline uintptr_t acpi_align_current(uintptr_t current) diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index 0a7a822..8fd5d2f 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -55,6 +55,7 @@ int romstage_handoff_is_resume(void) { + static int once; struct romstage_handoff *handoff; handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); @@ -62,5 +63,13 @@ if (handoff == NULL) return 0; + if (!once) { + if (handoff->s3_resume) + printk(BIOS_DEBUG, "S3 Resume\n"); + else + printk(BIOS_DEBUG, "Normal boot\n"); + once = 1; + } + return handoff->s3_resume; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff950d2bcf7eacbbdd40865abf62c35a2e8c3c69 Gerrit-Change-Number: 47694 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: util/docker: Replace all variables in Dockerfile
by Martin Roth (Code Review) 22 Jan '21

22 Jan '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47339 ) Change subject: util/docker: Replace all variables in Dockerfile ...................................................................... util/docker: Replace all variables in Dockerfile When updating the variables in the dockerfile, if there were two or more variables on a line, only the first would be updated. This fixes that issue. Change-Id: I011ccb299c7c8527b79d234075cab18be998ab43 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/docker/Makefile 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47339/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index eaa26e1..1a83220 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -43,9 +43,9 @@ coreboot-sdk: test-docker @echo "Building coreboot SDK $(crossgcc_version) from commit $(DOCKER_COMMIT)" cat coreboot-sdk/Dockerfile | \ - sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/" | \ - sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/" | \ - sed "s/{{CROSSGCC_PARAM}}/$(COREBOOT_CROSSGCC_PARAM)/" | \ + sed "s/{{DOCKER_COMMIT}}/$(DOCKER_COMMIT)/g" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/g" | \ + sed "s/{{CROSSGCC_PARAM}}/$(COREBOOT_CROSSGCC_PARAM)/g" | \ $(DOCKER) build -t coreboot/coreboot-sdk:$(COREBOOT_IMAGE_TAG) - upload-coreboot-sdk: test-docker-login @@ -53,7 +53,7 @@ coreboot-jenkins-node: test-docker cat coreboot-jenkins-node/Dockerfile | \ - sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/" | \ + sed "s/{{SDK_VERSION}}/$(COREBOOT_IMAGE_TAG)/g" | \ sed "s|{{SSH_KEY}}|$$(cat coreboot-jenkins-node/authorized_keys)|" | \ $(DOCKER) build -t coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) - -- To view, visit https://review.coreboot.org/c/coreboot/+/47339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ccb299c7c8527b79d234075cab18be998ab43 Gerrit-Change-Number: 47339 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: WIP: soc/amd/picasso/acpi: Add power resources for UART0
by Raul Rangel (Code Review) 22 Jan '21

22 Jan '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42474 ) Change subject: WIP: soc/amd/picasso/acpi: Add power resources for UART0 ...................................................................... WIP: soc/amd/picasso/acpi: Add power resources for UART0 BUG=b:153001807 TEST=suspend and resume with trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec --- M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42474/1 diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 6577cfc..036ebc0 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -140,6 +140,7 @@ AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) AOAC_DEVICE(I2C4, 9, 5) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 00774fd..cb186c4 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,17 @@ Return (Local0) } } + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec Gerrit-Change-Number: 42474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/mediatek/mt8183: Fix pq module size config
by Yu-Ping Wu (Code Review) 22 Jan '21

22 Jan '21

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46626 ) Change subject: soc/mediatek/mt8183: Fix pq module size config ...................................................................... soc/mediatek/mt8183: Fix pq module size config For pq module size registers such as DISP_AAL_SIZE, the high bits should be HSIZE, while low bits should be VSIZE. BUG=b:171167210 TEST=none BRANCH=kukui Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/ddp.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46626/1 diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index eba3f5e..395c821 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -34,7 +34,7 @@ static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, int enable_relay) { - write32(&regs->size, height << 16 | width); + write32(&regs->size, width << 16 | height); if (enable_relay) write32(&regs->cfg, PQ_RELAY_MODE); write32(&regs->en, PQ_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/46626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Gerrit-Change-Number: 46626 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Enable timed MWAIT if supported
by Angel Pons (Code Review) 22 Jan '21

22 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46916 ) Change subject: cpu/intel/haswell: Enable timed MWAIT if supported ...................................................................... cpu/intel/haswell: Enable timed MWAIT if supported Broadwell unconditionally enables it, but not all Haswell steppings support it. Thus, check the capability bit before attempting to set it. Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46916/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index b23fbac..2352489 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -36,6 +36,7 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) +#define TIMED_MWAIT_SUPPORTED (1 << (37 - 32)) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 438a317..21f3f4a 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -433,7 +433,9 @@ static void configure_c_states(void) { - msr_t msr; + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + + const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 30); // Package c-state Undemotion Enable @@ -443,6 +445,10 @@ msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection + + if (timed_mwait_capable) + msr.lo |= (1 << 31); // Timed MWAIT Enable + /* The deepest package c-state defaults to factory-configured value. */ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); -- To view, visit https://review.coreboot.org/c/coreboot/+/46916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a Gerrit-Change-Number: 46916 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 22 Jan '21

22 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45554 ) Change subject: mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax ...................................................................... mb/getac/p470/acpi: Convert 'battery.asl' to ASL 2.0 syntax Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/battery.asl 1 file changed, 81 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45554/1 diff --git a/src/mainboard/getac/p470/acpi/battery.asl b/src/mainboard/getac/p470/acpi/battery.asl index 7924edf..33b19ae 100644 --- a/src/mainboard/getac/p470/acpi/battery.asl +++ b/src/mainboard/getac/p470/acpi/battery.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope(\_SB) { +Scope(_SB) { Name(NIMH, "NiMH") Name(LION, "Lion") @@ -10,7 +10,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -18,7 +18,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT) { + If (^^PCI0.LPCB.EC0.BAT) { Return(0x1f) } Else { Return(0x0f) @@ -45,28 +45,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC0, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV0, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC0 + PBIF [4] = ^^PCI0.LPCB.EC0.BDV0 - Store(\_SB.PCI0.LPCB.EC0.BFC0, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC0 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTYP) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTYP) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -75,33 +75,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT) { - Store(\_SB.PCI0.LPCB.EC0.BPV0, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT) { + PBST [3] = ^^PCI0.LPCB.EC0.BPV0 - Multiply(\_SB.PCI0.LPCB.EC0.BRC0, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC0, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC0, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 * 0x64 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BFC0 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BFC0) + Local3 = ^^PCI0.LPCB.EC0.BFC0 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [0x02] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC0, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR0, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC0 + Local0 = ^^PCI0.LPCB.EC0.BPR0 + Local0 = (~Local0 & 0xFFFF) + PBST [1] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CHRG) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CHRG) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 0 } } } @@ -115,7 +117,7 @@ Name(_HID, EisaId("PNP0C0A")) Name(_UID, 1) - Name(_PCL, Package(){ \_SB }) + Name(_PCL, Package(){ _SB }) Name(PBST, Package() { 0x00, 0x04b0, 0x0bb8, 0x03e8 }) @@ -123,7 +125,7 @@ Method(_STA, 0) { Sleep(120) - If(\_SB.PCI0.LPCB.EC0.BAT2) { + If (^^PCI0.LPCB.EC0.BAT2) { Return(0x1f) } Else { Return(0x0f) @@ -150,28 +152,28 @@ }) // Is battery there? - Store(_STA(), Local0) - And(Local0, 0x10, Local0) - If(LNot(Local0)) { + Local0 = _STA () + Local0 &= 0x10 + If (!Local0) { Return (PBIF) } - Store(\_SB.PCI0.LPCB.EC0.BDC2, Index(PBIF, 1)) - Store(\_SB.PCI0.LPCB.EC0.BDV2, Index(PBIF, 4)) + PBIF [1] = ^^PCI0.LPCB.EC0.BDC2 + PBIF [0x04] = ^^PCI0.LPCB.EC0.BDV2 - Store(\_SB.PCI0.LPCB.EC0.BFC2, Local0) - Store(Local0, Index(PBIF, 2)) + Local0 = ^^PCI0.LPCB.EC0.BFC2 + PBIF [2] = Local0 - Divide(Local0, 10, , Local2) - Store(Local2, Index(PBIF, 5)) + Local2 = Local0 / 10 + PBIF [5] = Local2 - Divide(Local0, 20, , Local2) - Store(Local2, Index(PBIF, 6)) + Local2 = Local0 / 20 + PBIF [6] = Local2 - If(\_SB.PCI0.LPCB.EC0.BTY2) { - Store(NIMH, Index(PBIF, 11)) + If (^^PCI0.LPCB.EC0.BTY2) { + PBIF [11] = NIMH } Else { - Store(LION, Index(PBIF, 11)) + PBIF [11] = LION } Return(PBIF) @@ -180,33 +182,35 @@ /* Battery Status */ Method(_BST, 0) { - If(\_SB.PCI0.LPCB.EC0.BAT2) { - Store(\_SB.PCI0.LPCB.EC0.BPV2, Index(PBST, 3)) + If (^^PCI0.LPCB.EC0.BAT2) { + PBST [0x03] = ^^PCI0.LPCB.EC0.BPV2 - Multiply(\_SB.PCI0.LPCB.EC0.BRC2, 100, Local3) - Divide(Local3, \_SB.PCI0.LPCB.EC0.BFC2, Local3, Local0) - Multiply(\_SB.PCI0.LPCB.EC0.BFC2, Local0, Local3) - Divide(Local3, 0x64, Local3, Local0) - Increment(Local0) - Store(Local0, Index(PBST, 2)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 * 100 + Local0 = Local3 / ^^PCI0.LPCB.EC0.BRC2 + Local3 -= (Local0 * ^^PCI0.LPCB.EC0.BRC2) + Local3 = ^^PCI0.LPCB.EC0.BFC2 * Local0 + Local0 = Local3 / 0x64 + Local3 -= (Local0 * 0x64) + Local0++ + PBST [2] = Local0 - Store (\_SB.PCI0.LPCB.EC0.BRC2, Local3) - Store (\_SB.PCI0.LPCB.EC0.BPR2, Local0) - And (Not (Local0), 0xFFFF, Local0) - Store (Local0, Index(PBST,1)) + Local3 = ^^PCI0.LPCB.EC0.BRC2 + Local0 = ^^PCI0.LPCB.EC0.BPR2 + Local0 = (~Local0 & 0xFFFF) + PBST [One] = Local0 // AC Power connected? - If(\_SB.PCI0.LPCB.EC0.ADP) { - If(\_SB.PCI0.LPCB.EC0.CRG2) { - Store(2, Index(PBST, 0)) + If (^^PCI0.LPCB.EC0.ADP) { + If (^^PCI0.LPCB.EC0.CRG2) { + PBST [0] = 2 } Else { - Store(0, Index(PBST, 0)) + PBST [0] = 0 } } Else { - If(LLess(Local3, 25)) { - Store(5, Index(PBST, 0)) + If (Local3 < 25) { + PBST [0] = 5 } Else { - Store(1, Index(PBST, 0)) + PBST [0] = 1 } } } @@ -223,19 +227,19 @@ Name (ACST, 0x00) Method (_PSR, 0) { - If(ACFG) { - Store(ACST, Local0) + If (ACFG) { + Local0 = ACST } Else { - Store(\_SB.PCI0.LPCB.EC0.ADP, Local0) - Store(Local0, ACST) - Store(1, ACFG) + Local0 = ^^PCI0.LPCB.EC0.ADP + ACST = Local0 + ACFG = 1 } Sleep(120) Return (Local0) } Name(_PCL, Package(){ - \_SB, + _SB, BAT0, BAT1 }) -- To view, visit https://review.coreboot.org/c/coreboot/+/45554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc8bf4022838056bf1fff853eb2027af684064e Gerrit-Change-Number: 45554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: remove unuse I2C1
by Alec Wang (Code Review) 22 Jan '21

22 Jan '21

Alec Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46486 ) Change subject: mb/google/dedede: remove unuse I2C1 ...................................................................... mb/google/dedede: remove unuse I2C1 remove unuse I2C1 BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang(a)lcfc.corp-partner.google.com> Change-Id: I88b6f12728d9ae25882c141d6a8558f76591d3a2 --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46486/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 2ba6d9d..fd532d1 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -9,7 +9,6 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | #| I2C2 | Touchscreen | #| I2C4 | Audio | #+-------------------+---------------------------+ @@ -21,9 +20,6 @@ .i2c[0] = { .speed = I2C_SPEED_FAST, }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, .i2c[2] = { .speed = I2C_SPEED_FAST, }, @@ -39,7 +35,7 @@ register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/46486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88b6f12728d9ae25882c141d6a8558f76591d3a2 Gerrit-Change-Number: 46486 Gerrit-PatchSet: 1 Gerrit-Owner: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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