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Change in coreboot[master]: ec/lenovo/h8: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46101 ) Change subject: ec/lenovo/h8: Convert to ASL 2.0 syntax ...................................................................... ec/lenovo/h8: Convert to ASL 2.0 syntax Change-Id: I87bab2b11ba5e1fb585d5c88cf831b36e257c148 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/lenovo/h8/acpi/ac.asl M src/ec/lenovo/h8/acpi/battery.asl M src/ec/lenovo/h8/acpi/beep.asl M src/ec/lenovo/h8/acpi/ec.asl M src/ec/lenovo/h8/acpi/lid.asl M src/ec/lenovo/h8/acpi/sleepbutton.asl M src/ec/lenovo/h8/acpi/systemstatus.asl M src/ec/lenovo/h8/acpi/thermal.asl M src/ec/lenovo/h8/acpi/thinkpad.asl 9 files changed, 142 insertions(+), 140 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46101/1 diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl index ec7b7fc..436fdcf 100644 --- a/src/ec/lenovo/h8/acpi/ac.asl +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -15,8 +15,8 @@ Method(_PSR, 0, NotSerialized) { - Store(HPAC, Local0) - Store(Local0, \PWRS) + Local0 = HPAC + \PWRS = Local0 \PNOT() return (Local0) } diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 42b91b9..a43ffce 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -94,32 +94,32 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) - Store(0, Local0) - ^BPAG(Or(1, Arg0)) - Store(BAMA, Local1) + Local0 = 0 + ^BPAG(1 | Arg0) + Local1 = BAMA ^BPAG(Arg0) /* Battery dynamic information */ /* * Present rate is a 16bit signed int, positive while charging * and negative while discharging. */ - Store(BAPR, Local2) + Local2 = BAPR If (Arg2) // Charging { - Or(2, Local0, Local0) + Local0 |= 2 } Else { If (Arg3) // Discharging { - Or(1, Local0, Local0) + Local0 |= 1 // Negate present rate - Subtract(0x10000, Local2, Local2) + Local2 = 0x10000 - Local2 } Else // Full battery, force to 0 { - Store(0, Local2) + Local2 = 0 } } @@ -127,21 +127,21 @@ * The present rate value must be positive now, if it is not we have an * EC bug or inconsistency and force the value to 0. */ - If (LGreaterEqual (Local2, 0x8000)) { - Store(0, Local2) + If (Local2 >= 0x8000) { + Local2 = 0 } - Store(Local0, Index(Arg1, 0x00)) + Arg1 [0] = Local0 if (Local1) { - Multiply (BARC, 10, Index(Arg1, 2)) - Multiply (Local2, BAVO, Local2) - Divide (Local2, 1000, , Index(Arg1, 1)) + Arg1 [2] = BARC * 10 + Local2 *= BAVO + Arg1 [1] = Local2 / 1000 } else { - Store(BARC, Index(Arg1, 2)) - Store(Local2, Index(Arg1, 1)) + Arg1 [2] = BARC + Arg1 [1] = Local2 } - Store(BAVO, Index(Arg1, 3)) + Arg1 [3] = BAVO Release(ECLK) Return (Arg1) } @@ -149,44 +149,46 @@ Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) - ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ - Xor(BAMA, 1, Index(Arg0, 0)) - Store(BAMA, Local0) + ^BPAG(1 | Arg1) /* Battery 0 static information */ + Arg0 [0] = BAMA ^ 1 + Local0 = BAMA ^BPAG(Arg1) - Store(BAFC, Local2) - ^BPAG(Or(2, Arg1)) - Store(BADC, Local1) + Local2 = BAFC + ^BPAG(2 | Arg1) + Local1 = BADC if (Local0) { - Multiply (Local1, 10, Local1) - Multiply (Local2, 10, Local2) + Local1 *= 10 + Local2 *= 10 } - Store(Local1, Index(Arg0, 1)) // Design Capacity - Store(Local2, Index(Arg0, 2)) // Last full charge capacity - Store(BADV, Index(Arg0, 4)) // Design Voltage - Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + Arg0 [1] = Local1 // Design Capacity + Arg0 [2] = Local2 // Last full charge capacity + Arg0 [4] = BADV // Design Voltage + Local0 = Local2 % 20 /* FIXME: Local0 not used */ + Arg0 [5] = Local2 / 20 // Warning capacity - Store (BASN, Local0) + Local0 = BASN Name (SERN, Buffer (0x06) { " " }) - Store (4, Local1) + Local1 = 4 While (Local0) { - Divide (Local0, 0x0A, Local2, Local0) - Add (Local2, 48, Index (SERN, Local1)) - Decrement (Local1) + Local2 = Local0 % 10 + Local0 /= 10 + SERN [Local1] = Local2 + 48 + Local1-- } - Store (SERN, Index (Arg0, 10)) // Serial Number + Arg0 [10] = SERN // Serial Number ^BPAG(Or(4, Arg1)) Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - Store(BATY, TYPE) - Store(TYPE, Index (Arg0, 11)) // Battery type - ^BPAG(Or(5, Arg1)) - Store(BAOE, Index (Arg0, 12)) // OEM information - ^BPAG(Or(6, Arg1)) - Store(BANA, Index (Arg0, 9)) // Model number + TYPE = BATY + Arg0 [11] = TYPE // Battery type + ^BPAG(5 | Arg1) + Arg0 [12] = BAOE // OEM information + ^BPAG(6 | Arg1) + Arg0 [9] = BANA // Model number Release(ECLK) Return (Arg0) } diff --git a/src/ec/lenovo/h8/acpi/beep.asl b/src/ec/lenovo/h8/acpi/beep.asl index 214c8a9..3e51938 100644 --- a/src/ec/lenovo/h8/acpi/beep.asl +++ b/src/ec/lenovo/h8/acpi/beep.asl @@ -9,5 +9,5 @@ Method(BEEP, 1, NotSerialized) { - Store (Arg0, SNDS) + SNDS = Arg0 } diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 18463a5..0c77327 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -64,12 +64,12 @@ Method (_REG, 2, NotSerialized) { /* Wait for ERAM driver loaded */ - if (LEqual(Arg1, One)) { + if (Arg1 == 1) { /* Fill HKEY defaults on first boot */ - if (LEqual(^HKEY.INIT, Zero)) { - Store (BTEB, ^HKEY.WBDC) - Store (WWEB, ^HKEY.WWAN) - Store (One, ^HKEY.INIT) + if (^HKEY.INIT == 0) { + ^HKEY.WBDC = BTEB + ^HKEY.WWAN = WWEB + ^HKEY.INIT = 1 } } } @@ -86,13 +86,13 @@ Method (TLED, 1, NotSerialized) { - Store(Arg0, LEDS) + LEDS = Arg0 } /* Not used for coreboot. Provided for compatibility with thinkpad-acpi. */ Method (LED, 2, NotSerialized) { - TLED(Or(Arg0, Arg1)) + TLED (Arg0 | Arg1) } Method (_INI, 0, NotSerialized) @@ -101,24 +101,24 @@ Method (MUTE, 1, NotSerialized) { - Store(Arg0, AMUT) + AMUT = Arg0 } Method (RADI, 1, NotSerialized) { - Store(Arg0, WLEB) - Store(Arg0, WWEB) - Store(Arg0, BTEB) + WLEB = Arg0 + WWEB = Arg0 + BTEB = Arg0 } Method (USBP, 1, NotSerialized) { - Store(Arg0, USPW) + USPW = Arg0 } Method (LGHT, 1, NotSerialized) { - Store(Arg0, KBLT) + KBLT = Arg0 } @@ -157,7 +157,7 @@ Method(_Q27, 0, NotSerialized) { Notify (AC, 0x80) - Store(0x50, EVNT) + EVNT = 0x50 \PNOT() } @@ -318,11 +318,11 @@ Method (FANE, 1, Serialized) { If (Arg0) { - Store (One, FAND) - Store (Zero, FANA) + FAND = 1 + FANA = 0 } Else { - Store (Zero, FAND) - Store (One, FANA) + FAND = 0 + FANA = 1 } } diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index 8b74ecd..7695e4e 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -27,9 +27,9 @@ Method(_PSW, 1, NotSerialized) { if (Arg0) { - Store(1, WKLD) + WKLD = 1 } else { - Store(0, WKLD) + WKLD = 0 } } } diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index d3d6c9c..441dc65 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -20,11 +20,11 @@ Method(_PSW, 1, NotSerialized) { if (Arg0) { - Store(6, FNKY) /* Fn key acts as wake button */ - Store(1, WKFN) + FNKY = 6 /* Fn key acts as wake button */ + WKFN = 1 } else { - Store(0, FNKY) /* Fn key normal operation */ - Store(0, WKFN) + FNKY = 0 /* Fn key normal operation */ + WKFN = 0 } } } diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl index a5793be..7598154 100644 --- a/src/ec/lenovo/h8/acpi/systemstatus.asl +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -5,7 +5,7 @@ { Method(_SST, 1, NotSerialized) { - If (LEqual (Arg0, 0)) { + If (Arg0 == 0) { /* Indicator off */ /* power TLED off */ @@ -14,7 +14,7 @@ \_SB.PCI0.LPCB.EC.TLED(0x07) } - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { /* working state */ /* power TLED on */ @@ -23,7 +23,7 @@ \_SB.PCI0.LPCB.EC.TLED(0x07) } - If (LEqual (Arg0, 2)) { + If (Arg0 == 2) { /* waking state */ /* power LED on */ @@ -32,7 +32,7 @@ \_SB.PCI0.LPCB.EC.TLED(0xc7) } - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { /* sleep state */ /* power TLED pulsing */ diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index fe2d287..b72df1e 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -11,13 +11,13 @@ Method(C2K, 1, NotSerialized) { - Multiply(Arg0, 10, Local0) - Add (Local0, 2732, Local0) - if (LLessEqual(Local0, 2732)) { + Local0 = Arg0 * 10 + Local0 += 2732 + if (Local0 < 2732) { Return (3000) } - if (LGreater(Local0, 4012)) { + if (Local0 > 4012) { Return (3000) } Return (Local0) @@ -46,8 +46,8 @@ /* Get critical temperature in degree celsius */ Method (GCRT, 0, NotSerialized) { - Store (\TCRT, Local0) - if (LGreater (Local0, 0)) { + Local0 = \TCRT + if (Local0 > 0) { Return (Local0) } Return (127) @@ -55,8 +55,8 @@ /* Get passive temperature in degree celsius */ Method (GPSV, 0, NotSerialized) { - Store (\TPSV, Local0) - if (LGreater (Local0, 0)) { + Local0 = \TPSV + if (Local0 > 0) { Return (Local0) } Return (95) @@ -73,23 +73,23 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB1), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { + If (!MEB1 && (\_SB.PCI0.LPCB.EC.TMP0 == 128)) { Return (C2K(40)) } - Store (1, MEB1) + MEB1 = 1 #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } Method (_AC0) { - Store (GPSV (), Local0) + Local0 = GPSV () /* Active fan 10 degree below passive threshold */ - Subtract (Local0, 10, Local0) + Local0 -= 10 If (\FLVL) { /* Turn of 5 degree below trip point */ - Subtract (Local0, 5, Local0) + Local0 -= 5 } Return (C2K (Local0)) @@ -113,13 +113,13 @@ */ Method (_ON) { \_SB.PCI0.LPCB.EC.FANE(One) - Store (One, \FLVL) + \FLVL = 1 Notify (\_TZ.THM0, NOTIFY_TZ_TRIPPTCHG) } Method (_OFF) { \_SB.PCI0.LPCB.EC.FANE(Zero) - Store (Zero, \FLVL) + \FLVL = 0 Notify (\_TZ.THM0, NOTIFY_TZ_TRIPPTCHG) } } @@ -160,10 +160,10 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEB2), LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128))) { + If (!MEB2 && (\_SB.PCI0.LPCB.EC.TMP1 == 128)) { Return (C2K(40)) } - Store (1, MEB2) + MEB2 = 1 #endif Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) } diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index eca0d44..944a301 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -34,16 +34,16 @@ /* Retrieve event. */ Method (MHKP, 0, NotSerialized) { - Store (BTN, Local0) - If (LNotEqual (Local0, Zero)) { - Store (Zero, BTN) - Add (Local0, 0x1000, Local0) + Local0 = BTN + If (Local0 != 0) { + BTN = 0 + Local0 += 0x1000 Return (Local0) } - Store (BTAB, Local0) - If (LNotEqual (Local0, Zero)) { - Store (Zero, BTAB) - Add (Local0, 0x5000, Local0) + Local0 = BTAB + If (Local0 != 0) { + BTAB = 0 + Local0 += 0x5000 Return (Local0) } Return (Zero) @@ -51,18 +51,18 @@ /* Report event */ Method (RHK, 1, NotSerialized) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) - If (And (EMSK, Local0)) { - Store (Arg0, BTN) + Local0 = 1 << (Arg0 - 1) + If (EMSK & Local0) { + BTN = Arg0 Notify (HKEY, 0x80) } } /* Report tablet */ Method (RTAB, 1, NotSerialized) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) - If (And (ETAB, Local0)) { - Store (Arg0, BTAB) + Local0 = 1 << (Arg0 - 1) + If (ETAB & Local0) { + BTAB = Arg0 Notify (HKEY, 0x80) } } @@ -70,32 +70,32 @@ /* Enable/disable all events. */ Method (MHKC, 1, NotSerialized) { If (Arg0) { - Store (DHKN, EMSK) - Store (Ones, ETAB) + EMSK = DHKN + ETAB = Ones } Else { - Store (Zero, EMSK) - Store (Zero, ETAB) + EMSK = 0 + ETAB = 0 } - Store (Arg0, EN) + EN = Arg0 } /* Enable/disable event. */ Method (MHKM, 2, NotSerialized) { - If (LLessEqual (Arg0, 0x20)) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) + If (Arg0 <= 0x20) { + Local0 = 1 << (Arg0 - 1) If (Arg1) { - Or (DHKN, Local0, DHKN) + DHKN |= Local0 } Else { - And (DHKN, Not (Local0), DHKN) + DHKN &= ~Local0 } If (EN) { - Store (DHKN, EMSK) + EMSK = DHKN } } } @@ -115,7 +115,7 @@ /* Mute audio */ Method (SSMS, 1, NotSerialized) { - Store(Arg0, ALMT) + ALMT = Arg0 } /* Control mute microphone LED */ @@ -159,15 +159,15 @@ */ Method (GBDC, 0) { - Store (One, HAST) + HAST = 1 If (HBDC) { - Store(One, Local0) + Local0 = 1 If(\_SB.PCI0.LPCB.EC.BTEB) { - Or(Local0, 2, Local0) + Local0 |= 2 } - Or(Local0, ShiftLeft(WBDC, 2), Local0) + Local0 |= WBDC << 2 Return (Local0) } Else { Return (0) @@ -181,13 +181,13 @@ */ Method (SBDC, 1) { - Store (One, HAST) + HAST = 1 If (HBDC) { - ShiftRight (And(Arg0, 2), 1, Local0) - Store (Local0, \_SB.PCI0.LPCB.EC.BTEB) - ShiftRight (And(Arg0, 4), 2, Local0) - Store (Local0, WBDC) + Local0 = (Arg0 & 2) >> 1 + \_SB.PCI0.LPCB.EC.BTEB = Local0 + Local0 = (Arg0 & 4) >> 2 + WBDC = Local0 } } @@ -201,15 +201,15 @@ */ Method (GWAN, 0) { - Store (One, HAST) + HAST = 1 If (HWAN) { - Store(One, Local0) + Local0 = 1 If(\_SB.PCI0.LPCB.EC.WWEB) { - Or(Local0, 2, Local0) + Local0 |= 2 } - Or(Local0, ShiftLeft(WWAN, 2), Local0) + Local0 |= WWAN << 2 Return (Local0) } Else { Return (0) @@ -223,12 +223,12 @@ */ Method (SWAN, 1) { - Store (One, HAST) + HAST = 1 If (HWAN) { - ShiftRight (And(Arg0, 2), 1, Local0) - Store (Local0, \_SB.PCI0.LPCB.EC.WWEB) - ShiftRight (And(Arg0, 4), 2, WWAN) + Local0 = (Arg0 & 2) >> 1 + \_SB.PCI0.LPCB.EC.WWEB = Local0 + WWAN = (Arg0 & 4) >> 2 } } @@ -241,9 +241,9 @@ Method (MLCG, 1) { If (HKBL) { - Store (0x200, Local0) + Local0 = 0x200 /* FIXME: Support 2bit brightness control */ - Or (Local0, \_SB.PCI0.LPCB.EC.KBLT, Local0) + Local0 = \_SB.PCI0.LPCB.EC.KBLT Return (Local0) } Else { Return (0) @@ -258,7 +258,7 @@ { If (HKBL) { /* FIXME: Support 2bit brightness control */ - Store (And(Arg0, 1), \_SB.PCI0.LPCB.EC.WWEB) + \_SB.PCI0.LPCB.EC.WWEB = Arg0 & 1 } } @@ -270,10 +270,10 @@ Method (GUWB, 0) { If (HUWB) { - Store (One, Local0) + Local0 = 1 If(\_SB.PCI0.LPCB.EC.UWBE) { - Or(Local0, 2, Local0) + Local0 |= 2 } Return (Local0) } Else { @@ -288,8 +288,8 @@ Method (SUWB, 1) { If (HUWB) { - ShiftRight (And(Arg0, 2), 1, Local0) - Store (Local0, \_SB.PCI0.LPCB.EC.UWBE) + Local0 = (Arg0 & 2) >> 1 + \_SB.PCI0.LPCB.EC.UWBE = Local0 } } @@ -299,8 +299,8 @@ Method (WAKE, 1) { If (HAST) { - Store (WBDC, \_SB.PCI0.LPCB.EC.BTEB) - Store (WWAN, \_SB.PCI0.LPCB.EC.WWEB) + \_SB.PCI0.LPCB.EC.BTEB = WBDC + \_SB.PCI0.LPCB.EC.WWEB = WWAN } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87bab2b11ba5e1fb585d5c88cf831b36e257c148 Gerrit-Change-Number: 46101 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45735 ) Change subject: sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax ...................................................................... sb/intel/i82801ix/acpi: Convert to ASL 2.0 syntax Change-Id: I198f8df954f423ca5e19a7ee740ab062108ad14b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/usb.asl 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45735/1 diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 25a756e..11595d2 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -174,7 +174,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -183,7 +183,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1|= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801ix/acpi/usb.asl b/src/southbridge/intel/i82801ix/acpi/usb.asl index 55929af..f55ed66 100644 --- a/src/southbridge/intel/i82801ix/acpi/usb.asl +++ b/src/southbridge/intel/i82801ix/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -60,9 +60,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -100,9 +100,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -175,9 +175,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -214,9 +214,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -254,9 +254,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I198f8df954f423ca5e19a7ee740ab062108ad14b Gerrit-Change-Number: 45735 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45734 ) Change subject: sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax ...................................................................... sb/intel/i82801jx/acpi: Convert to ASL 2.0 syntax Change-Id: I93becba4cbb43625096c631b4a013d3db3fbff67 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/usb.asl 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45734/1 diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index e62f8a1..b4b7f83 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -175,7 +175,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -184,7 +184,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1|= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl index 55929af..f55ed66 100644 --- a/src/southbridge/intel/i82801jx/acpi/usb.asl +++ b/src/southbridge/intel/i82801jx/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -60,9 +60,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -100,9 +100,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -175,9 +175,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -214,9 +214,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -254,9 +254,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93becba4cbb43625096c631b4a013d3db3fbff67 Gerrit-Change-Number: 45734 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: soc/amd/stoneyridge/acpi.c: Use macros
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46266 ) Change subject: soc/amd/stoneyridge/acpi.c: Use macros ...................................................................... soc/amd/stoneyridge/acpi.c: Use macros Change-Id: I1fa3a22cbf59a13c902beca6f19375c6e6663f4a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46266/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index e62f235..c1c0b2e 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -11,6 +11,7 @@ #include <acpi/acpigen.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <device/device.h> @@ -35,7 +36,7 @@ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24); + CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, IO_APIC_INTERRUPTS); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ @@ -43,8 +44,9 @@ /* 5 mean: 0101 --> Edge-triggered, Active high */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xf); + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *)current, 0, 9, 9, + MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, @@ -89,15 +91,15 @@ fadt->century = 0; /* 0x7f to make rtc alarm work */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON; + fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa3a22cbf59a13c902beca6f19375c6e6663f4a Gerrit-Change-Number: 46266 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: util/cbfstool: Introduce concept of mmap_window
by Furquan Shaikh (Code Review) 13 Feb '21

13 Feb '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47831 ) Change subject: util/cbfstool: Introduce concept of mmap_window ...................................................................... util/cbfstool: Introduce concept of mmap_window This change adds the concept of mmap_window to describe how the SPI flash address space is mapped to host address space. It gets rid of the assumption that the SPI flash address space is mapped only below the 4G boundary in host space. This is required in follow up changes to be able to add more decode windows for the SPI flash into the host address space. Currently, a single mmap window is added i.e. the default x86 decode window of maximum 16MiB size living just below the 4G boundary. Change-Id: I8dd3d1c922cc834c1e67f279ffce8fa438d8209c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M util/cbfstool/cbfstool.c 1 file changed, 125 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47831/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 061ff82..08d3cd0 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -17,6 +17,7 @@ #include <commonlib/fsp.h> #include <commonlib/endian.h> #include <commonlib/helpers.h> +#include <commonlib/region.h> #define SECTION_WITH_FIT_TABLE "BOOTBLOCK" @@ -107,18 +108,130 @@ CBFS_FILE_MAGIC, strlen(CBFS_FILE_MAGIC)); } -/* - * Converts between offsets from the start of the specified image region and - * "top-aligned" offsets from the top of the entire boot media. - */ -static unsigned convert_to_from_absolute_top_aligned( - const struct buffer *region, unsigned offset) +/* This describes a window from the SPI flash address space into the host address space. */ +struct mmap_window { + struct region flash_space; + struct region host_space; +}; + +enum mmap_window_type { + X86_DEFAULT_DECODE_WINDOW, /* Decode window just below 4G boundary */ + MMAP_MAX_WINDOWS, +}; + +/* Table of all the decode windows supported by the platform. */ +static struct mmap_window mmap_window_table[MMAP_MAX_WINDOWS]; + +static void add_mmap_window(enum mmap_window_type idx, size_t flash_offset, size_t host_offset, + size_t window_size) +{ + if (idx >= MMAP_MAX_WINDOWS) { + ERROR("Incorrect mmap window index(%d)\n", idx); + return; + } + + mmap_window_table[idx].flash_space.offset = flash_offset; + mmap_window_table[idx].host_space.offset = host_offset; + mmap_window_table[idx].flash_space.size = window_size; + mmap_window_table[idx].host_space.size = window_size; +} + +static void create_mmap_windows(void) +{ + static bool done; + + if (done) + return; + + const size_t image_size = partitioned_file_total_size(param.image_file); + const size_t window_size = MIN(16 * MiB, image_size); + + /* + * Default decode window lives just below 4G boundary in host space and maps upto a + * maximum of 16MiB. + */ + add_mmap_window(X86_DEFAULT_DECODE_WINDOW, image_size - window_size, + 4ULL * GiB - window_size, window_size); + + done = true; +} + +static unsigned convert_address(const struct region *to, const struct region *from, + unsigned addr) +{ + /* + * Calculate the offset in the "from" region and use that offset to calculate + * corresponding address in the "to" region. + */ + size_t offset = addr - region_offset(from); + return region_offset(to) + offset; +} + +static int find_mmap_window(size_t struct_offset, unsigned addr) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(mmap_window_table); i++) { + const struct region *reg; + reg = (struct region *)((char *)&mmap_window_table[i] + struct_offset); + if (region_offset(reg) <= addr && region_end(reg) >= addr) + return i; + } + + return -1; +} + +static unsigned convert_host_to_flash(const struct buffer *region, unsigned addr) +{ + int idx; + const struct region *to, *from; + + idx = find_mmap_window(offsetof(struct mmap_window, host_space), addr); + if (idx == -1) { + ERROR("Host address(%x) not in any mmap window!\n", addr); + return 0; + } + + to = &mmap_window_table[idx].flash_space; + from = &mmap_window_table[idx].host_space; + + /* region->offset is subtracted because caller expects offset in the given region. */ + return convert_address(to, from, addr) - region->offset; +} + +static unsigned convert_flash_to_host(const struct buffer *region, unsigned addr) +{ + int idx; + const struct region *to, *from; + + /* + * region->offset is added because caller provides offset in the given region. This is + * converted to an absolute address in the SPI flash space. + */ + addr += region->offset; + idx = find_mmap_window(offsetof(struct mmap_window, flash_space), addr); + + if (idx == -1) { + ERROR("SPI flash address(%x) not in any mmap window!\n", addr); + return 0; + } + + to = &mmap_window_table[idx].host_space; + from = &mmap_window_table[idx].flash_space; + + return convert_address(to, from, addr); +} + +static unsigned convert_addr_space(const struct buffer *region, unsigned addr) { assert(region); - size_t image_size = partitioned_file_total_size(param.image_file); + create_mmap_windows(); - return image_size - region->offset - offset; + if (IS_HOST_SPACE_ADDRESS(addr)) + return convert_host_to_flash(region, addr); + else + return convert_flash_to_host(region, addr); } /* @@ -564,8 +677,8 @@ } if (IS_HOST_SPACE_ADDRESS(offset)) - offset = convert_to_from_absolute_top_aligned(param.image_region, - -offset); + offset = convert_addr_space(param.image_region, offset); + if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); free(header); @@ -647,8 +760,7 @@ */ if (param.stage_xip) { if (!IS_HOST_SPACE_ADDRESS(address)) - address = -convert_to_from_absolute_top_aligned( - param.image_region, address); + address = convert_addr_space(param.image_region, address); } else { if (param.baseaddress_assigned == 0) { INFO("Honoring pre-linked FSP module.\n"); @@ -721,9 +833,7 @@ * x86 semantics about the boot media being directly mapped * below 4GiB in the CPU address space. **/ - address = -convert_to_from_absolute_top_aligned( - param.image_region, address); - *offset = address; + *offset = convert_addr_space(param.image_region, address); ret = parse_elf_to_xip_stage(buffer, &output, offset, param.ignore_section); -- To view, visit https://review.coreboot.org/c/coreboot/+/47831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd3d1c922cc834c1e67f279ffce8fa438d8209c Gerrit-Change-Number: 47831 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

10 27

Change in coreboot[master]: trogdor: fix EC/SPI communication after qclib
by mturney mturney (Code Review) 12 Feb '21

12 Feb '21

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37482 ) Change subject: trogdor: fix EC/SPI communication after qclib ...................................................................... trogdor: fix EC/SPI communication after qclib Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/37482/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 8849911..6b79004 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -20,6 +20,8 @@ #include <timestamp.h> #include <soc/usb.h> #include <soc/qupv3_fw_config.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, @@ -36,6 +38,9 @@ { setup_usb(); qupv3_fw_init(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ + qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ + } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36ff5f81adb495ad762ce74e224add03520260d Gerrit-Change-Number: 37482 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: [WIP] mainboard: Add MSI H81M-P33
by Angel Pons (Code Review) 12 Feb '21

12 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41260 ) Change subject: [WIP] mainboard: Add MSI H81M-P33 ...................................................................... [WIP] mainboard: Add MSI H81M-P33 Untested and missing SuperIO support. (NCT5532D) Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xc563, rev=0x00 Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/msi/h81m-p33/Kconfig A src/mainboard/msi/h81m-p33/Kconfig.name A src/mainboard/msi/h81m-p33/Makefile.inc A src/mainboard/msi/h81m-p33/acpi/ec.asl A src/mainboard/msi/h81m-p33/acpi/platform.asl A src/mainboard/msi/h81m-p33/acpi/superio.asl A src/mainboard/msi/h81m-p33/acpi_tables.c A src/mainboard/msi/h81m-p33/board_info.txt A src/mainboard/msi/h81m-p33/devicetree.cb A src/mainboard/msi/h81m-p33/dsdt.asl A src/mainboard/msi/h81m-p33/gma-mainboard.ads A src/mainboard/msi/h81m-p33/gpio.c A src/mainboard/msi/h81m-p33/hda_verb.c A src/mainboard/msi/h81m-p33/romstage.c 14 files changed, 470 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/41260/1 diff --git a/src/mainboard/msi/h81m-p33/Kconfig b/src/mainboard/msi/h81m-p33/Kconfig new file mode 100644 index 0000000..d8ad2b0 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_MSI_H81M_P33 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + +config MAINBOARD_DIR + string + default msi/h81m-p33 + +config MAINBOARD_PART_NUMBER + string + default "H81M-P33" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/msi/h81m-p33/Kconfig.name b/src/mainboard/msi/h81m-p33/Kconfig.name new file mode 100644 index 0000000..ac4bd28 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_H81M_P33 + bool "H81M-P33 (MS-7817 v1.2)" diff --git a/src/mainboard/msi/h81m-p33/Makefile.inc b/src/mainboard/msi/h81m-p33/Makefile.inc new file mode 100644 index 0000000..ea035d3 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/msi/h81m-p33/acpi/ec.asl b/src/mainboard/msi/h81m-p33/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/ec.asl diff --git a/src/mainboard/msi/h81m-p33/acpi/platform.asl b/src/mainboard/msi/h81m-p33/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/msi/h81m-p33/acpi/superio.asl b/src/mainboard/msi/h81m-p33/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi/superio.asl diff --git a/src/mainboard/msi/h81m-p33/acpi_tables.c b/src/mainboard/msi/h81m-p33/acpi_tables.c new file mode 100644 index 0000000..f00b3e7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/acpi_tables.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/msi/h81m-p33/board_info.txt b/src/mainboard/msi/h81m-p33/board_info.txt new file mode 100644 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb new file mode 100644 index 0000000..98f4104 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -0,0 +1,67 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1462 0x7817 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x001c0a01" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x85" + register "pirqh_routing" = "0x8b" + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: PCIe x1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on end # RP #3: RTL8111 GbE NIC + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + # FIXME: SuperIO + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/msi/h81m-p33/dsdt.asl b/src/mainboard/msi/h81m-p33/dsdt.asl new file mode 100644 index 0000000..f2a3003 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/h81m-p33/gma-mainboard.ads b/src/mainboard/msi/h81m-p33/gma-mainboard.ads new file mode 100644 index 0000000..8483695 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- FIXME: Only one is actually HDMI + HDMI2, + HDMI3, + Analog, -- VGA + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/msi/h81m-p33/gpio.c b/src/mainboard/msi/h81m-p33/gpio.c new file mode 100644 index 0000000..6553f42 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/gpio.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c new file mode 100644 index 0000000..23e64b7 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1462d817, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1462d817), + AZALIA_PIN_CFG(0, 0x11, 0x4037c040), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025c603), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c new file mode 100644 index 0000000..1fc56e1 --- /dev/null +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .gbe_enable = 0, /* FIXME: check this */ + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235 Gerrit-Change-Number: 41260 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices
by Angel Pons (Code Review) 11 Feb '21

11 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46972 ) Change subject: soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices ...................................................................... soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices SerialIO is in ACPI mode for google/auron and intel/wtm2, and is disabled for google/jecht and purism/librem_bdw. Since Broadwell SerialIO is never used in PCI mode, _ADR can safely be dropped. Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46972/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 35b15b4..2bacd2b 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -122,7 +122,6 @@ // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -168,7 +167,6 @@ Return ("INT33C2") } Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +243,6 @@ Return ("INT33C3") } Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -322,7 +319,6 @@ Return ("INT33C0") } Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -384,7 +380,6 @@ Return ("INT33C1") } Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -458,7 +453,6 @@ Return ("INT33C4") } Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -532,7 +526,6 @@ Return ("INT33C5") } Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -595,7 +588,6 @@ } Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/46972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e Gerrit-Change-Number: 46972 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45526 ) Change subject: soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros ...................................................................... soc/amd/{picasso,stoneyridge}/romstage.c: Use post_codes macros Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45526/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b967431..09fc987 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -145,7 +145,7 @@ { int s3_resume; - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); console_init(); post_code(0x41); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103ef..0940569 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -69,7 +69,7 @@ bsp_agesa_call(); if (!s3_resume) { - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); do_agesawrapper(AMD_INIT_POST, "amdinitpost"); post_code(0x41); @@ -102,7 +102,7 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_ENABLING_CACHE); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); post_code(0x61); -- To view, visit https://review.coreboot.org/c/coreboot/+/45526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51782996602a4ae17058e6ff85d4e05f751a2bfd Gerrit-Change-Number: 45526 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/skylake: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46242 ) Change subject: soc/intel/skylake: Convert to ASL 2.0 syntax ...................................................................... soc/intel/skylake: Convert to ASL 2.0 syntax Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/xhci.asl 11 files changed, 134 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46242/1 diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl index fca9590..97c8355 100644 --- a/src/soc/intel/skylake/acpi/dptf/charger.asl +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -26,11 +26,11 @@ Method (PPPC) { /* Convert size of PPSS table to index */ - Store (SizeOf (\_SB.CHPS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CHPS) + Local0-- /* Check if charging is disabled (AC removed) */ - If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + If (\_SB.PCI0.LPCB.EC0.ACEX == 0) { /* Return last power state */ Return (Local0) } Else { @@ -45,8 +45,7 @@ Method (SPPC, 1) { /* Retrieve Control (index 4) for specified PPSS level */ - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CHPS [ToInteger (Arg0)]) [4]) /* Pass Control value to EC to limit charging */ \_SB.PCI0.LPCB.EC0.CHGS (Local0) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 9931f6c..181b01a 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -17,7 +17,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -35,7 +35,7 @@ Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -60,8 +60,8 @@ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._PSS) + Local0-- Return (Local0) } Else { Return (0) diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 8852e0a..e72437a 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -24,7 +24,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -41,7 +41,7 @@ Method (_OSC, 4, Serialized) { /* Check for Passive Policy UUID */ - If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + If (DeRefOf (IDSP [0]) == Arg0) { /* Initialize Thermal Devices */ ^TINI () @@ -73,10 +73,10 @@ /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl index 6d60c63..eb75ba9 100644 --- a/src/soc/intel/skylake/acpi/dptf/fan.asl +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -32,19 +32,19 @@ Method (_FST, 0, Serialized,,PkgObj) { /* Fill in TFST with current control. */ - Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + TFST [1] = \_SB.PCI0.LPCB.EC0.FAND Return (TFST) } /* _FSL: Fan Speed Level */ Method (_FSL, 1, Serialized) { - Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND) + \_SB.PCI0.LPCB.EC0.FAND = Arg0 } Method (_STA) { - If (LEqual (\DPTE, One)) + If (\DPTE == 1) { Return (0xF) } Else { diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 3aead2b..95912a4 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -8,22 +8,22 @@ { #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR0_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR1_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR2_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } #endif #ifdef DPTF_TSR3_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR3_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR3_SENSOR_ID) { Notify (^TSR3, 0x90) } #endif @@ -78,7 +78,7 @@ Method (DTRP, 2, Serialized) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.RCDP)) { - If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) { + If (\_SB.PCI0.LPCB.EC0.RCDP == 1) { Return (CTOK (Arg0)) } } @@ -106,7 +106,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -215,7 +215,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -312,7 +312,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -376,7 +376,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index abcde94..de1c026 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -66,23 +66,23 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) + \S3U0 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) + \S3U0 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) + \S5U0 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) + \S5U0 = 0 } diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index da82523..31fea42 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -10,9 +10,8 @@ * https://bugs.acpica.org/show_bug.cgi?id=1201 */ OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) + PCR_ITSS_PIRQA_ROUT + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), + 8) Field (ITSS, ByteAcc, NoLock, Preserve) { PIRA, 8, /* PIRQA Routing Control */ @@ -46,10 +45,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRA & ^^IREM) Return (RTLA) } @@ -58,13 +57,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRA) + Local0-- + ^^PIRA = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRA, ^^IREN)) { + If (^^PIRA & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -73,7 +72,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRA, ^^IREN, ^^PIRA) + ^^PIRA |= ^^IREN } } @@ -95,10 +94,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRB & ^^IREM) Return (RTLA) } @@ -107,13 +106,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRB) + Local0-- + ^^PIRB = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRB, ^^IREN)) { + If (^^PIRB & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -122,7 +121,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRB, ^^IREN, ^^PIRB) + ^^PIRB |= ^^IREN } } @@ -144,10 +143,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRC & ^^IREM) Return (RTLA) } @@ -156,13 +155,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRC) + Local0-- + ^^PIRC = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRC, ^^IREN)) { + If (^^PIRC & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -171,7 +170,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRC, ^^IREN, ^^PIRC) + ^^PIRC |= ^^IREN } } @@ -193,10 +192,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRD & ^^IREM) Return (RTLA) } @@ -205,13 +204,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRD) + Local0-- + ^^PIRD = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRD, ^^IREN)) { + If (^^PIRD & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -220,7 +219,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRD, ^^IREN, ^^PIRD) + ^^PIRD |= ^^IREN } } @@ -242,10 +241,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRE & ^^IREM) Return (RTLA) } @@ -254,13 +253,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRE) + Local0-- + ^^PIRE = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRE, ^^IREN)) { + If (^^PIRE & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -269,7 +268,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRE, ^^IREN, ^^PIRE) + ^^PIRE |= ^^IREN } } @@ -291,10 +290,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRF & ^^IREM) Return (RTLA) } @@ -303,13 +302,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRF) + Local0-- + ^^PIRF = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRF, ^^IREN)) { + If (^^PIRF & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -318,7 +317,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRF, ^^IREN, ^^PIRF) + ^^PIRF |= ^^IREN } } @@ -340,10 +339,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRG & ^^IREM) Return (RTLA) } @@ -352,13 +351,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRG) + Local0-- + ^^PIRG = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRG, ^^IREN)) { + If (^^PIRG & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -367,7 +366,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRG, ^^IREN, ^^PIRG) + ^^PIRG |= ^^IREN } } @@ -389,10 +388,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRH & ^^IREM) Return (RTLA) } @@ -401,13 +400,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRH) + Local0-- + ^^PIRH = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRH, ^^IREN)) { + If (^^PIRH & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -416,6 +415,6 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRH, ^^IREN, ^^PIRH) + ^^PIRH |= ^^IREN } } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 6eea5bb..e088ca1 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -47,7 +47,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -56,7 +56,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/soc/intel/skylake/acpi/pch_hda.asl b/src/soc/intel/skylake/acpi/pch_hda.asl index 04e974f..3de64b7 100644 --- a/src/soc/intel/skylake/acpi/pch_hda.asl +++ b/src/soc/intel/skylake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 356a7e0..2b88706 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -27,13 +27,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delay in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -41,7 +41,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -64,7 +64,7 @@ Method (_PS0, 0, Serialized) { /* Disable Power Gate */ - Store (0, ^PGEN) + ^PGEN = 0 /* Clear bits 31, 6, 2, 0 */ ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA) @@ -74,18 +74,18 @@ ^^PCRO (PID_SCS, 0x600, 0x80000045) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method (_PS3, 0, Serialized) { /* Enable Power Gate */ - Store (1, ^PGEN) + ^PGEN = 1 /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR } Device (CARD) @@ -126,7 +126,7 @@ ^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF) /* Disable Power Gate */ - Store (0, ^PGEN) + ^PGEN = 0 /* Clear bits 8, 7, 2, 0 */ ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) @@ -136,18 +136,18 @@ ^^PCRO (PID_SCS, 0x600, 0x00000185) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method (_PS3, 0, Serialized) { /* Enable Power Gate */ - Store (1, ^PGEN) + ^PGEN = 1 /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR /* Enable 20K pull-down on CLK, CMD and DAT lines */ ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 2f5d8b2..b891b2f 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -118,37 +118,37 @@ Method (_PS0, 0, Serialized) { - If (!LEqual (^DVID, 0xFFFF)) { - If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^DVID != 0xFFFF) { + If (!((^XMEM == 0xFFFF) || (^XMEM == 0x0000))) { /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + ^D3HE = 0 + ^STGE = 0 /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + If (^D0D3 == 3) { + Local0 = 0 + ^D0D3 = Local0 + Local0 = ^D0D3 } /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) + ^UPSW = 0 /* * Apply USB2 PHPY Power Gating workaround if needed. */ If (^^PMC.UWAB) { /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) + ^^PMC.MPMC = 1 /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) + Local0 = 10 While (^^PMC.PMFS) { - If (LNot (Local0)) { + If (!Local0) { Break } - Decrement (Local0) + Local0-- Sleep (10) } } @@ -158,33 +158,33 @@ Method (_PS3, 0, Serialized) { - If (!LEqual (^DVID, 0xFFFF)) { - If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^DVID != 0xFFFF) { + If (!((^XMEM == 0xFFFF) || (^XMEM == 0x0000))) { /* Clear PME Status */ - Store (1, ^PMES) + ^PMES = 1 /* Enable PME */ - Store (1, ^PMEE) + ^PMEE= 1 /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + If (^D0D3 == 3) { + Local0 = 0 + ^D0D3 = Local0 + Local0 = ^D0D3 } /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) + ^UPSW = 3 /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) + ^D3HE = 1 + ^STGE = 1 /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + Local0 = 3 + ^D0D3 = Local0 + Local0 = ^D0D3 /* * Apply USB2 PHPY Power Gating workaround if needed. @@ -193,15 +193,15 @@ */ If (^^PMC.UWAB) { /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) + ^^PMC.MPMC = 3 /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) + Local0 = 10 While (^^PMC.PMFS) { - If (LNot (Local0)) { + If (!Local0) { Break } - Decrement (Local0) + Local0-- Sleep (10) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Gerrit-Change-Number: 46242 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020