coreboot-gerrit November 2020

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Change in coreboot[master]: nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46281 ) Change subject: nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: If8f30f558c422d1168efd218759a406b26338ef5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/finalize.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 3 files changed, 103 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46281/1 diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 88bc98d..6b91965 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -4,13 +4,13 @@ void intel_ironlake_finalize_smm(void) { - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + mchbar32_or(0x5500, 1 << 0); /* PAVP */ + mchbar32_or(0x5f00, 1 << 31); /* SA PM */ + mchbar32_or(0x6020, 1 << 0); /* UMA GFX */ + mchbar32_or(0x63fc, 1 << 0); /* VTDTRK */ + mchbar32_or(0x6800, 1 << 31); + mchbar32_or(0x7000, 1 << 31); + mchbar32_or(0x77fc, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(0x50fc) = 0x8f; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index b9e5322..4d30500 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -98,19 +98,6 @@ #define MSAC 0x62 /* Multi Size Aperture Control */ /* - * MCHBAR - */ - -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -/* * EPBAR - Egress Port Root Complex Register Block */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 05323f1..fe20c8c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -323,10 +323,10 @@ MCHBAR8(0x5ff) = 0x0; MCHBAR8(0x5ff) = 0x80; MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; - MCHBAR8_OR(0x580 + (channel << 10), 1); + mchbar8_or(0x580 + (channel << 10), 1); while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) ; - MCHBAR8_AND(0x580 + (channel << 10), ~1); + mchbar8_unset(0x580 + (channel << 10), 1); return ret; } @@ -478,7 +478,7 @@ } } - MCHBAR32_OR(0x130, 1); + mchbar32_or(0x130, 1); while (MCHBAR8(0x130) & 1) ; } @@ -1235,7 +1235,7 @@ if (MCHBAR8(0x2ca9) & 1) some_delay_3_half_cycles = 3; for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); + mchbar32_or(0x220 + (channel << 10), 0x18001117); MCHBAR32(0x224 + (channel << 10)) = (info->max_slots_used_in_channel - 1) | ((info->cas_latency - 5 - info->clock_speed_index) @@ -1258,7 +1258,7 @@ MCHBAR8(0x267 + (channel << 10)) = 0x4; MCHBAR16(0x272 + (channel << 10)) = 0x155; - MCHBAR32_AND_OR(0x2bc + (channel << 10), 0xFF000000, 0x707070); + mchbar32_unset_and_set(0x2bc + (channel << 10), 0x00ffffff, 0x707070); write_500(info, channel, ((!info->populated_ranks[channel][1][1]) @@ -1332,8 +1332,8 @@ MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; - MCHBAR16_OR(0x612, 0x100); - MCHBAR16_OR(0x214, 0x3E00); + mchbar16_or(0x612, 0x100); + mchbar16_or(0x214, 0x3E00); for (i = 0; i < 8; i++) { pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); @@ -2227,7 +2227,7 @@ write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); failmask = check_testing(info, total_rank, 0); - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3); } @@ -2292,7 +2292,7 @@ check_testing_type2(info, total_rank, 3, i, 1); } - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -2393,7 +2393,7 @@ 1); } - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -3520,8 +3520,8 @@ 2 * info->cas_latency - 7 + 11); delay_d_ps += info->revision >= 8 ? 2758 : 4428; - MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000); - MCHBAR32_AND_OR(0x138, 0xfaffffff, 0x2000000); + mchbar32_unset_and_set(0x140, 0x05000000, 0x2000000); + mchbar32_unset_and_set(0x138, 0x05000000, 0x2000000); if ((MCHBAR8(0x144) & 0x1f) > 0x13) delay_d_ps += 650; delay_c_ps = delay_d_ps + 1800; @@ -3580,9 +3580,9 @@ info->training.reg274265[channel][2] << 8; } if (info->training.reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); } static void restore_274265(struct raminfo *info) @@ -3597,9 +3597,9 @@ info->cached_training->reg274265[channel][2] << 8; } if (info->cached_training->reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); } static void dmi_setup(void) @@ -3607,7 +3607,7 @@ gav(DMIBAR8(0x254)); DMIBAR8(0x254) = 0x1; DMIBAR16(0x1b8) = 0x18f2; - MCHBAR16_AND_OR(0x48, 0, 0x2); + mchbar16_unset_and_set(0x48, 0xffff, 0x2); DMIBAR32(0xd68) |= 0x08000000; @@ -3634,7 +3634,7 @@ MCHBAR16(0x1170) = 0xa880; MCHBAR8(0x11c1) = 0x1; MCHBAR16(0x1170) = 0xb880; - MCHBAR8_AND_OR(0x1210, 0, 0x84); + mchbar8_unset_and_set(0x1210, 0xff, 0x84); if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { /* 0 for 32MB */ @@ -3651,9 +3651,9 @@ if (deven & 8) { MCHBAR8(0x2c30) = 0x20; pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18 - MCHBAR16_OR(0x2c30, 0x200); + mchbar16_or(0x2c30, 0x200); MCHBAR16(0x2c32) = 0x434; - MCHBAR32_AND_OR(0x2c44, 0, 0x1053687); + mchbar32_unset_and_set(0x2c44, 0xffffffff, 0x1053687); pci_read_config8(GMA, MSAC); // = 0x2 pci_write_config8(GMA, MSAC, 0x2); read8(DEFAULT_RCBA + 0x2318); @@ -3662,7 +3662,7 @@ write8(DEFAULT_RCBA + 0x2320, 0xfc); } - MCHBAR32_AND_OR(0x30, 0, 0x40); + mchbar32_unset_and_set(0x30, 0xffffffff, 0x40); pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); @@ -3815,7 +3815,7 @@ /* after SPD */ timestamp_add_now(102); - MCHBAR8_AND(0x2ca8, 0xfc); + mchbar8_unset(0x2ca8, 3); collect_system_info(&info); calculate_timings(&info); @@ -3851,9 +3851,9 @@ MCHBAR16(0x2c20) = 0x10; } - MCHBAR32_OR(0x18b4, 0x210000); - MCHBAR32_OR(0x1890, 0x2000000); - MCHBAR32_OR(0x18b4, 0x8000); + mchbar32_or(0x18b4, 0x210000); + mchbar32_or(0x1890, 0x2000000); + mchbar32_or(0x18b4, 0x8000); gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!! pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12); @@ -3861,10 +3861,10 @@ gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; gav(MCHBAR16(0x2c10)); - MCHBAR16_OR(0x2c12, 0x100); + mchbar16_or(0x2c12, 0x100); gav(MCHBAR8(0x2ca8)); // !!!! - MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); + mchbar32_unset_and_set(0x1804, 0x00000003, 0x8400080); pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0); @@ -3872,7 +3872,7 @@ gav(MCHBAR32(0x1804)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); + mchbar8_or(0x2ca8, 1); } MCHBAR32(0x18d8) = 0x120000; @@ -3894,13 +3894,13 @@ gav(MCHBAR32(0x18dc)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } MCHBAR32(0x188c) = 0x20bc09; pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; - MCHBAR32_OR(0x18b8, 0x200); + mchbar32_or(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! MCHBAR32(0x1918) = 0x332; @@ -3910,17 +3910,17 @@ MCHBAR32(0x182c) = 0x10202; gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202); - MCHBAR32_AND(0x1a1c, 0x8fffffff); - MCHBAR32_OR(0x1a70, 0x100000); + mchbar32_unset(0x1a1c, 0x70000000); + mchbar32_or(0x1a70, 0x100000); - MCHBAR32_AND(0x18b4, 0xffff7fff); + mchbar32_unset(0x18b4, 0x00008000); gav(MCHBAR32(0x1a68)); // !!!! MCHBAR32(0x1a68) = 0x343800; gav(MCHBAR32(0x1e68)); // !!!! gav(MCHBAR32(0x1a68)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! @@ -3936,7 +3936,7 @@ gav(MCHBAR32(0x1af0)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } gav(MCHBAR32(0x1890)); // !!!! @@ -3974,14 +3974,14 @@ set_2dxx_series(&info, s3resume); if (!(deven & 8)) { - MCHBAR32_AND_OR(0x2cb0, 0, 0x40); + mchbar32_unset_and_set(0x2cb0, 0xffffffff, 0x40); } udelay(1000); if (deven & 8) { - MCHBAR32_OR(0xff8, 0x1800); - MCHBAR32_AND(0x2cb0, 0x00); + mchbar32_or(0xff8, 0x1800); + mchbar32_unset(0x2cb0, 0xffffffff); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); @@ -4040,11 +4040,11 @@ MCHBAR16(0x11c0) = 0xc40b; MCHBAR16(0x11c2) = 0x303; MCHBAR16(0x11c4) = 0x301; - MCHBAR32_AND_OR(0x1190, 0, 0x8900080a); + mchbar32_unset_and_set(0x1190, 0xffffffff, 0x8900080a); MCHBAR32(0x11b8) = 0x70c3000; MCHBAR8(0x11ec) = 0xa; MCHBAR16(0x1100) = 0x800; - MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800); + mchbar32_unset_and_set(0x11bc, 0xffffffff, 0x1e84800); MCHBAR16(0x11ca) = 0xfa; MCHBAR32(0x11e4) = 0x4e20; MCHBAR8(0x11bc) = 0xf; @@ -4078,8 +4078,8 @@ if ((deven & 8) && x2ca8 == 0) { MCHBAR16(0x1214) = 0x320; MCHBAR32(0x1600) = 0x40000000; - MCHBAR32_AND_OR(0x11f4, 0, 0x10000000); - MCHBAR16_AND_OR(0x1230, 0, 0x8000); + mchbar32_unset_and_set(0x11f4, 0xffffffff, 0x10000000); + mchbar16_unset_and_set(0x1230, 0xffff, 0x8000); MCHBAR32(0x1400) = 0x13040020; MCHBAR32(0x1404) = 0xe090120; MCHBAR32(0x1408) = 0x5120220; @@ -4176,14 +4176,14 @@ MCHBAR16(0x1220) = 0x1388; } - MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x1053688); // !!!! MCHBAR32(0x1c04); // !!!! MCHBAR32(0x1804) = 0x406080; MCHBAR8(0x2ca8); if (x2ca8 == 0) { - MCHBAR8_AND(0x2ca8, ~3); + mchbar8_unset(0x2ca8, 3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? /* This issues a CPU reset without resetting the platform */ printk(BIOS_DEBUG, "Issuing a CPU reset\n"); @@ -4192,12 +4192,12 @@ if (s3resume) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (SLP_TYP_S3 << 10)); - MCHBAR32_OR(0x1af0, 0x10); + mchbar32_or(0x1af0, 0x10); halt(); } MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); - MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x53688); // !!!! pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! @@ -4214,8 +4214,8 @@ MCHBAR16(0x616) = 0x26a; MCHBAR32(0x134) = 0x856000; MCHBAR32(0x160) = 0x5ffffff; - MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! - MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! + mchbar32_unset_and_set(0x114, 0xffffffff, 0xc2024440); // !!!! + mchbar32_unset_and_set(0x118, 0xffffffff, 0x4); // !!!! for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20); @@ -4256,7 +4256,7 @@ program_base_timings(&info); - MCHBAR8_OR(0x5ff, 0x80); + mchbar8_or(0x5ff, 0x80); write_1d0(0x2, 0x1d5, 2, 1); write_1d0(0x20, 0x166, 7, 1); @@ -4304,9 +4304,9 @@ write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); } - MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! + mchbar32_unset_and_set(0x1f4, 0xffffffff, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; - MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! + mchbar8_unset_and_set(0x1f0, 0xff, 0x1); // !!!! MCHBAR8(0x1f0); // !!!! program_board_delay(&info); @@ -4315,7 +4315,7 @@ MCHBAR8(0x5ff) = 0x80; MCHBAR8(0x5f4) = 0x1; - MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? + mchbar32_unset(0x130, 2); // | 2 when ? while (MCHBAR32(0x130) & 1) ; gav(read_1d0(0x14b, 7)); // = 0x81023100 @@ -4335,10 +4335,10 @@ write_1d0(0, 0xae, 6, 1); read_1d0(0x300, 4); // = 0x48088080 // !!!! write_1d0(0, 0x300, 6, 1); - MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!! - MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!! - MCHBAR32_AND(0x140, ~0x07000000); - MCHBAR32_AND(0x138, ~0x07000000); + mchbar16_unset_and_set(0x356, 0xffff, 0x1040); // !!!! + mchbar16_unset_and_set(0x756, 0xffff, 0x1040); // !!!! + mchbar32_unset(0x140, 0x07000000); + mchbar32_unset(0x138, 0x07000000); MCHBAR32(0x130) = 0x31111301; /* Wait until REG130b0 is 1. */ while (MCHBAR32(0x130) & 1) @@ -4404,13 +4404,13 @@ 1); write_500(&info, channel, 0x3, 0x69b, 2, 1); } - MCHBAR32_AND_OR(0x2d0, 0xff2c01ff, 0x200000); + mchbar32_unset_and_set(0x2d0, 0x00d3fe00, 0x200000); MCHBAR16(0x6c0) = 0x14a0; - MCHBAR32_AND_OR(0x6d0, 0xff0080ff, 0x8000); + mchbar32_unset_and_set(0x6d0, 0x00ff7f00, 0x8000); MCHBAR16(0x232) = 0x8; /* 0x40004 or 0 depending on ? */ - MCHBAR32_AND_OR(0x234, 0xfffbfffb, 0x40004); - MCHBAR32_AND_OR(0x34, 0xfffffffd, 5); + mchbar32_unset_and_set(0x234, 0x00040004, 0x40004); + mchbar32_unset_and_set(0x34, 0x00000002, 5); MCHBAR32(0x128) = 0x2150d05; MCHBAR8(0x12c) = 0x1f; MCHBAR8(0x12d) = 0x56; @@ -4422,10 +4422,10 @@ for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; - MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); - MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); + mchbar32_unset_and_set(0x134, 0x03fe0000, 0x10000); + mchbar32_unset_and_set(0x134, 0x037a0000, 0x850000); for (channel = 0; channel < NUM_CHANNELS; channel++) - MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | + mchbar32_unset_and_set(0x400*ch + 0x598, 0x18c00000, 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20)); if (!s3resume) @@ -4443,8 +4443,8 @@ MCHBAR8(0x12c) = 0x9f; - MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!! - MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! + mchbar8_unset_and_set(0x271, 0xff, 0xe); // 2 // !!!! + mchbar8_unset_and_set(0x671, 0xff, 0xe); // !!!! if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -4455,7 +4455,7 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!! { u8 a, b; @@ -4492,7 +4492,7 @@ pci_write_config16(NORTHBRIDGE, 0xc8, 3); write_26c(0, 0x820); write_26c(1, 0x820); - MCHBAR32_OR(0x130, 2); + mchbar32_or(0x130, 2); /* end */ if (s3resume) { @@ -4504,10 +4504,10 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!! } - MCHBAR32_AND(0xfa4, ~0x01000002); + mchbar32_unset(0xfa4, 0x01000002); MCHBAR32(0xfb0) = 0x2000e019; /* Before training. */ @@ -4533,20 +4533,20 @@ else MCHBAR8(0x111) = 0x20 | (3 << 2) | (1 << 6) | (0 << 7); - MCHBAR32_AND(0xfac, ~0x80000000); + mchbar32_unset(0xfac, 0x80000000); MCHBAR32(0xfb4) = 0x4800; MCHBAR32(0xfb8) = (info.revision < 8) ? 0x20 : 0x0; MCHBAR32(0xe94) = 0x7ffff; MCHBAR32(0xfc0) = 0x80002040; MCHBAR32(0xfc4) = 0x701246; - MCHBAR8_AND(0xfc8, ~0x70); - MCHBAR32_OR(0xe5c, 0x1000000); - MCHBAR32_AND_OR(0x1a70, ~0x00100000, 0x00200000); + mchbar8_unset(0xfc8, 0x70); + mchbar32_or(0xe5c, 0x1000000); + mchbar32_unset_and_set(0x1a70, 0x00100000, 0x00200000); MCHBAR32(0x50) = 0x700b0; MCHBAR32(0x3c) = 0x10; MCHBAR8(0x1aa8) = (MCHBAR8(0x1aa8) & ~0x35) | 0xa; - MCHBAR8_OR(0xff4, 0x2); - MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020); + mchbar8_or(0xff4, 0x2); + mchbar32_unset_and_set(0xff8, 0xe008, 0x1020); MCHBAR32(0xd00) = IOMMU_BASE2 | 1; MCHBAR32(0xd40) = IOMMU_BASE1 | 1; @@ -4560,28 +4560,28 @@ u32 eax; eax = info.fsb_frequency / 9; - MCHBAR32_AND_OR(0xfcc, 0xfffc0000, + mchbar32_unset_and_set(0xfcc, 0x0003ffff, (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); MCHBAR32(0x20) = 0x33001; } for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); + mchbar32_unset(0x220 + (channel << 10), 0x7770); if (info.max_slots_used_in_channel == 1) - MCHBAR16_OR(0x237 + (channel << 10), 0x0201); + mchbar16_or(0x237 + (channel << 10), 0x0201); else - MCHBAR16_AND(0x237 + (channel << 10), ~0x0201); + mchbar16_unset(0x237 + (channel << 10), 0x0201); - MCHBAR8_OR(0x241 + (channel << 10), 1); + mchbar8_or(0x241 + (channel << 10), 1); if (info.clock_speed_index <= 1 && (info.silicon_revision == 2 || info.silicon_revision == 3)) - MCHBAR32_OR(0x248 + (channel << 10), 0x00102000); + mchbar32_or(0x248 + (channel << 10), 0x00102000); else - MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000); + mchbar32_unset(0x248 + (channel << 10), 0x00102000); } - MCHBAR32_OR(0x115, 0x1000000); + mchbar32_or(0x115, 0x1000000); { u8 al; @@ -4605,7 +4605,7 @@ EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 - MCHBAR8_OR(0x1210, 2); + mchbar8_or(0x1210, 2); MCHBAR32(0x1200) = 0x8800440; MCHBAR32(0x1204) = 0x53ff0453; MCHBAR32(0x1208) = 0x19002043; @@ -4613,10 +4613,10 @@ if (info.revision == 0x10 || info.revision == 0x11) { MCHBAR16(0x1214) = 0x220; - MCHBAR8_OR(0x1210, 0x40); + mchbar8_or(0x1210, 0x40); } - MCHBAR8_OR(0x1214, 0x4); + mchbar8_or(0x1214, 0x4); MCHBAR8(0x120c) = 0x1; MCHBAR8(0x1218) = 0x3; MCHBAR8(0x121a) = 0x3; @@ -4627,13 +4627,13 @@ /* revision dependent here. */ - MCHBAR16_OR(0x1230, 0x1f07); + mchbar16_or(0x1230, 0x1f07); if (info.uma_enabled) - MCHBAR32_OR(0x11f4, 0x10000000); + mchbar32_or(0x11f4, 0x10000000); - MCHBAR16_OR(0x1230, 0x8000); - MCHBAR8_OR(0x1214, 1); + mchbar16_or(0x1230, 0x8000); + mchbar8_or(0x1214, 1); u8 bl, ebpb; u16 reg_1020; @@ -4663,7 +4663,7 @@ MCHBAR8(0x123e) = (MCHBAR8(0x123e) & 0xf) | 0x60; if (reg_1020 != 0) { - MCHBAR32_AND_OR(0x123c, ~0x00900000, 0x600000); + mchbar32_unset_and_set(0x123c, 0x00900000, 0x600000); MCHBAR8(0x101c) = 0xb8; } @@ -4671,20 +4671,20 @@ if (info.uma_enabled) { u16 ax; - MCHBAR32_OR(0x11b0, 0x4000); - MCHBAR32_OR(0x11b4, 0x4000); - MCHBAR16_OR(0x1190, 0x4000); + mchbar32_or(0x11b0, 0x4000); + mchbar32_or(0x11b4, 0x4000); + mchbar16_or(0x1190, 0x4000); ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080; - MCHBAR16_OR(0x1170, 0x1000); + mchbar16_or(0x1170, 0x1000); udelay(1000); u16 ecx; for (ecx = 0xffff; ecx && (MCHBAR16(0x1170) & 0x1000); ecx--) ; - MCHBAR16_AND(0x1190, ~0x4000); + mchbar16_unset(0x1190, 0x4000); } pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, -- To view, visit https://review.coreboot.org/c/coreboot/+/46281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8f30f558c422d1168efd218759a406b26338ef5 Gerrit-Change-Number: 46281 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: nb/intel/pineview: Use new mchbar{8,16,32}_and_or()
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45517 ) Change subject: nb/intel/pineview: Use new mchbar{8,16,32}_and_or() ...................................................................... nb/intel/pineview: Use new mchbar{8,16,32}_and_or() Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/northbridge/intel/common/mchbar_ops.c A src/northbridge/intel/common/mchbar_ops.h M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 6 files changed, 417 insertions(+), 344 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45517/1 diff --git a/src/northbridge/intel/common/mchbar_ops.c b/src/northbridge/intel/common/mchbar_ops.c new file mode 100644 index 0000000..c3fccad --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include "mchbar_ops.h" + +void mchbar8_and_or(int offset, u8 mask, u8 or) +{ + u8 reg8 = MCHBAR8(offset); + + reg8 &= mask; + reg8 |= or; + MCHBAR8(offset) = reg8; +} + +void mchbar16_and_or(int offset, u16 mask, u16 or) +{ + u16 reg16 = MCHBAR32(offset); + + reg16 &= mask; + reg16 |= or; + MCHBAR16(offset) = reg16; +} + +void mchbar32_and_or(int offset, u32 mask, u32 or) +{ + u32 reg32 = MCHBAR32(offset); + + reg32 &= mask; + reg32 |= or; + MCHBAR32(offset) = reg32; +} + +void mchbar8_and(int offset, u8 and) +{ + mchbar8_and_or(offset, and, 0); +} + +void mchbar16_and(int offset, u16 and) +{ + mchbar16_and_or(offset, and, 0); +} + +void mchbar32_and(int offset, u32 and) +{ + mchbar32_and_or(offset, and, 0); +} + +void mchbar8_or(int offset, u8 or) +{ + mchbar8_and_or(offset, 0xff, or); +} + +void mchbar16_or(int offset, u16 or) +{ + mchbar16_and_or(offset, 0xffff, or); +} + +void mchbar32_or(int offset, u32 or) +{ + mchbar32_and_or(offset, 0xffffffff, or); +} diff --git a/src/northbridge/intel/common/mchbar_ops.h b/src/northbridge/intel/common/mchbar_ops.h new file mode 100644 index 0000000..cf39c2b --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MCHBAR_OPS_H +#define MCHBAR_OPS_H + +#include <stdint.h> +#include <northbridge/intel/pineview/memmap.h> + +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +void mchbar8_and_or(int offset, u8 mask, u8 or); +void mchbar16_and_or(int offset, u16 mask, u16 or); +void mchbar32_and_or(int offset, u32 mask, u32 or); +void mchbar8_and(int offset, u8 and); +void mchbar16_and(int offset, u16 and); +void mchbar32_and(int offset, u32 and); +void mchbar8_or(int offset, u8 or); +void mchbar16_or(int offset, u16 or); +void mchbar32_or(int offset, u32 or); + +#endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 08e04f2..4ba902e 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c +romstage-y += ../common/mchbar_ops.c postcar-y += memmap.c diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..ec7c575 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <option.h> @@ -67,10 +68,10 @@ if (config->use_crt) { /* Enable VGA */ - MCHBAR32_OR(DACGIOCTRL1, 1 << 15); + mchbar32_or(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); + mchbar32_and(DACGIOCTRL1, ~(1 << 15)); } if (config->use_lvds) { @@ -79,17 +80,17 @@ reg32 &= ~0xf1000000; reg32 |= 0x90000000; MCHBAR32(LVDSICR2) = reg32; - MCHBAR32_OR(IOCKTRR1, 1 << 9); + mchbar32_or(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32_OR(DACGIOCTRL1, 3 << 25); + mchbar32_or(DACGIOCTRL1, 3 << 25); } MCHBAR32(CICTRL) = 0xc6db8b5f; MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); - MCHBAR32_OR(DACGIOCTRL1, 1 << 5); + mchbar32_and(DACGIOCTRL1, 0xffffff00); + mchbar32_or(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ pci_write_config8(GMCH_IGD, 0xf4, 0x4c); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..121c65b 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -5,6 +5,7 @@ #include <northbridge/intel/pineview/memmap.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/common/mchbar_ops.h> #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 @@ -36,23 +37,8 @@ /* * MCHBAR + *As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ - #include "mchbar_regs.h" /* diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be..b190781 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <delay.h> #include <lib.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "pineview.h" #include "raminit.h" #include <spd.h> @@ -501,7 +502,7 @@ if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32_OR(PMSTS, 1); + mchbar32_or(PMSTS, 1); reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -566,7 +567,7 @@ MCHBAR32(HMCCPEXT) = 0; MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; - MCHBAR32_OR(HMCCMC, 1 << 7); + mchbar32_or(HMCCMC, 1 << 7); if ((fsb_freq == 0) && (ddr_freq == 1)) { MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; @@ -616,8 +617,8 @@ u8 ddr_freq; u16 mpll_ctl; - MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); - MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); + mchbar16_and(CSHRMISCCTL1, (u16)~(1 << 8)); + mchbar8_and(CSHRMISCCTL1, (u8)~0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { ddr_freq = 0; @@ -627,10 +628,10 @@ mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); + mchbar16_and_or(MPLLCTL, (u16)~(0x033f), mpll_ctl); MCHBAR32(C0GNT2LNCH1) = 0x58001117; - MCHBAR32_OR(C0STATRDCTRL, 1 << 23); + mchbar32_or(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ @@ -682,7 +683,7 @@ flag = 1; } - MCHBAR8_OR(C0PVCFG, 0x03); + mchbar8_or(C0PVCFG, 0x03); MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; @@ -699,7 +700,7 @@ /* FIXME: Only applies to DDR2 */ reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; - MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); + mchbar16_and_or(SHCYCTRKCKEL, (u16)~0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; MCHBAR16(C0CYCTRKWR) = reg16; @@ -714,10 +715,10 @@ MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); - MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + mchbar16_and_or(C0CKECTRL, (u16)~0x03fe, 100 << 1); + mchbar8_and_or(C0CYCTRKPCHG2, (u8)~0x3f, s->selected_timings.tRAS); MCHBAR16(C0ARBCTRL) = 0x2310; - MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); + mchbar8_and_or(C0ADDCSCTRL, (u8)~0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -730,7 +731,7 @@ reg2 = 5000; } reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, reg16); flag = 0; if (wl > 2) { @@ -739,13 +740,13 @@ reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x01ff, reg16); MCHBAR16(C0RDQCTRL) = 0x1585; - MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + mchbar8_and(C0PWLRCTRL, (u8)~0x1f); /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ - MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); + mchbar16_and_or(C0PWLRCTRL, (u16)~0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg16 = 0x0514; @@ -754,115 +755,115 @@ reg16 = 0x0618; reg32 = 0x0c30; } - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x0fffff00, (0x3f << 22) | (reg32 << 8)); /* FIXME: Is this weird access necessary? Reference code does it */ MCHBAR8(C0REFRCTRL + 3) = 0; - MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + mchbar16_and_or(C0REFCTRL, 0xc000, reg16); /* NPUT Static Mode */ - MCHBAR8_OR(C0DYNRDCTRL, 1); + mchbar8_or(C0DYNRDCTRL, 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32_OR(C0STATRDCTRL, 1 << 24); + mchbar32_or(C0STATRDCTRL, 1 << 24); } - MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); - MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); + mchbar8_and(C0RDFIFOCTRL, (u8)~0x3); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x7c00, (wl + 10) << 10); + mchbar32_and_or(C0CKECTRL, (u32)~0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); + mchbar16_and_or(C0REFRCTRL + 4, (u16)~0x7fff, reg16); reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); - MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); - MCHBAR8_AND(C0JEDEC, ~(1 << 7)); - MCHBAR8_AND(C0DYNRDCTRL, ~0x6); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x30000000, reg32 << 8); + mchbar8_and_or(C0REFRCTRL + 3, (u8)~0xfa, reg32 >> 24); + mchbar8_and(C0JEDEC, (u8)~(1 << 7)); + mchbar8_and(C0DYNRDCTRL, (u8)~0x6); /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; MCHBAR32(C0WRWMFLSH) = reg32; - MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); - MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + mchbar16_and_or(C0WRWMFLSH + 4, (u16)~0x1ff, (8 << 3) | (6 >> 2)); + mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5)); /* FIXME: Why not do a single word write? */ - MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); - MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); - MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + mchbar8_and_or(SHPAGECTRL, (u8)~0xff, 0x40); + mchbar8_and_or(SHPAGECTRL + 1, (u8)~0x07, 0x05); + mchbar8_or(SHCMPLWRCMD, 0x1f); reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); - MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); - MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + mchbar8_and_or(SHBONUSREG, (u8)~0xdf, reg8); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); + mchbar8_and_or(C0MISCTM, (u8)~0x07, 0x02); + mchbar16_and_or(C0BYPCTRL, (u16)~0x3fc, 4 << 2); /* [31..29] = 0b010 for kN = 2 (2N) */ reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~0xffb00000, reg32); reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); - MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + mchbar8_and_or(BYPACTSF, (u8)~0xf0, reg8 << 4); reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); - MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + mchbar8_and_or(BYPACTSF, (u8)~0x0f, reg8); /* FIXME: Why not clear everything at once? */ - MCHBAR8_AND(BYPKNRULE, ~0xfc); - MCHBAR8_AND(BYPKNRULE, ~0x03); - MCHBAR8_AND(SHBONUSREG, ~0x03); - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); + mchbar8_and(BYPKNRULE, (u8)~0xfc); + mchbar8_and(BYPKNRULE, (u8)~0x03); + mchbar8_and(SHBONUSREG, (u8)~0x03); + mchbar8_or(C0BYPCTRL, 1); + mchbar16_or(CSHRMISCCTL1, 1 << 9); for (i = 0; i < 8; i++) { /* FIXME: Hardcoded for DDR2 SO-DIMMs */ - MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); + mchbar32_and_or(C0DLLRCVCTLy(i), (u32)~0x3f3f3f3f, 0x0c0c0c0c); } /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, (s->selected_timings.CAS + 1) << 16); /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); - MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); + mchbar8_and(C0RXRCVyDLL(i), (u8)~0x3f); + mchbar16_and(C0RCVMISCCTL2, (u16)~(3 << (i * 2))); + mchbar16_and(C0RCVMISCCTL1, (u16)~(3 << (i * 2))); + mchbar16_and(C0COARSEDLY0, (u16)~(3 << (i * 2))); } - MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ - MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ - MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ - MCHBAR32_OR(C0COREBONUS, 0x000c0400); - MCHBAR32_OR(C0CMDTX1, 1 << 31); + mchbar8_and(C0DLLPIEN, (u8)~1); /* Power up receiver */ + mchbar8_or(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + mchbar8_or(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + mchbar32_or(C0COREBONUS, 0x000c0400); + mchbar32_or(C0CMDTX1, 1 << 31); } /* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16_AND_OR(C0CKTX, ~0xc440, + mchbar16_and_or(C0CKTX, (u16)~0xc440, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | (pll->dbsel[f][i] << 6)); - MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK0DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { /* FIXME: This is actually a dword write! */ - MCHBAR16_AND_OR(C0CKTX, ~0x00030880, + mchbar16_and_or(C0CKTX, (u16)~0x00030880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | (pll->dbsel[f][i] << 7)); - MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK1DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -872,14 +873,14 @@ /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); + mchbar8_and_or(C0CMDTX1, (u8)~0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); + mchbar8_and_or(C0CMDTX2, (u8)~0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCMD0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCMD1DLL, (u8)~0x3f, reg8); } /* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -895,11 +896,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); + mchbar32_and_or(C0CTLTX2, (u32)~0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL1DLL, (u8)~0x3f, reg8); /* CTRL2 and CTRL3 */ reg32 = ((u32) pll->dbsel[f][i]) << 12; @@ -908,11 +909,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); + mchbar32_and_or(C0CMDTX2, (u32)~0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL2DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL3DLL, (u8)~0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -934,11 +935,11 @@ & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQS0R0DLL + j, (u8)~0x3f, reg8); } @@ -961,10 +962,10 @@ & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQ0R0DLL + j, (u8)~0x3f, reg8); } /* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ @@ -1055,8 +1056,8 @@ } /* Disable Dynamic DQS Slave Setting Per Rank */ - MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); - MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); + mchbar8_and(CSHRDQSCMN, (u8)~(1 << 7)); + mchbar16_and_or(CSHRPDCTL4, (u16)~0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); @@ -1079,13 +1080,13 @@ s->async = 0; reg8 = 0; - MCHBAR16_OR(CSHRPDCTL, 1 << 15); - MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); - MCHBAR8_OR(CSHRPDCTL, 1 << 3); - MCHBAR8_OR(CSHRPDCTL, 1 << 2); + mchbar16_or(CSHRPDCTL, 1 << 15); + mchbar8_and(CSHRPDCTL, (u8)~(1 << 7)); + mchbar8_or(CSHRPDCTL, 1 << 3); + mchbar8_or(CSHRPDCTL, 1 << 2); /* Start hardware HMC calibration */ - MCHBAR8_OR(CSHRPDCTL, 1 << 7); + mchbar8_or(CSHRPDCTL, 1 << 7); /* Busy-wait until calibration is done */ while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) @@ -1110,80 +1111,80 @@ } else { reg32 = 0x00014221; } - MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); - MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); + mchbar32_and_or(CSHRMSTRCTL1, (u32)~0x0fffffff, reg32); + mchbar32_or(CSHRMSTRCTL1, 1 << 23); + mchbar32_or(CSHRMSTRCTL1, 1 << 15); + mchbar32_and(CSHRMSTRCTL1, (u32)~(1 << 15)); if (s->nodll) { /* Disable the Master DLLs by setting these bits, IN ORDER! */ - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); + mchbar16_or(CSHRMSTRCTL0, 1 << 0); + mchbar16_or(CSHRMSTRCTL0, 1 << 2); + mchbar16_or(CSHRMSTRCTL0, 1 << 4); + mchbar16_or(CSHRMSTRCTL0, 1 << 8); + mchbar16_or(CSHRMSTRCTL0, 1 << 10); + mchbar16_or(CSHRMSTRCTL0, 1 << 12); + mchbar16_or(CSHRMSTRCTL0, 1 << 14); } else { /* Enable the Master DLLs by clearing these bits, IN ORDER! */ - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 0)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 2)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 4)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 8)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 10)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 12)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 14)); } /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); + mchbar8_and_or(CREFPI, (u8)~0x3f, 0x07); } else { - MCHBAR8_AND(CREFPI, ~0x3f); + mchbar8_and(CREFPI, (u8)~0x3f); } sdram_calibratepll(s, 0); // XXX check /* Enable all modular Slave DLL */ - MCHBAR16_OR(C0DLLPIEN, 1 << 11); - MCHBAR16_OR(C0DLLPIEN, 1 << 12); + mchbar16_or(C0DLLPIEN, 1 << 11); + mchbar16_or(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); + mchbar16_or(C0DLLPIEN, (1 << 10) >> i); } /* Enable DQ/DQS output */ - MCHBAR8_OR(C0SLVDLLOUTEN, 1); + mchbar8_or(C0SLVDLLOUTEN, 1); MCHBAR16(CSPDSLVWT) = 0x5005; - MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); - MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); + mchbar16_and_or(CSHRPDCTL2, (u16)~0x1f1f, 0x051a); + mchbar16_and_or(CSHRPDCTL5, (u16)~0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x6b); } else { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x55); sdram_calibratehwpll(s); } /* Disable Dynamic Diff Amp */ - MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); + mchbar32_and(C0STATRDCTRL, (u32)~(1 << 22)); /* Now, start initializing the transmit FIFO */ - MCHBAR8_AND(C0MISCCTL, ~0x02); + mchbar8_and(C0MISCCTL, (u8)~0x02); /* Disable (gate) mdclk and mdclkb */ - MCHBAR8_OR(CSHWRIOBONUS, 0xc0); + mchbar8_or(CSHWRIOBONUS, 0xc0); /* Select mdmclk */ - MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + mchbar8_and(CSHWRIOBONUS, (u8)~(1 << 5)); /* Ungate mdclk */ - MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); - MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + mchbar8_and_or(CSHWRIOBONUS, (u8)~0xc0, 1 << 6); + mchbar8_and_or(CSHRFIFOCTL, (u8)~0x3f, 0x1a); /* Enable the write pointer count */ - MCHBAR8_OR(CSHRFIFOCTL, 1); + mchbar8_or(CSHRFIFOCTL, 1); /* Set the DDR3 Reset Enable bit */ - MCHBAR8_OR(CSHRDDR3CTL, 1); + mchbar8_or(CSHRDDR3CTL, 1); /* Configure DQS-DQ Transmit */ MCHBAR32(CSHRDQSTXPGM) = 0x00551803; @@ -1191,10 +1192,10 @@ reg8 = 0; /* Switch all clocks on anyway */ /* Enable clock groups depending on rank population */ - MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + mchbar32_and_or(C0CKTX, (u32)~0x3f000000, reg8 << 24); /* Enable DDR command output buffers from core */ - MCHBAR8_AND(0x594, ~1); + mchbar8_and(0x594, (u8)~1); reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { @@ -1209,7 +1210,7 @@ if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16_OR(C0CTLTX2, reg16); + mchbar16_or(C0CTLTX2, reg16); } /* Define a shorter name for these to make the lines fit in 96 characters */ @@ -1344,54 +1345,54 @@ FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); - MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + mchbar8_and_or(C0RCOMPCTRLx(i), (u8)~1, reg8); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~2); reg16 = rcompslew; - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay[i]); if (i == 2) { /* FIXME: Why are we rewriting this? */ - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + mchbar16_and(C0SLEWBASEx(i), (u16)~0x7f7f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i) + 2, (u16)~0x3f3f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i) + 2, (u16)~0x3f3f); } /* FIXME: Hardcoded */ - MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); - MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); + mchbar8_and_or(C0ODTRECORDX, (u8)~0x3f, 0x36); + mchbar8_and_or(C0DQSODTRECORDX, (u8)~0x3f, 0x36); FOR_EACH_RCOMP_GROUP(i) { - MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); - MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); - MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); - MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); - MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); - MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~0x60); + mchbar16_and(C0RCOMPCTRLx(i) + 2, (u16)~0x0706); + mchbar16_and(C0RCOMPOSVx(i), (u16)~0x7f7f); + mchbar16_and(C0SCOMPOFFx(i), (u16)~0x3f3f); + mchbar16_and(C0DCOMPOFFx(i), (u16)~0x1f1f); + mchbar8_and(C0DCOMPOFFx(i) + 2, (u8)~0x1f); } - MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); + mchbar16_and(C0ODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0ODTRECORDX + 2, (u16)~0x000f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + mchbar16_and(C0DQSODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0DQSODTRECORDX + 2, (u16)~0x000f); FOR_EACH_RCOMP_GROUP(i) { MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; @@ -1401,33 +1402,33 @@ MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); + mchbar32_and_or(DCMEASBUFOVR, (u32)~0x001f1f1f, 0x000c1219); /* FIXME: Why not do a single word write? */ - MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); - MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + mchbar16_and_or(XCOMPSDR0BNS, (u16)~0x1f00, 0x1200); + mchbar8_and_or(XCOMPSDR0BNS, (u8)~0x1f, 0x12); MCHBAR32(COMPCTRL3) = 0x007C9007; MCHBAR32(OFREQDELSEL) = rcomp1; MCHBAR16(XCOMPCMNBNS) = 0x1f7f; MCHBAR32(COMPCTRL2) = rcomp2; - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 1); MCHBAR16(ZQCALCTRL) = 0x0134; MCHBAR32(COMPCTRL1) = 0x4C293600; /* FIXME: wtf did these MRC guys smoke */ - MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); - MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); - MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + mchbar8_and_or(COMPCTRL1 + 3, (u8)~0x44, (1 << 6) | (1 << 2)); + mchbar16_and(XCOMPSDR0BNS, (u16)~(1 << 13)); + mchbar8_and(XCOMPSDR0BNS, (u8)~(1 << 5)); FOR_EACH_RCOMP_GROUP(i) { /* FIXME: This should be an _AND_OR */ - MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; + MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & (u8)~0x71; } if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { /* Start COMP */ - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); /* Wait until COMP is done */ while ((MCHBAR8(COMPCTRL1) & 1) != 0) @@ -1443,55 +1444,55 @@ /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + mchbar16_and_or(C0SLEWBASEx(i), (u16)~0x7f00, reg16); reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); + mchbar8_and_or(C0SLEWBASEx(i), (u8)~0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); + mchbar8_and_or(C0SLEWPULUTx(0) + i, (u8)~0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); + mchbar8_and_or(C0SLEWPULUTx(2) + i, (u8)~0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); - MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(3) + i, (u8)~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(4) + i, (u8)~0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); - MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(5) + i, (u8)~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(6) + i, (u8)~0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); + mchbar8_and_or(C0SLEWPDLUTx(0) + i, (u8)~0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); + mchbar8_and_or(C0SLEWPDLUTx(2) + i, (u8)~0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(3) + i, (u8)~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(4) + i, (u8)~0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(5) + i, (u8)~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(6) + i, (u8)~0x3f, rcomplut[j][9]); } } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); } /* FIXME: The ODT tables are for DDR2 only! */ @@ -1566,24 +1567,24 @@ if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x100001); MCHBAR32(C0DRA01) = 0x00000001; MCHBAR32(C0DRB0) = 0x00020002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + mchbar32_and_or(C0CKECTRL, (u32)~1, w260[s->dimm_config[0]]); MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; @@ -1652,10 +1653,10 @@ u32 reg32a, reg32b; ok = 0; - MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); - MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); + mchbar8_and(XCOMPDFCTRL, (u8)~(1 << 3)); + mchbar8_and(COMPCTRL1, (u8)~(1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1668,7 +1669,7 @@ reg32a |= (1 << 31) | (1 << 15); MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1681,7 +1682,7 @@ reg32 = jval << 3; reg32 |= rank * (1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); + mchbar8_and_or(C0JEDEC, (u8)~0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1690,10 +1691,10 @@ static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); - MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); + mchbar32_or(C0CKECTRL, 1 << 27); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); + mchbar32_and_or(C0REFRCTRL2, (u32)~(3 << 30), 3 << 30); } } @@ -1759,12 +1760,12 @@ reg32 = 0; reg32 |= (4 << 13); reg32 |= (6 << 8); - MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); - MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar32_and_or(C0DYNRDCTRL, (u32)~0x3ff00, reg32); + mchbar8_and(C0DYNRDCTRL, (u8)~(1 << 7)); + mchbar8_or(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); } else { sdram_zqcl(s); } @@ -1861,10 +1862,10 @@ reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + mchbar8_and_or(C0CKECTRL + 2, (u8)~0xf0, reg8); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_OR(C0CKECTRL, 1); + mchbar8_or(C0CKECTRL, 1); } addr = C0DRB0; @@ -1885,9 +1886,9 @@ { u8 dqsmatches = 1; while (count--) { - MCHBAR8_AND(C0RSTCTL, ~2); + mchbar8_and(C0RSTCTL, (u8)~2); hpet_udelay(1); - MCHBAR8_OR(C0RSTCTL, 2); + mchbar8_or(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1906,12 +1907,12 @@ { if (*medium < 3) { (*medium)++; - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, *coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); } } @@ -1930,8 +1931,8 @@ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8_AND(C0RSTCTL, ~0x0c); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); + mchbar8_and(C0RSTCTL, (u8)~0x0c); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); PRINTK_DEBUG("rcven 0\n"); for (lane = 0; lane < maxlane; lane++) { @@ -1943,10 +1944,10 @@ pi = 0; medium = 0; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); - MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + mchbar8_and(C0RXRCVyDLL(lane), (u8)~0x3f); savecoarse = coarse; savemedium = medium; @@ -1955,7 +1956,7 @@ PRINTK_DEBUG("rcven 0.1\n"); // XXX comment out - // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); + // mchbar16_and_or(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); @@ -1986,8 +1987,8 @@ PRINTK_DEBUG("rcven 0.3\n"); coarse = savecoarse; medium = savemedium; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; @@ -1998,12 +1999,12 @@ break; // } } - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); rcvenclock(&coarse, &medium, lane); if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { @@ -2013,7 +2014,7 @@ PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { coarse--; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; @@ -2040,10 +2041,10 @@ do { lane--; offset = lanecoarse[lane] - minlanecoarse; - MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + mchbar16_and_or(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); } while (lane != 0); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, minlanecoarse << 16); s->coarsectrl = minlanecoarse; s->coarsedelay = MCHBAR16(C0COARSEDLY0); @@ -2051,14 +2052,14 @@ s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8_AND(C0RSTCTL, ~0x0e); - MCHBAR8_OR(C0RSTCTL, 0x02); - MCHBAR8_OR(C0RSTCTL, 0x04); - MCHBAR8_OR(C0RSTCTL, 0x08); + mchbar8_and(C0RSTCTL, (u8)~0x0e); + mchbar8_or(C0RSTCTL, 0x02); + mchbar8_or(C0RSTCTL, 0x04); + mchbar8_or(C0RSTCTL, 0x08); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); - MCHBAR8_OR(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); + mchbar8_or(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } @@ -2138,20 +2139,20 @@ { u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8_OR(C0ADDCSCTRL, 1); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar8_or(C0ADDCSCTRL, 1); + mchbar8_or(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~mask32, reg32); MCHBAR8(C0DITCTRL + 1) = 2; MCHBAR16(C0DITCTRL + 2) = 0x0804; MCHBAR16(C0DITCTRL + 4) = 0x2010; MCHBAR8(C0DITCTRL + 6) = 0x40; MCHBAR16(C0DITCTRL + 8) = 0x091c; MCHBAR8(C0DITCTRL + 10) = 0xf2; - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR8_OR(C0CWBCTRL, 1); - MCHBAR16_OR(C0ARBSPL, 0x0100); + mchbar8_or(C0BYPCTRL, 1); + mchbar8_or(C0CWBCTRL, 1); + mchbar16_or(C0ARBSPL, 0x0100); pci_or_config8(HOST_BRIDGE, 0xf0, 1); MCHBAR32(SBCTL) = 0x00000002; @@ -2162,7 +2163,7 @@ MCHBAR32(HIT2) = 0x07000000; MCHBAR32(HIT3) = 0x01014010; MCHBAR32(HIT4) = 0x0f038000; - pci_and_config8(HOST_BRIDGE, 0xf0, ~1); + pci_and_config8(HOST_BRIDGE, 0xf0, (u8)~1); u32 nranks, curranksize, maxranksize, dra; u8 rankmismatch; @@ -2209,14 +2210,14 @@ die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); - MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); + mchbar8_and_or(CHDECMISC, (u8)~0xfc, reg8 & 0xfc); + mchbar32_and(NOACFGBUSCTL, (u32)~0x80000000); MCHBAR32(HTBONUS0) = 0x0000000f; - MCHBAR8_OR(C0COREBONUS + 4, 1); + mchbar8_or(C0COREBONUS + 4, 1); - MCHBAR32_AND(HIT3, ~0x0e000000); - MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); + mchbar32_and(HIT3, (u32)~0x0e000000); + mchbar32_and_or(HIT4, (u32)~0x000c0000, 0x00040000); u32 clkcx[2][2][3] = { { @@ -2236,20 +2237,20 @@ MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; - MCHBAR8_AND(HIT4, ~0x02); + mchbar8_and(HIT4, (u8)~0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8_AND(COMPCTRL1, ~0x02); + mchbar8_and(COMPCTRL1, (u8)~0x02); while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16_AND(CSHRMISCCTL, ~0x3000); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); + mchbar16_and(CSHRMISCCTL, (u16)~0x3000); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 0x09); - MCHBAR8_OR(COMPCTRL1, 0x82); + mchbar8_or(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2337,7 +2338,7 @@ } } - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2347,26 +2348,26 @@ /* Thermal sensor */ MCHBAR8(TSC1) = 0x9b; - MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + mchbar32_and_or(TSTTP, (u32)~0x00ffffff, 0x1d00); MCHBAR8(THERM1) = 0x08; MCHBAR8(TSC3) = 0x00; - MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); - MCHBAR8_AND_OR(THERM1, ~1, 1); - MCHBAR8_AND_OR(TCO, ~0x80, 0x80); + mchbar8_and_or(TSC2, (u8)~0x0f, 0x04); + mchbar8_and_or(THERM1, (u8)~1, 1); + mchbar8_and_or(TCO, (u8)~0x80, 0x80); /* Clock gating */ - MCHBAR32_AND(PMMISC, ~0x00040001); - MCHBAR8_AND(SBCTL3 + 3, ~0x80); - MCHBAR8_AND(CISDCTRL + 3, ~0x80); - MCHBAR16_AND(CICGDIS, ~0x1fff); - MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); - MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); - MCHBAR8_AND(TSMISC, ~1); + mchbar32_and(PMMISC, (u32)~0x00040001); + mchbar8_and(SBCTL3 + 3, (u8)~0x80); + mchbar8_and(CISDCTRL + 3, (u8)~0x80); + mchbar16_and(CICGDIS, (u16)~0x1fff); + mchbar32_and(SBCLKGATECTRL, (u32)~0x0001ffff); + mchbar16_and(HICLKGTCTL, (u16)~0x03ff & 0x06); + mchbar32_and_or(HTCLKGTCTL, (u32)~0xffffffff, 0x20); + mchbar8_and(TSMISC, (u8)~1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x07fc, 0x0040); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x0fff, 0x0d00); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0d80); MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ @@ -2379,15 +2380,15 @@ MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x00c8); else - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x0100); j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); - MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); - MCHBAR8_AND(PMBAK, ~0x02); + mchbar32_and_or(PMCLKRC, (u32)~0x01fff37f, 0x10810700); + mchbar8_and_or(PMPXPRC, (u8)~0x07, 1); + mchbar8_and(PMBAK, (u8)~0x02); static const u16 ddr2lut[2][4][2] = { { @@ -2407,8 +2408,8 @@ MCHBAR16(C0C2REG) = 0x7a89; MCHBAR8(SHC2REGII) = 0xaa; MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + mchbar16_and_or(SHC2REGI, (u16)~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, 0xf000); MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); reg32 = s->nodll ? 0x30000000 : 0; @@ -2416,72 +2417,72 @@ /* FIXME: Compacting this results in changes to the binary */ MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); - MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); - MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + mchbar32_and_or(CLOCKGATINGI, (u32)~0x00f00000, 0x00f00000); + mchbar32_and_or(CLOCKGATINGII - 1, (u32)~0x001ff000, 0xbf << 20); + mchbar16_and_or(SHC3C4REG2, (u16)~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); MCHBAR16(SHC3C4REG3) = 0x3264; - MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + mchbar16_and_or(SHC3C4REG4, (u16)~0x3f3f, (0x14 << 8) | 0x0a); - MCHBAR32_OR(C1COREBONUS, 0x80002000); + mchbar32_or(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x03ff, 0x0100); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0x003f, 0x0010); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x7000, 0x2000); - MCHBAR8_AND(CSHRPDCTL, ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); - MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + mchbar8_and(CSHRPDCTL, (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x0c); + mchbar8_and(C0MISCCTLy(0), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(1), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(2), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(3), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(4), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(5), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(6), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(7), (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); - MCHBAR16_AND(CSHRMISCCTL, ~0x0400); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); - MCHBAR8_AND(C0WRDPYN, ~0x80); - MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); - MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); - MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + mchbar16_and(CSHRMISCCTL, (u16)~0x0400); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0dc0); + mchbar8_and(C0WRDPYN, (u8)~0x80); + mchbar32_and(C0COREBONUS, (u32)~(1 << 22)); + mchbar16_and(CLOCKGATINGI, (u16)~0x80fc); + mchbar16_and(CLOCKGATINGII, (u16)~0x0c00); - MCHBAR8_AND(CSHRPDCTL, ~0x0d); - MCHBAR8_AND(C0MISCCTLy(0), ~1); - MCHBAR8_AND(C0MISCCTLy(1), ~1); - MCHBAR8_AND(C0MISCCTLy(2), ~1); - MCHBAR8_AND(C0MISCCTLy(3), ~1); - MCHBAR8_AND(C0MISCCTLy(4), ~1); - MCHBAR8_AND(C0MISCCTLy(5), ~1); - MCHBAR8_AND(C0MISCCTLy(6), ~1); - MCHBAR8_AND(C0MISCCTLy(7), ~1); + mchbar8_and(CSHRPDCTL, (u8)~0x0d); + mchbar8_and(C0MISCCTLy(0), (u8)~1); + mchbar8_and(C0MISCCTLy(1), (u8)~1); + mchbar8_and(C0MISCCTLy(2), (u8)~1); + mchbar8_and(C0MISCCTLy(3), (u8)~1); + mchbar8_and(C0MISCCTLy(4), (u8)~1); + mchbar8_and(C0MISCCTLy(5), (u8)~1); + mchbar8_and(C0MISCCTLy(6), (u8)~1); + mchbar8_and(C0MISCCTLy(7), (u8)~1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); - MCHBAR32_AND(C0COREBONUS, ~0x00100000); - MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); - MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); - MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); - MCHBAR16_OR(C0STATRDCTRL, 0x6000); - MCHBAR32_OR(C0CKECTRL, 0x00010000); - MCHBAR8_OR(C0COREBONUS, 0x10); - MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); - MCHBAR8_OR(CSHWRIOBONUS, 0x07); - MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); - MCHBAR8_OR(SHC2REGIII, 7); - MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); - MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); - MCHBAR16_OR(C0COREBONUS, 0x01e0); - MCHBAR8_OR(CSHWRIOBONUS, 0x18); - MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); - MCHBAR16_OR(SHC3C4REG1, 0x0a3f); - MCHBAR8_OR(C0STATRDCTRL, 3); - MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); - MCHBAR8_AND(C0COREBONUS + 4, ~0x60); - MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x00700000, 3 << 20); + mchbar32_and(C0COREBONUS, (u32)~0x00100000); + mchbar8_or(C0DYNSLVDLLEN, 0x1e); + mchbar8_or(C0DYNSLVDLLEN2, 0x03); + mchbar32_and_or(SHCYCTRKCKEL, (u32)~0x0c000000, 0x04000000); + mchbar16_or(C0STATRDCTRL, 0x6000); + mchbar32_or(C0CKECTRL, 0x00010000); + mchbar8_or(C0COREBONUS, 0x10); + mchbar32_or(CLOCKGATINGI - 1, 0xf << 24); + mchbar8_or(CSHWRIOBONUS, 0x07); + mchbar8_or(C0DYNSLVDLLEN, 0xc0); + mchbar8_or(SHC2REGIII, 7); + mchbar16_and_or(SHC2MINTM, (u16)~0xffff, 0x0080); + mchbar8_and_or(SHC2IDLETM, (u8)~0xff, 0x10); + mchbar16_or(C0COREBONUS, 0x01e0); + mchbar8_or(CSHWRIOBONUS, 0x18); + mchbar8_or(CSHRMSTDYNDLLENB, 0x0d); + mchbar16_or(SHC3C4REG1, 0x0a3f); + mchbar8_or(C0STATRDCTRL, 3); + mchbar8_and_or(C0REFRCTRL2, (u8)~0xff, 0x4a); + mchbar8_and(C0COREBONUS + 4, (u8)~0x60); + mchbar16_or(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2541,13 +2542,13 @@ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); + mchbar32_and(C0COREBONUS, (u32)~(1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32_OR(C0COREBONUS, 1 << 23); + mchbar32_or(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } @@ -2556,10 +2557,10 @@ MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8_OR(CLOCKGATINGI, 3); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); - MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); - MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); + mchbar8_or(CLOCKGATINGI, 3); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, pimdclk << 12); + mchbar8_and_or(CSHWRIOBONUSX, (u8)~0x77, (push << 4) | push); + mchbar32_and_or(C0COREBONUS, (u32)~0x0f000000, 0x03000000); } /** @@ -2592,7 +2593,7 @@ /* Enable HPET */ enable_hpet(); - MCHBAR16_OR(CPCTL, 1 << 15); + mchbar16_or(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2627,16 +2628,16 @@ PRINTK_DEBUG("Done mmap\n"); /* Enable DDR IO buffer */ - MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); - MCHBAR8_OR(C0RSTCTL, 1); + mchbar8_and_or(C0IOBUFACTCTL, (u8)~0x3f, 0x08); + mchbar8_or(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8_OR(HIT4, 2); + mchbar8_or(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); + mchbar32_or(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2649,7 +2650,7 @@ PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0REFRCTRL2, 3 << 30); + mchbar32_or(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2680,7 +2681,7 @@ PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32_OR(C0REFRCTRL2, 1 << 30); + mchbar32_or(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Gerrit-Change-Number: 45517 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 74

Change in coreboot[master]: soc/intel/braswell: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46237 ) Change subject: soc/intel/braswell: Convert to ASL 2.0 syntax ...................................................................... soc/intel/braswell: Convert to ASL 2.0 syntax Change-Id: Ie353ee16c80cc720202c5e32a20c8630acbba84e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/braswell/acpi/dptf/charger.asl M src/soc/intel/braswell/acpi/dptf/cpu.asl M src/soc/intel/braswell/acpi/dptf/dptf.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl M src/soc/intel/braswell/acpi/dptf/wifi.asl M src/soc/intel/braswell/acpi/dptf/wwan.asl M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/gpio.asl M src/soc/intel/braswell/acpi/irqlinks.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/acpi/lpss.asl M src/soc/intel/braswell/acpi/scc.asl M src/soc/intel/braswell/acpi/southcluster.asl 14 files changed, 185 insertions(+), 186 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46237/1 diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl index fca9590..97c8355 100644 --- a/src/soc/intel/braswell/acpi/dptf/charger.asl +++ b/src/soc/intel/braswell/acpi/dptf/charger.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -26,11 +26,11 @@ Method (PPPC) { /* Convert size of PPSS table to index */ - Store (SizeOf (\_SB.CHPS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CHPS) + Local0-- /* Check if charging is disabled (AC removed) */ - If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + If (\_SB.PCI0.LPCB.EC0.ACEX == 0) { /* Return last power state */ Return (Local0) } Else { @@ -45,8 +45,7 @@ Method (SPPC, 1) { /* Retrieve Control (index 4) for specified PPSS level */ - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CHPS [ToInteger (Arg0)]) [4]) /* Pass Control value to EC to limit charging */ \_SB.PCI0.LPCB.EC0.CHGS (Local0) diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index e219c99..728d094 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -40,7 +40,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -100,8 +100,8 @@ Method (_TDL) { If (CondRefOf (\_SB.CP00._TSS)) { - Store (SizeOf (\_SB.CP00._TSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._TSS ()) + Local0-- Return (Local0) } Else { Return (0) @@ -119,7 +119,7 @@ Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -143,8 +143,8 @@ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._PSS ()) + Local0-- Return (Local0) } Else { Return (0) diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl index b41effc..4897159 100644 --- a/src/soc/intel/braswell/acpi/dptf/dptf.asl +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -19,7 +19,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -36,7 +36,7 @@ Method (_OSC, 4, Serialized) { /* Check for Passive Policy UUID */ - If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + If (DeRefOf (IDSP [0]) == Arg0) { /* Initialize Thermal Devices */ ^TINI () @@ -60,10 +60,10 @@ /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 3d92487..2f49ffe 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -6,20 +6,20 @@ #if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) + Local0 = ToInteger (Arg0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (Local0 == DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (Local0 == DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (Local0 == DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } #endif @@ -52,7 +52,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -108,7 +108,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -164,7 +164,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl index 0554d61..9ea9ef6 100644 --- a/src/soc/intel/braswell/acpi/dptf/wifi.asl +++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl index f40889d..91dbf93 100644 --- a/src/soc/intel/braswell/acpi/dptf/wwan.asl +++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index c983d93..a68fde1 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -66,27 +66,27 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index ee26b3c3..36fdbe8 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -22,7 +22,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS) + RBAS = IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST Return (^RBUF) } @@ -51,7 +51,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS) + RBAS = IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH, Return (^RBUF) } @@ -80,7 +80,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS) + RBAS = IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST Return (^RBUF) } @@ -109,7 +109,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS) + RBAS = IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index 6f88459..b1d9d6a 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -8,7 +8,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } /* Possible Resource Settings for this Link */ @@ -28,10 +28,10 @@ CreateWordField(RTLA, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTA */ - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } /* Possible Resource Settings for this Link */ @@ -87,10 +87,10 @@ CreateWordField(RTLB, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTB */ - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -103,14 +103,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } /* Possible Resource Settings for this Link */ @@ -146,10 +146,10 @@ CreateWordField(RTLC, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTC */ - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -162,14 +162,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } /* Possible Resource Settings for this Link */ @@ -205,10 +205,10 @@ CreateWordField(RTLD, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTD */ - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -221,14 +221,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } /* Possible Resource Settings for this Link */ @@ -264,10 +264,10 @@ CreateWordField(RTLE, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTE */ - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -280,14 +280,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } /* Possible Resource Settings for this Link */ @@ -323,10 +323,10 @@ CreateWordField(RTLF, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTF */ - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -339,14 +339,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } /* Possible Resource Settings for this Link */ @@ -382,10 +382,10 @@ CreateWordField(RTLG, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTG */ - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -398,14 +398,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } /* Possible Resource Settings for this Link */ @@ -441,10 +441,10 @@ CreateWordField(RTLH, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTH */ - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -457,14 +457,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 0a22162..53598ef 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -35,9 +35,9 @@ { CreateDwordField (^RBUF, ^FBAR._BAS, FBAS) CreateDwordField (^RBUF, ^FBAR._LEN, FLEN) - Multiply(CONFIG_COREBOOT_ROMSIZE_KB, 1024, Local0) - Store(Local0, FLEN) - Add(Subtract(0xffffffff, Local0), 1, FBAS) + Local0 = CONFIG_COREBOOT_ROMSIZE_KB * 1024 + FLEN = Local0 + FBAS = 0xffffffff - Local0 + 1 Return (^RBUF) } } diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index d655ae8..8b8444a 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -43,15 +43,15 @@ { /* Update BAR0 from NVS */ CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) - Store (\LPB0, BAS0) + BAS0 = \LPB0 /* Update BAR1 from NVS */ CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) + BAS1 = \LPB1 /* Update LPE FW from NVS */ CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) - Store (\LPFW, BAS2) + BAS2 = \LPFW /* Append any Mainboard defined GPIOs */ If (CondRefOf (^GBUF)) { @@ -64,7 +64,7 @@ Method (_STA) { - If (LEqual (\LPEN, 1)) { + If (\LPEN == 1) { Return (0xF) } Else { Return (0x0) @@ -87,14 +87,14 @@ Method (_OFF) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_ON) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } } diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 2516a9f..0080a4f 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -49,13 +49,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S0B0, RBAS) + RBAS = \S0B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S0EN, 1)) { + If (\S0EN == 1) { Return (0xF) } Else { Return (0x0) @@ -81,13 +81,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S8B0, RBAS) + RBAS = \S8B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S8EN, 1)) { + If (\S8EN == 1) { Return (0xF) } Else { Return (0x0) @@ -121,13 +121,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S1B0, RBAS) + RBAS = \S1B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -143,14 +143,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -180,13 +180,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S2B0, RBAS) + RBAS = \S2B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -202,14 +202,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -239,13 +239,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S3B0, RBAS) + RBAS = \S3B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S3EN, 1)) { + If (\S3EN == 1) { Return (0xF) } Else { Return (0x0) @@ -261,14 +261,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -298,13 +298,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S4B0, RBAS) + RBAS = \S4B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S4EN, 1)) { + If (\S4EN == 1) { Return (0xF) } Else { Return (0x0) @@ -320,14 +320,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -357,13 +357,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S5B0, RBAS) + RBAS = \S5B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S5EN, 1)) { + If (\S5EN == 1) { Return (0xF) } Else { Return (0x0) @@ -379,14 +379,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -416,13 +416,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S6B0, RBAS) + RBAS = \S6B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S6EN, 1)) { + If (\S6EN == 1) { Return (0xF) } Else { Return (0x0) @@ -438,14 +438,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -475,13 +475,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S7B0, RBAS) + RBAS = \S7B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S7EN, 1)) { + If (\S7EN == 1) { Return (0xF) } Else { Return (0x0) @@ -497,14 +497,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -528,13 +528,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SCB0, RBAS) + RBAS = \SCB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SCEN, 1)) { + If (\SCEN == 1) { Return (0xF) } Else { Return (0x0) @@ -550,14 +550,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -581,13 +581,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SDB0, RBAS) + RBAS = \SDB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SDEN, 1)) { + If (\SDEN == 1) { Return (0xF) } Else { Return (0x0) @@ -603,13 +603,13 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 1260d0c..988e474 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -19,13 +19,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C0B0, RBAS) + RBAS = \C0B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C0EN, 1)) { + If (\C0EN == 1) { Return (0xF) } Else { Return (0x0) @@ -41,14 +41,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } Device (EM45) @@ -78,7 +78,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\C0EN, 1)) { + If (\C0EN == 1) { Return (0x0) } Else @@ -120,13 +120,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C1B0, RBAS) + RBAS = \C1B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C1EN, 1)) { + If (\C1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -142,14 +142,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -172,13 +172,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C2B0, RBAS) + RBAS = \C2B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C2EN, 1)) { + If (\C2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -194,13 +194,13 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 2c31d40..5deb0ff 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -161,17 +161,17 @@ CreateDWordField (MCRS, LMEM._MIN, LMIN) CreateDWordField (MCRS, LMEM._MAX, LMAX) CreateDWordField (MCRS, LMEM._LEN, LLEN) - If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) + If ((LPFW != 0) && (LPEN == 1)) { - Store (LPFW, LMIN) - Store (Add (LMIN, 0x001FFFFF), LMAX) - Store (0x00200000, LLEN) + LMIN = LPFW + LMAX = LMIN + 0x001FFFFF + LLEN = 0x00200000 } Else { - Store (Zero, LMIN) - Store (Zero, LMAX) - Store (Zero, LLEN) + LMIN = 0 + LMAX = 0 + LLEN = 0 } /* Update PCI resource area */ @@ -180,9 +180,9 @@ CreateDwordField(MCRS, PMEM._LEN, PLEN) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ - Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \TOLM + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1 Return (MCRS) } @@ -214,7 +214,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -223,7 +223,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } @@ -244,7 +244,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + RBAS = MCFG_BASE_ADDRESS + 0xD0 Return (^RBUF) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie353ee16c80cc720202c5e32a20c8630acbba84e Gerrit-Change-Number: 46237 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: soc/intel/baytrail: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46236 ) Change subject: soc/intel/baytrail: Convert to ASL 2.0 syntax ...................................................................... soc/intel/baytrail: Convert to ASL 2.0 syntax Change-Id: I0033698580439f90ac91570f1a4e73f9b235e53a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/baytrail/acpi/dptf/charger.asl M src/soc/intel/baytrail/acpi/dptf/cpu.asl M src/soc/intel/baytrail/acpi/dptf/dptf.asl M src/soc/intel/baytrail/acpi/dptf/thermal.asl M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/gpio.asl M src/soc/intel/baytrail/acpi/irqlinks.asl M src/soc/intel/baytrail/acpi/lpe.asl M src/soc/intel/baytrail/acpi/lpss.asl M src/soc/intel/baytrail/acpi/scc.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/acpi/xhci.asl 12 files changed, 183 insertions(+), 184 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/46236/1 diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl index b8c6d14..908d3a9 100644 --- a/src/soc/intel/baytrail/acpi/dptf/charger.asl +++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -26,11 +26,11 @@ Method (PPPC) { /* Convert size of PPSS table to index */ - Store (SizeOf (\_SB.CHPS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CHPS) + Local0-- /* Check if charging is disabled (AC removed) */ - If (LEqual (\PWRS, Zero)) { + If (\PWRS == 0) { /* Return last power state */ Return (Local0) } Else { @@ -45,8 +45,7 @@ Method (SPPC, 1) { /* Retrieve Control (index 4) for specified PPSS level */ - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CHPS [ToInteger (Arg0)]) [4]) /* Pass Control value to EC to limit charging */ \_SB.PCI0.LPCB.EC0.CHGS (Local0) diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index cd6a572..61eb452 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -13,7 +13,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -73,8 +73,8 @@ Method (_TDL) { If (CondRefOf (\_SB.CP00._TSS)) { - Store (SizeOf (\_SB.CP00._TSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._TSS ()) + Local0-- Return (Local0) } Else { Return (0) @@ -92,7 +92,7 @@ Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -116,8 +116,8 @@ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS ()), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._PSS ()) + Local0-- Return (Local0) } Else { Return (0) diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl index 66bfa45..3f49fe5 100644 --- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -19,7 +19,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -36,7 +36,7 @@ Method (_OSC, 4, Serialized) { /* Check for Passive Policy UUID */ - If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + If (DeRefOf (IDSP [0]) == Arg0) { /* Initialize Thermal Devices */ ^TINI () @@ -60,10 +60,10 @@ /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index 816c169..1f99301 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -6,20 +6,20 @@ #if CONFIG(EC_SUPPORTS_DPTF_TEVT) Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) + Local0 = ToInteger (Arg0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (Local0 == DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (Local0 == DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (Local0 == DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } #endif @@ -52,7 +52,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -108,7 +108,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -164,7 +164,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index c472d06..5fca68d 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -65,27 +65,27 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index 4e48cc6..e6dc536 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -22,7 +22,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + RBAS = IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE Return (^RBUF) } @@ -51,7 +51,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + RBAS = IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE Return (^RBUF) } @@ -80,7 +80,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + RBAS = IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS Return (^RBUF) } diff --git a/src/soc/intel/baytrail/acpi/irqlinks.asl b/src/soc/intel/baytrail/acpi/irqlinks.asl index ef3bdd4..af89c33 100644 --- a/src/soc/intel/baytrail/acpi/irqlinks.asl +++ b/src/soc/intel/baytrail/acpi/irqlinks.asl @@ -8,7 +8,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } /* Possible Resource Settings for this Link */ @@ -28,10 +28,10 @@ CreateWordField(RTLA, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTA */ - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } /* Possible Resource Settings for this Link */ @@ -87,10 +87,10 @@ CreateWordField(RTLB, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTB */ - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -103,14 +103,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } /* Possible Resource Settings for this Link */ @@ -146,10 +146,10 @@ CreateWordField(RTLC, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTC */ - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -162,14 +162,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } /* Possible Resource Settings for this Link */ @@ -205,10 +205,10 @@ CreateWordField(RTLD, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTD */ - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -221,14 +221,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } /* Possible Resource Settings for this Link */ @@ -264,10 +264,10 @@ CreateWordField(RTLE, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTE */ - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -280,14 +280,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } /* Possible Resource Settings for this Link */ @@ -323,10 +323,10 @@ CreateWordField(RTLF, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTF */ - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -339,14 +339,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } /* Possible Resource Settings for this Link */ @@ -382,10 +382,10 @@ CreateWordField(RTLG, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTG */ - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -398,14 +398,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ /* Disable method */ Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } /* Possible Resource Settings for this Link */ @@ -441,10 +441,10 @@ CreateWordField(RTLH, 1, IRQ0) /* Clear the WordField */ - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PRTH */ - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -457,14 +457,14 @@ /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } /* Status */ Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/baytrail/acpi/lpe.asl b/src/soc/intel/baytrail/acpi/lpe.asl index a0a08b8..0e52cc8 100644 --- a/src/soc/intel/baytrail/acpi/lpe.asl +++ b/src/soc/intel/baytrail/acpi/lpe.asl @@ -43,15 +43,15 @@ { /* Update BAR0 from NVS */ CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) - Store (\LPB0, BAS0) + BAS0 = \LPB0 /* Update BAR1 from NVS */ CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) + BAS1 = \LPB1 /* Update LPE FW from NVS */ CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) - Store (\LPFW, BAS2) + BAS2 = \LPFW /* Append any Mainboard defined GPIOs */ If (CondRefOf (^GBUF)) { @@ -64,7 +64,7 @@ Method (_STA) { - If (LEqual (\LPEN, 1)) { + If (\LPEN == 1) { Return (0xF) } Else { Return (0x0) @@ -87,14 +87,14 @@ Method (_OFF) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_ON) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } } diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index 6ba615d..94f16ea 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -18,13 +18,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S0B0, RBAS) + RBAS = \S0B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S0EN, 1)) { + If (\S0EN == 1) { Return (0xF) } Else { Return (0x0) @@ -50,13 +50,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S8B0, RBAS) + RBAS = \S8B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S8EN, 1)) { + If (\S8EN == 1) { Return (0xF) } Else { Return (0x0) @@ -90,13 +90,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S1B0, RBAS) + RBAS = \S1B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -112,14 +112,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -149,13 +149,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S2B0, RBAS) + RBAS = \S2B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -171,14 +171,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -208,13 +208,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S3B0, RBAS) + RBAS = \S3B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S3EN, 1)) { + If (\S3EN == 1) { Return (0xF) } Else { Return (0x0) @@ -230,14 +230,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -267,13 +267,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S4B0, RBAS) + RBAS = \S4B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S4EN, 1)) { + If (\S4EN == 1) { Return (0xF) } Else { Return (0x0) @@ -289,14 +289,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -326,13 +326,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S5B0, RBAS) + RBAS = \S5B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S5EN, 1)) { + If (\S5EN == 1) { Return (0xF) } Else { Return (0x0) @@ -348,14 +348,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -385,13 +385,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S6B0, RBAS) + RBAS = \S6B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S6EN, 1)) { + If (\S6EN == 1) { Return (0xF) } Else { Return (0x0) @@ -407,14 +407,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -444,13 +444,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S7B0, RBAS) + RBAS = \S7B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S7EN, 1)) { + If (\S7EN == 1) { Return (0xF) } Else { Return (0x0) @@ -466,14 +466,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -497,13 +497,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\S9B0, RBAS) + RBAS = \S9B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\S9EN, 1)) { + If (\S9EN == 1) { Return (0xF) } Else { Return (0x0) @@ -519,14 +519,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -544,13 +544,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SAB0, RBAS) + RBAS = \SAB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SAEN, 1)) { + If (\SAEN == 1) { Return (0xF) } Else { Return (0x0) @@ -572,13 +572,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SBB0, RBAS) + RBAS = \SBB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SBEN, 1)) { + If (\SBEN == 1) { Return (0xF) } Else { Return (0x0) @@ -606,13 +606,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SCB0, RBAS) + RBAS = \SCB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SCEN, 1)) { + If (\SCEN == 1) { Return (0xF) } Else { Return (0x0) @@ -628,14 +628,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -659,13 +659,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\SDB0, RBAS) + RBAS = \SDB0 Return (^RBUF) } Method (_STA) { - If (LEqual (\SDEN, 1)) { + If (\SDEN == 1) { Return (0xF) } Else { Return (0x0) @@ -681,13 +681,13 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl index cf0debd..7f58687 100644 --- a/src/soc/intel/baytrail/acpi/scc.asl +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -19,13 +19,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C0B0, RBAS) + RBAS = \C0B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C0EN, 1)) { + If (\C0EN == 1) { Return (0xF) } Else { Return (0x0) @@ -41,14 +41,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } Device (EM45) @@ -82,13 +82,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C1B0, RBAS) + RBAS = \C1B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C1EN, 1)) { + If (\C1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -104,14 +104,14 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } @@ -134,13 +134,13 @@ Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) - Store (\C2B0, RBAS) + RBAS = \C2B0 Return (^RBUF) } Method (_STA) { - If (LEqual (\C2EN, 1)) { + If (\C2EN == 1) { Return (0xF) } Else { Return (0x0) @@ -156,13 +156,13 @@ Method (_PS3) { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT |= 0x00000003 + PSAT |= 0x00000000 } Method (_PS0) { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) + PSAT &= 0xfffffffc + PSAT |= 0x00000000 } } diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index e3997d7..fb4a79c 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -158,9 +158,9 @@ CreateDwordField(MCRS, ^PMEM._LEN, PLEN) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ - Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \TOLM + PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 + PLEN = PMAX - PMIN + 1 Return (MCRS) } @@ -192,7 +192,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -201,7 +201,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } @@ -222,7 +222,7 @@ Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + RBAS = MCFG_BASE_ADDRESS + 0xD0 Return (^RBUF) } } diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index bfed3c6..d3706a4 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -18,11 +18,11 @@ // REV: Revision 0x02 for ACPI 5.0 CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + REV = 0x02 // VISI: Port visibility to user per port CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + VISI = Arg0 Return (PCKG) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0033698580439f90ac91570f1a4e73f9b235e53a Gerrit-Change-Number: 46236 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: nb/intel/haswell: Use `chromeos_reserve_ram_oops` function
by Angel Pons (Code Review) 16 Feb '21

16 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46980 ) Change subject: nb/intel/haswell: Use `chromeos_reserve_ram_oops` function ...................................................................... nb/intel/haswell: Use `chromeos_reserve_ram_oops` function Taken from Broadwell and assumed to be equivalent. Change-Id: Iffc2e3450e98182139dc5020b466186d0d28d20c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46980/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 2d19ccd..a6f187c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -13,6 +13,7 @@ #include <device/pci_ops.h> #include <boot/tables.h> #include <security/intel/txt/txt_register.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "chip.h" #include "haswell.h" @@ -373,11 +374,9 @@ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif + if (CONFIG(CHROMEOS)) + chromeos_reserve_ram_oops(dev, index++); + *resource_cnt = index; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffc2e3450e98182139dc5020b466186d0d28d20c Gerrit-Change-Number: 46980 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: cpu/x86/smm: Fix getting the save state for multiple segments
by Arthur Heymans (Code Review) 15 Feb '21

15 Feb '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47081 ) Change subject: cpu/x86/smm: Fix getting the save state for multiple segments ...................................................................... cpu/x86/smm: Fix getting the save state for multiple segments The map for for the base of smm save states is a bit more complicated when a system uses multiple segments. Instead of redoing the segment computation, copy over the map used in during relocation to the permanent handler, via relocatable module parameters. Untested. Change-Id: I480d00c55bedd0d2e4a7984cd577b7f5aaf6078d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 3 files changed, 20 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47081/1 diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index b6ef077..77432fd 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,6 +18,8 @@ static volatile __attribute__((aligned(4))) smi_semaphore smi_handler_status = SMI_UNLOCKED; +const struct smm_handler_params params __attribute__((unused,section(".module_parameters"))); + static int smi_obtain_lock(void) { u8 ret = SMI_LOCKED; @@ -91,18 +93,17 @@ struct global_nvs *gnvs; -/* TODO: handle multiple segments! */ +/* This returns the base of the save state allocated for a CPU. + * Note that if a size larger than the actual save state is allocated + * this is not the 'real' base of the save state as those are top aligned + * and not bottom aligned. + */ void *smm_get_save_state(int cpu) { - char *base; + if (cpu < CONFIG_MAX_CPUS) + return (void *)params.ss_start[cpu]; - /* This function assumes all save states start at top of default - * SMRAM size space and are staggered down by save state size. */ - base = (void *)(uintptr_t)smm_runtime->smbase; - base += SMM_DEFAULT_SIZE; - base -= (cpu + 1) * smm_runtime->save_state_size; - - return base; + return NULL; } uint32_t smm_revision(void) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 66d0268..7c35433 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -562,6 +562,7 @@ void *fxsave_area; size_t total_size = 0; char *base; + struct smm_handler_params *handler_params; if (size <= SMM_DEFAULT_SIZE) return -1; @@ -637,6 +638,10 @@ params->handler = rmodule_entry(&smm_mod); params->handler_arg = rmodule_parameters(&smm_mod); + handler_params = params->handler_arg; + /* Copy over the CPU save state map to the permanent handler. */ + for (int i = 0; i < CONFIG_MAX_CPUS; i++) + handler_params->ss_start[i] = cpus[i].ss_start; printk(BIOS_DEBUG, "%s: smram_start: 0x%p\n", __func__, smram); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7491d95..3d109a1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -153,6 +153,11 @@ unsigned int smram_end; }; +/* These are the relocatable module parameters for the permanent handler */ +struct smm_handler_params { + uintptr_t ss_start[CONFIG_MAX_CPUS]; +}; + /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/47081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I480d00c55bedd0d2e4a7984cd577b7f5aaf6078d Gerrit-Change-Number: 47081 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: src/drivers/spi: Use common 'SPI_OPCODE_*'
by HAOUAS Elyes (Code Review) 15 Feb '21

15 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45092 ) Change subject: src/drivers/spi: Use common 'SPI_OPCODE_*' ...................................................................... src/drivers/spi: Use common 'SPI_OPCODE_*' Change-Id: Ie0ec13ba56c813ffc5a62c3013f32221061ae94d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/include/spi_flash.h 10 files changed, 20 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/45092/1 diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 6538905..9e786e0 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -12,20 +12,6 @@ #include "spi_flash_internal.h" -/* at25dfxx-specific commands */ -#define CMD_AT25DF_WREN 0x06 /* Write Enable */ -#define CMD_AT25DF_WRDI 0x04 /* Write Disable */ -#define CMD_AT25DF_RDSR 0x05 /* Read Status Register */ -#define CMD_AT25DF_WRSR 0x01 /* Write Status Register */ -#define CMD_AT25DF_READ 0x03 /* Read Data Bytes */ -#define CMD_AT25DF_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_AT25DF_PP 0x02 /* Page Program */ -#define CMD_AT25DF_SE 0x20 /* Sector (4K) Erase */ -#define CMD_AT25DF_BE 0xd8 /* Block (64K) Erase */ -#define CMD_AT25DF_CE 0xc7 /* Chip Erase */ -#define CMD_AT25DF_DP 0xb9 /* Deep Power-down */ -#define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* AT25SL128A */ diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 5e74616..9afa9fb 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* A25L-specific commands */ -#define CMD_A25_WREN 0x06 /* Write Enable */ -#define CMD_A25_WRDI 0x04 /* Write Disable */ -#define CMD_A25_RDSR 0x05 /* Read Status Register */ -#define CMD_A25_WRSR 0x01 /* Write Status Register */ -#define CMD_A25_READ 0x03 /* Read Data Bytes */ -#define CMD_A25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_A25_PP 0x02 /* Page Program */ -#define CMD_A25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_A25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_A25_CE 0xc7 /* Chip Erase */ -#define CMD_A25_DP 0xb9 /* Deep Power-down */ -#define CMD_A25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* A25L16PU */ diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 4dcc5b5..ab8b0fa 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* M25Pxx-specific commands */ -#define CMD_AT25_WREN 0x06 /* Write Enable */ -#define CMD_AT25_WRDI 0x04 /* Write Disable */ -#define CMD_AT25_RDSR 0x05 /* Read Status Register */ -#define CMD_AT25_WRSR 0x01 /* Write Status Register */ -#define CMD_AT25_READ 0x03 /* Read Data Bytes */ -#define CMD_AT25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_AT25_PP 0x02 /* Page Program */ -#define CMD_AT25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_AT25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_AT25_CE 0xc7 /* Chip Erase */ -#define CMD_AT25_DP 0xb9 /* Deep Power-down */ -#define CMD_AT25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* AT25X16 */ diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 1212c6b..f6ef3d0 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -7,19 +7,6 @@ #include "spi_flash_internal.h" -/* EN25*-specific commands */ -#define CMD_EN25_WREN 0x06 /* Write Enable */ -#define CMD_EN25_WRDI 0x04 /* Write Disable */ -#define CMD_EN25_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25_PP 0x02 /* Page Program */ -#define CMD_EN25_SE 0x20 /* Sector Erase */ -#define CMD_EN25_BE 0xd8 /* Block Erase */ -#define CMD_EN25_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25_RES 0xab /* Release from DP, and Read Signature */ - #define EON_ID_EN25B80 0x2014 #define EON_ID_EN25B16 0x2015 #define EON_ID_EN25B32 0x2016 diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 6c5a167..0d20758 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* GD25Pxx-specific commands */ -#define CMD_GD25_WREN 0x06 /* Write Enable */ -#define CMD_GD25_WRDI 0x04 /* Write Disable */ -#define CMD_GD25_RDSR 0x05 /* Read Status Register */ -#define CMD_GD25_WRSR 0x01 /* Write Status Register */ -#define CMD_GD25_READ 0x03 /* Read Data Bytes */ -#define CMD_GD25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_GD25_PP 0x02 /* Page Program */ -#define CMD_GD25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_GD25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_GD25_CE 0xc7 /* Chip Erase */ -#define CMD_GD25_DP 0xb9 /* Deep Power-down */ -#define CMD_GD25_RES 0xab /* Release from DP, and Read Signature */ - static const struct spi_flash_part_id flash_table[] = { { /* GD25T80 */ diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index f3f7e2d..f8f773a 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* MX25xx-specific commands */ -#define CMD_MX25XX_WREN 0x06 /* Write Enable */ -#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ -#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ -#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ -#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ -#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_MX25XX_PP 0x02 /* Page Program */ -#define CMD_MX25XX_SE 0x20 /* Sector Erase */ -#define CMD_MX25XX_BE 0xD8 /* Block Erase */ -#define CMD_MX25XX_CE 0xc7 /* Chip Erase */ -#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ -#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ - #define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ static const struct spi_flash_part_id flash_table[] = { diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fe0e265..ff912bd 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* S25FLxx-specific commands */ -#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ -#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ -#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ -#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ -#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ -#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ -#define CMD_S25FLXX_PP 0x02 /* Page Program */ -#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ -#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ -#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ -#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ - #define SPSN_ID_S25FL008A 0x0213 #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 887380f..02e5129 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -11,15 +11,8 @@ #include "spi_flash_internal.h" -#define CMD_SST_WREN 0x06 /* Write Enable */ -#define CMD_SST_WRDI 0x04 /* Write Disable */ -#define CMD_SST_RDSR 0x05 /* Read Status Register */ -#define CMD_SST_WRSR 0x01 /* Write Status Register */ #define CMD_SST_EWSR 0x50 /* Enable Write Status Register */ -#define CMD_SST_READ 0x03 /* Read Data Bytes */ -#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ -#define CMD_SST_PP 0x02 /* Page Program */ #define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ #define CMD_SST_SE 0x20 /* Sector Erase */ @@ -90,7 +83,7 @@ static int sst_enable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(&flash->spi, CMD_SST_WREN, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, SPI_OPCODE_WREN, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Enabling Write failed\n"); return ret; @@ -108,7 +101,7 @@ static int sst_disable_writing(const struct spi_flash *flash) { - int ret = spi_flash_cmd(&flash->spi, CMD_SST_WRDI, NULL, 0); + int ret = spi_flash_cmd(&flash->spi, SPI_OPCODE_WRDI, NULL, 0); if (ret) printk(BIOS_WARNING, "SF: Disabling Write failed\n"); return ret; @@ -127,7 +120,7 @@ #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "BP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(&flash->spi, SPI_OPCODE_RDSR), buf, cmd[0], offset); #endif ret = sst_enable_writing(flash); @@ -170,7 +163,7 @@ for (; actual < len - 1; actual += 2) { #if CONFIG(DEBUG_SPI_FLASH) printk(BIOS_SPEW, "WP[%02x]: %p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(&flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(&flash->spi, SPI_OPCODE_RDSR), buf + actual, cmd[0], offset); #endif @@ -215,21 +208,21 @@ if (ret) return ret; - cmd = CMD_SST_WRSR; + cmd = SPI_OPCODE_WRSR; status = 0; ret = spi_flash_cmd_write(&flash->spi, &cmd, 1, &status, 1); if (ret) printk(BIOS_WARNING, "SF: Unable to set status byte\n"); - printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, CMD_SST_RDSR)); + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(&flash->spi, SPI_OPCODE_RDSR)); return ret; } static const struct spi_flash_ops_descriptor descai = { .erase_cmd = CMD_SST_SE, - .status_cmd = CMD_SST_RDSR, - .wren_cmd = CMD_SST_WREN, + .status_cmd = SPI_OPCODE_RDSR, + .wren_cmd = SPI_OPCODE_WREN, .ops = { .read = spi_flash_cmd_read, .write = sst_write_ai, diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..63b6451 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -7,20 +7,6 @@ #include "spi_flash_internal.h" -/* M25Pxx-specific commands */ -#define CMD_M25PXX_WREN 0x06 /* Write Enable */ -#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ -#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ -#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ -#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ -#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_M25PXX_PP 0x02 /* Page Program */ -#define CMD_M25PXX_SSE 0x20 /* Subsector Erase */ -#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ -#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ -#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ -#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ - /* * Device ID = (memory_type << 8) + memory_capacity */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 1061e99..d5ba116 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -9,8 +9,18 @@ #include <boot/coreboot_tables.h> /* SPI Flash opcodes */ -#define SPI_OPCODE_WREN 0x06 -#define SPI_OPCODE_FAST_READ 0x0b +#define SPI_OPCODE_WREN 0x06 /* Write Enable */ +#define SPI_OPCODE_WRDI 0x04 /* Write Disable */ +#define SPI_OPCODE_RDSR 0x05 /* Read Status Register */ +#define SPI_OPCODE_WRSR 0x01 /* Write Status Register */ +#define SPI_OPCODE_READ 0x03 /* Read Data Bytes */ +#define SPI_OPCODE_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define SPI_OPCODE_PP 0x02 /* Page Program */ +#define SPI_OPCODE_SE 0x20 /* Sector (4K) Erase */ +#define SPI_OPCODE_BE 0xd8 /* Block (64K) Erase */ +#define SPI_OPCODE_CE 0xc7 /* Chip Erase */ +#define SPI_OPCODE_DP 0xb9 /* Deep Power-down */ +#define SPI_OPCODE_RES 0xab /* Release from DP, and Read Signature */ struct spi_flash; -- To view, visit https://review.coreboot.org/c/coreboot/+/45092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0ec13ba56c813ffc5a62c3013f32221061ae94d Gerrit-Change-Number: 45092 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/cedarisland_crb: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46183 ) Change subject: mb/intel/cedarisland_crb: Convert to ASL 2.0 syntax ...................................................................... mb/intel/cedarisland_crb: Convert to ASL 2.0 syntax Change-Id: Idb9b6d1b4abd310a47f009e35756d56577a83c4e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/cedarisland_crb/acpi/platform.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46183/1 diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl index 9649592..ebde468 100644 --- a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -23,7 +23,7 @@ Method(_PIC, 1) { - Store(Arg0, PICM) + PICM = Arg0 } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/46183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb9b6d1b4abd310a47f009e35756d56577a83c4e Gerrit-Change-Number: 46183 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45772 ) Change subject: mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax ...................................................................... mb/51nb/x210/acpi: Convert to to ASL 2.0 syntax Generated build/dsdt.dsl before and after current patch are same. Change-Id: Ia0354e535229e832cf0e65cb8744a1ee8d5e8a34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/acpi/battery.asl M src/mainboard/51nb/x210/acpi/ec.asl M src/mainboard/51nb/x210/acpi/platform.asl 3 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45772/1 diff --git a/src/mainboard/51nb/x210/acpi/battery.asl b/src/mainboard/51nb/x210/acpi/battery.asl index f9022a4..b81af1f 100644 --- a/src/mainboard/51nb/x210/acpi/battery.asl +++ b/src/mainboard/51nb/x210/acpi/battery.asl @@ -37,19 +37,19 @@ Method (_BIF, 0, Serialized) { /* Design Capacity */ - Store (DGCP * 10000 / DGVO, Index (PBIF, 1)) + PBIF [One] = (DGCP * 10000) / DGVO /* Last Full Charge Capacity */ - Store (FLCP * 10000 / DGVO, Index (PBIF, 2)) + PBIF [2] = (FLCP * 10000) / DGVO /* Design Voltage */ - Store (DGVO, Index (PBIF, 4)) + PBIF [4] = DGVO /* Design Capacity of Warning */ - Store (BDW * 10000 / DGVO, Index (PBIF, 5)) + PBIF [5] = (BDW * 10000) / DGVO /* Design Capacity of Low */ - Store (BDL, Index (PBIF, 6)) + PBIF [6] = BDL Return (PBIF) } @@ -70,22 +70,22 @@ * bit 1 = charging * bit 2 = critical level */ - Store (BSTS, Index (PBST, 0)) + PBST [0] = BSTS /* * 1: BATTERY PRESENT RATE */ - Store (BPR, Index (PBST, 1)) + PBST [1] = BPR /* * 2: BATTERY REMAINING CAPACITY */ - Store (BRC * 10000 / DGVO, Index (PBST, 2)) + PBST [2] = (BRC * 10000) / DGVO /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BPV, Index (PBST, 3)) + PBST [3] = BPV Return (PBST) } diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index 78e156c..fc1aafc 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -45,10 +45,10 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACIN, \PWRS) + PWRS = ACIN /* Initialize LID switch state */ - Store (LIDC, \LIDS) + LIDS = LIDC } /* KEY_BRIGHTNESSUP */ @@ -79,7 +79,7 @@ /* Lid event */ Method (_Q0E) { - Store (LIDC, \LIDS) + LIDS = LIDC Notify (LID0, 0x80) } diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl index 6cf3f32..3415767 100644 --- a/src/mainboard/51nb/x210/acpi/platform.asl +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -14,7 +14,7 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } /* @@ -30,7 +30,7 @@ Method (_WAK, 1) { - Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS) - Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS) + LIDS = \_SB.PCI0.LPCB.EC.LIDC + PWRS = \_SB.PCI0.LPCB.EC.ACIN Return (Package (){ 0, 0 }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0354e535229e832cf0e65cb8744a1ee8d5e8a34 Gerrit-Change-Number: 45772 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/quanta/ene_kb3940q: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 14 Feb '21

14 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46103 ) Change subject: ec/quanta/ene_kb3940q: Convert to ASL 2.0 syntax ...................................................................... ec/quanta/ene_kb3940q: Convert to ASL 2.0 syntax Change-Id: Ifc90fb7707c07f2f364e1fdd710fe52522e8ab5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/quanta/ene_kb3940q/acpi/ac.asl M src/ec/quanta/ene_kb3940q/acpi/battery.asl M src/ec/quanta/ene_kb3940q/acpi/ec.asl 3 files changed, 60 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46103/1 diff --git a/src/ec/quanta/ene_kb3940q/acpi/ac.asl b/src/ec/quanta/ene_kb3940q/acpi/ac.asl index b086bf5..cc14b33 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ac.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ac.asl @@ -9,7 +9,7 @@ Method (_PSR) { - Store(ADPT, Local0) + Local0 = ADPT Return(Local0) } diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index 09c1b29..b5a7db7 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -44,13 +44,13 @@ // Method to enable full battery workaround Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } // Method to disable full battery workaround Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } // Device insertion/removal control method that returns a device's status. @@ -68,18 +68,18 @@ Method (_BIF, 0, Serialized) { // Update fields from EC - Store (BDC0, Index (PBIF, 1)) // Batt Design Capacity - Store (BFC0, Index (PBIF, 2)) // Batt Last Full Charge Capacity - Store (BDV0, Index (PBIF, 4)) // Batt Design Voltage - Divide(BFC0, 0x64, , Local1) - Multiply(Local1, 0x0A, Local0) - Store(Local0, Index(PBIF, 5)) - Multiply(Local1, 0x05, Local0) - Store (Local0, Index (PBIF, 6)) - Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // Model Number - Store (ToDecimalString(BSN0), Index (PBIF, 10)) // Serial Number - Store (ToString(Concatenate(BCHM, 0x00)), Index (PBIF, 11)) // Battery Type - Store (\BATV, Index (PBIF, 12)) // OEM information + PBIF [1] = BDC0 // Batt Design Capacity + PBIF [2] = BFC0 // Batt Last Full Charge Capacity + PBIF [4] = BDV0 // Batt Design Voltage + Local1 = BFC0 / 100 + Local0 *= 10 + PBIF [5] = Local0 + Local0 = Local1 * 5 + PBIF [6] = Local0 + PBIF [9] = ToString (Concatenate (BATD, 0x00)) // Model Number + PBIF [10] = ToDecimalString(BSN0) // Serial Number + PBIF [11] = ToString (Concatenate (BCHM, 0x00)) // Battery Type + PBIF [12] = \BATV // OEM information Return (PBIF) } @@ -95,45 +95,44 @@ // // Get battery state from EC - Store (BST0, Local0) - Store (Local0, Index (PBST, 0)) + Local0 = BST0 + PBST [0] = Local0 // // 1: BATTERY PRESENT RATE/CURRENT // - Store (BPC0, Local1) - If (LAnd (Local1, 0x8000)) { - Xor (Local1, 0xFFFF, Local1) - Increment (Local1) + Local1 = BPC0 + If (Local1 && 0x8000) { + Local1 ^= 0xFFFF + Local1++ } - Store (Local1, Index (PBST, 1)) + PBST [1] = Local1 // // 2: BATTERY REMAINING CAPACITY // Store (BRC0, Local1) - If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) { + If (BFWK && ADPT && !Local0) { // On AC power and battery is neither charging // nor discharging. Linux expects a full battery // to report same capacity as last full charge. // https://bugzilla.kernel.org/show_bug.cgi?id=12632 - Store (BFC0, Local2) + Local2 = BFC0 // See if within ~3% of full - ShiftRight (Local2, 5, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + Local3 = Local2 >> 5 + If ((Local1 > (Local2 - Local3)) && (Local1 < (Local2 + Local3))) { - Store (Local2, Local1) + Local1 = Local2 } } - Store (Local1, Index (PBST, 2)) + PBST [2] = Local1 // // 3: BATTERY PRESENT VOLTAGE // - Store (BPV0, Index (PBST, 3)) + PBST [3] = BPV0 Return (PBST) } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 9d8cc28..d43ec27 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -122,26 +122,26 @@ Method (_REG, 2, NotSerialized) { // Initialize AC power state - Store (ADPT, \PWRS) + \PWRS = ADPT // Initialize LID switch state - Store (LIDF, \LIDS) + \LIDS = LIDF // Force a read of CPU temperature - Store (CTMP, Local0) + Local0 = CTMP // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones // Find and program number of P-States - Store (SizeOf (\_SB.CP00._PSS), MPST) - Store ("Programming number of P-states: ", Debug) - Store (MPST, Debug) + MPST = SizeOf (\_SB.CP00._PSS) + Debug = "Programming number of P-states: " + Debug = MPST // Find and program the current P-State - Store(\_SB.CP00._PPC, NPST) - Store ("Programming Current P-state: ", Debug) - Store (NPST, Debug) + NPST = \_SB.CP00._PPC + Debug = "Programming Current P-state: " + Debug = NPST } /* @@ -163,51 +163,51 @@ // Wifi Button Event Method (_Q07) { - Store ("Wifi Button Event 0x07", Debug) + Debug = "Wifi Button Event 0x07" } // Thermal Event Method (_Q08) { - Store ("Thermal Event 0x08", Debug) + Debug = "Thermal Event 0x08" Notify(\_TZ.THRM, 0x80) } // Pstate Down Method (_Q0E) { - Store ("Pstate Event 0x0E", Debug) + Debug = "Pstate Event 0x0E" - Store(\_SB.CP00._PPC, Local0) - Subtract(PPCM, 0x01, Local1) + Local0 = \_SB.CP00._PPC + Local1 = PPCM - 1 - If(LLess(Local0, Local1)) { - Increment(Local0) + If (Local0 < Local1) { + Local0++ \PPCN () } - Store(Local0, NPST) + NPST = Local0 } // Pstate Up Method (_Q0F) { - Store ("Pstate Event 0x0F", Debug) - Store(\_SB.CP00._PPC, Local0) + Debug = "Pstate Event 0x0F" + Local0 = \_SB.CP00._PPC If(Local0) { - Decrement(Local0) + Local0-- \PPCN () } - Store(Local0, NPST) + NPST = Local0 } // AC Power Connected Method (_Q10, 0, NotSerialized) { - Store ("AC Insertion Event 0x10", Debug) - Store (One, \PWRS) + Debug = "AC Insertion Event 0x10" + \PWRS = 1 Notify (AC, 0x80) Notify (BATX, 0x80) \PNOT () @@ -216,8 +216,8 @@ // AC Power Removed Method (_Q11, 0, NotSerialized) { - Store ("AC Detach Event 0x11", Debug) - Store (Zero, \PWRS) + Debug = "AC Detach Event 0x11" + \PWRS = 0 Notify (AC, 0x80) Notify (BATX, 0x80) \PNOT () @@ -226,7 +226,7 @@ // Battery State Change - Attach Event Method (_Q12, 0, NotSerialized) { - Store ("Battery Insertion Event 0x12", Debug) + Debug = "Battery Insertion Event 0x12" Notify (BATX, 0x81) Notify (BATX, 0x80) @@ -236,7 +236,7 @@ // Battery State Change - Detach Event Method (_Q13, 0, NotSerialized) { - Store ("Battery Detach Event 0x13", Debug) + Debug = "Battery Detach Event 0x13" Notify (BATX, 0x81) Notify (BATX, 0x80) @@ -247,7 +247,7 @@ // Battery State Change Event Method (_Q14, 0, NotSerialized) { - Store ("Battery State Change Event 0x14", Debug) + Debug = "Battery State Change Event 0x14" Notify (BATX, 0x80) } @@ -255,9 +255,9 @@ // Lid Switch Event Method (_Q06) { - Store ("Lid Switch Event 0x06", Debug) + Debug = "Lid Switch Event 0x06" sleep(20) - Store (LIDF, \LIDS) + \LIDS = LIDF Notify (\_SB.LID0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc90fb7707c07f2f364e1fdd710fe52522e8ab5e Gerrit-Change-Number: 46103 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020