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Change in coreboot[master]: cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4
by Julius Werner (Code Review) 18 Feb '21

18 Feb '21

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47827 to review the following change. Change subject: cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4 ...................................................................... cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4 cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename field to be aligned upwards to the next 16-byte boundary. This was presumably done to align the file contents (which used to come immediately after the filename field). However, this hasn't really worked right ever since we introduced CBFS attributes. Attributes come between the filename and the contents, so what this code currently does is fill up the filename field with extra NUL-bytes to the boundary, and then just put the attributes behind it with whatever size they may be. The file contents don't end up with any alignment guarantee and the filename field is just wasting space. This patch removes the old FILENAME_ALIGN, and instead adds a new alignment of 4 for the attributes. 4 seems like a reasonable alignment to enforce since all existing attributes (with the exception of weird edge cases with the padding attribute) already use sizes divisible by 4 anyway, and the common attribute header fields have a natural alignment of 4. This means file contents will also have a minimum alignment guarantee of 4 -- files requiring a larger guarantee can still be added with the --alignment flag as usual. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I43f3906977094df87fdc283221d8971a6df01b53 --- M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfstool.c 3 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47827/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index c31d995..7cdea26 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -115,6 +115,9 @@ uint8_t data[0]; } __packed; +/* All attribute sizes must be divisible by this! */ +#define CBFS_ATTRIBUTE_ALIGN 4 + /* Depending on how the header was initialized, it may be backed with 0x00 or * 0xff. Support both. */ enum cbfs_file_attr_tag { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index c7531d6..20df20b 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -34,10 +34,6 @@ * removing said guarantees. */ -/* The file name align is not defined in CBFS spec -- only a preference by - * (old) cbfstool. */ -#define CBFS_FILENAME_ALIGN (16) - static const char *lookup_name_by_type(const struct typedesc_t *desc, uint32_t type, const char *default_value) { @@ -70,7 +66,7 @@ size_t cbfs_calculate_file_header_size(const char *name) { return (sizeof(struct cbfs_file) + - align_up(strlen(name) + 1, CBFS_FILENAME_ALIGN)); + align_up(strlen(name) + 1, CBFS_ATTRIBUTE_ALIGN)); } /* Only call on legacy CBFSes possessing a master header. */ @@ -1836,6 +1832,7 @@ uint32_t tag, uint32_t size) { + assert(IS_ALIGNED(size, CBFS_ATTRIBUTE_ALIGN)); struct cbfs_file_attribute *attr, *next; next = cbfs_file_first_attr(header); do { diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 68c2c22..8df0fa1 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -740,7 +740,8 @@ if (param.padding) { const uint32_t hs = sizeof(struct cbfs_file_attribute); - uint32_t size = MAX(hs, param.padding); + uint32_t size = ALIGN_UP(MAX(hs, param.padding), + CBFS_ATTRIBUTE_ALIGN); INFO("Padding %d bytes\n", size); struct cbfs_file_attribute *attr = (struct cbfs_file_attribute *)cbfs_add_file_attr( -- To view, visit https://review.coreboot.org/c/coreboot/+/47827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f3906977094df87fdc283221d8971a6df01b53 Gerrit-Change-Number: 47827 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cbfstool: Ensure attributes always come last in the metadata
by Julius Werner (Code Review) 18 Feb '21

18 Feb '21

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47824 ) Change subject: cbfstool: Ensure attributes always come last in the metadata ...................................................................... cbfstool: Ensure attributes always come last in the metadata In a rare placement edge case when adding a file with alignment requirements, cbfstool may need to generate a CBFS header that's slightly larger than it needs to be. The way we do this is by just increasing the data offset field in the CBFS header until the data falls to the desired value. This approach works but it may confuse parsing code in the presence of CBFS attributes. Normally, the whole area between the attribute offset and the data offset is filled with valid attributes written back to back, but when this header expansion occurs the attributes are followed by some garbage data (usually 0xff). Parsers are resilient against this but may show unexpected error messages. This patch solves the problem by moving the attribute offset forwards together with the data offset, so that the total area used for attributes doesn't change. Instead, the filename field becomes the expanded area, which is a closer match to how this worked when it was originally implemented (before attributes existed) and is less confusing for parsers since filenames are zero-terminated anyway. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I3dd503dd5c9e6c4be437f694a7f8993a57168c2b --- M util/cbfstool/cbfs_image.c 1 file changed, 19 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47824/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index a51f941..c7531d6 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -666,15 +666,28 @@ len = content_offset - addr - header_size; memcpy(entry, header, header_size); if (len != 0) { - /* the header moved backwards a bit to accommodate cbfs_file + /* + * The header moved backwards a bit to accommodate cbfs_file * alignment requirements, so patch up ->offset to still point - * to file data. + * to file data. Move attributes forward so the end of the + * attribute list still matches the end of the metadata. */ + uint32_t offset = ntohl(entry->offset); + uint32_t attrs = ntohl(entry->attributes_offset); DEBUG("|..|header|content|... <use offset to create entry>\n"); - DEBUG("before: offset=0x%x\n", ntohl(entry->offset)); - // TODO reset expanded name buffer to 0xFF. - entry->offset = htonl(ntohl(entry->offset) + len); - DEBUG("after: offset=0x%x\n", ntohl(entry->len)); + DEBUG("before: attr_offset=0x%x, offset=0x%x\n", attrs, offset); + if (attrs == 0) { + memset((uint8_t *)entry + offset, 0, len); + } else { + uint8_t *p = (uint8_t *)entry + attrs; + memmove(p + len, p, offset - attrs); + memset(p, 0, len); + attrs += len; + entry->attributes_offset = htonl(attrs); + } + offset += len; + entry->offset = htonl(offset); + DEBUG("after: attr_offset=0x%x, offset=0x%x\n", attrs, offset); } // Ready to fill data into entry. -- To view, visit https://review.coreboot.org/c/coreboot/+/47824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dd503dd5c9e6c4be437f694a7f8993a57168c2b Gerrit-Change-Number: 47824 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: SMBIOS: Update smbios.h
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44850 ) Change subject: SMBIOS: Update smbios.h ...................................................................... SMBIOS: Update smbios.h Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add support for CXL 2.0. add EDSFF slot types Type 17: add new memory device types DDR5 and LPDDR5 Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..a91f6a6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -174,6 +174,8 @@ MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, MEMORY_TYPE_HBM = 0x20, MEMORY_TYPE_HBM2 = 0x21, + MEMORY_TYPE_DDR5 = 0x22, + MEMORY_TYPE_LPDDR5 = 0x23, } smbios_memory_type; typedef enum { @@ -664,6 +666,11 @@ SlotTypePciExpressMini52pinWithBSKO = 0x21, SlotTypePciExpressMini52pinWithoutBSKO = 0x22, SlotTypePciExpressMini76pin = 0x23, + SlotTypePciExpressGen4SFF8639 = 0x24, + SlotTypePciExpressGen5SFF8639 = 0x25, + SlotTypeOcpNic3SFF = 0x26, + SlotTypeOcpNic3LFF = 0x27, + SlotTypeOcpNicPriorTo3 = 0x28, SlotTypePC98C20 = 0xA0, SlotTypePC98C24 = 0xA1, SlotTypePC98E = 0xA2, @@ -692,7 +699,16 @@ SlotTypePciExpressGen4x2 = 0xBA, SlotTypePciExpressGen4x4 = 0xBB, SlotTypePciExpressGen4x8 = 0xBC, - SlotTypePciExpressGen4x16 = 0xBD + SlotTypePciExpressGen4x16 = 0xBD, + SlotTypePciExpressGen5 = 0xBE, + SlotTypePciExpressGen5x1 = 0xBF, + SlotTypePciExpressGen5x2 = 0xC0, + SlotTypePciExpressGen5x4 = 0xC1, + SlotTypePciExpressGen5x8 = 0xC2, + SlotTypePciExpressGen5x16 = 0xC3, + SlotTypePciExpressGen6 = 0xC4, + SlotTypeEDSFFE1 = 0xC5, + SlotTypeEDSFFE3 0xC6 }; /* System Slots - Slot Data Bus Width. */ @@ -744,6 +760,9 @@ #define SMBIOS_SLOT_HOTPLUG (1 << 1) #define SMBIOS_SLOT_SMBUS (1 << 2) #define SMBIOS_SLOT_BIFURCATION (1 << 3) +#define SMBIOS_SLOT_ASYNC (1 << 4) +#define SMBIOS_SLOT_CXL_1 (1 << 5) +#define SMBIOS_SLOT_CXL_2 (1 << 6) struct slot_peer_groups { u16 peer_seg_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/44850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Gerrit-Change-Number: 44850 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46283 ) Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..5a394c6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -105,18 +105,18 @@ pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); + mchbar32_or(SAPMCTL, (1 << 9) | (1 << 10)); /* Enable SA Clock Gating */ - MCHBAR32_OR(SAPMCTL, 1); + mchbar32_or(SAPMCTL, 1); /* GPU RC6 workaround for sighting 366252 */ - MCHBAR32_OR(SSKPD_HI, 1 << 31); + mchbar32_or(SSKPD_HI, 1 << 31); /* VLW (Virtual Legacy Wire?) */ - MCHBAR32_AND(0x6120, ~(1 << 0)); + mchbar32_unset(0x6120, (1 << 0)); - MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); + mchbar32_or(INTRDIRCTL, (1 << 4) | (1 << 5)); } static void start_peg_link_training(void) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 26c5306..1550253 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -18,13 +18,13 @@ pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_or(PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_or(SAPMCTL, 1 << 31); /* SA PM */ + mchbar32_or(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_or(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_or(REQLIM, 1 << 31); + mchbar32_or(DMIVCLIM, 1 << 31); + mchbar32_or(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 541bf73..db768a8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -359,10 +359,10 @@ * * FIXME: Never clock gate on Ivy Bridge stepping A0! */ - MCHBAR32_OR(PEGCTL, 1); + mchbar32_or(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } else { - MCHBAR32_AND(PEGCTL, ~1); + mchbar32_unset(PEGCTL, 1); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..4c6c284 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -190,11 +190,11 @@ stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + mchbar32_unset_and_set(addr, 0x00003c00, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + mchbar32_unset_and_set(addr, 0x000f0000, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -254,7 +254,7 @@ MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); + mchbar32_or(addr, 0x00020000); dram_odt_stretch(ctrl, channel); @@ -271,7 +271,7 @@ printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + mchbar32_or(TC_RFP_ch(channel), 0xff); /* Self-refresh timing parameters */ reg = 0; @@ -652,19 +652,19 @@ MCHBAR32(MC_INIT_STATE_G) = reg; /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + mchbar32_unset(MC_INIT_STATE_G, 2); /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + mchbar32_or(MC_INIT_STATE_G, 2); /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + mchbar32_or(MC_INIT_STATE_G, 4); /* XXX Wait 20ns */ udelay(1); @@ -957,10 +957,10 @@ } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x200000); wait_for_iosav(channel); @@ -2637,15 +2637,15 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + mchbar32_or(TC_RWP_ch(channel), 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2678,10 +2678,10 @@ wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x00200000); MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); @@ -2723,7 +2723,7 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); } FOR_ALL_POPULATED_CHANNELS { @@ -2747,7 +2747,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); } return 0; } @@ -2978,11 +2978,11 @@ iosav_run_once(channel); wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); } /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); @@ -3985,8 +3985,8 @@ FOR_ALL_POPULATED_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + mchbar32_unset_and_set(GDCRCMDDEBUGMUXCFG_Cz_S(channel), + 0x3f000000, rege3c_b24[i] << 24); udelay(2); @@ -4053,7 +4053,7 @@ FOR_ALL_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); } @@ -4423,7 +4423,7 @@ FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + mchbar32_or(TC_RAP_ch(channel), 0x20000000); } udelay(1); @@ -4463,7 +4463,7 @@ int channel; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + mchbar32_unset(TC_RAP_ch(channel), 0x20000000); } } @@ -4487,7 +4487,7 @@ MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + mchbar32_unset_and_set(TC_OTHP_ch(channel), 0x00003000, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,14 +4522,14 @@ } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); - MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); + mchbar32_unset_and_set(MEM_TRML_THRESHOLDS_CONFIG, 0x00ffffff, 0x00e4d5d0); + mchbar32_unset(MEM_TRML_INTERRUPT, 0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + mchbar32_unset_and_set(TC_RFP_ch(channel), (3 << 16), 1 << 16); - MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + mchbar32_or(MC_INIT_STATE_G, 1); + mchbar32_or(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel */ @@ -4555,7 +4555,7 @@ /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + mchbar32_unset_and_set(SSKPD, 3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } @@ -4586,11 +4586,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + mchbar32_or(TC_RWP_ch(channel), 0x08000000); FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x00200000); } printram("CPE\n"); @@ -4646,7 +4646,7 @@ MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index c86b524..217b186 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -50,16 +50,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #include "registers/epbar.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/46283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Gerrit-Change-Number: 46283 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: crossgcc: Upgrade GCC to 10.1.0
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42251 ) Change subject: crossgcc: Upgrade GCC to 10.1.0 ...................................................................... crossgcc: Upgrade GCC to 10.1.0 nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore. Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.1.0_gnat.patch R util/crossgcc/patches/gcc-10.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 9 files changed, 2 insertions(+), 21,441 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

9 41

Change in coreboot[master]: nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46279 ) Change subject: nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I89fe15143abcbb74abae6ebf126b219ed88b4153 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 2 files changed, 282 insertions(+), 292 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46279/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 617ce11..5e5f473 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -36,7 +36,7 @@ { u8 i, j; u32 reg32; - MCHBAR16_OR(0xc1c, (1 << 15)); + mchbar16_or(0xc1c, (1 << 15)); static const u32 clkxtab[6][3][13] = { /* MEMCLK 400 N/A */ @@ -108,7 +108,7 @@ } MCHBAR32(0xc50) = reg32; MCHBAR32(0xc54) = clkxtab[i][j][2]; - MCHBAR8_OR(0xc08, (1 << 7)); + mchbar8_or(0xc08, (1 << 7)); MCHBAR32(0x6d8) = clkxtab[i][j][3]; MCHBAR32(0x6e0) = clkxtab[i][j][3]; MCHBAR32(0x6dc) = clkxtab[i][j][4]; @@ -126,29 +126,29 @@ static void setioclk_dram(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; - MCHBAR16_OR(0x1c0, 0x200); - MCHBAR16_OR(0x1c0, 0x100); - MCHBAR16_OR(0x1c0, 0x20); - MCHBAR16_AND(0x1c0, ~1); + mchbar16_or(0x1c0, 0x200); + mchbar16_or(0x1c0, 0x100); + mchbar16_or(0x1c0, 0x20); + mchbar16_unset(0x1c0, 1); switch (s->selected_timings.mem_clk) { default: case MEM_CLOCK_800MHz: case MEM_CLOCK_1066MHz: - MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2); - MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0); + mchbar8_unset_and_set(0x5d9, 0x2, 0x2); + mchbar8_unset_and_set(0x9d9, 0x2, 0x2); + mchbar8_unset_and_set(0x189, 0xf0, 0xc0); + mchbar8_unset_and_set(0x189, 0xf0, 0xe0); + mchbar8_unset_and_set(0x189, 0xf0, 0xa0); break; case MEM_CLOCK_667MHz: case MEM_CLOCK_1333MHz: - MCHBAR8_AND(0x5d9, ~0x2); - MCHBAR8_AND(0x9d9, ~0x2); - MCHBAR8_AND_OR(0x189, ~0xf0, 0x40); + mchbar8_unset(0x5d9, 0x2); + mchbar8_unset(0x9d9, 0x2); + mchbar8_unset_and_set(0x189, 0xf0, 0x40); break; } - MCHBAR32_OR(0x594, 1 << 31); - MCHBAR32_OR(0x994, 1 << 31); + mchbar32_or(0x594, 1 << 31); + mchbar32_or(0x994, 1 << 31); } static void launch_dram(struct sysinfo *s) @@ -236,84 +236,84 @@ MCHBAR32(0x400*i + 0x220) = launch1; MCHBAR32(0x400*i + 0x224) = launch2; MCHBAR32(0x400*i + 0x21c) = 0; - MCHBAR32_OR(0x400*i + 0x248, 1 << 23); + mchbar32_or(0x400*i + 0x248, 1 << 23); } - MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000); - MCHBAR32_OR(0x2c0, 0x1e0); - MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc); + mchbar32_unset_and_set(0x2c0, 0x58000000, 0x48000000); + mchbar32_or(0x2c0, 0x1e0); + mchbar32_unset_and_set(0x2c4, 0xf, 0xc); if (s->spd_type == DDR3) - MCHBAR32_OR(0x2c4, 0x100); + mchbar32_or(0x2c4, 0x100); } static void clkset0(u8 ch, const struct dll_setting *setting) { - MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440, + mchbar32_unset_and_set(0x260 + (channel << 10), 0xf00000, (setting->clk_delay << 14) | (setting->db_sel << 6) | (setting->db_en << 10)); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x581, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x581, 0xf, setting->tap); } static void clkset1(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880, + mchbar16_unset_and_set(0x400*i + 0x260, 0x3fe, (setting->clk_delay << 16) | (setting->db_sel << 7) | (setting->db_en << 11)); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x582, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x582, 0xf, setting->tap); } static void ctrlset0(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000, + mchbar16_unset_and_set(0x400*i + 0x265, 0x3f00, (setting->clk_delay << 24) | (setting->db_sel << 20) | (setting->db_en << 21)); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x584, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x584, 0xf, setting->tap); } static void ctrlset1(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000, + mchbar8_unset_and_set(0x400*ch + 0x500 + lane * 4 + rank, 0x7f, (setting->clk_delay << 27) | (setting->db_sel << 22) | (setting->db_en << 23)); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x585, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x585, 0xf, setting->tap); } static void ctrlset2(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4)), (setting->clk_delay << 14) | (setting->db_sel << 12) | (setting->db_en << 13)); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x586, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x586, 0xf, setting->tap); } static void ctrlset3(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4)), (setting->clk_delay << 10) | (setting->db_sel << 8) | (setting->db_en << 9)); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x587, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x587, 0xf, setting->tap); } static void cmdset(u8 ch, const struct dll_setting *setting) { - MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4); - MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60, + mchbar8_unset_and_set(0x400*ch + 0x598, 0x30, setting->clk_delay << 4); + mchbar16_unset_and_set(0x400*i + 0x320, 0xffff, (setting->db_sel << 5) | (setting->db_en << 6)); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x580, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x580, 0xf, setting->tap); } /** @@ -324,16 +324,16 @@ { int rank; - MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)), + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4 + 1)), setting->coarse << (lane * 4 + 1)); for (rank = 0; rank < 4; rank++) { - MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane), + mchbar8_unset_and_set(0x400*ch + 0x594, 0x60, (setting->db_en << (9 + lane)) | (setting->db_sel << lane)); - MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4, - ~(0x3 << (16 + lane * 2)), + mchbar32_unset_and_set(0x400*ch + 0x5c8 + rank * 4, + 3 << (16 + lane * 2)), setting->clk_delay << (16+lane * 2)); MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) = @@ -346,18 +346,18 @@ void dqset(u8 ch, u8 lane, const struct dll_setting *setting) { int rank; - MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)), + mchbar32_unset_and_set(0x400 * ch + 0x5b4 + rank * 4, (0x201 << lane), setting->coarse << (lane * 4)); for (rank = 0; rank < 4; rank++) { - MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane), + mchbar32_unset_and_set(0x400*ch + 0x598, 0x18c00000, (setting->db_en << (9 + lane)) | (setting->db_sel << lane)); - MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4, - ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane)); + mchbar32_unset_and_set(0x400 * ch + 0x5c8 + rank * 4, + 3 << lane * 2, setting->clk_delay << (2 * lane)); - MCHBAR8_AND_OR(0x400*ch + 0x500 + lane * 4 + rank, ~0x7f, + mchbar32_unset_and_set(0x400*i + addr[j], 0xff000, (setting->pi << 4) | setting->tap); } } @@ -498,12 +498,12 @@ } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR8_OR(0x400*i + 0x26f, 0x3); - MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2); + mchbar8_or(0x400*i + 0x26f, 0x3); + mchbar8_unset_and_set(0x400*i + 0x228, 0x7, 0x2); /* tWL - x ?? */ - MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4); - MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas); - MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00, + mchbar8_unset_and_set(0x400*i + 0x240, 0xf0, 0 << 4); + mchbar8_unset_and_set(0x400*i + 0x240, 0xf, adjusted_cas); + mchbar16_unset_and_set(C0CKTX, 0x00030880, (adjusted_cas + 9) << 8); reg16 = (s->selected_timings.tRAS << 11) | @@ -539,10 +539,10 @@ MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | s->selected_timings.tRFC; - MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe, + mchbar16_unset_and_set(C0CKTX, 0xc440, (s->spd_type == DDR2 ? 100 : 256) << 1); MCHBAR8(0x400*i + 0x264) = 0xff; - MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f, + mchbar8_unset_and_set(0x400*i + addr[j], 1, s->selected_timings.tRAS); MCHBAR16(0x400*i + 0x244) = 0x2310; @@ -555,7 +555,7 @@ break; } - MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1); + mchbar8_unset_and_set(0x400*i + 0x246, 0x1f, (reg8 << 2) | 1); fsb = fsb_to_ps[s->selected_timings.fsb_clk]; ddr = ddr_to_ps[s->selected_timings.mem_clk]; @@ -566,7 +566,7 @@ ddr_to_mhz(s->selected_timings.mem_clk)) > 2) { reg32 |= 1 << 24; } - MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32); + mchbar32_unset_and_set(0x400*i + 0x248, 0x0f001f00, reg32); if (twl > 2) flag1 = 1; @@ -582,13 +582,13 @@ } reg16 |= flag1 << 8; reg16 |= flag2 << 9; - MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16); + mchbar16_unset_and_set(0x400*i + 0x24d, 0x1ff, reg16); MCHBAR16(0x400*i + 0x25e) = 0x15a5; - MCHBAR32_AND(0x400*i + 0x265, ~0x1f); - MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff, + mchbar32_unset(0x400*i + 0x265, 0x1f); + mchbar8_unset_and_set(0x400*i + 0x25d, 0x3f, (0x3f << 14) | lut1[s->selected_timings.mem_clk]); - MCHBAR8_OR(0x400*i + 0x274, 1); - MCHBAR8_AND(0x400*i + 0x24c, ~0x3); + mchbar8_or(0x400*i + 0x274, 1); + mchbar8_unset(0x400*i + 0x24c, 0x3); reg16 = 0; if (s->spd_type == DDR2) { @@ -620,36 +620,36 @@ reg16 &= 0x7; reg16 += twl + 9; reg16 <<= 10; - MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16); - MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13); - MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a); + mchbar16_unset_and_set(0x400*i + 0x24d, 0x7c00, reg16); + mchbar8_unset_and_set(0x400*i + 0x267, 0x3f, 0x13); + mchbar8_unset_and_set(0x400*i + 0x268, 0xff, 0x4a); reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; reg16 += 2 << 12; reg16 |= (0x15 << 6) | 0x1f; - MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16); + mchbar16_unset_and_set(0x400*i + 0x26d, 0x7fff, reg16); reg32 = (1 << 25) | (6 << 27); - MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32); - MCHBAR8_AND(0x400*i + 0x271, ~0x80); - MCHBAR8_AND(0x400*i + 0x274, ~0x6); + mchbar32_unset_and_set(0x400*i + 0x269, 0xfa300000, reg32); + mchbar8_unset(0x400*i + 0x271, 0x80); + mchbar8_unset(0x400*i + 0x274, 0x6); } // END EACH POPULATED CHANNEL reg16 = 0x1f << 5; reg16 |= 0xe << 10; - MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16); - MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540); - MCHBAR8_OR(0x129, 0x1f); - MCHBAR8_OR(0x12c, 0xa0); - MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11); - MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11); - MCHBAR8_AND(0x246, ~0x10); - MCHBAR8_AND(0x646, ~0x10); + mchbar16_unset_and_set(0x125, 0x3fe0, reg16); + mchbar16_unset_and_set(0x127, 0x7ff, 0x540); + mchbar8_or(0x129, 0x1f); + mchbar8_or(0x12c, 0xa0); + mchbar32_unset_and_set(0x241, 0x1ffff, 0x11); + mchbar32_unset_and_set(0x641, 0x1ffff, 0x11); + mchbar8_unset(0x246, 0x10); + mchbar8_unset(0x646, 0x10); MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); - MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4); + mchbar8_unset_and_set(0x12d, 0xf0, reg8 << 4); reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); - MCHBAR8_AND_OR(0x12d, ~0xf, reg8); + mchbar8_unset_and_set(0x12d, 0xf, reg8); MCHBAR8(0x12f) = 0x4c; reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); if (s->spd_type == DDR3) { @@ -660,8 +660,8 @@ reg16 &= 0x1ff; reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); } - MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32); - MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2); + mchbar32_unset_and_set(0x6c0, 0xffffff00, reg32); + mchbar8_unset_and_set(0x6c4, 0x7, 0x2); } static void program_dll(struct sysinfo *s) @@ -673,11 +673,11 @@ const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 }; - MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); - MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); - MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f); - MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100); - MCHBAR8_AND_OR(0x194, ~0x77, 0x33); + mchbar16_unset_and_set(0x180, 0x7e06, 0xc04); + mchbar16_unset_and_set(0x182, 0x3ff, 0xc8); + mchbar16_unset_and_set(0x18a, 0x1f1f, 0x0f0f); + mchbar16_unset_and_set(0x1b4, 0x8020, 0x100); + mchbar8_unset_and_set(0x194, 0x77, 0x33); switch (s->selected_timings.mem_clk) { default: case MEM_CLOCK_667MHz: @@ -691,48 +691,48 @@ reg16 = (0x7 << 9) | 0x7; break; } - MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16); - MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010); + mchbar16_unset_and_set(0x19c, 0x1e0f, reg16); + mchbar16_unset_and_set(0x19c, 0x2030, 0x2010); udelay(1); - MCHBAR16_AND(0x198, ~0x100); + mchbar16_unset(0x198, 0x100); - MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd); + mchbar16_unset_and_set(0x1c8, 0x1f, 0xd); udelay(1); - MCHBAR8_AND(0x190, ~1); + mchbar8_unset(0x190, 1); udelay(1); // 533ns - MCHBAR32_AND(0x198, ~0x11554000); + mchbar32_unset(0x198, 0x11554000); udelay(1); - MCHBAR32_AND(0x198, ~0x1455); + mchbar32_unset(0x198, 0x1455); udelay(1); - MCHBAR8_AND(0x583, ~0x1c); - MCHBAR8_AND(0x983, ~0x1c); + mchbar8_unset(0x583, 0x1c); + mchbar8_unset(0x983, 0x1c); udelay(1); // 533ns - MCHBAR8_AND(0x583, ~0x3); - MCHBAR8_AND(0x983, ~0x3); + mchbar8_unset(0x583, 0x3); + mchbar8_unset(0x983, 0x3); udelay(1); // 533ns // ME related - MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, + mchbar32_unset_and_set(0x400*ch + 0x59c, 0x18c00000, s->spd_type == DDR2 ? 0x551803 : 0x555801); - MCHBAR16_AND(0x1b4, ~0x800); + mchbar16_unset(0x1b4, 0x800); if (s->spd_type == DDR2) { - MCHBAR8_OR(0x1a8, 0xf0); + mchbar8_or(0x1a8, 0xf0); } else { /* DDR3 */ reg8 = 0x9; /* 0x9 << 4 ?? */ if (s->dimms[0].ranks == 2) reg8 &= ~0x80; if (s->dimms[3].ranks == 2) reg8 &= ~0x10; - MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8); + mchbar8_unset_and_set(0x1a8, 0xf0, reg8); } FOR_EACH_CHANNEL(i) { reg16 = 0; if ((s->spd_type == DDR3) && (i == 0)) reg16 = (0x3 << 12); - MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16); + mchbar16_unset_and_set(0x400*i + 0x59c, 0x3000, reg16); reg32 = 0; FOR_EACH_RANK_IN_CHANNEL(r) { @@ -740,8 +740,8 @@ reg32 |= 0x111 << r; } - MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32); - MCHBAR8_AND(0x400*i + 0x594, ~1); + mchbar32_unset_and_set(0x400*i + 0x59c, 0xfff, reg32); + mchbar8_unset(0x400*i + 0x594, 1); if (s->spd_type == DDR2) { if (!CHANNEL_IS_POPULATED(s->dimms, i)) { @@ -766,13 +766,13 @@ } else { die("Unhandled case\n"); } - MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, + mchbar32_unset_and_set(0x400*i + 0x269, 0x000fffff, (u32)(reg8 << 24)); } else { /* DDR3 */ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { - MCHBAR8_AND(0x400 * i + 0x5a0 + 3, - ~rank2clken[r + i * 4]); + mchbar8_unset(0x400 * i + 0x5a0 + 3, + rank2clken[r + i * 4]); } } @@ -780,24 +780,24 @@ } // END EACH CHANNEL if (s->spd_type == DDR2) { - MCHBAR8_OR(0x1a8, 1); - MCHBAR8_AND(0x1a8, ~0x4); + mchbar8_or(0x1a8, 1); + mchbar8_unset(0x1a8, 0x4); } else { /* DDR3 */ - MCHBAR8_AND(0x1a8, ~1); - MCHBAR8_OR(0x1a8, 0x4); + mchbar8_unset(0x1a8, 1); + mchbar8_or(0x1a8, 0x4); } // Update DLL timing - MCHBAR8_AND(0x1a4, ~0x80); - MCHBAR8_OR(0x1a4, 0x40); - MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400); + mchbar8_unset(0x1a4, 0x80); + mchbar8_or(0x1a4, 0x40); + mchbar16_unset_and_set(0x5f0, 0x400, 0x400); FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); - MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); - MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, + mchbar16_unset_and_set(0x400*i + 0x5f0, 0x3fc, 0x3fc); + mchbar32_unset(0x400*i + 0x5fc, 0xcccccccc); + mchbar32_unset_and_set(0xfa0, 0x20002, s->spd_type == DDR2 ? 0x70 : 0x60); - MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff, + mchbar16_unset_and_set(0x400*ch + 0x5a0, 0xc440, s->spd_type == DDR2 ? 0x5555 : 0xa955); } @@ -833,12 +833,12 @@ } // XXX if not async mode - MCHBAR16_AND(0x180, ~0x8200); - MCHBAR8_OR(0x180, 0x4); + mchbar16_unset(0x180, 0x8200); + mchbar8_or(0x180, 0x4); j = 0; for (i = 0; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0xffffffff) { @@ -858,8 +858,8 @@ j = 0; i++; for (; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x4); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x4); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0) { @@ -868,8 +868,8 @@ } } for (; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0xffffffff) { @@ -881,8 +881,8 @@ } } if (j < 2) { - MCHBAR8_AND(0x1c8, ~0x1f); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset(0x1c8, 0x1f); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; j = 2; @@ -890,7 +890,7 @@ } if (j < 2) { - MCHBAR8_AND(0x1c8, ~0x1f); + mchbar8_unset(0x1c8, 0x1f); async = 1; } @@ -917,7 +917,7 @@ break; } - MCHBAR8_AND(0x180, ~0x80); + mchbar8_unset(0x180, 0x80); if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz @@ -927,8 +927,8 @@ i = (i + 10) % 14; else /* DDR3 */ i = (i + 3) % 12; - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; } @@ -942,7 +942,7 @@ MCHBAR8(0x188) = reg8; if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) - MCHBAR8_OR(0x18c, 1); + mchbar8_or(0x18c, 1); } static void select_default_dq_dqs_settings(struct sysinfo *s) @@ -1091,65 +1091,65 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { for (j = 0; j < 6; j++) { if (j == 0) { - MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000, + mchbar32_unset_and_set(0x400*i + addr[j], 0xff000, 0xaa000); - MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, + mchbar32_unset_and_set(C0DQSDQRyTX3(rank), ((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), 0x6666); for (k = 0; k < 8; k++) { - MCHBAR32_AND_OR(0x400*i + addr[j] + + mchbar32_unset_and_set(0x400*i + addr[j] + 0xe + (k << 2), - ~0x3f3f3f3f, x32a[k]); - MCHBAR32_AND_OR(0x400*i + addr[j] + + 0x3f3f3f3f, x32a[k]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x2e + (k << 2), - ~0x3f3f3f3f, x32a[k]); + 0x3f3f3f3f, x32a[k]); } } else { - MCHBAR16_AND_OR(0x400*i + addr[j], - ~0xf000, 0xa000); - MCHBAR16_AND_OR(0x400*i + addr[j] + 4, - ~0xffff, x378[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe, - ~0x3f3f3f3f, x382[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, - ~0x3f3f3f3f, x386[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, - ~0x3f3f3f3f, x38a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, - ~0x3f3f3f3f, x38e[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, - ~0x3f3f3f3f, x392[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, - ~0x3f3f3f3f, x396[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, - ~0x3f3f3f3f, x39a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, - ~0x3f3f3f3f, x39e[j]); + mchbar16_unset_and_set(0x400*i + addr[j], + 0xf000, 0xa000); + mchbar16_unset_and_set(0x400*i + addr[j] + 4, + 0xffff, x378[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0xe, + 0x3f3f3f3f, x382[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x12, + 0x3f3f3f3f, x386[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x16, + 0x3f3f3f3f, x38a[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x1a, + 0x3f3f3f3f, x38e[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x1e, + 0x3f3f3f3f, x392[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x22, + 0x3f3f3f3f, x396[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x26, + 0x3f3f3f3f, x39a[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x2a, + 0x3f3f3f3f, x39e[j]); } if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { - MCHBAR16_AND_OR(0x378 + 0x400 * i, - ~0xffff, 0xcccc); + mchbar16_unset_and_set(0x378 + 0x400 * i, + 0xffff, 0xcccc); } - MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); + mchbar8_unset_and_set(0x400*i + addr[j], 1, bit[j]); } reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36; - MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x45a, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x45e, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x462, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x466, 0x3f, reg8); } // END EACH POPULATED CHANNEL - MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00); - MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff); + mchbar32_unset_and_set(0x134, 0x63c00, 0x63c00); + mchbar16_unset_and_set(0x174, 0x63ff, 0x63ff); MCHBAR16(0x178) = 0x0135; - MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0); + mchbar32_unset_and_set(0x130, 0x7bdffe0, 0x7a9ffa0); if (!CHANNEL_IS_POPULATED(s->dimms, 0)) - MCHBAR32_AND(0x130, ~(1 << 27)); + mchbar32_unset(0x130, (1 << 27)); if (!CHANNEL_IS_POPULATED(s->dimms, 1)) - MCHBAR32_AND(0x130, ~(1 << 28)); + mchbar32_unset(0x130, (1 << 28)); - MCHBAR8_OR(0x130, 1); + mchbar8_or(0x130, 1); } static void program_odt(struct sysinfo *s) @@ -1209,7 +1209,7 @@ reg16 &= ~0xfff; reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778); MCHBAR16(0x400*i + 0x29c) = reg16; - MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00); + mchbar32_unset_and_set(0x400*i + 0x260, 0x70e3c00, 0x3063c00); } } @@ -1242,8 +1242,8 @@ * by the SPD. */ /* Set rank 0-3 populated */ - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000); - MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000); + mchbar32_unset_and_set(C0CKECTRL, 1, 0xf00000); + mchbar32_unset_and_set(C1CKECTRL, 1, 0xf00000); /* Set size of each rank to 128M */ MCHBAR16(C0DRA01) = 0x0101; MCHBAR16(C0DRA23) = 0x0101; @@ -1259,7 +1259,7 @@ /* In stacked mode the last present rank on ch1 needs to have its size doubled in c1drbx */ MCHBAR16(C1DRB3) = 0x0010; - MCHBAR8_OR(0x111, STACKED_MEM); + mchbar8_or(0x111, STACKED_MEM); MCHBAR32(0x104) = 0; MCHBAR16(0x102) = 0x400; MCHBAR8(0x110) = (2 << 5) | (3 << 3); @@ -1305,8 +1305,8 @@ data8 = (u8)mirror_shift_bit(data8, 4); } - MCHBAR8_AND_OR(0x271, ~0x3e, data8); - MCHBAR8_AND_OR(0x671, ~0x3e, data8); + mchbar8_unset_and_set(0x271, 0x3e, data8); + mchbar8_unset_and_set(0x671, 0x3e, data8); data32 = val; if (s->spd_type == DDR3 && (r & 1) && s->dimms[ch * 2 + (r >> 1)].mirrored) { @@ -1318,8 +1318,8 @@ read32((void *)((data32 | addr))); udelay(10); - MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); - MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); + mchbar8_unset_and_set(0x271, 0x3e, NORMALOP_CMD); + mchbar8_unset_and_set(0x671, 0x3e, NORMALOP_CMD); } static void jedec_ddr2(struct sysinfo *s) @@ -1545,22 +1545,22 @@ MCHBAR32(0x208) = c0dra; MCHBAR32(0x608) = c1dra; - MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0); - MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0); + mchbar8_unset_and_set(0x262, 0xf0, (rankpop0 << 4) & 0xf0); + mchbar8_unset_and_set(0x662, 0xf0, (rankpop1 << 4) & 0xf0); if (s->spd_type == DDR3) { FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { /* ZQCAL enable */ - MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26); + mchbar32_or(0x269 + 0x400 * ch, 1 << 26); } } if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) - MCHBAR8_OR(0x260, 1); + mchbar8_or(0x260, 1); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) - MCHBAR8_OR(0x660, 1); + mchbar8_or(0x660, 1); // DRB lastrank_ch1 = 0; @@ -1604,10 +1604,10 @@ size_me = ME_UMA_SIZEMB; if (s->stacked_mode) { - MCHBAR8_OR(0x111, STACKED_MEM); + mchbar8_or(0x111, STACKED_MEM); } else { - MCHBAR8_AND(0x111, ~STACKED_MEM); - MCHBAR8_OR(0x111, 1 << 4); + mchbar8_unset(0x111, STACKED_MEM); + mchbar8_or(0x111, 1 << 4); } if (s->stacked_mode) { @@ -1623,7 +1623,7 @@ /* Set ME UMA size in MiB */ MCHBAR16(0x100) = size_me; /* Set ME UMA Present bit */ - MCHBAR32_OR(0x111, 1); + mchbar32_or(0x111, 1); } dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2; } @@ -1753,21 +1753,21 @@ MCHBAR32(0xfbc) = 0xf; MCHBAR32(0xfc4) = 0xfe22244; MCHBAR8(0x12f) = 0x5c; - MCHBAR8_OR(0xfb0, 1); + mchbar8_or(0xfb0, 1); if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) - MCHBAR8_OR(0x12f, 0x2); + mchbar8_or(0x12f, 0x2); else - MCHBAR8_AND(0x12f, ~0x2); - MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0); + mchbar8_unset(0x12f, 0x2); + mchbar8_unset_and_set(0x6c0, 0xf0, 0xa0); MCHBAR32(0xfa8) = 0x30d400; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR8_OR(0x400*ch + 0x26c, 1); + mchbar8_or(0x400*ch + 0x26c, 1); MCHBAR32(0x400*ch + 0x278) = 0x88141881; MCHBAR16(0x400*ch + 0x27c) = 0x0041; MCHBAR8(0x400*ch + 0x292) = 0xf2; - MCHBAR16_OR(0x400*ch + 0x272, 0x100); - MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1); + mchbar16_or(0x400*ch + 0x272, 0x100); + mchbar8_unset_and_set(0x400*ch + 0x243, 0x2, 1); MCHBAR32(0x400*ch + 0x288) = 0x8040200; MCHBAR32(0x400*ch + 0x28c) = 0xff402010; MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; @@ -1775,7 +1775,7 @@ reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); - MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == + mchbar8_unset_and_set(0x400*i + 0x5d9, 0xf0, 0x2 | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz ? 0x20000 : 0)); reg32 = 0x219100c2; if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { @@ -1785,7 +1785,7 @@ } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { reg32 &= ~0x10000; } - MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32); + mchbar32_unset_and_set(0xfa4, 0x219100c3, reg32); reg32 = 0x44a00; switch (s->selected_timings.fsb_clk) { case FSB_CLOCK_1333MHz: @@ -1811,7 +1811,7 @@ reg32 = 0x8f038000; if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) reg32 &= ~0x4000000; - MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32); + mchbar32_unset_and_set(0x40, 0x8f038000, reg32); reg32 = 0x00013001; if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) reg32 |= 0x20000; @@ -1884,50 +1884,50 @@ MCHBAR32(0x14) = 0x0010691f; MCHBAR32(0x18) = 0xdf6437f7; MCHBAR32(0x1c) = 0x0; - MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000); - MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000); + mchbar32_unset_and_set(0x24, 0xe0000000, 0x60000000); + mchbar32_unset_and_set(0x44, 0x1fef0000, 0x6b0000); MCHBAR16(0x115) = (u16) reg1; - MCHBAR32_AND_OR(0x117, ~0xffffff, reg2); + mchbar32_unset_and_set(0x117, 0xffffff, reg2); MCHBAR8(0x124) = 0x7; // not sure if dummy reads are needed - MCHBAR16_AND_OR(0x12a, 0, 0x80); - MCHBAR8_AND_OR(0x12c, 0, 0xa0); - MCHBAR16_AND(0x174, ~(1 << 15)); - MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00); - MCHBAR8_AND(0x18c, ~0x8); - MCHBAR8_OR(0x192, 1); - MCHBAR8_OR(0x193, 0xf); - MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80); - MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii + mchbar16_unset_and_set(0x12a, 0xffff, 0x80); + mchbar8_unset_and_set(0x12c, 0xff, 0xa0); + mchbar16_unset(0x174, (1 << 15)); + mchbar16_unset_and_set(0x188, 0x1f00, 0x1f00); + mchbar8_unset(0x18c, 0x8); + mchbar8_or(0x192, 1); + mchbar8_or(0x193, 0xf); + mchbar16_unset_and_set(0x1b4, 0x480, 0x80); + mchbar16_unset_and_set(0x210, 0x1fff, 0x3f); // | clockgatingiii // non-aligned access: possible bug? - MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate); - MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f); - MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0); - MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70); + mchbar32_unset_and_set(0x6d1, 0xff03ff, 0x100 | clkgate); + mchbar8_unset_and_set(0x212, 0x7f, 0x7f); + mchbar32_unset_and_set(0x2c0, 0xffff0, 0xcc5f0); + mchbar8_unset_and_set(0x2c4, 0x70, 0x70); // non-aligned access: possible bug? - MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi + mchbar32_unset_and_set(0x2d1, 0xffffff, 0xff2831); // | clockgatingi MCHBAR32(0x2d4) = 0x40453600; MCHBAR32(0x300) = 0xc0b0a08; MCHBAR32(0x304) = 0x6040201; - MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405); + mchbar32_unset_and_set(0x30c, 0x43c0f, 0x41405); MCHBAR16(0x610) = reg3; MCHBAR16(0x612) = reg4; - MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000); + mchbar32_unset_and_set(0x62c, 0xc000000, 0x4000000); MCHBAR32(0xae4) = 0; - MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000); + mchbar32_unset_and_set(0xc00, 0xf0000, 0x10000); MCHBAR32(0xf00) = 0x393a3b3c; MCHBAR32(0xf04) = 0x3d3e3f40; MCHBAR32(0xf08) = 0x393a3b3c; MCHBAR32(0xf0c) = 0x3d3e3f40; - MCHBAR32_AND(0xf18, ~0xfff00001); + mchbar32_unset(0xf18, 0xfff00001); MCHBAR32(0xf48) = 0xfff0ffe0; MCHBAR32(0xf4c) = 0xffc0ff00; MCHBAR32(0xf50) = 0xfc00f000; MCHBAR32(0xf54) = 0xc0008000; - MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000); - MCHBAR32_AND(0xfac, ~0x80000000); - MCHBAR32_AND(0xfb8, ~0xff000000); - MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000); + mchbar32_unset_and_set(0xf6c, 0xffff0000, 0xffff0000); + mchbar32_unset(0xfac, 0x80000000); + mchbar32_unset(0xfb8, 0xff000000); + mchbar32_unset_and_set(0xfbc, 0x7f800, 0xf000); MCHBAR32(0x1104) = 0x3003232; MCHBAR32(0x1108) = 0x74; if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) @@ -1943,31 +1943,31 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { MCHBAR8(0x400*ch + 0x239) = twl + 15; MCHBAR16(0x400*ch + 0x23c) = x23c; - MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033); - MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16); + mchbar32_unset_and_set(0x400*ch + 0x248, 0x706033, 0x406033); + mchbar32_unset_and_set(0x400*ch + 0x260, (1 << 16), 1 << 16); MCHBAR8(0x400*ch + 0x264) = x264; - MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592); - MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e); + mchbar8_unset_and_set(0x400*ch + 0x592, 0x3f, 0x3c & x592); + mchbar8_unset_and_set(0x400*ch + 0x593, 0x1f, 0x1e); } for (lane = 0; lane < 8; lane++) - MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3)); + mchbar8_unset(0x561 + (lane << 2), (1 << 3)); } static void software_ddr3_reset(struct sysinfo *s) { printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); - MCHBAR8_OR(0x1a8, 0x02); - MCHBAR8_AND(0x5da, ~0x80); - MCHBAR8_AND(0x1a8, ~0x02); - MCHBAR8_AND_OR(0x5da, ~0x03, 1); + mchbar8_or(0x1a8, 0x02); + mchbar8_unset(0x5da, 0x80); + mchbar8_unset(0x1a8, 0x02); + mchbar8_unset_and_set(0x5da, 0x03, 1); udelay(200); - MCHBAR8_AND(0x1a8, ~0x02); - MCHBAR8_OR(0x5da, 0x80); - MCHBAR8_AND(0x5da, ~0x80); + mchbar8_unset(0x1a8, 0x02); + mchbar8_or(0x5da, 0x80); + mchbar8_unset(0x5da, 0x80); udelay(500); - MCHBAR8_OR(0x5da, 0x03); - MCHBAR8_AND(0x5da, ~0x03); + mchbar8_or(0x5da, 0x03); + mchbar8_unset(0x5da, 0x03); /* After write leveling the dram needs to be reset and reinitialised */ jedec_ddr3(s); } @@ -1984,16 +1984,16 @@ | PMSTS_BOTH_SELFREFRESH; // Clear host clk gate reg - MCHBAR32_OR(0x1c, 0xffffffff); + mchbar32_or(0x1c, 0xffffffff); // Select type if (s->spd_type == DDR2) - MCHBAR8_AND(0x1a8, ~0x4); + mchbar8_unset(0x1a8, 0x4); else - MCHBAR8_OR(0x1a8, 0x4); + mchbar8_or(0x1a8, 0x4); // Set freq - MCHBAR32_AND_OR(0xc00, ~0x70, + mchbar32_unset_and_set(0x400*i + 0x5a0, 0x3f000000, (s->selected_timings.mem_clk << 4) | (1 << 10)); // Overwrite freq if chipset rejects it @@ -2046,36 +2046,36 @@ // IOBUFACT if (CHANNEL_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); - MCHBAR8_OR(0x5d8, 0x7); + mchbar8_unset_and_set(0x5dd, 0x3f, 0x3f); + mchbar8_or(0x5d8, 0x7); } if (CHANNEL_IS_POPULATED(s->dimms, 1)) { if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { - MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); - MCHBAR8_OR(0x5d8, 1); + mchbar8_unset_and_set(0x5dd, 0x3f, 0x3f); + mchbar8_or(0x5d8, 1); } - MCHBAR8_OR(0x9dd, 0x3f); - MCHBAR8_OR(0x9d8, 0x7); + mchbar8_or(0x9dd, 0x3f); + mchbar8_or(0x9d8, 0x7); } /* DDR3 reset */ if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { printk(BIOS_DEBUG, "DDR3 Reset.\n"); - MCHBAR8_AND(0x1a8, ~0x2); - MCHBAR8_OR(0x5da, 0x80); + mchbar8_unset(0x1a8, 0x2); + mchbar8_or(0x5da, 0x80); udelay(500); - MCHBAR8_AND(0x1a8, ~0x2); - MCHBAR8_AND(0x5da, ~0x80); + mchbar8_unset(0x1a8, 0x2); + mchbar8_unset(0x5da, 0x80); udelay(500); } // Pre jedec - MCHBAR8_OR(0x40, 0x2); + mchbar8_or(0x40, 0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR32_OR(0x400*ch + 0x260, 1 << 27); + mchbar32_or(0x400*ch + 0x260, 1 << 27); } - MCHBAR16_OR(0x212, 0xf000); - MCHBAR16_OR(0x212, 0xf00); + mchbar16_or(0x212, 0xf000); + mchbar16_or(0x212, 0xf00); printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset @@ -2096,7 +2096,7 @@ } // After JEDEC reset - MCHBAR8_AND(0x40, ~0x2); + mchbar8_unset(0x40, 0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { reg32 = (2 << 18); reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] @@ -2113,23 +2113,23 @@ [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8; } - MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); - MCHBAR8_AND(0x400*ch + 0x274, ~0x80); - MCHBAR8_OR(0x400*ch + 0x26c, 1); + mchbar32_unset_and_set(0x400*ch + 0x274, 0xfff00, reg32); + mchbar8_unset(0x400*ch + 0x274, 0x80); + mchbar8_or(0x400*ch + 0x26c, 1); MCHBAR32(0x400*ch + 0x278) = 0x88141881; MCHBAR16(0x400*ch + 0x27c) = 0x41; MCHBAR8(0x400*ch + 0x292) = 0xf2; - MCHBAR8_OR(0x400*ch + 0x271, 0xe); + mchbar8_or(0x400*ch + 0x271, 0xe); } - MCHBAR8_OR(0x2c4, 0x8); - MCHBAR8_OR(0x2c3, 0x40); - MCHBAR8_OR(0x2c4, 0x4); + mchbar8_or(0x2c4, 0x8); + mchbar8_or(0x2c3, 0x40); + mchbar8_or(0x2c4, 0x4); printk(BIOS_DEBUG, "Done post-jedec\n"); // Set DDR init complete FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); + mchbar32_or(0x400*ch + 0x268, 0xc0000000); } // Dummy reads @@ -2147,14 +2147,14 @@ // Finish rcven FOR_EACH_CHANNEL(ch) { - MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x2); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x4); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x8); + mchbar8_unset(0x400*ch + 0x5d8, 0xe); + mchbar8_or(0x400*ch + 0x5d8, 0x2); + mchbar8_or(0x400*ch + 0x5d8, 0x4); + mchbar8_or(0x400*ch + 0x5d8, 0x8); } - MCHBAR8_OR(0x5dc, 0x80); - MCHBAR8_AND(0x5dc, ~0x80); - MCHBAR8_OR(0x5dc, 0x80); + mchbar8_or(0x5dc, 0x80); + mchbar8_unset(0x5dc, 0x80); + mchbar8_or(0x5dc, 0x80); // XXX tRD @@ -2180,9 +2180,9 @@ printk(BIOS_DEBUG, "Done enhanced mode\n"); // Periodic RCOMP - MCHBAR16_AND_OR(0x160, ~0xfff, 0x999); - MCHBAR16_OR(0x1b4, 0x3000); - MCHBAR8_OR(0x130, 0x82); + mchbar16_unset_and_set(0x160, 0xfff, 0x999); + mchbar16_or(0x1b4, 0x3000); + mchbar8_or(0x130, 0x82); printk(BIOS_DEBUG, "Done PRCOMP\n"); // Power settings @@ -2197,11 +2197,11 @@ if (ME_UMA_SIZEMB != 0) { if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0)) - MCHBAR8_OR(0xa2f, 1 << 0); + mchbar8_or(0xa2f, 1 << 0); if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1)) - MCHBAR8_OR(0xa2f, 1 << 1); - MCHBAR32_OR(0xa30, 1 << 26); + mchbar8_or(0xa2f, 1 << 1); + mchbar32_or(0xa30, 1 << 26); } printk(BIOS_DEBUG, "Done raminit\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 58160b7..89165e0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -41,16 +41,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - #define CHDECMISC 0x111 #define STACKED_MEM (1 << 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fe15143abcbb74abae6ebf126b219ed88b4153 Gerrit-Change-Number: 46279 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: nb/intel/haswell: Use common MCHBAR accessor functions
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45574 ) Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ...................................................................... nb/intel/haswell: Use common MCHBAR accessor functions This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord. Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 8 files changed, 19 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5f3debb..86c69f8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -14,6 +14,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> #include <cpu/intel/common/common.h> diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2fd530..8f9f33d 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -11,14 +11,17 @@ ramstage-y += acpi.c ramstage-y += minihd.c +ramstage-y += ../common/mchbar_ops.c romstage-y += memmap.c romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += ../common/mchbar_ops.c smm-y += finalize.c +smm-y += ../common/mchbar_ops.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index cc4487c..81ed757 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h> unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b1fe430 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..ebce6e9 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "haswell.h" void intel_northbridge_haswell_finalize_smm(void) @@ -17,13 +19,13 @@ pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); - MCHBAR32_OR(DMIVCLIM, 1UL << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_set(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_set(SAPMCTL, 1UL << 31); /* SA PM */ + mchbar32_set(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_set(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_set(REQLIM, 1UL << 31); + mchbar32_set(DMIVCLIM, 1UL << 31); + mchbar32_set(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 44ea9b9..5cacec6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -27,22 +27,8 @@ /* * MCHBAR + * As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d1..fd4a238 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00f..f382db5 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -16,6 +16,8 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "raminit.h" #include "pei_data.h" #include "haswell.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Gerrit-Change-Number: 45574 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 23

Change in coreboot[master]: nb/i945: Drop unneeded loop
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40369 ) Change subject: nb/i945: Drop unneeded loop ...................................................................... nb/i945: Drop unneeded loop At sdram_power_management() function, MCHBAR32(UPMC3) bit 16 is already set. Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40369/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dad1cb2..4353a9c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2147,7 +2147,6 @@ u16 reg16; u32 reg32; int integrated_graphics = pci_read_config16(PCI_DEV(0, 0x00, 0), GGC) & 2; - int i; reg32 = MCHBAR32(C0DRT2); reg32 &= 0xffffff00; @@ -2193,11 +2192,6 @@ MCHBAR32(UPMC3) = 0x000f06ff; - for (i = 0; i < 5; i++) { - MCHBAR32(UPMC3) &= ~(1 << 16); - MCHBAR32(UPMC3) |= (1 << 16); - } - MCHBAR32(GIPMC1) = 0x8000000c; reg16 = MCHBAR16(CPCTL); -- To view, visit https://review.coreboot.org/c/coreboot/+/40369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Gerrit-Change-Number: 40369 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1)
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40370 ) Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ...................................................................... nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40370/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4353a9c..bb886d4 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2171,18 +2171,14 @@ MCHBAR32(C1DRC1) = reg32; if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = MCHBAR16(UPMC1); + peg_bits &= ((1 << 5) | (1 << 0)); + if (i945_silicon_revision() > 1) MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + else /* Rev 0 and 1 */ MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } } reg16 = MCHBAR16(UPMC2); -- To view, visit https://review.coreboot.org/c/coreboot/+/40370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Gerrit-Change-Number: 40370 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45273 ) Change subject: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax ...................................................................... nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/igd.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45273/1 diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c52..43662d1 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -28,7 +28,7 @@ Method (XBCM, 1, NotSerialized) { - Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) + ^^DSPC.BRTC = ((Arg0 << 0x04) | 0x0F) #ifdef SMI_SAVE_CMOS Trap(SMI_SAVE_CMOS) #endif @@ -36,8 +36,8 @@ Method (XBQC, 0, NotSerialized) { - Store (^^DSPC.BRTC, Local0) - ShiftRight (Local0, 4, Local0) + Local0 = ^^DSPC.BRTC + Local0 >>= 4 Return (Local0) } #include <drivers/intel/gma/acpi/common.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Gerrit-Change-Number: 45273 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 20

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