HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34438 )
Change subject: bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT
......................................................................
bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT
Found-by: util/lint/kconfig_lint
Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/mainboard/emulation/qemu-q35/bootblock.c
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/sandybridge/bootblock.c
M src/soc/intel/broadwell/bootblock/systemagent.c
6 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34438/1
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index d5ca7f9..354db3c 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -26,12 +26,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index c076c55..8ac89d8 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -23,12 +23,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 2c1bd58..c63283d 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -21,12 +21,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 604088b..68a0f63 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -22,12 +22,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true.
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true.
* That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 15e2de1..86882fc 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -22,12 +22,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
index 7aaed78..01a77d9 100644
--- a/src/soc/intel/broadwell/bootblock/systemagent.c
+++ b/src/soc/intel/broadwell/bootblock/systemagent.c
@@ -24,12 +24,12 @@
/*
* The "io" variant of the config access is explicitly used to
- * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
+ * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
- * CONFIG_MMCONF_SUPPORT option to do PCI config accesses.
+ * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128
Gerrit-Change-Number: 34438
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-MessageType: newchange