coreboot-gerrit September 2019

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Change in ...coreboot[master]: src/soc/amd/picasso: Update UARTs
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33767 Change subject: src/soc/amd/picasso: Update UARTs ...................................................................... src/soc/amd/picasso: Update UARTs Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/uart.c 2 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33767/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index b9d1ab5..b06e101 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -59,8 +59,11 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_UART_MAX_PORT 3 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d5d3006..339bd27 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -16,12 +16,19 @@ #include <console/uart.h> #include <soc/southbridge.h> +static const uintptr_t uart_addresses[] = { + APU_UART0_BASE, + APU_UART1_BASE, + APU_UART2_BASE, + APU_UART3_BASE, +}; + uintptr_t uart_platform_base(int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx < 0 || idx > APU_UART_MAX_PORT) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_addresses[uart]; } unsigned int uart_platform_refclk(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Gerrit-Change-Number: 33767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd/picasso: Update for vbios
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34422 to review the following change. Change subject: soc/amd/picasso: Update for vbios ...................................................................... soc/amd/picasso: Update for vbios Add Picasso's Device ID and default filename. Only a single Device ID is documented for Picasso so remove the oprom remapper function. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/northbridge.c 3 files changed, 3 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34422/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 10e1930..840de12 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -93,14 +93,14 @@ config VGA_BIOS_ID string - default "1002,98e4" + default "1002,15d8" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/picasso/VBIOS.bin" + default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" config S3_VGA_ROM_RUN bool diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index d6887f9..acde455 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -42,7 +42,7 @@ /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 627ce03..a39e79a 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -329,19 +329,3 @@ assign_resources(dev->link_list); } -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", - vendev, new_vendev); - - return new_vendev; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 Gerrit-Change-Number: 34422 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/amd/common: Add AcpiMmio access for SMBus PCI device
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34914 ) Change subject: soc/amd/common: Add AcpiMmio access for SMBus PCI device ...................................................................... soc/amd/common: Add AcpiMmio access for SMBus PCI device The PCI register space is accessible at 0xfed80000. Add functions for use as helpers. Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/34914/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882..7fad456 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -65,7 +65,39 @@ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ +#if SUPPORTS_ACPIMMIO_SM_PCI_BASE +/* smbus pci read/write - access registers at 0xfed80000 */ + +u8 sm_pci_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u16 sm_pci_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u32 sm_pci_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +void sm_pci_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} +#endif #if SUPPORTS_ACPIMMIO_SMI_BASE /* smi read/write - access registers at 0xfed80200 */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 32da867..0913a5a 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -20,6 +20,9 @@ /* iomap.h must indicate if the device uses a block, optional if unused. */ #include <soc/iomap.h> +#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE + #define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0 +#endif #ifndef SUPPORTS_ACPIMMIO_SMI_BASE #define SUPPORTS_ACPIMMIO_SMI_BASE 0 #endif @@ -161,6 +164,14 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); +/* Access SMBus PCI registers at 0xfed80000 */ +uint8_t sm_pci_read8(uint8_t reg); +uint16_t sm_pci_read16(uint8_t reg); +uint32_t sm_pci_read32(uint8_t reg); +void sm_pci_write8(uint8_t reg, uint8_t value); +void sm_pci_write16(uint8_t reg, uint16_t value); +void sm_pci_write32(uint8_t reg, uint32_t value); + /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); uint16_t pm_io_read16(uint8_t reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/34914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Gerrit-Change-Number: 34914 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/amd/common/lpc: Add SuperIO decode function
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35271 ) Change subject: soc/amd/common/lpc: Add SuperIO decode function ...................................................................... soc/amd/common/lpc: Add SuperIO decode function The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35271/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 0f4f616..4b20ba7 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -75,6 +75,8 @@ #define LPC_WIDEIO0_ENABLE BIT(2) #define DECODE_ALTERNATE_SIO_ENABLE BIT(1) #define DECODE_SIO_ENABLE BIT(0) +#define DECODE_SIO_4E4F 1 +#define DECODE_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 /* Assuming word access to higher word (register 0x4a) */ @@ -141,6 +143,8 @@ void lpc_enable_port80(void); void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); +/* base = index/data I/O to enable. 0: 2e/2f, 1: 4e/4f */ +void lpc_enable_sio_decode(int base); uintptr_t lpc_spibase(void); void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 485eeda..27a5f4e 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -165,6 +165,19 @@ pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } +/* base = index/data I/O to enable. 0: 2e/2f, 1: 4e/4f */ +void lpc_enable_sio_decode(int base) +{ + uint32_t decodes; + + if (base > 1) + return; + + decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + decodes |= 1 << base; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes); +} + void lpc_enable_decode(uint32_t decodes) { pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); -- To view, visit https://review.coreboot.org/c/coreboot/+/35271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Gerrit-Change-Number: 35271 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: _WIP_ soc/amd/picasso: Update for USB3.1
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34420 to review the following change. Change subject: _WIP_ soc/amd/picasso: Update for USB3.1 ...................................................................... _WIP_ soc/amd/picasso: Update for USB3.1 todo: still need OC support b:130280788 Change to the appropriate device IDs. Remove the ehci resource call. Remove unused USB2 ACPI name assignment. Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/usb.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34420/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 65d98b1..8d49271 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -49,19 +49,6 @@ case 0: /* Root Hub */ return "RHUB"; - case 2: - /* USB2 ports */ - switch (dev->path.usb.port_id) { - case 0: return "HS01"; - case 1: return "HS02"; - case 2: return "HS03"; - case 3: return "HS04"; - case 4: return "HS05"; - case 5: return "HS06"; - case 6: return "HS07"; - case 7: return "HS08"; - } - break; case 3: /* USB3 ports */ switch (dev->path.usb.port_id) { diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 66c8266..7d3201c 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -56,7 +56,7 @@ }; static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, @@ -66,12 +66,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_SB900_USB_18_0, - PCI_DEVICE_ID_AMD_SB900_USB_18_2, - PCI_DEVICE_ID_AMD_SB900_USB_20_5, - PCI_DEVICE_ID_AMD_CZ_USB_0, - PCI_DEVICE_ID_AMD_CZ_USB_1, - PCI_DEVICE_ID_AMD_CZ_USB3_0, + PCI_DEVICE_ID_AMD_PCO_XHCI0, + PCI_DEVICE_ID_AMD_PCO_XHCI1, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/34420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Gerrit-Change-Number: 34420 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: soc/amd/picasso: Update all PSP and amdfw.rom building
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33764 Change subject: soc/amd/picasso: Update all PSP and amdfw.rom building ...................................................................... soc/amd/picasso: Update all PSP and amdfw.rom building Add Kconfig options and Makefile comand line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are NDA only. See PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 385 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33764/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5fefbde..5f0bb22 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,43 +75,6 @@ int default 200 -config ROMSTAGE_ADDR - hex "DRAM address of first execution stage" - default 0x9b00000 - help - The base address where romstage should be linked and the PSP - uncompresses the image. - -config ROMSTAGE_MAX_SIZE - hex "Size of first execution stage" - default 0x10000 - help - The base address where romstage should be linked. This is the - uncompressed size of romstage. - -config DCACHE_RAM_BASE - hex - default 0x9fa0000 - help - Although this product begins execution in DRAM, the DCACHE symbols - are maintained for backward compatibility with the romstage - mechanism for migrating values from CAR. Notice that in this - design, stack writes modify memory and are not contained solely - within the cache. As a result, this memory must be marked reserved - and not usable by the OS. - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK - hex - default 0x4000 - help - The amount of stack space allocated prior to placing the stack - in cbmem. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -155,7 +118,7 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" config PICASSO_SATA_MODE int "SATA Mode" @@ -263,14 +226,65 @@ ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. -config USE_PSPSECUREOS - bool "Include PSP SecureOS blobs in AMD firmware" - default y - help - Include the PspSecureOs, PspTrustlet and TrustletKey binaries - in the amdfw section. +config DIMM_SPD_SIZE + int + default 512 # DDR4 - If unsure, answer 'y' +config RO_REGION_ONLY + string + depends on CHROMEOS + default "apu/amdfw" + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + +menu "PSP Configuration Options" + +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 + help + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config DCACHE_RAM_BASE + hex + default 0x9f70000 + help + Although this product begins execution in DRAM, the DCACHE symbols + are maintained for backward compatibility with the romstage + mechanism for migrating values from CAR. Notice that in this + design, stack writes modify memory and are not contained solely + within the cache. As a result, this memory must be marked reserved + and not usable by the OS. + +config DCACHE_RAM_SIZE + hex + default 0x40000 + +config DCACHE_BSP_STACK_SIZE + depends on C_ENVIRONMENT_BOOTBLOCK + hex + default 0x4000 + help + The amount of stack space allocated prior to placing the stack + in cbmem. config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" @@ -313,25 +327,95 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config DIMM_SPD_SIZE - int - default 512 # DDR4 +config AMD_PUBKEY_FILE + string "AMD public Key" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" -config RO_REGION_ONLY - string - depends on CHROMEOS - default "apu/amdfw" - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config MAINBOARD_POWER_RESTORE - def_bool n +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 help - This option determines what state to go to once power is restored - after having been lost in S0. Select this option to automatically - return to S0. Otherwise the system will remain in S5 once power - is restored. + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config PSP_APCB_FILE + string "APCB file" + help + The name of the AGESA Parameter Customization Block. + +config PSP_APOB_DESTINATION + hex + default 0x9f00000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_NV_ADDRESS + hex "Base address of APOB NV" + default 0xffa68000 + help + Location in flash where the PSP can find the S3 restore information. + Place this on a boundary that the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache base address should be used. + +config PSP_APOB_NV_SIZE + hex "Size of APOB NV to be reserved" + default 0x10000 + help + Size of the S3 restore information. Make this a multiple of the + size the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache size should be used. + +config USE_PSPSCUREOS + bool "Include PSP SecureOS blobs in PSP build" + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool "Include MP2 blobs in PSP build" + default y + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_S0I3_FW + bool "Include S0I3 blob in PSP build" + help + Select this item to include the S0i3 file into the PSP build. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + number? this feature requires a signed whitelist image and + bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_BL_FILE + string "Whitelist-capable bootloader file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/PspBootLoader_WL_RV.sbin" + +config PSP_WHITELIST_FILE + string "Debug whitelist file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/whitelist.bin" + +endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 43ae48b..cac6ab5 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,6 +1,6 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. +# Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc. # 2013 - 2014 Sage Electronic Engineering, LLC # All rights reserved. # @@ -113,93 +113,230 @@ # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) -### 0 +# +# PSP Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=ST -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +# type = 0x1 +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x5 +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSignedRV.key -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x3 +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_RV.sbin -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +# types = 0x8 and 0x18 +PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +# type = 0x9 +PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin + +# type = 0xb +PSP_SOFTFUSE="0x0000000010000001" + +ifeq ($(CONFIG_USE_PSPSCUREOS),y) +# types = 0x2, 0xc +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin +# type = 0x13 +PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +# type = 0x21 +PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin +# type = 0x24 +PSP_SECG1_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) - -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +# type = 0x25 +PSP_MP2FW1_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin +# BIOS type = 0x6a +PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +else +PSP_SOFTFUSE="0x0000000030000001" endif -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +# type = 0x28 +PSP_DRIVERS_FILE=$(top)/$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +PSP_S0I3_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin endif +# types = 0x30 - 0x37 +PSP_ABL0_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +PSPBTLDR_FILE=$(CONFIG_PSP_WHITELIST_BL_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) +PSP_BIOSBIN_SIZE=$(CONFIG_ROMSTAGE_MAX_SIZE) + +# type = 0x63 +PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) +PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) + +# type2 = 0x64, 0x65 +PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin + +# type = 0x66 +PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +xOPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +OOPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) +OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) +OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) +OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) +OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) +OPT_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) +OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) +OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) +OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) +OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) +OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) +OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) +OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) +OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) +OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) +OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) +OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) +OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) +OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) +OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) +OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +OPT_APCB_FILE=$(call add_opt_prefix, $(PSP_APCB_FILE), --apcb) +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) +OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base) +OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size) +OPT_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) +OPT_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) +OPT_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) +OPT_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) +OPT_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) +OPT_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) +OPT_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) +OPT_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) +OPT_UCODE_FILE1=$(call add_opt_prefix, $(PSP_UCODE_FILE1), --instance 0 --ucode) +OPT_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) +OPT_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) +OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ + $(call strip_quotes, $(SMUFWM_FN_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(call strip_quotes, $(PSP_APCB_FILE)) \ + $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(call strip_quotes, $(PSP_PMUI_FILE1)) \ + $(call strip_quotes, $(PSP_PMUI_FILE2)) \ + $(call strip_quotes, $(PSP_PMUI_FILE3)) \ + $(call strip_quotes, $(PSP_PMUI_FILE4)) \ + $(call strip_quotes, $(PSP_PMUD_FILE1)) \ + $(call strip_quotes, $(PSP_PMUD_FILE2)) \ + $(call strip_quotes, $(PSP_PMUD_FILE3)) \ + $(call strip_quotes, $(PSP_PMUD_FILE4)) \ + $(call strip_quotes, $(PSP_UCODE_FILE1)) \ + $(call strip_quotes, $(PSP_UCODE_FILE2)) \ + $(call strip_quotes, $(PSP_UCODE_FILE3)) \ + $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_ABL0_FILE)) \ + $(call strip_quotes, $(PSP_ABL1_FILE)) \ + $(call strip_quotes, $(PSP_ABL2_FILE)) \ + $(call strip_quotes, $(PSP_ABL3_FILE)) \ + $(call strip_quotes, $(PSP_ABL4_FILE)) \ + $(call strip_quotes, $(PSP_ABL5_FILE)) \ + $(call strip_quotes, $(PSP_ABL6_FILE)) \ + $(call strip_quotes, $(PSP_ABL7_FILE)) \ + $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ + $(call strip_quotes, $(PSP_SECG1_FILE)) \ + $(call strip_quotes, $(PSP_SECG2_FILE)) \ + $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ + $(call_strip_quotes, $(PSP_S0I3_FILE)) \ + $(call_strip_quotes, $(PSP_IKEK_FILE)) \ + $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -210,29 +347,65 @@ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ $(OPT_SMUFIRMWARE2_FILE) \ $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_APCB_FILE) \ + $(OPT_APOB_ADDR) \ + $(OPT_APOBNV_ADDR) \ + $(OPT_APOBNV_SIZE) \ + $(OPT_BIOSBIN_FILE) \ + $(OPT_BIOSBIN_DEST) \ + $(OPT_BIOSBIN_SIZE) \ + $(OPT_SOFTFUSE) \ + $(OPT_PMUI_FILE1) \ + $(OPT_PMUI_FILE2) \ + $(OPT_PMUI_FILE3) \ + $(OPT_PMUI_FILE4) \ + $(OPT_PMUD_FILE1) \ + $(OPT_PMUD_FILE2) \ + $(OPT_PMUD_FILE3) \ + $(OPT_PMUD_FILE4) \ + $(OPT_UCODE_FILE1) \ + $(OPT_UCODE_FILE2) \ + $(OPT_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ + --token-unlock \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf +$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -259,11 +432,4 @@ endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -cbfs-files-y += smu_fw -cbfs-files-y += smu_fw2 -smu_fw-file := $(SMUFWM_FILE) -smu_fw-type := raw -smu_fw2-file := $(SMUFIRMWARE2_FILE) -smu_fw2-type := raw - endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/33764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Gerrit-Change-Number: 33764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: superio: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 20 Oct '19

20 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32830 Change subject: superio: Use 'include <stdlib.h>' when appropriate ...................................................................... superio: Use 'include <stdlib.h>' when appropriate Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81216h/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/superio.c M src/superio/intel/i8900/superio.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8671f/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/superio.c M src/superio/ite/it8721f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8772f/superio.c M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/npcd378/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/fdc37n972/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/early_serial.c M src/superio/smsc/lpc47n217/superio.c M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/sio10n268/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/via/vt1211/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83697hf/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 60 files changed, 38 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32830/1 diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 4719923..1e833c4 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "f71805f.h" static void f71805f_init(struct device *dev) diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c index 200b21e..05132cc 100644 --- a/src/superio/fintek/f71808a/superio.c +++ b/src/superio/fintek/f71808a/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include "f71808a.h" diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index da998d0..2cd1bb1 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include "f71859.h" static void f71859_init(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 634888b..a044dc2 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f71863fg.h" static void f71863fg_init(struct device *dev) diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 15fdf3e..67b39ef 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include "fintek_internal.h" diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 3316ee2..7694f41 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f71872.h" static void f71872_init(struct device *dev) diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index e55ec57..106ab0e 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -19,7 +19,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <console/console.h> -#include <stdlib.h> #include "chip.h" #include "f81216h.h" diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index b6156ee..d62fc82 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f81865f.h" static void f81865f_init(struct device *dev) diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index 53a5aac..c66bf27 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -19,8 +19,8 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "f81866d.h" #include "fintek_internal.h" diff --git a/src/superio/intel/i8900/superio.c b/src/superio/intel/i8900/superio.c index 24805bc..e56c192 100644 --- a/src/superio/intel/i8900/superio.c +++ b/src/superio/intel/i8900/superio.c @@ -14,13 +14,13 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/device.h> #include <device/pnp.h> #include <drivers/uart/uart8250reg.h> -#include "i8900.h" #include <arch/io.h> +#include "i8900.h" + static void pnp_enter_ext_func_mode(struct device *dev) { outb(0x80, dev->path.pnp.port); diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1b93036..7f60f22 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -17,10 +17,10 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <console/console.h> #include <delay.h> +#include <stddef.h> #include "env_ctrl.h" #include "env_ctrl_chip.h" diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c index 1ed8fe0..d7169e6 100644 --- a/src/superio/ite/it8528e/superio.c +++ b/src/superio/ite/it8528e/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8528e.h" diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index 5fdfcef..0448832 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include <superio/ite/common/env_ctrl.h> diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 70da2ab..761c9fb 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -17,8 +17,8 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> + #include "it8671f.h" static void init(struct device *dev) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 6f096b0..2004236 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8712f.h" diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index de1ef0d..a3b8ec4 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "it8716f.h" diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index ed15955..297aead 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/ite/common/env_ctrl.h> #include <superio/conf_mode.h> diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index cf3ca3f..5426992 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -18,8 +18,8 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> + #include "it8721f.h" static void init(struct device *dev) diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 7107bb4..58a837e 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -18,7 +18,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/ite/common/env_ctrl.h> #include "chip.h" diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index ed46e73..7c21f10 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -20,7 +20,6 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <delay.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "chip.h" /* FIXME */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 4f8f967..1c4b476 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87309.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 33f27e1..f8ad4d5 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87360.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 6d8c66e..3cf62cd 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87366.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..c90ebd9 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87382.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index cef7ff7..87dd265 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87384.h" static struct device_operations ops = { diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..4a5bed2 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> + #include "pc87392.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f867ff3..f98ba84 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "pc87417.h" static void init(struct device *dev) diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 42f5434..397c3ea 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -16,8 +16,8 @@ #include <device/device.h> #include <device/pnp.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "pc97317.h" static void init(struct device *dev) diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200..493e0ce 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -16,7 +16,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "nct5104d.h" #include "chip.h" diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index e8249d4..3084687 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> #include <arch/acpi.h> #include <superio/conf_mode.h> diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index e399c0a..78e07b6 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6776.h" diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 49e6306..7ef3488 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6779d.h" diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 3a6d740..23d5a6f 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include "nct6791d.h" diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index c1f557e..f11e75a 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -23,7 +23,6 @@ #include <device/pnp.h> #include <option.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include <superio/conf_mode.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index c666818..aeb394a 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "wpcm450.h" static void init(struct device *dev) diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 522d647..857caa1 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -17,7 +17,6 @@ #include <device/pnp.h> #include <console/console.h> #include <device/smbus.h> -#include <stdlib.h> #include <pc80/keyboard.h> void m3885_configure_multikey(void); diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 0bfd3b8..5a62478 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -21,7 +21,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "dme1737.h" static void dme1737_init(struct device *dev) diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index 0ee9850..3706dec 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -17,7 +17,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include "fdc37n972.h" diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index e43e791..3c2ded5 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "kbc1100.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 6ac2d6d..bfe7b45 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -24,7 +24,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47b272.h" /** diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ad8153f..a18714d 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47b397.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index cd13854..7b88c72 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -23,7 +23,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47m10x.h" /** diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 80ed456..4aeeb23 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "lpc47m15x.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index b8e5c0b..9bda334 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -16,7 +16,7 @@ #include <arch/io.h> #include <device/pnp.h> #include <stdint.h> -#include <stdlib.h> + #include "lpc47n207.h" /* diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index b10e8a1..246a853 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -25,7 +25,7 @@ #include <console/console.h> #include <device/smbus.h> #include <assert.h> -#include <stdlib.h> + #include "lpc47n217.h" /* Forward declarations */ diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 610f685..c21cdda 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <device/smbus.h> #include <assert.h> -#include <stdlib.h> #include <pc80/keyboard.h> #include <superio/conf_mode.h> diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 74b8b2e..12e9af2 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <device/smbus.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "mec1308.h" static void mec1308_init(struct device *dev) diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 5e49aa7..0e102e6 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -19,7 +19,6 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> #include "sch4037.h" diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index a192831..6ed6954 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> #include "sio1036.h" diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c index b8243ec..cf432a0 100644 --- a/src/superio/smsc/sio10n268/superio.c +++ b/src/superio/smsc/sio10n268/superio.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/device.h> #include <device/pnp.h> #include <pc80/keyboard.h> + #include "sio10n268.h" static void init(struct device *dev) diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 4ce006d..aa5af38 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -35,7 +35,6 @@ #include <superio/conf_mode.h> #include <console/console.h> #include <pc80/keyboard.h> -#include <stdlib.h> /* The following Super I/O chips are currently supported by this driver: */ #define LPC47M172 0x14 diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c index 4d7c8de..24443c2 100644 --- a/src/superio/via/vt1211/superio.c +++ b/src/superio/via/vt1211/superio.c @@ -19,7 +19,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <stdlib.h> + #include "vt1211.h" static u8 hwm_io_regs[] = { diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 9e15037..bd9900b 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -17,7 +17,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "w83627dhg.h" static void w83627dhg_enable_UR2(struct device *dev) diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 88fbc31..7fe6a2f 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> + #include "w83627ehg.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 318eaa4..4365652 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> + #include "w83627hf.h" static void enable_hwm_smbus(struct device *dev) diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 82974ba..e783740 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -18,8 +18,8 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <stdint.h> -#include <stdlib.h> #include <pc80/keyboard.h> + #include "w83627uhg.h" /* diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 0735f04..4a995d6 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -21,7 +21,6 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> -#include <stdlib.h> #include <arch/acpi.h> #include <superio/conf_mode.h> diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index a3c132c..4323088 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -20,7 +20,7 @@ #include <superio/conf_mode.h> #include <console/console.h> #include <lib.h> -#include <stdlib.h> + #include "chip.h" #include "w83697hf.h" diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index b4f316b..b11e5be 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -20,7 +20,7 @@ #include <device/pnp.h> #include <superio/conf_mode.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "w83977tf.h" static void w83977tf_init(struct device *dev) diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index ae4fce4..70457e6 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <drivers/uart/uart8250reg.h> #include <pc80/keyboard.h> -#include <stdlib.h> + #include "chip.h" #include "wpcd376i.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Gerrit-Change-Number: 32830 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: security/memory: Add x86_64 support
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35682 ) Change subject: security/memory: Add x86_64 support ...................................................................... security/memory: Add x86_64 support Fix compiler warning by adding an additional check for the fastpath memset. Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/security/memory/memory_clear.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35682/1 diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 638c41a..45bee91 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -127,7 +127,8 @@ __func__, range_entry_base(r), range_entry_end(r)); /* Does regular memset work? */ - if (!(range_entry_end(r) >> sizeof(void *) * 8)) { + if (sizeof(resource_t) == sizeof(void *) || + !(range_entry_end(r) >> (sizeof(void *) * 8))) { /* fastpath */ memset((void *)(uintptr_t)range_entry_base(r), 0, range_entry_size(r)); -- To view, visit https://review.coreboot.org/c/coreboot/+/35682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a80438995bafe7e436f3fe2180b8c9574eeff23 Gerrit-Change-Number: 35682 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/supermicro/x11-lga1151-series: Rename to x11-lga1151-skykbl
by Christian Walter (Code Review) 20 Oct '19

20 Oct '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35622 ) Change subject: mainboard/supermicro/x11-lga1151-series: Rename to x11-lga1151-skykbl ...................................................................... mainboard/supermicro/x11-lga1151-series: Rename to x11-lga1151-skykbl The LGA1151 supports multiple chip generations like SKylake, Kaby Lake, Coffee Lake and so on. The x11sch for example is a Coffee Lake platform with a LGA1151 socket. TO cover those changes aswell, we need to rename the folder to x11-lga1151-skykbl. Change-Id: Id213e79d7bcb5b6630dd0354cfce542e30ec9573 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- R src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig R src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig.name R src/mainboard/supermicro/x11-lga1151-skykbl/Makefile.inc R src/mainboard/supermicro/x11-lga1151-skykbl/acpi/ec.asl R src/mainboard/supermicro/x11-lga1151-skykbl/acpi/mainboard.asl R src/mainboard/supermicro/x11-lga1151-skykbl/acpi/superio.asl R src/mainboard/supermicro/x11-lga1151-skykbl/acpi_tables.c R src/mainboard/supermicro/x11-lga1151-skykbl/board_info.txt R src/mainboard/supermicro/x11-lga1151-skykbl/bootblock.c R src/mainboard/supermicro/x11-lga1151-skykbl/cmos.layout R src/mainboard/supermicro/x11-lga1151-skykbl/devicetree.cb R src/mainboard/supermicro/x11-lga1151-skykbl/dsdt.asl R src/mainboard/supermicro/x11-lga1151-skykbl/ramstage.c R src/mainboard/supermicro/x11-lga1151-skykbl/romstage.c R src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/board_info.txt R src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/include/variant/gpio.h R src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/overridetree.cb R src/mainboard/supermicro/x11-lga1151-skykbl/vboot-ro-rwab.fmd 18 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35622/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/Kconfig rename to src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig.name similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/Kconfig.name rename to src/mainboard/supermicro/x11-lga1151-skykbl/Kconfig.name diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-skykbl/Makefile.inc similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/Makefile.inc rename to src/mainboard/supermicro/x11-lga1151-skykbl/Makefile.inc diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl b/src/mainboard/supermicro/x11-lga1151-skykbl/acpi/ec.asl similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl rename to src/mainboard/supermicro/x11-lga1151-skykbl/acpi/ec.asl diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl b/src/mainboard/supermicro/x11-lga1151-skykbl/acpi/mainboard.asl similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl rename to src/mainboard/supermicro/x11-lga1151-skykbl/acpi/mainboard.asl diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl b/src/mainboard/supermicro/x11-lga1151-skykbl/acpi/superio.asl similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl rename to src/mainboard/supermicro/x11-lga1151-skykbl/acpi/superio.asl diff --git a/src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c b/src/mainboard/supermicro/x11-lga1151-skykbl/acpi_tables.c similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c rename to src/mainboard/supermicro/x11-lga1151-skykbl/acpi_tables.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/board_info.txt b/src/mainboard/supermicro/x11-lga1151-skykbl/board_info.txt similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/board_info.txt rename to src/mainboard/supermicro/x11-lga1151-skykbl/board_info.txt diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-skykbl/bootblock.c similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/bootblock.c rename to src/mainboard/supermicro/x11-lga1151-skykbl/bootblock.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-skykbl/cmos.layout similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/cmos.layout rename to src/mainboard/supermicro/x11-lga1151-skykbl/cmos.layout diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-skykbl/devicetree.cb similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/devicetree.cb rename to src/mainboard/supermicro/x11-lga1151-skykbl/devicetree.cb diff --git a/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-skykbl/dsdt.asl similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/dsdt.asl rename to src/mainboard/supermicro/x11-lga1151-skykbl/dsdt.asl diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-skykbl/ramstage.c similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/ramstage.c rename to src/mainboard/supermicro/x11-lga1151-skykbl/ramstage.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-skykbl/romstage.c similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/romstage.c rename to src/mainboard/supermicro/x11-lga1151-skykbl/romstage.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt b/src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/board_info.txt similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt rename to src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/board_info.txt diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/include/variant/gpio.h similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/include/variant/gpio.h diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/overridetree.cb similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb rename to src/mainboard/supermicro/x11-lga1151-skykbl/variants/x11ssh-tf/overridetree.cb diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-skykbl/vboot-ro-rwab.fmd similarity index 100% rename from src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd rename to src/mainboard/supermicro/x11-lga1151-skykbl/vboot-ro-rwab.fmd -- To view, visit https://review.coreboot.org/c/coreboot/+/35622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id213e79d7bcb5b6630dd0354cfce542e30ec9573 Gerrit-Change-Number: 35622 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

6 29

Change in coreboot[master]: src: Remove unneeded 'include <gpio.h>'
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34233 ) Change subject: src: Remove unneeded 'include <gpio.h>' ...................................................................... src: Remove unneeded 'include <gpio.h>' Change-Id: I570c6fcc889b37297fed7f1e252de1ff1ff632fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/cheza/board.h M src/mainboard/google/dragonegg/smihandler.c M src/mainboard/google/eve/bootblock.c M src/mainboard/google/foster/boardid.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/blsp.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/gru/board.h M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/nyan_big/boardid.c M src/mainboard/google/nyan_blaze/boardid.c M src/mainboard/google/oak/tpm_tis.c M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/yorp/gpio.c M src/mainboard/google/poppy/smihandler.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/reef/variants/baseboard/nhlt.c M src/mainboard/google/reef/variants/pyro/memory.c M src/mainboard/google/smaug/gpio.h M src/mainboard/google/storm/boardid.c M src/mainboard/google/storm/cdp.c M src/mainboard/google/urara/chromeos.c M src/mainboard/google/veyron/board.h M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/board.h M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/board.h M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/memory.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/memory.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/mainboard.c M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/kblrvp/spd/spd.h M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/soc/cavium/cn81xx/include/soc/gpio.h M src/soc/intel/skylake/uart.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8183/gpio.c M src/soc/nvidia/tegra124/chip.h M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/qcs405/uart.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/mipi.c 66 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34233/1 diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h index f83ca06..d9ebdd9 100644 --- a/src/mainboard/google/cheza/board.h +++ b/src/mainboard/google/cheza/board.h @@ -16,7 +16,6 @@ #ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H #define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H -#include <gpio.h> #include <soc/gpio.h> #define GPIO_EC_IN_RW GPIO(11) diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c index 9c72cb6..ef11835 100644 --- a/src/mainboard/google/dragonegg/smihandler.c +++ b/src/mainboard/google/dragonegg/smihandler.c @@ -15,7 +15,6 @@ #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/smm.h> #include <variant/ec.h> diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 5e92bb0..079144b 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -16,7 +16,6 @@ #include <bootblock_common.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/gpio.h> #include "gpio.h" diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c index ed37bab..4d77722 100644 --- a/src/mainboard/google/foster/boardid.c +++ b/src/mainboard/google/foster/boardid.c @@ -15,7 +15,6 @@ */ #include <boardid.h> -#include <gpio.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 7ce1300..5fe5c07 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -17,7 +17,6 @@ #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 2bc562a..ebc9525 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. */ -#include <gpio.h> #include <soc/gpio.h> #include <soc/blsp.h> #include <soc/qup.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 11a0f68..7c159a6 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 8025374..46a699e 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -17,7 +17,6 @@ #include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/soc_services.h> #include <soc/usb.h> diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index a4a1cca..e7e2740 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -20,7 +20,6 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <ec/google/chromeec/smm.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 9503582..ab7eca5 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -16,7 +16,6 @@ #include <cbfs.h> #include <console/console.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/romstage.h> #include <string.h> diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index acf3fb9..7863823 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -18,7 +18,6 @@ #define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H #include <assert.h> -#include <gpio.h> #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 5e9e15f..38bd598 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 2a2911c..039b0f8 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <stdlib.h> uint32_t board_id(void) diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 2a2911c..039b0f8 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <stdlib.h> uint32_t board_id(void) diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 303cfc7..aa78781 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <security/tpm/tis.h> #include "gpio.h" diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index cf3bc4c..5e4ba2e 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 6bfe54a..01407b2 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 3a9a441..9332fb4 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index d2d0d64..dd3083f 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 90601ce..634fe98 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> enum { diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 7b47bf1..eef4743 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 281bde0..a392fcd 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index 5719888..479a942 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> /* GPIOs needed prior to ramstage. */ diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 4f45687..5bc5bc3 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -17,7 +17,6 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/smm.h> diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 20b6a26..fca47dd 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> -#include <gpio.h> #include <nhlt.h> #include <smbios.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index f2ef80f..55cca0b 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <nhlt.h> #include <soc/nhlt.h> -#include <gpio.h> #include <baseboard/gpio.h> void __weak variant_nhlt_init(struct nhlt *nhlt) diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index 71ee060..340da5c 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -14,7 +14,6 @@ */ #include <baseboard/variants.h> -#include <gpio.h> #include <soc/meminit.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/smaug/gpio.h b/src/mainboard/google/smaug/gpio.h index bf6fd53..0352c4f 100644 --- a/src/mainboard/google/smaug/gpio.h +++ b/src/mainboard/google/smaug/gpio.h @@ -16,7 +16,6 @@ #ifndef __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ #define __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ -#include <gpio.h> #include <base3.h> /* Board ID definitions. */ diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 87f6d2a..f73e464 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -14,7 +14,6 @@ */ #include <boardid.h> -#include <gpio.h> #include <console/console.h> #include <stdlib.h> diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 3c27491..efded9e 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <gpio.h> #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c index 3f7ec32..e9148a3 100644 --- a/src/mainboard/google/urara/chromeos.c +++ b/src/mainboard/google/urara/chromeos.c @@ -16,7 +16,6 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> #include <console/console.h> -#include <gpio.h> int get_write_protect_state(void) { diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h index e6c300c..a83dd85 100644 --- a/src/mainboard/google/veyron/board.h +++ b/src/mainboard/google/veyron/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_BACKLIGHT GPIO(7, A, 2) #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 291bc33..0246d0d 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/google/veyron_mickey/board.h b/src/mainboard/google/veyron_mickey/board.h index c99146f..4e7be43 100644 --- a/src/mainboard/google/veyron_mickey/board.h +++ b/src/mainboard/google/veyron_mickey/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 291bc33..0246d0d 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/google/veyron_rialto/board.h b/src/mainboard/google/veyron_rialto/board.h index def5246..0a9d9e7 100644 --- a/src/mainboard/google/veyron_rialto/board.h +++ b/src/mainboard/google/veyron_rialto/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 8eae71d..0d68a96 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 44254bc..d1186bb 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index a581217..ad03823 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index b093a20..114a869 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <gpio.h> #include <soc/cnl_memcfg_init.h> static const struct cnl_mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 4edd4a0..75c928d 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c index 1173ee4..8663ed8 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c @@ -14,7 +14,6 @@ */ #include <baseboard/variants.h> -#include <gpio.h> #include <soc/meminit.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ce8e548..87614b6 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index ff93d27..42bb74d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> -#include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 78c7ae4..3ef3c512 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <device/device.h> -#include <gpio.h> #include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 0385e29..34aa405 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -16,7 +16,6 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/api.h> -#include <gpio.h> #include "gpio.h" #include <soc/romstage.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index c24baa0..33aa475 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -17,7 +17,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#include <gpio.h> #include <variant/gpio.h> #define RCOMP_TARGET_PARAMS 0x5 diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f900ca3..28327e8 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/romstage.h> #include "gpio.h" #include "spd/spd.h" diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 5364693..ec46ec2 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -14,7 +14,6 @@ */ #include <fsp/api.h> -#include <gpio.h> #include "gpio.h" #include <soc/romstage.h> #include <soc/gpio.h> diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h index 6986482..7c17547 100644 --- a/src/soc/cavium/cn81xx/include/soc/gpio.h +++ b/src/soc/cavium/cn81xx/include/soc/gpio.h @@ -20,7 +20,6 @@ #include <types.h> typedef u32 gpio_t; -#include <gpio.h> /* The following functions must be implemented by SoC/board code. */ diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 8b7c99e..9dd23de 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <device/pci_def.h> -#include <gpio.h> #include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index a29c1c1..ec96bdf 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> #include <assert.h> -#include <gpio.h> #include <types.h> enum { diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 3eccfbd..36aa28c5 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <gpio.h> #include <assert.h> #include <soc/spi.h> diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 7e930d1..2c260dc 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -16,7 +16,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ #include <arch/cache.h> -#include <gpio.h> #include <soc/addressmap.h> #define EFAULT 1 diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb..3ce46d2 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..9f92347 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -32,7 +32,6 @@ #include <boot/coreboot_tables.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/blsp.h> #include <soc/ipq_uart.h> diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2657b9c..e749ba6 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 66c3103..aefaf31 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -35,7 +35,6 @@ #include <boot/coreboot_tables.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/gsbi.h> #include <soc/ipq_uart.h> diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 13b9dae..c205e6d 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a43312..2b951ed 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/blsp.h> #include <soc/uart.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 04a5992..729cfa6 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <delay.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <stddef.h> #include <string.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 0f9d85c..eac1f5c 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index bda9553..335b578 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -17,7 +17,6 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> -#include <gpio.h> #include <soc/display.h> #include <soc/soc.h> #include <soc/sdram.h> diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index e2e9f7d..3a49dcc 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <delay.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 7fe2c19..8984eaa 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/addressmap.h> #include <soc/gpio.h> #include <soc/grf.h> diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 1f3f02c..2898f20 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -18,7 +18,6 @@ #include <delay.h> #include <device/device.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <string.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570c6fcc889b37297fed7f1e252de1ff1ff632fb Gerrit-Change-Number: 34233 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019