coreboot-gerrit September 2019

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Change in coreboot[master]: mainboard: Add Lenovo ThinkPad T440p
by Iru Cai (vimacs) (Code Review) 30 Oct '19

30 Oct '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34359 to review the following change. Change subject: mainboard: Add Lenovo ThinkPad T440p ...................................................................... mainboard: Add Lenovo ThinkPad T440p The code is based on autoport. Tested: - i5-4300M, 8G+8G - keyboard and trackpoint - USB - SATA - WLAN - Arch Linux loaded from SeaBIOS - libgfxinit - ACPI support Issues: - The touchpad is misconfigured, there's no middle button, and the 3 keys on top are all identified as left button - The Fn key is on by default Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/lenovo/t440p/Kconfig A src/mainboard/lenovo/t440p/Kconfig.name A src/mainboard/lenovo/t440p/Makefile.inc A src/mainboard/lenovo/t440p/acpi/ec.asl A src/mainboard/lenovo/t440p/acpi/platform.asl A src/mainboard/lenovo/t440p/acpi/superio.asl A src/mainboard/lenovo/t440p/acpi_tables.c A src/mainboard/lenovo/t440p/board_info.txt A src/mainboard/lenovo/t440p/devicetree.cb A src/mainboard/lenovo/t440p/dsdt.asl A src/mainboard/lenovo/t440p/gma-mainboard.ads A src/mainboard/lenovo/t440p/gpio.c A src/mainboard/lenovo/t440p/hda_verb.c A src/mainboard/lenovo/t440p/mainboard.c A src/mainboard/lenovo/t440p/romstage.c A src/mainboard/lenovo/t440p/smihandler.c 16 files changed, 837 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34359/1 diff --git a/src/mainboard/lenovo/t440p/Kconfig b/src/mainboard/lenovo/t440p/Kconfig new file mode 100644 index 0000000..59a257e --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig @@ -0,0 +1,41 @@ +if BOARD_LENOVO_THINKPAD_T440P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default lenovo/t440p + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T440p" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/t440p/Kconfig.name b/src/mainboard/lenovo/t440p/Kconfig.name new file mode 100644 index 0000000..e90299d --- /dev/null +++ b/src/mainboard/lenovo/t440p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T440P + bool "ThinkPad T440p" diff --git a/src/mainboard/lenovo/t440p/Makefile.inc b/src/mainboard/lenovo/t440p/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/t440p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t440p/acpi/ec.asl b/src/mainboard/lenovo/t440p/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl new file mode 100644 index 0000000..dfced7a --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t440p/acpi/superio.asl b/src/mainboard/lenovo/t440p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c new file mode 100644 index 0000000..5dc98d8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/t440p/board_info.txt b/src/mainboard/lenovo/t440p/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb new file mode 100644 index 0000000..df98ef8 --- /dev/null +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -0,0 +1,165 @@ +chip northbridge/intel/haswell # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x12ba12ba" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12ba12ba" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x89" + register "pirqe_routing" = "0x86" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8b" + register "pirqh_routing" = "0x87" + register "sata_ahci" = "1" + # 0(HDD), 5(ODD) + register "sata_port_map" = "0x21" + device pci 14.0 on # xHCI Controller + subsystemid 0x17aa 0x220e + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x220e + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x220e + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x220e + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x220e + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x220e + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x220e + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x220e + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x220e + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x0d" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x220e + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x220e + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x220e + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x220e + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x17aa 0x220e + end + end +end diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl new file mode 100644 index 0000000..4838877 --- /dev/null +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -0,0 +1,31 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/t440p/gma-mainboard.ads b/src/mainboard/lenovo/t440p/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/lenovo/t440p/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t440p/gpio.c b/src/mainboard/lenovo/t440p/gpio.c new file mode 100644 index 0000000..16fef44 --- /dev/null +++ b/src/mainboard/lenovo/t440p/gpio.c @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t440p/hda_verb.c b/src/mainboard/lenovo/t440p/hda_verb.c new file mode 100644 index 0000000..ac509bf --- /dev/null +++ b/src/mainboard/lenovo/t440p/hda_verb.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t440p/mainboard.c b/src/mainboard/lenovo/t440p/mainboard.c new file mode 100644 index 0000000..dcfd503 --- /dev/null +++ b/src/mainboard/lenovo/t440p/mainboard.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c new file mode 100644 index 0000000..28f766b --- /dev/null +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0, 0xa2, 0 }, + .ec_present = 0, + .dimm_channel0_disabled = 0, + .dimm_channel1_disabled = 0, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */ + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */ + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + .bist = bist, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c new file mode 100644 index 0000000..5ea7118 --- /dev/null +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +/* lynxpoint doesn't have gpi_route_interrupt, so add it */ +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + +static void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Gerrit-Change-Number: 34359 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 44

Change in ...coreboot[master]: src/cpu: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Oct '19

28 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33680 Change subject: src/cpu: Use 'include <stdlib.h>' when appropriate ...................................................................... src/cpu: Use 'include <stdlib.h>' when appropriate Also add some missing includes spotted by Jenkins Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/processor_name.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mirror_payload.c 4 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33680/1 diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index c5d523a..95985cd 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -94,6 +94,7 @@ #include <device/pci_ops.h> #include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> +#include <stdlib.h> static inline void print_debug_fv(const char *str, u32 val) { diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index 5672efd..ac0b57f 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -32,6 +32,8 @@ #include <device/pci.h> #include <device/pnp.h> #include <device/pci_ops.h> +#include <stddef.h> +#include <stdlib.h> /* The maximum length of CPU names is 48 bytes, including the final NULL byte. * If you change these names your BIOS will _NOT_ pass the AMD validation and diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0f73e71..e1908d8 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -34,6 +34,7 @@ #include <smp/spinlock.h> #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <stdlib.h> #include <thread.h> /* This is a lot more paranoid now, since Linux can NOT handle diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c index 88c5e81..f6420f2 100644 --- a/src/cpu/x86/mirror_payload.c +++ b/src/cpu/x86/mirror_payload.c @@ -14,12 +14,12 @@ */ #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <commonlib/helpers.h> #include <console/console.h> #include <bootmem.h> #include <program_loading.h> +#include <stddef.h> void mirror_payload(struct prog *payload) { -- To view, visit https://review.coreboot.org/c/coreboot/+/33680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bd999b59d1c0bdfa5999bf5805576f94c9a2390 Gerrit-Change-Number: 33680 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/southbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Oct '19

28 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33683 Change subject: src/southbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... src/southbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/cimx/sb800/smbus_spd.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb800/sm.c M src/southbridge/intel/lynxpoint/me_9.x.c 8 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33683/1 diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 46eca33..92bb5c1 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -20,7 +20,7 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index a6881bb..a574072 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -15,7 +15,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> +#include <stddef.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ /* warning: Porting.h includes an open #pragma pack(1) */ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index ffda0a8..d17f99f 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> @@ -21,6 +20,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <stddef.h> #include "SBPLATFORM.h" #include <vendorcode/amd/cimx/sb800/ECfan.h> diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 0387567..0b4cee7 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -20,7 +20,7 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "hudson.h" #include "smbus.c" diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6631682..535e5e4 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index ee031e9..4c0cc68 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi-generic.h> @@ -23,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <stddef.h> #define AMD_SB_SPI_TX_LEN 8 diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 1d2daed8..e1cf05c 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> + #include "sb800.h" #include "smbus.c" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 09eeff2..1b77aff 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -34,6 +34,7 @@ #include <delay.h> #include <elog.h> #include <halt.h> +#include <stdlib.h> #include "me.h" #include "pch.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1a3483aae0e3f0a7bc2eb2c1862ae7a325fd9c Gerrit-Change-Number: 33683 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified ...
by Frans Hendriks (Code Review) 28 Oct '19

28 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30811 Change subject: lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. ...................................................................... lib/prog_loaders.c: Add prog_locate_hook() for measured and verified boot. Before images are loaded from cbfs it needs to be measured and/or verified. prog_locate_hook() is added and can be used to start measured/verified boot. BUG=N/A TEST=Created verified binary and verify logging on Facebook FBG-1701 Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/include/program_loading.h M src/lib/prog_loaders.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30811/1 diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 468f0b3..a382daf 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -3,6 +3,7 @@ * * Copyright 2015 Google Inc. * Copyright (C) 2014 Imagination Technologies + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -136,6 +137,7 @@ /* Locate the identified program to run. Return 0 on success. < 0 on error. */ int prog_locate(struct prog *prog); +int prog_locate_hook(struct prog *prog); /* Run the program described by prog. */ void prog_run(struct prog *prog); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index b763417..4fa9a03 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,6 +40,9 @@ { struct cbfsf file; + if (prog_locate_hook(prog)) + return -1; + cbfs_prepare_program_locate(); if (cbfs_boot_locate(&file, prog_name(prog), NULL)) @@ -74,6 +78,7 @@ halt(); } +int __weak prog_locate_hook(struct prog *prog) {return 0; } void __weak stage_cache_add(int stage_id, const struct prog *stage) {} void __weak stage_cache_load_stage(int stage_id, -- To view, visit https://review.coreboot.org/c/coreboot/+/30811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12207fc8f2e9ca45d048cf8c8d9c057f53e5c2c7 Gerrit-Change-Number: 30811 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

9 45

Change in ...coreboot[master]: src/{device,drivers}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 27 Oct '19

27 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33681 Change subject: src/{device,drivers}: Use 'include <stdlib.h>' when appropriate ...................................................................... src/{device,drivers}: Use 'include <stdlib.h>' when appropriate Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/device_util.c M src/device/oprom/realmode/x86.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/smmstore/store.c M src/drivers/spi/flashconsole.c M src/drivers/spi/spi-generic.c M src/drivers/spi/spi_flash.c 8 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33681/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 47df305..fdb78fa 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -23,6 +23,7 @@ #include <device/path.h> #include <device/pci_def.h> #include <device/resource.h> +#include <stdlib.h> #include <string.h> /** diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1..e002c47 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -28,6 +28,7 @@ #include <lib/jpeg.h> #include <pc80/i8259.h> #include <pc80/i8254.h> +#include <stdlib.h> #include <string.h> #include <vbe.h> diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 19c8f6b..54d1f86 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -40,6 +40,8 @@ #include <endian.h> #include <timer.h> #include <security/tpm/tis.h> +#include <stdlib.h> + #include "tpm.h" #define CR50_MAX_BUFSIZE 63 diff --git a/src/drivers/i2c/tpm/tis_atmel.c b/src/drivers/i2c/tpm/tis_atmel.c index 4456567..e4fc9e1 100644 --- a/src/drivers/i2c/tpm/tis_atmel.c +++ b/src/drivers/i2c/tpm/tis_atmel.c @@ -22,6 +22,8 @@ #include <endian.h> #include <lib.h> #include <security/tpm/tis.h> +#include <stddef.h> +#include <stdlib.h> #include <timer.h> #define RECV_TIMEOUT (1 * 1000) /* 1 second */ diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 833407d..377eebe 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -20,6 +20,8 @@ #include <commonlib/region.h> #include <console/console.h> #include <smmstore.h> +#include <stddef.h> +#include <stdlib.h> /* * The region format is still not finalized, but so far it looks like this: diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index 3109012..b6351e3 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -19,6 +19,8 @@ #include <fmap.h> #include <console/console.h> #include <console/flash.h> +#include <stddef.h> +#include <stdlib.h> #define LINE_BUFFER_SIZE 128 #define READ_BUFFER_SIZE 0x100 diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 84a42d1..d4e17fc 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -16,6 +16,8 @@ #include <assert.h> #include <spi-generic.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index a81306e..5afb2f7 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -12,7 +12,7 @@ #include <boot_device.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248 Gerrit-Change-Number: 33681 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: util/crosgcc/patches: facilitate successful build of ipxe
by Name of user not set (Code Review) 26 Oct '19

26 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35098 ) Change subject: util/crosgcc/patches: facilitate successful build of ipxe ...................................................................... util/crosgcc/patches: facilitate successful build of ipxe New changes in the latest binutils(2.32) leads to assembler errors causes ipxe build failure. IPXE uses the divide test which requires /dev/null as input as well as the output file name. This patch facilitates the /dev/null as an exception to the current changes in binutils package while building crossgcc for coreboot leads to successful build of ipxe and further tests to pass based on /dev/null and applies automatically during the crossgcc rebuild. Also this can be reverted once binutils/ipxe provides update release in this respect. Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- A util/crossgcc/patches/binutils-2.32_as-ipxe.patch 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35098/1 diff --git a/util/crossgcc/patches/binutils-2.32_as-ipxe.patch b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch new file mode 100644 index 0000000..ab5b9b2 --- /dev/null +++ b/util/crossgcc/patches/binutils-2.32_as-ipxe.patch @@ -0,0 +1,35 @@ +From 6984bd861cc595e56d26ea033851d9174e855129 Mon Sep 17 00:00:00 2001 +From: CunningLearner <sahdev.himan(a)gmail.com> +Date: Mon, 26 Aug 2019 16:57:13 +0530 +Subject: [PATCH] as: facilitate tests based on /dev/null Signed-off-by: + Himanshu Sahdev <himanshusah(a)hcl.com> + +--- + gas/as.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gas/as.c b/gas/as.c +index 728811bc..78b4802c 100644 +--- a/gas/as.c ++++ b/gas/as.c +@@ -1203,7 +1203,7 @@ main (int argc, char ** argv) + { + char ** argv_orig = argv; + struct stat sob; +- ++ const char *dev_null_file="/dev/null"; + int macro_strip_at; + + start_time = get_run_time (); +@@ -1252,7 +1252,7 @@ main (int argc, char ** argv) + so that switches like --hash-size can be honored. */ + parse_args (&argc, &argv); + +- if (argc > 1 && stat (out_file_name, &sob) == 0) ++ if (argc > 1 && stat (out_file_name, &sob) == 0 && strcmp(out_file_name,dev_null_file)!=0) + { + int i; + +-- +2.17.1 + -- To view, visit https://review.coreboot.org/c/coreboot/+/35098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a Gerrit-Change-Number: 35098 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: trogdor: initial mainboard + libpayload support
by mturney mturney (Code Review) 25 Oct '19

25 Oct '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35495 ) Change subject: trogdor: initial mainboard + libpayload support ...................................................................... trogdor: initial mainboard + libpayload support Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M payloads/libpayload/Kconfig A payloads/libpayload/configs/config.trogdor M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/sc7180.c A src/mainboard/google/trogdor/Kconfig A src/mainboard/google/trogdor/Kconfig.name A src/mainboard/google/trogdor/Makefile.inc A src/mainboard/google/trogdor/board.h A src/mainboard/google/trogdor/board_info.txt A src/mainboard/google/trogdor/boardid.c A src/mainboard/google/trogdor/bootblock.c A src/mainboard/google/trogdor/chromeos.c A src/mainboard/google/trogdor/chromeos.fmd A src/mainboard/google/trogdor/devicetree.cb A src/mainboard/google/trogdor/mainboard.c A src/mainboard/google/trogdor/memlayout.ld A src/mainboard/google/trogdor/reset.c A src/mainboard/google/trogdor/romstage.c 18 files changed, 492 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35495/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 97b970b..0bab0db 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -263,6 +263,11 @@ depends on SERIAL_CONSOLE default n +config SC7180_SERIAL_CONSOLE + bool "SC7180 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor new file mode 100644 index 0000000..0625ff5 --- /dev/null +++ b/payloads/libpayload/configs/config.trogdor @@ -0,0 +1,5 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_SC7180_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e7594..701434d 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/qcs405.c serial/serial.c +libc-$(CONFIG_LP_SC7180_SERIAL_CONSOLE) += serial/sc7180.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c diff --git a/payloads/libpayload/drivers/serial/sc7180.c b/payloads/libpayload/drivers/serial/sc7180.c new file mode 100644 index 0000000..0908ee6 --- /dev/null +++ b/payloads/libpayload/drivers/serial/sc7180.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2012, 2014, 2016, 2019, The Linux Foundation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <libpayload.h> + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + +} diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig new file mode 100644 index 0000000..12e3423 --- /dev/null +++ b/src/mainboard/google/trogdor/Kconfig @@ -0,0 +1,55 @@ + +config BOARD_GOOGLE_TROGDOR_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_6144 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7180 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default google/trogdor + +config MAINBOARD_VENDOR + string + default "Google" + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Trogdor" if BOARD_GOOGLE_TROGDOR + +config GBB_HWID + string + depends on CHROMEOS + default "TROGDOR TEST 1859" if BOARD_GOOGLE_TROGDOR + +endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name new file mode 100644 index 0000000..425c9bf --- /dev/null +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_TROGDOR + bool "Trogdor" + select BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc new file mode 100644 index 0000000..5657df8 --- /dev/null +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -0,0 +1,38 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## Copyright 2019 The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += boardid.c +bootblock-y += memlayout.ld +bootblock-y += chromeos.c +bootblock-y += bootblock.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += memlayout.ld +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h new file mode 100644 index 0000000..23e40fc --- /dev/null +++ b/src/mainboard/google/trogdor/board.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ + +#include <gpio.h> +#include <soc/gpio.h> + +/* TODO: update these for Trogdor hardware */ +#define GPIO_EC_IN_RW GPIO(11) +#define GPIO_AP_EC_INT GPIO(122) +#define GPIO_AP_SUSPEND GPIO(126) +#define GPIO_WP_STATE GPIO(128) +#define GPIO_H1_AP_INT GPIO(129) + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/board_info.txt b/src/mainboard/google/trogdor/board_info.txt new file mode 100644 index 0000000..a4b8b4e --- /dev/null +++ b/src/mainboard/google/trogdor/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Trogdor Qualcomm Trogdor reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c new file mode 100644 index 0000000..2de72ba --- /dev/null +++ b/src/mainboard/google/trogdor/boardid.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Trogdor */ + const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Trogdor */ + const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Trogdor */ + const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c new file mode 100644 index 0000000..c658093 --- /dev/null +++ b/src/mainboard/google/trogdor/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c new file mode 100644 index 0000000..f5764c0 --- /dev/null +++ b/src/mainboard/google/trogdor/chromeos.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include "board.h" + +int get_write_protect_state(void) +{ +#if 0 + return !gpio_get(GPIO_WP_STATE); +#else + return 0; +#endif +} + +void setup_chromeos_gpios(void) +{ +#if 0 + /* Example of what needs to be done here */ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_output(GPIO_AP_SUSPEND, 1); + gpio_input(GPIO_WP_STATE); + gpio_input_pullup(GPIO_H1_AP_INT); +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +#if 0 + /* Example of what needs to be done here */ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +#endif +} diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd new file mode 100644 index 0000000..c7a0ad1 --- /dev/null +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# TODO: update for Trogdor +FLASH@0x0 6M { + WP_RO 3M { + RO_SECTION 0x184000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + #TODO: Move FMAP to 2M or 3M once FSG can be smaller + FMAP@0x180000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 16K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + RO_FSG(PRESERVE) + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1024K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1024K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/trogdor/devicetree.cb b/src/mainboard/google/trogdor/devicetree.cb new file mode 100644 index 0000000..d64ade4 --- /dev/null +++ b/src/mainboard/google/trogdor/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 and +## only version 2 as published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/qualcomm/sc7180 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c new file mode 100644 index 0000000..ce03ce1 --- /dev/null +++ b/src/mainboard/google/trogdor/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <arch/mmio.h> +#include <gpio.h> +#include <timestamp.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/trogdor/memlayout.ld b/src/mainboard/google/trogdor/memlayout.ld new file mode 100644 index 0000000..e9b147c --- /dev/null +++ b/src/mainboard/google/trogdor/memlayout.ld @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <soc/memlayout.ld> diff --git a/src/mainboard/google/trogdor/reset.c b/src/mainboard/google/trogdor/reset.c new file mode 100644 index 0000000..558f63d --- /dev/null +++ b/src/mainboard/google/trogdor/reset.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/trogdor/romstage.c b/src/mainboard/google/trogdor/romstage.c new file mode 100644 index 0000000..7185387 --- /dev/null +++ b/src/mainboard/google/trogdor/romstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stages.h> +#include <soc/qclib_common.h> + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007 Gerrit-Change-Number: 35495 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/skylake: lock aesni msr
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35188 ) Change subject: soc/skylake: lock aesni msr ...................................................................... soc/skylake: lock aesni msr Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/cpu.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..984c134 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,6 +420,16 @@ wrmsr(MSR_EMULATE_PM_TIMER, msr); } +void cpu_lock_aesni(void) { + msr_t msr; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; /* Lock it */ + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -442,6 +452,9 @@ /* Configure Intel Speed Shift */ configure_isst(); + /* Lock AES-NI MSR */ + cpu_lock_aesni(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); -- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

9 47

Change in coreboot[master]: mb/supermicro/x11: add x11ssm-f board
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35427 ) Change subject: mb/supermicro/x11: add x11ssm-f board ...................................................................... mb/supermicro/x11: add x11ssm-f board Add support for the X11SSM-F which is based on Intel KBL. This change depends on I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11/ssm-f/x11ssh-tf.md M src/mainboard/supermicro/x11/Kconfig A src/mainboard/supermicro/x11/mainboard.c M src/mainboard/supermicro/x11/ramstage.c A src/mainboard/supermicro/x11/variants/ssm-f/Kconfig A src/mainboard/supermicro/x11/variants/ssm-f/Kconfig.name A src/mainboard/supermicro/x11/variants/ssm-f/board_info.txt A src/mainboard/supermicro/x11/variants/ssm-f/devicetree.cb A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/apic.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/dmar.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/dsdt.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/facp.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/facs.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/hpet.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/mcfg.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/spmi.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/ssdt.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/biosdecode.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/cpuinfo.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/dmesg.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/dmidecode.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/input_bustypes.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/intelmetool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool_gpio.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool_pcrs.txt A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/list_sys_proc.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.html A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.txt A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.xml A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lspci.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lsusb.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/msrtool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/nvramtool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/buddyinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cgroups A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cmdline A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/config.gz A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/consoles A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cpuinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/crypto A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/devices A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/diskstats A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/execdomains A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/filesystems A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/interrupts A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/iomem A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/ioports A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/key-users A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/keys A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/loadavg A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/locks A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/mdstat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/meminfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/misc A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/mtrr A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/pagetypeinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/partitions A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/slabinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/softirqs A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/stat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/swaps A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/timer_list A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/uptime A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/version A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/vmallocinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/vmstat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/zoneinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/superiotool.log A src/mainboard/supermicro/x11/variants/ssm-f/include/variant/gpio.h A src/mainboard/supermicro/x11/variants/ssm-f/ramstage.c A src/mainboard/supermicro/x11/variants/ssm-f/todo.txt A src/mainboard/supermicro/x11/variants/ssm-f/working_config 75 files changed, 88,362 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35427/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Gerrit-Change-Number: 35427 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

9 94

Change in ...coreboot[master]: [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33563 Change subject: [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode ...................................................................... [UNTESTED]soc/intel/braswell: Use native code to update BSP microcode This removes the need to specify the microcode size and location in Kconfig. Change-Id: I9a391a3956b30dd8727bec669cb79a0a8588d5f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S M src/mainboard/facebook/fbg1701/Kconfig M src/soc/intel/braswell/Kconfig 3 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33563/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3460b9d..733c523 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -53,6 +53,15 @@ * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. */ + +#if CONFIG(MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + lea fake_fsp_stack, %esp jmp find_fsp find_fsp_ret: diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index b3c589d..e92022b 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -56,16 +56,6 @@ hex default 0x00800000 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x10C00 - help - This should be updated when the microcode patch changes. - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFFE9400 - config MRC_SETTINGS_CACHE_SIZE hex default 0x08000 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 920179f83..45a0cf8 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -52,6 +52,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select C_ENVIRONMENT_BOOTBLOCK + select MICROCODE_UPDATE_PRE_RAM config DCACHE_BSP_STACK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/33563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a391a3956b30dd8727bec669cb79a0a8588d5f0 Gerrit-Change-Number: 33563 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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