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Change in ...coreboot[master]: security/intel/stm STM support
by Name of user not set (Code Review) 08 Feb '20

08 Feb '20

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33234 Change subject: security/intel/stm STM support ...................................................................... security/intel/stm STM support Initial commit for Coreboot STM supporX Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec --- M src/security/Kconfig M src/security/Makefile.inc A src/security/intel/stm/Kconfig A src/security/intel/stm/Makefile.inc A src/security/intel/stm/SmmStm.c A src/security/intel/stm/SmmStm.h A src/security/intel/stm/StmApi.h A src/security/intel/stm/StmPlatformResource.c A src/security/intel/stm/StmPlatformResource.h A src/security/intel/stm/StmPlatformSmm.c 10 files changed, 2,235 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33234/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..e9b5225 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/intel/stm/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..e49c172 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,4 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += intel/stm + diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig new file mode 100644 index 0000000..e8eea02 --- /dev/null +++ b/src/security/intel/stm/Kconfig @@ -0,0 +1,17 @@ + +menu "SMI Transfer Monitor (STM)" + +config STM + bool "Enable STM" + default y + depends on (PLATFORM_USES_FSP2_0||PLATFORM_USES_FSP1_1||PLATFORM_USES_FSP1_0) + +if STM + +config MSEG_SIZE + hex "mseg size" + default 0x400000 + +endif #STM + +endmenu diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc new file mode 100644 index 0000000..24d7bac --- /dev/null +++ b/src/security/intel/stm/Makefile.inc @@ -0,0 +1,16 @@ + +# put the stm where is can be found + +cbfs-files-y += stm.bin +stm.bin-file = stm.bin +stm.bin-type = raw + +ramstage-y += SmmStm.c +ramstage-y += StmPlatformSmm.c +ramstage-y += StmPlatformResource.c + +smm-y += StmPlatformResource.c +smm-y += SmmStm.c +smm-y += StmPlatformSmm.c + + diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c new file mode 100644 index 0000000..677d514 --- /dev/null +++ b/src/security/intel/stm/SmmStm.c @@ -0,0 +1,894 @@ +/** @file + + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> +#include <string.h> +#include <cpu/x86/mp.h> +#include <console/console.h> + +#define TXT_EVTYPE_BASE 0x400 +#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +#define SIZE_4KB 0x00001000 +#define SIZE_4MB 0x00400000 + +#define IA32_PG_P (1<<0) +#define IA32_PG_RW (1<<1) +#define IA32_PG_PS (1<<7) + +#define STM_PAGE_SHIFT 12 +#define STM_PAGE_MASK 0xFFF +#define STM_SIZE_TO_PAGES(a) (((a) >> STM_PAGE_SHIFT) + (((a) & STM_PAGE_MASK) ? 1 : 0)) +#define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT) + +#define STM_ACCESS_DENIED 15 +#define STM_UNSUPPORTED 3 + +#define STM_BUFFER_TOO_SMALL 1 + +#define STM_SM_MONITOR_STATE_ENABLED 1 + +#define RESOURCEHEAPSIZE 4096 + +uint32_t GetVmcsSize(void); +void StmGen4GPageTableIa32(uint32_t PageTableBase); +void StmGen4GPageTableX64(uint32_t PageTableBase); +bool StmCheckStmImage(void * StmImage, uint32_t StmImageSize); +void StmLoadStmImage(void * StmImage, UINTN StmImageSize); + +bool HandleSingleResource(STM_RSC *Resource, STM_RSC *Record); +void AddSingleResource(STM_RSC *Resource); +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries); +bool ValidateResource(STM_RSC *ResourceList, uint32_t NumEntries); +UINTN GetResourceSize(STM_RSC *ResourceList, uint32_t NumEntries); + +typedef struct { + + uint64_t VmcsRevisionID:31; + uint64_t AlwaysZero:1; + uint64_t VmcsSize:13; + uint64_t Reserved1:3; + uint64_t VmxonAddWidth:1; + uint64_t StmSupported:1; + uint64_t VmcsMemoryType:4; + uint64_t InOutReporting:1; + uint64_t MayClearDefaults:1; + uint64_t Reserved2:8; +} VMX_BASIC_MSR_BITS; + +typedef union { + VMX_BASIC_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} VMX_BASIC_MSR; + +typedef struct { + uint64_t valid:1; + uint64_t reserved1:1; + uint64_t VmxOffBlockSmi:1; + uint64_t reserved2:9; + uint64_t MsegAddress:20; + uint64_t reserved3:32; +} SMM_MONITOR_CTL_MSR_BITS; + +extern struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +typedef union { + SMM_MONITOR_CTL_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} SMM_MONITOR_CTL_MSR; + +// +// Template of STM_RSC_END structure for copying. +// + +STM_RSC_END mRscEndNode = { + {END_OF_RESOURCES, sizeof(STM_RSC_END)}, +}; + +uint8_t *mStmResourcesPtr = NULL; +UINTN mStmResourceTotalSize = 0x0; +UINTN mStmResourceSizeUsed = 0x0; +UINTN mStmResourceSizeAvailable = 0x0; + +uint8_t StmResourceHeap[RESOURCEHEAPSIZE]; + +uint32_t mStmState = 0; + +/** + + Handle single Resource to see if it can be merged into Record. + + @param Resource A pointer to resource node to be added + @param Record A pointer to record node to be merged + + @retval true resource handled + @retval false resource is not handled + +**/ + +bool +HandleSingleResource( + STM_RSC *Resource, + STM_RSC *Record + ) +{ + uint64_t ResourceLo; + uint64_t ResourceHi; + uint64_t RecordLo; + uint64_t RecordHi; + + ResourceLo = 0; + ResourceHi = 0; + RecordLo = 0; + RecordHi = 0; + + // + // Calling code is responsible for making sure that + // Resource->Header.RscType == (*Record)->Header.RscType + // thus we use just one of them as switch variable. + // + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + ResourceLo = Resource->Mem.Base; + ResourceHi = Resource->Mem.Base + Resource->Mem.Length; + RecordLo = Record->Mem.Base; + RecordHi = Record->Mem.Base + Record->Mem.Length; + if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes; + return true; + } else { + return false; + } + } + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + ResourceLo = (uint64_t) Resource->Io.Base; + ResourceHi = (uint64_t) Resource->Io.Base + (uint64_t) Resource->Io.Length; + RecordLo = (uint64_t) Record->Io.Base; + RecordHi = (uint64_t) Record->Io.Base + (uint64_t) Record->Io.Length; + break; + case PCI_CFG_RANGE: + if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || + (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) { + return false; + } + if (memcmp (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) { + return false; + } + ResourceLo = (uint64_t) Resource->PciCfg.Base; + ResourceHi = (uint64_t) Resource->PciCfg.Base + (uint64_t) Resource->PciCfg.Length; + RecordLo = (uint64_t) Record->PciCfg.Base; + RecordHi = (uint64_t) Record->PciCfg.Base + (uint64_t) Record->PciCfg.Length; + if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; + return true; + } else { + return false; + } + } + break; + case MACHINE_SPECIFIC_REG: + // + // Special case - merge MSR masks in place. + // + if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { + return false; + } + Record->Msr.ReadMask |= Resource->Msr.ReadMask; + Record->Msr.WriteMask |= Resource->Msr.WriteMask; + return true; + default: + return false; + } + // + // If resources are disjoint + // + if ((ResourceHi < RecordLo) || (ResourceLo > RecordHi)) { + return false; + } + + // + // If resource is consumed by record. + // + if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) { + return true; + } + // + // Resources are overlapping. + // Resource and record are merged. + // + ResourceLo = (ResourceLo < RecordLo) ? ResourceLo : RecordLo; + ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi; + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + Record->Mem.Base = ResourceLo; + Record->Mem.Length = ResourceHi - ResourceLo; + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + Record->Io.Base = (uint64_t) ResourceLo; + Record->Io.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + case PCI_CFG_RANGE: + Record->PciCfg.Base = (uint64_t) ResourceLo; + Record->PciCfg.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + default: + return false; + } + + return true; +} + +/** + + Add resource node. + + @param Resource A pointer to resource node to be added + +**/ +void AddSingleResource(STM_RSC *Resource) +{ + STM_RSC *Record; + + Record = (STM_RSC *)mStmResourcesPtr; + + while (true) { + if (Record->Header.RscType == END_OF_RESOURCES) { + break; + } + // + // Go to next record if resource and record types don't match. + // + if (Resource->Header.RscType != Record->Header.RscType) { + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + continue; + } + // + // Record is handled inside of procedure - don't adjust. + // + if (HandleSingleResource (Resource, Record)) { + return ; + } + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + } + + // + // Add resource to the end of area. + // + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode), + Resource, + Resource->Header.Length + ); + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length, + &mRscEndNode, + sizeof(mRscEndNode) + ); + mStmResourceSizeUsed += Resource->Header.Length; + mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed; + + return ; +} + +/** + + Add resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + +**/ +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + return ; + } + AddSingleResource (Resource); + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return ; +} + +/** + + Validate resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +bool +ValidateResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + UINTN SubIndex; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + printk(BIOS_DEBUG, "ValidateResource (%llu) - RscType(%x)\n", Index, Resource->Header.RscType); + // + // Validate resource. + // + switch (Resource->Header.RscType) { + case END_OF_RESOURCES: + if (Resource->Header.Length != sizeof (STM_RSC_END)) { + return false; + } + // + // If we are passed actual number of resources to add, + // END_OF_RESOURCES structure between them is considered an + // error. If NumEntries == 0 END_OF_RESOURCES is a termination. + // + if (NumEntries != 0) { + return false; + } else { + // + // If NumEntries == 0 and list reached end - return success. + // + return true; + } + break; + + case MEM_RANGE: + case MMIO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_MEM_DESC)) { + return false; + } + + if (Resource->Mem.RWXAttributes > FULL_ACCS) { + return false; + } + break; + + case IO_RANGE: + case TRAPPED_IO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_IO_DESC)) { + return false; + } + + if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) { + return false; + } + break; + + case PCI_CFG_RANGE: + printk(BIOS_DEBUG, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction); + if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { + return false; + } + for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) { + if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) { + return false; + } + } + if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) { + return false; + } + break; + + case MACHINE_SPECIFIC_REG: + if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) { + return false; + } + break; + + default : + printk(BIOS_DEBUG, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType); + return false; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return true; +} + +/** + + Get resource list. + EndResource is excluded. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +UINTN +GetResourceSize ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + Resource = ResourceList; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + break; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return (UINTN)((uint32_t)Resource - (uint32_t) ResourceList); +} + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are added + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int +AddPiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + //int Status; + UINTN ResourceSize; + //void * NewResource; + //UINTN NewResourceSize; + + printk (BIOS_DEBUG, "AddPiResource - Enter\n"); + + if (!ValidateResource (ResourceList, NumEntries)) { + return -1; //EFI_INVALID_PARAMETER; + } + + ResourceSize = GetResourceSize (ResourceList, NumEntries); + printk (BIOS_DEBUG, "ResourceSize - 0x%08llx\n", ResourceSize); + if (ResourceSize == 0) { + return -1;//EFI_INVALID_PARAMETER; + } + + if (mStmResourcesPtr == NULL) { + // + // Copy EndResource for intialization + // + //mStmResourcesPtr = (uint8_t *)(UINTN)NewResource; + //mStmResourceTotalSize = NewResourceSize; + + mStmResourcesPtr = StmResourceHeap; + mStmResourceTotalSize = RESOURCEHEAPSIZE; + memset(mStmResourcesPtr, 0, RESOURCEHEAPSIZE); + + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + + // + // Let SmmCore change resource ptr + // + //NotifyStmResourceChange (mStmResourcesPtr); + } else if (mStmResourceSizeAvailable < ResourceSize) { + // + // Need enlarge + // + printk(BIOS_DEBUG, "ERROR - not enough soace for SMM resource list\n"); + return -1; + } + + // + // Check duplication + // + AddResource (ResourceList, NumEntries); + + return 0;//EFI_SUCCESS; +} + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are deleted + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + +**/ +int32_t +DeletePiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + if (ResourceList != NULL) { + // TBD + //ASSERT (false); + return -1;//EFI_UNSUPPORTED; + } + // + // Delete all + // + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + return 0;//EFI_SUCCESS; +} + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if size of too small. + + @retval EFI_SUCCESS If resources are returned. + @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources. + +**/ +int32_t +GetPiResource ( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ) +{ + if (*ResourceSize < mStmResourceSizeUsed) { + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return -1;//EFI_BUFFER_TOO_SMALL; + } + + memcpy (ResourceList, mStmResourcesPtr, mStmResourceSizeUsed); + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return 0;//EFI_SUCCESS; +} + +/** + Get 4K page aligned VMCS size. + @return 4K page aligned VMCS size + +**/ +uint32_t +GetVmcsSize ( + void + ) +{ + uint32_t ThisVmcsSize; + VMX_BASIC_MSR MsrData64; + int StmSupport; + + MsrData64.msr = rdmsr (IA32_VMX_BASIC_MSR_INDEX); + + ThisVmcsSize = MsrData64.bits.VmcsSize; + StmSupport = MsrData64.bits.StmSupported; + printk(BIOS_DEBUG, "GetVmcsSize: Size %d StmSupport %d\n", ThisVmcsSize, StmSupport); + + // + // VMCS require 0x1000 alignment + // + ThisVmcsSize = STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (ThisVmcsSize)); + + return ThisVmcsSize; +} + +/** + + Create 4G page table for STM. + 4M Non-PAE page table in IA32 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableIa32 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + uint32_t *Pte; + uint32_t Address; + + Pte = (uint32_t*)(uint32_t)PageTableBase; + + Address = 0; + for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) { + *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + Address += SIZE_4MB; + } + + return ; +} + +/** + + Create 4G page table for STM. + 2M PAE page table in X64 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableX64 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + UINTN SubIndex; + uint64_t *Pde; + uint64_t *Pte; + uint64_t *Pml4; + + Pml4 = (uint64_t*)(uint32_t) PageTableBase; + PageTableBase += SIZE_4KB; + *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; + + Pde = (uint64_t*)(uint32_t)PageTableBase; + PageTableBase += SIZE_4KB; + Pte = (uint64_t *)(uint32_t)PageTableBase; + + for (Index = 0; Index < 4; Index++) { + *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P; + Pde++; + PageTableBase += SIZE_4KB; + + for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) { + *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + } + } + + return ; +} + +/** + + Check STM image size. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval true check pass + @retval false check fail +**/ + +bool StmCheckStmImage ( + void * StmImage, + uint32_t StmImageSize + ) +{ + UINTN MinMsegSize; + STM_HEADER *StmHeader; + + StmHeader = (STM_HEADER *)StmImage; + + // + // Get Minimal required Mseg size + // + MinMsegSize = (STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (StmHeader->SwStmHdr.StaticImageSize)) + + StmHeader->SwStmHdr.AdditionalDynamicMemorySize + + (StmHeader->SwStmHdr.PerProcDynamicMemorySize + GetVmcsSize () * 2) * mp_state.cpu_count); + if (MinMsegSize < StmImageSize) { + MinMsegSize = StmImageSize; + } + + if (StmHeader->HwStmHdr.Cr3Offset >= StmHeader->SwStmHdr.StaticImageSize) { + // + // We will create page table, just in case that SINIT does not create it. + // + if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6)) { + MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6); + } + } + + // + // Check if it exceeds MSEG size + // + if (MinMsegSize > CONFIG_MSEG_SIZE) { + return false; + } + + return true; + +} + + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + +**/ +void +StmLoadStmImage ( + void * StmImage, + UINTN StmImageSize + ) +{ + uint32_t MsegBase; + STM_HEADER *StmHeader; + SMM_MONITOR_CTL_MSR SmmMonitorMsr; + + StmHeader = (STM_HEADER *)(uint32_t)StmImage; + SmmMonitorMsr.msr = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + MsegBase = SmmMonitorMsr.bits.MsegAddress << 12; + + //ZeroMem ((void *)(uint32_t)MsegBase, (uint32_t)PcdGet32 (PcdCpuMsegSize)); + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); + //memcpy ((void *)(uint32_t)MsegBase, (void *)(uint32_t)StmImage, StmImageSize); + memcpy((void *) MsegBase, (void *) StmImage, (size_t) StmImageSize); + + + if (sizeof(UINTN) == sizeof(uint64_t)) { + StmGen4GPageTableX64 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } else { + StmGen4GPageTableIa32 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } + + // BUGBUG: SNB can not write 0x9B twice +// WriteCpuMsegInfo (); +} + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval EFI_SUCCESS Load STM to MSEG successfully + @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image + @retval EFI_UNSUPPORTED MSEG is not enabled + +**/ +int LoadMonitor ( + void * StmImage, + uint32_t StmImageSize + ) +{ + SMM_MONITOR_CTL_MSR SmmMonCtlMsr; + + SmmMonCtlMsr.msr = (msr_t) rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + + if (SmmMonCtlMsr.bits.MsegAddress == 0) { + return STM_UNSUPPORTED; + } + if (SmmMonCtlMsr.bits.valid != 0) { + // BUGBUG: SNB can not write 0x9B twice +// return EFI_ALREADY_STARTED; + } + + if (!StmCheckStmImage (StmImage, StmImageSize)) { + return STM_BUFFER_TOO_SMALL; + } + +#ifdef TPMSUPPORT + // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence. + TpmMeasureAndLogData( + 0, // PcrIndex + TXT_EVTYPE_STM_HASH, // EventType + NULL, // EventLog + 0, // LogLen + (void *)StmImage, // HashData + StmImageSize // HashDataLen + ); +#endif + StmLoadStmImage (StmImage, StmImageSize); + + mStmState |= STM_SM_MONITOR_STATE_ENABLED; + + return STM_SUCCESS; +} + +/** + This function return BIOS STM resource. + Produced by SmmStm. + Comsumed by SmmMpService when Init. + + @return BIOS STM resource +**/ +void * +GetStmResource( + void + ) +{ + return mStmResourcesPtr; +} + diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h new file mode 100644 index 0000000..4442a63 --- /dev/null +++ b/src/security/intel/stm/SmmStm.h @@ -0,0 +1,122 @@ +/** @file + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may + be found at http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED + +**/ + +#ifndef _SMM_STM_H_ +#define _SMM_STM_H_ + +#include "StmApi.h" + +#define IA32_VMX_BASIC_MSR_INDEX 0x480 +#define IA32_VMX_MISC_MSR_INDEX 0x485 +#define IA32_SMM_MONITOR_CTL_MSR_INDEX 0x9B +#define IA32_SMM_MONITOR_VALID (1<<0) + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval SUCCESS Load STM to MSEG successfully + @retval BUFFER_TOO_SMALL MSEG is smaller than minimal size of STM image + +**/ +int LoadMonitor( + void *StmImage, + uint32_t StmImageSize + ); + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are added + @retval INVALID_PARAMETER If nested procedure detected resource failer + @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int AddPiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are deleted + @retval NVALID_PARAMETER If nested procedure detected resource failer + +**/ +int DeletePiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if + size of too small. + + @retval SUCCESS If resources are returned. + @retval BUFFER_TOO_SMALL If resource list buffer is too small to + hold the whole resources. + +**/ +int GetPiResource( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ); + +/** + This function notify STM resource change. + + @param StmResource BIOS STM resource + +**/ +void +NotifyStmResourceChange( + void *StmResource + ); + +/** + This function return BIOS STM resource. + + @return BIOS STM resource + +**/ +void * +GetStmResource( + void + ); + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, + int32_t entry32_off); + +#endif diff --git a/src/security/intel/stm/StmApi.h b/src/security/intel/stm/StmApi.h new file mode 100644 index 0000000..2328b32 --- /dev/null +++ b/src/security/intel/stm/StmApi.h @@ -0,0 +1,753 @@ +/** @file + STM API definition + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_API_H_ +#define _STM_API_H_ + +#include <stdint.h> + +// definition in STM spec + +#define STM_SPEC_VERSION_MAJOR 1 +#define STM_SPEC_VERSION_MINOR 0 + +typedef uint64_t UINTN; + +#pragma pack (push, 1) + +#define STM_HARDWARE_FIELD_FILL_TO_2K (2048 - sizeof(uint32_t) * 8) +typedef struct { + uint32_t StmHeaderRevision; + uint32_t MonitorFeatures; + uint32_t GdtrLimit; + uint32_t GdtrBaseOffset; + uint32_t CsSelector; + uint32_t EipOffset; + uint32_t EspOffset; + uint32_t Cr3Offset; + uint8_t Reserved[STM_HARDWARE_FIELD_FILL_TO_2K]; +} HARDWARE_STM_HEADER; + +#define STM_FEATURES_IA32E 0x1 + +typedef struct { + uint32_t Intel64ModeSupported :1; // bitfield + uint32_t EptSupported :1; // bitfield + uint32_t Reserved :30; // must be 0 +} STM_FEAT; + +typedef struct { + uint8_t StmSpecVerMajor; + uint8_t StmSpecVerMinor; + uint16_t Reserved; // must be zero + uint32_t StaticImageSize; + uint32_t PerProcDynamicMemorySize; + uint32_t AdditionalDynamicMemorySize; + STM_FEAT StmFeatures; + uint32_t NumberOfRevIDs; + uint32_t StmSmmRevID[1]; + // + // The total STM_HEADER should be 4K. + // +} SOFTWARE_STM_HEADER; + +typedef struct { + HARDWARE_STM_HEADER HwStmHdr; + SOFTWARE_STM_HEADER SwStmHdr; +} STM_HEADER; + +#define SHA1 1 +#define SHA256 2 +typedef struct { + uint64_t BiosComponentBase; + uint32_t ImageSize; + uint32_t HashAlgorithm; // SHA1 or SHA256 + uint8_t Hash[32]; +} TXT_BIOS_COMPONENT_STATUS; + +#define PAGE_SIZE 4096 +typedef struct { + uint32_t ImageSize; + uint32_t Reserved; + uint64_t ImagePageBase[1]; //[NumberOfPages]; +} TXT_BIOS_COMPONENT_UPDATE; + +// If (ImageSizeInBytes % PAGE_SIZE == 0) { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE +// } else { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE + 1 +// } + + +typedef struct { + uint64_t SpeRip; + uint64_t SpeRsp; + uint16_t SpeSs; + uint16_t PageViolationException:1; + uint16_t MsrViolationException:1; + uint16_t RegisterViolationException:1; + uint16_t IoViolationException:1; + uint16_t PciViolationException:1; + uint16_t Reserved1:11; + uint32_t Reserved2; +} STM_PROTECTION_EXCEPTION_HANDLER; + +typedef struct { + uint8_t ExecutionDisableOutsideSmrr:1; + uint8_t Intel64Mode:1; + uint8_t Cr4Pae : 1; + uint8_t Cr4Pse : 1; + uint8_t Reserved1 : 4; +} STM_SMM_ENTRY_STATE; + +typedef struct { + uint8_t SmramToVmcsRestoreRequired : 1; // BIOS restore hint + uint8_t ReinitializeVmcsRequired : 1; // BIOS request + uint8_t Reserved2 : 6; +} STM_SMM_RESUME_STATE; + +typedef struct { + uint8_t DomainType : 4; // STM input to BIOS on each SM + uint8_t XStatePolicy : 2; // STM input to BIOS on each SMI + uint8_t EptEnabled : 1; + uint8_t Reserved3 : 1; +} STM_SMM_STATE; + +typedef struct { + uint64_t Signature; + uint16_t Size; + uint8_t SmmDescriptorVerMajor; + uint8_t SmmDescriptorVerMinor; + uint32_t LocalApicId; + STM_SMM_ENTRY_STATE SmmEntryState; + STM_SMM_RESUME_STATE SmmResumeState; + STM_SMM_STATE StmSmmState; + uint8_t Reserved4; + uint16_t SmmCs; + uint16_t SmmDs; + uint16_t SmmSs; + uint16_t SmmOtherSegment; + uint16_t SmmTr; + uint16_t Reserved5; + uint64_t SmmCr3; + uint64_t SmmStmSetupRip; + uint64_t SmmStmTeardownRip; + uint64_t SmmSmiHandlerRip; + uint64_t SmmSmiHandlerRsp; + uint64_t SmmGdtPtr; + uint32_t SmmGdtSize; + uint32_t RequiredStmSmmRevId; + STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler; + uint64_t Reserved6; + uint64_t BiosHwResourceRequirementsPtr; + // extend area + uint64_t AcpiRsdp; + uint8_t PhysicalAddressBits; +} TXT_PROCESSOR_SMM_DESCRIPTOR; + +#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE "TXTPSSIG" +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0 + +#define SMM_PSD_OFFSET 0xfb00 + +typedef enum { + TxtSmmPageViolation = 1, + TxtSmmMsrViolation, + TxtSmmRegisterViolation, + TxtSmmIoViolation, + TxtSmmPciViolation +} TXT_SMM_PROTECTION_EXCEPTION_TYPE; + +typedef struct { + uint32_t Rdi; + uint32_t Rsi; + uint32_t Rbp; + uint32_t Rdx; + uint32_t Rcx; + uint32_t Rbx; + uint32_t Rax; + uint32_t Cr3; + uint32_t Cr2; + uint32_t Cr0; + uint32_t VmcsExitInstructionInfo; + uint32_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint32_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint32_t Rip; + uint32_t Cs; + uint32_t Rflags; + uint32_t Rsp; + uint32_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32; + +typedef struct { + uint64_t R15; + uint64_t R14; + uint64_t R13; + uint64_t R12; + uint64_t R11; + uint64_t R10; + uint64_t R9; + uint64_t R8; + uint64_t Rdi; + uint64_t Rsi; + uint64_t Rbp; + uint64_t Rdx; + uint64_t Rcx; + uint64_t Rbx; + uint64_t Rax; + uint64_t Cr8; + uint64_t Cr3; + uint64_t Cr2; + uint64_t Cr0; + uint64_t VmcsExitInstructionInfo; + uint64_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint64_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint64_t Rip; + uint64_t Cs; + uint64_t Rflags; + uint64_t Rsp; + uint64_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64; + +typedef union { + STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame; + STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame; +} STM_PROTECTION_EXCEPTION_STACK_FRAME; + +#define STM_SMM_REV_ID 0x80010100 + +typedef struct _STM_SMM_CPU_STATE { + uint8_t Reserved1[0x1d0]; // fc00h + uint32_t GdtBaseHiDword; // fdd0h : NO + uint32_t LdtBaseHiDword; // fdd4h : NO + uint32_t IdtBaseHiDword; // fdd8h : NO + uint8_t Reserved2[0x4]; // fddch + uint64_t IoRdi; // fde0h : NO + // - restricted + uint64_t IoEip; // fde8h : YES + uint64_t IoRcx; // fdf0h : NO + // - restricted + uint64_t IoRsi; // fdf8h : NO + // - restricted + uint8_t Reserved3[0x40]; // fe00h + uint32_t Cr4; // fe40h : NO + uint8_t Reserved4[0x48]; // fe44h + uint32_t GdtBaseLoDword; // fe8ch : NO + uint32_t GdtLimit; // fe90h : NO + // - RESTRICTED + uint32_t IdtBaseLoDword; // fe94h : NO + uint32_t IdtLimit; // fe98h : NO + // - RESTRICTED + uint32_t LdtBaseLoDword; // fe9ch : NO + uint32_t LdtLimit; // fea0h : NO + // - RESTRICTED + uint32_t LdtInfo; // fea4h : NO + // - RESTRICTED + uint8_t Reserved5[0x30]; // fea8h + uint64_t Eptp; // fed8h : NO + uint32_t EnabledEPT; // fee0h : NO + uint8_t Reserved6[0x14]; // fee4h + uint32_t Smbase; // fef8h : YES + // - NO for STM + uint32_t SMMRevId; // fefch : NO + uint16_t IORestart; // ff00h : YES + uint16_t AutoHALTRestart; // ff02h : YES + uint8_t Reserved7[0x18]; // ff04h + uint64_t R15; // ff1ch : YES + uint64_t R14; // ff24h : YES + uint64_t R13; // ff2ch : YES + uint64_t R12; // ff34h : YES + uint64_t R11; // ff3ch : YES + uint64_t R10; // ff44h : YES + uint64_t R9; // ff4ch : YES + uint64_t R8; // ff54h : YES + uint64_t Rax; // ff5ch : YES + uint64_t Rcx; // ff64h : YES + uint64_t Rdx; // ff6ch : YES + uint64_t Rbx; // ff74h : YES + uint64_t Rsp; // ff7ch : YES + uint64_t Rbp; // ff84h : YES + uint64_t Rsi; // ff8ch : YES + uint64_t Rdi; // ff94h : YES + uint64_t IOMemAddr; // ff9ch : NO + uint32_t IOMisc; // ffa4h : NO + uint32_t Es; // ffa8h : NO + uint32_t Cs; // ffach : NO + uint32_t Ss; // ffb0h : NO + uint32_t Ds; // ffb4h : NO + uint32_t Fs; // ffb8h : NO + uint32_t Gs; // ffbch : NO + uint32_t Ldtr; // ffc0h : NO + uint32_t Tr; // ffc4h : NO + uint64_t Dr7; // ffc8h : NO + uint64_t Dr6; // ffd0h : NO + uint64_t Rip; // ffd8h : YES + uint64_t Ia32Efer; // ffe0h : YES + // - NO for STM + uint64_t Rflags; // ffe8h : YES + uint64_t Cr3; // fff0h : NO + uint64_t Cr0; // fff8h : NO +} STM_SMM_CPU_STATE; + +// +// STM Mapping +// + +typedef struct { + uint64_t PhysicalAddress; + uint64_t VirtualAddress; + uint32_t PageCount; + uint32_t PatCacheType; +} STM_MAP_ADDRESS_RANGE_DESCRIPTOR; +#define ST_UC 0x00 +#define WC 0x01 +#define WT 0x04 +#define WP 0x05 +#define WB 0x06 +#define UC 0x07 +#define FOLLOW_MTRR 0xFFFFFFFF + +typedef struct { + uint64_t VirtualAddress; + uint32_t Length; +} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR; + +typedef struct { + uint64_t InterruptedGuestVirtualAddress; + uint32_t Length; + uint64_t InterruptedCr3; + uint64_t InterruptedEptp; + uint32_t MapToSmmGuest:2; + uint32_t InterruptedCr4Pae:1; + uint32_t InterruptedCr4Pse:1; + uint32_t InterruptedIa32eMode:1; + uint32_t Reserved1:27; + uint32_t Reserved2; + uint64_t PhysicalAddress; + uint64_t SmmGuestVirtualAddress; +} STM_ADDRESS_LOOKUP_DESCRIPTOR; +#define DO_NOT_MAP 0 +#define ONE_TO_ONE 1 +#define VIRTUAL_ADDRESS_SPECIFIED 3 + +// +// STM_RESOURCE_LIST +// +#define END_OF_RESOURCES 0 +#define MEM_RANGE 1 +#define IO_RANGE 2 +#define MMIO_RANGE 3 +#define MACHINE_SPECIFIC_REG 4 +#define PCI_CFG_RANGE 5 +#define TRAPPED_IO_RANGE 6 +#define ALL_RESOURCES 7 +#define REGISTER_VIOLATION 8 +#define MAX_DESC_TYPE 8 + +typedef struct { + uint32_t RscType; + uint16_t Length; + uint16_t ReturnStatus:1; + uint16_t Reserved:14; + uint16_t IgnoreResource:1; +} STM_RSC_DESC_HEADER; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t ResourceListContinuation; +} STM_RSC_END; + +// byte granular Memory range support +#define STM_RSC_BGM 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MEM_DESC; +#define STM_RSC_MEM_R 0x1 +#define STM_RSC_MEM_W 0x2 +#define STM_RSC_MEM_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint32_t Reserved; +} STM_RSC_IO_DESC; + +// byte granular MMIO range support +#define STM_RSC_BGI 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MMIO_DESC; +#define STM_RSC_MMIO_R 0x1 +#define STM_RSC_MMIO_W 0x2 +#define STM_RSC_MMIO_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t MsrIndex; + uint32_t KernelModeProcessing:1; + uint32_t Reserved:31; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_RSC_MSR_DESC; + +// bit granular MSR resource support +#define STM_RSC_MSR 0x8 + +typedef struct { + uint8_t Type; // must be 1, indicating Hardware Device Path + uint8_t Subtype; // must be 1, indicating PCI + uint16_t Length; // sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6 + uint8_t PciFunction; + uint8_t PciDevice; +} STM_PCI_DEVICE_PATH_NODE; +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t RWAttributes:2; + uint16_t Reserved:14; + uint16_t Base; + uint16_t Length; + uint8_t OriginatingBusNumber; + uint8_t LastNodeIndex; + STM_PCI_DEVICE_PATH_NODE PciDevicePath[1]; +//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1]; +} STM_RSC_PCI_CFG_DESC; + +#define STM_RSC_PCI_CFG_R 0x1 +#define STM_RSC_PCI_CFG_W 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint16_t In:1; + uint16_t Out:1; + uint16_t Api:1; + uint16_t Reserved1:13; + uint16_t Reserved2; +} STM_RSC_TRAPPED_IO_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; +} STM_RSC_ALL_RESOURCES_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t RegisterType; + uint32_t Reserved; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_REGISTER_VIOLATION_DESC; + +typedef enum { + StmRegisterCr0, + StmRegisterCr2, + StmRegisterCr3, + StmRegisterCr4, + StmRegisterCr8, + StmRegisterMax, +} STM_REGISTER_VIOLATION_TYPE; + +typedef union { + STM_RSC_DESC_HEADER Header; + STM_RSC_END End; + STM_RSC_MEM_DESC Mem; + STM_RSC_IO_DESC Io; + STM_RSC_MMIO_DESC Mmio; + STM_RSC_MSR_DESC Msr; + STM_RSC_PCI_CFG_DESC PciCfg; + STM_RSC_TRAPPED_IO_DESC TrappedIo; + STM_RSC_ALL_RESOURCES_DESC All; + STM_REGISTER_VIOLATION_DESC RegisterViolation; +} STM_RSC; + +// +// VMCS database +// +#define STM_VMCS_DATABASE_REQUEST_ADD 1 +#define STM_VMCS_DATABASE_REQUEST_REMOVE 0 + +// Values for DomainType +// Intepreter of DomainType +#define DOMAIN_DISALLOWED_IO_OUT (1u << 0) +#define DOMAIN_DISALLOWED_IO_IN (1u << 1) +#define DOMAIN_INTEGRITY (1u << 2) +#define DOMAIN_CONFIDENTIALITY (1u << 3) + +#define DOMAIN_UNPROTECTED 0x00 +#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY) +//#define DOMAIN_INTEGRITY_PROT_OUT (DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY) +//#define DOMAIN_FULLY_PROT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_OUT) +//#define DOMAIN_FULLY_PROT_OUT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT) + +// Values for XStatePolicy +#define XSTATE_READWRITE 0x00 +#define XSTATE_READONLY 0x01 +#define XSTATE_SCRUB 0x03 + +typedef struct { + uint64_t VmcsPhysPointer; // bits 11:0 are reserved and must be 0 + uint32_t DomainType :4; + uint32_t XStatePolicy :2; + uint32_t DegradationPolicy :4; + uint32_t Reserved1 :22; // Must be 0 + uint32_t AddOrRemove; +} STM_VMCS_DATABASE_REQUEST; + +// +// Event log +// +#define NEW_LOG 1 +#define CONFIGURE_LOG 2 +#define START_LOG 3 +#define STOP_LOG 4 +#define CLEAR_LOG 5 +#define DELETE_LOG 6 +typedef enum { + EvtLogStarted, + EvtLogStopped, + EvtLogInvalidParameterDetected, + EvtHandledProtectionException, + // unhandled protection exceptions result in reset & cannot be logged + EvtBiosAccessToUnclaimedResource, + EvtMleResourceProtectionGranted, + EvtMleResourceProtectionDenied, + EvtMleResourceUnprotect, + EvtMleResourceUnprotectError, + EvtMleDomainTypeDegraded, + // add more here + EvtMleMax, + // Not used + EvtInvalid = 0xFFFFFFFF, +} EVENT_TYPE; + +//#define STM_EVENT_LOG_PAGE_COUNT_MAX 62 + +typedef struct { + uint32_t PageCount; + uint64_t Pages[1]; // number of elements is PageCount +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER; + +typedef union { + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER LogBuffer; + uint32_t EventEnableBitmap; // bitmap of EVENT_TYPE +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA; + +typedef struct { + uint32_t SubFunctionIndex; + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA Data; +} STM_EVENT_LOG_MANAGEMENT_REQUEST; + +// +// VMCALL API Numbers +// + +// API number convention: BIOS facing VMCALL interfaces have bit 16 clear +#define STM_API_MAP_ADDRESS_RANGE 0x00000001 +#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002 +#define STM_API_ADDRESS_LOOKUP 0x00000003 +#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004 + +// API number convention: MLE facing VMCALL interfaces have bit 16 set +// +// The STM configuration lifecycle is as follows: +// 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked). +// 2. MLE invokes InitializeProtectionVMCALL() to prepare STM for setup of +// initial protection profile. This is done on a single CPU and has global +// effect. +// 3. MLE invokes ProtectResourceVMCALL() to define the initial protection +// profile. The protection profile is global across all CPUs. +// 4. MLE invokes StartStmVMCALL() to enable the STM to begin receiving SMI +// events. This must be done on every logical CPU. +// 5. MLE may invoke ProtectResourceVMCALL() or UnProtectResourceVMCALL() +// during runtime as many times as necessary. +// 6. MLE invokes StopStmVMCALL() to disable the STM. SMI is again masked +// following StopStmVMCALL(). +// +#define STM_API_START 0x00010001 +#define STM_API_STOP 0x00010002 +#define STM_API_PROTECT_RESOURCE 0x00010003 +#define STM_API_UNPROTECT_RESOURCE 0x00010004 +#define STM_API_GET_BIOS_RESOURCES 0x00010005 +#define STM_API_MANAGE_VMCS_DATABASE 0x00010006 +#define STM_API_INITIALIZE_PROTECTION 0x00010007 +#define STM_API_MANAGE_EVENT_LOG 0x00010008 + +// +// Return codes +// +typedef uint32_t STM_STATUS; + +#define STM_SUCCESS 0x00000000 +#define SMM_SUCCESS 0x00000000 +// all error codes have bit 31 set +// STM errors have bit 16 set +#define ERROR_STM_SECURITY_VIOLATION 0x80010001 +#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED 0x80010002 +#define ERROR_STM_PAGE_NOT_FOUND 0x80010003 +#define ERROR_STM_BAD_CR3 0x80010004 +#define ERROR_STM_PHYSICAL_OVER_4G 0x80010005 +#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL 0x80010006 +#define ERROR_STM_UNPROTECTABLE_RESOURCE 0x80010007 +#define ERROR_STM_ALREADY_STARTED 0x80010008 +#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED 0x80010009 +#define ERROR_STM_STOPPED 0x8001000A +#define ERROR_STM_BUFFER_TOO_SMALL 0x8001000B +#define ERROR_STM_INVALID_VMCS_DATABASE 0x8001000C +#define ERROR_STM_MALFORMED_RESOURCE_LIST 0x8001000D +#define ERROR_STM_INVALID_PAGECOUNT 0x8001000E +#define ERROR_STM_LOG_ALLOCATED 0x8001000F +#define ERROR_STM_LOG_NOT_ALLOCATED 0x80010010 +#define ERROR_STM_LOG_NOT_STOPPED 0x80010011 +#define ERROR_STM_LOG_NOT_STARTED 0x80010012 +#define ERROR_STM_RESERVED_BIT_SET 0x80010013 +#define ERROR_STM_NO_EVENTS_ENABLED 0x80010014 +#define ERROR_STM_OUT_OF_RESOURCES 0x80010015 +#define ERROR_STM_FUNCTION_NOT_SUPPORTED 0x80010016 +#define ERROR_STM_UNPROTECTABLE 0x80010017 +#define ERROR_STM_UNSUPPORTED_MSR_BIT 0x80010018 +#define ERROR_STM_UNSPECIFIED 0x8001FFFF + +// SMM errors have bit 17 set +#define ERROR_SMM_BAD_BUFFER 0x80020001 +#define ERROR_SMM_INVALID_RSC 0x80020004 +#define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005 +#define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006 +#define ERROR_SMM_INVALID_LIST 0x80020007 +#define ERROR_SMM_OUT_OF_MEMORY 0x80020008 +#define ERROR_SMM_AFTER_INIT 0x80020009 +#define ERROR_SMM_UNSPECIFIED 0x8002FFFF + +// Errors that apply to both have bits 15, 16, and 17 set +#define ERROR_INVALID_API 0x80038001 +#define ERROR_INVALID_PARAMETER 0x80038002 + +// +// STM TXT.ERRORCODE codes +// +#define STM_CRASH_PROTECTION_EXCEPTION 0xC000F001 +#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE 0xC000F002 +#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE 0xC000F003 +#define STM_CRASH_BIOS_PANIC 0xC000E000 + +typedef struct { + uint32_t EventSerialNumber; + uint16_t Type; + uint16_t Lock :1; + uint16_t Valid :1; + uint16_t ReadByMle :1; + uint16_t Wrapped :1; + uint16_t Reserved :12; +} LOG_ENTRY_HEADER; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STARTED; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STOPPED; + +typedef struct { + uint32_t VmcallApiNumber; +} ENTRY_EVT_LOG_INVALID_PARAM; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_GRANTED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_DENIED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT_ERROR; + +typedef struct { + uint64_t VmcsPhysPointer; + uint8_t ExpectedDomainType; + uint8_t DegradedDomainType; +} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED; + +typedef union { + ENTRY_EVT_LOG_STARTED Started; + ENTRY_EVT_LOG_STOPPED Stopped; + ENTRY_EVT_LOG_INVALID_PARAM InvalidParam; + ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException; + ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc; + ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted; + ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied; + ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot; + ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError; + ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded; +} LOG_ENTRY_DATA; + +typedef struct { + LOG_ENTRY_HEADER Hdr; + LOG_ENTRY_DATA Data; +} STM_LOG_ENTRY; + +#define STM_LOG_ENTRY_SIZE 256 + +// +// +// +#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF 0x1 + +// +// TXT debug +// +#define SW_SMI_STM_ADD_RUNTIME_RESOURCES_SUB_FUNC 0 +#define SW_SMI_STM_READ_BIOS_RESOURCES_SUB_FUNC 1 +#define SW_SMI_STM_REPLACE_BIOS_RESOURCES_SUB_FUNC 2 + +typedef struct { + uint32_t BufferSize; + uint32_t Reserved; + //uint8_t Data[]; +} TXT_BIOS_DEBUG; + +#pragma pack (pop) + +#endif diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c new file mode 100644 index 0000000..ad8a69b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.c @@ -0,0 +1,259 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <stdint.h> +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <security/intel/stm/StmPlatformResource.h> + +#include <southbridge/intel/common/pmutil.h> +#include <cpu/x86/msr.h> + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +uint32_t mMaxBus; +uint32_t mTsegBase; +uint32_t mTsegSize; +uint16_t mPmBase; + +typedef union { + uint64_t uint64; + msr_t msr; +} msr64_t; + +//uint64_t PciRead64 (UINTN Address); +void ResourceInit(void); +void FixupPciexResource(void); +void AddSimpleResources(void); +void AddMsrResources(void); + +// +// Fixed memory ranges +// + +// +// TSEG memory! +// +STM_RSC_MEM_DESC RscTsegMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0, + 0, + FULL_ACCS +}; +// +// Flash part +// +STM_RSC_MEM_DESC RscSpiMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0xFE000000, + 0x01000000, + FULL_ACCS +}; +// +// ACPI +// +STM_RSC_IO_DESC RscPmIo = { + {IO_RANGE, sizeof (STM_RSC_IO_DESC)}, + 0, + 128 +}; + +// +// PCIE MMIO +// +STM_RSC_MMIO_DESC RscPcieMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0, // Length + RDWR_ACCS +}; +// +// Local APIC +// +STM_RSC_MMIO_DESC RscApicMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0x400, + RDWR_ACCS +}; +// +// Software SMI +// +STM_RSC_TRAPPED_IO_DESC RscSwSmiTrapIo = { + {TRAPPED_IO_RANGE, sizeof (STM_RSC_TRAPPED_IO_DESC)}, + 0xB2, + 2 +}; +// +// End of list +// +STM_RSC_END RscListEnd = { + {END_OF_RESOURCES, sizeof (STM_RSC_END)}, + 0 +}; + +// +// Common PCI devices +// +// +// LPC bridge +// +STM_RSC_PCI_CFG_DESC RscLpcBridgePci = { + {PCI_CFG_RANGE, sizeof (STM_RSC_PCI_CFG_DESC)}, + RDWR_ACCS, 0, + 0, + 0x1000, + 0, + 0, + { + {1, 1, sizeof(STM_PCI_DEVICE_PATH_NODE), LPC_FUNCTION, LPC_DEVICE}, + }, +}; + +// +// Template for MSR resources. +// +STM_RSC_MSR_DESC RscMsrTpl = { + {MACHINE_SPECIFIC_REG, sizeof (STM_RSC_MSR_DESC)}, +}; + +// +// MSR indices to register +// +typedef struct { + uint32_t MsrIndex; + uint64_t ReadMask; + uint64_t WriteMask; +} MSR_TABLE_ENTRY; + +MSR_TABLE_ENTRY MsrTable[] = { + // Index Read Write // MASK64 means need access, MASK0 means no need access. + {SMRR_PHYSBASE_MSR, MASK64, MASK0}, + {SMRR_PHYSMASK_MSR, MASK64, MASK0}, +}; + +/** + + BIOS resources initialization. + +**/ +void ResourceInit(void) +{ + mMaxBus = 255; + + msr_t MsrRead; + + mPmBase = get_pmbase(); + + //mTsegBase = (uint32_t)rdmsr(SMRR_PHYSBASE_MSR) & 0xFFFFF000; + + MsrRead = rdmsr(SMRR_PHYSBASE_MSR); + mTsegBase = MsrRead.lo & 0xFFFFF000; + + //mTsegSize = (uint32_t)(~((uint32_t)rdmsr(SMRR_PHYSMASK_MSR) & 0xFFFFF000) + 1); + + MsrRead = rdmsr(SMRR_PHYSMASK_MSR); + mTsegSize = (~(MsrRead.lo & 0xFFFFF000) + 1); +} + +/** + + Fix up PCIE resource. + +**/ +void FixupPciexResource(void) +{ + // bug, bug, need to fix for coreboot + // + // Find max bus number and PCIEX length + // + //RscPcieMmio.Length = 0x10000000; // 256 MB + //RscPcieMmio.Base = PcdGet64 (PcdPciExpressBaseAddress); +} + +/** + + Add basic resources to BIOS resource database. + +**/ +void +AddSimpleResources(void) +{ + int Status; + msr64_t ReadMsr; + + // + // Fix-up values + // + RscTsegMemory.Base = mTsegBase; + RscTsegMemory.Length = mTsegSize; + + RscPmIo.Base = (uint16_t) mPmBase; + + // + // Local APIC. We assume that all thteads are programmed identically + // despite that it is possible to have individual APIC address for + // each of the threads. If this is the case this programming should + // be corrected. + // + //RscApicMmio.Base = AsmReadMsr64 (IA32_APIC_BASE_MSR_INDEX) & 0xFFFFFF000ull; + + ReadMsr.msr = rdmsr(IA32_APIC_BASE_MSR_INDEX); + RscApicMmio.Base = ReadMsr.uint64 & 0xFFFFFF000ull; + + // + // PCIEX BAR + // + FixupPciexResource (); + + Status = AddPiResource((void *) &RscTsegMemory, 0); + //ASSERT_EFI_ERROR (Status); + Status = AddPiResource((void *) &RscLpcBridgePci, 1); + //ASSERT_EFI_ERROR (Status); +} + +/** + + Add MSR resources to BIOS resource database. + +**/ +void AddMsrResources(void) +{ + uint32_t Status; + uint32_t Index; + + for (Index = 0; Index < sizeof(MsrTable)/sizeof(MsrTable[0]); Index ++) { + + RscMsrTpl.MsrIndex = (uint32_t) MsrTable[Index].MsrIndex; + RscMsrTpl.ReadMask = (uint64_t) MsrTable[Index].ReadMask; + RscMsrTpl.WriteMask = (uint64_t) MsrTable[Index].WriteMask; + + Status = AddPiResource ((void *) &RscMsrTpl, 1); + } +} + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void) +{ + ResourceInit(); + + AddSimpleResources(); + + AddMsrResources(); +} diff --git a/src/security/intel/stm/StmPlatformResource.h b/src/security/intel/stm/StmPlatformResource.h new file mode 100644 index 0000000..e31e74b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.h @@ -0,0 +1,43 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_PLATFORM_RESOURCE_H_ +#define _STM_PLATFORM_RESOURCE_H_ + +#define MASK0 0 +#define MASK64 0xFFFFFFFFFFFFFFFFull + +// +// LPC +// +#define LPC_BUS 0 +#define LPC_DEVICE 31 +#define LPC_FUNCTION 0 +#define R_ACPI_PM_BASE 0x40 +#define ACPI_PM_BASE_MASK 0xFFF8 + +// +// MSRs +// +#define IA32_APIC_BASE_MSR_INDEX 0x1B +#define SMRR_PHYSBASE_MSR 0x1F2 +#define SMRR_PHYSMASK_MSR 0x1F3 + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void); +#endif diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c new file mode 100644 index 0000000..bd9cea5 --- /dev/null +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -0,0 +1,128 @@ +/** @file + STM platform SMM API + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/smm.h> + +#include <stddef.h> +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <stdint.h> + +int LoadStmImage(uint32_t mseg); + +extern bool StmCheckStmImage(void *StmImage, uint32_t StmImageSize); +extern void StmGen4GPageTableIa32(uint32_t PageTableBase); +extern void StmGen4GPageTableX64(uint32_t PageTableBase); + +/** + Load STM image. + + @retval EFI_SUCCESS STM is loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is too small + @retval EFI_UNSUPPORTED MSEG is not enabled +**/ +int LoadStmImage(uint32_t mseg) +{ + int Status; + void *MsegBase; + uint32_t StmBufferSize; + uint32_t StmImageSize; + bool StmStatus; + + STM_HEADER *StmHeader; + + // + // Extract STM image from FV + // + MsegBase = (void *) mseg; + StmBufferSize = CONFIG_MSEG_SIZE; + StmImageSize = 0; + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); // clear the mseg + + StmImageSize = cbfs_boot_load_file("stm.bin", MsegBase, StmBufferSize, CBFS_TYPE_RAW); + printk(BIOS_DEBUG, "STM loaded into mseg: 0x%08x size: %u \n", (uint32_t) MsegBase, StmImageSize); /* status is number of bytes loaded */ + + StmStatus = StmCheckStmImage(MsegBase, StmImageSize); + + StmHeader = MsegBase; + + StmGen4GPageTableX64 ((uint32_t)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + + // Debug stuff + + printk(BIOS_DEBUG, "STM Header - Revision: 0x%08x Features: 0x%08x ... Cr3Offset: 0x%08x\n", + StmHeader->HwStmHdr.StmHeaderRevision, + StmHeader->HwStmHdr.MonitorFeatures, + StmHeader->HwStmHdr.Cr3Offset); + printk(BIOS_DEBUG, "STM Header - StaticImageSize: %d Cr3Location: 0x%08x \n", + StmHeader->SwStmHdr.StaticImageSize, + ((uint32_t) MsegBase + StmHeader->HwStmHdr.Cr3Offset)); + + Status = 0; // always return good for now + + return Status; +} + +struct descriptor +{ + uint16_t limit; + uintptr_t base; +} __attribute__((packed)); + + +void ReadGdtr( struct descriptor *gdtr); + +void ReadGdtr( struct descriptor *gdtr) +{ + __asm__ __volatile__ ( + "sgdt %0" + : "=m" (*gdtr) + ); +} + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, int32_t entry32_off) +{ + struct descriptor Gdtr; + + TXT_PROCESSOR_SMM_DESCRIPTOR * Psd; + + Psd = smbase + SMM_PSD_OFFSET - (apic_id * state_size); + + printk(BIOS_DEBUG, "Setting up Smm Descriptor - Smbase: %p Psd: %p\n", smbase, Psd); + + memset(Psd, 0, sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR)); + + memcpy(&Psd->Signature, TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE, 8); + Psd->SmmDescriptorVerMajor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR; + Psd->SmmDescriptorVerMinor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR; + Psd->SmmSmiHandlerRip = (uint64_t)((uint32_t)smbase + SMM_ENTRY_OFFSET + entry32_off); + Psd->LocalApicId = apic_id; + Psd->Size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + Psd->AcpiRsdp = 0; + Psd->BiosHwResourceRequirementsPtr = (uint64_t)((uint32_t)GetStmResource()); + Psd->SmmCs = 0x8; + Psd->SmmDs = 0x10; + Psd->SmmSs = 0x10; + Psd->SmmOtherSegment = 0x10; + Psd->SmmTr = 0x18; + + ReadGdtr(&Gdtr); + + Psd->SmmGdtPtr = Gdtr.base; + Psd->SmmGdtSize = Gdtr.limit + 1; // the stm will subtract, so need to compensate +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Gerrit-Change-Number: 33234 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

11 128

Change in ...coreboot[master]: intel/apollolake: Add early smbus support
by Christian Gmeiner (Code Review) 08 Feb '20

08 Feb '20

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31461 Change subject: intel/apollolake: Add early smbus support ...................................................................... intel/apollolake: Add early smbus support Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/smbus.h 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31461/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..f7ddc6f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..99a9467 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -23,6 +23,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -112,6 +113,9 @@ /* Program TCO Timer Halt */ tco_configure(); + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); + /* Use Nx and paging to prevent the frontend from writing back dirty * cache-as-ram lines to backing store that doesn't exist when the L1I * speculatively fetches a line that is sitting in the L1D. */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index 4b252d6..a4ff451 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -16,6 +16,9 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_RCV_SLVA 0x09 + /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) @@ -25,4 +28,7 @@ #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic472c71998064d09c9caddc5c80c01e85a381c69 Gerrit-Change-Number: 31461 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: Kconfig: Display a warning if the board is updated incorrectly
by Martin Roth (Code Review) 26 Jan '20

26 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33641 Change subject: Kconfig: Display a warning if the board is updated incorrectly ...................................................................... Kconfig: Display a warning if the board is updated incorrectly Even though we have a comment to run make distclean before switching mainboards, people still ignore this and end up with confusing results. To try to fix this, save the mainboard directory in a Kconfig symbol that will not get updated when the mainboard gets changed. This allows us to compare it to the actual mainboard directory which will be updated when the platform changes and put up an obnoxious warning in the mainboard directory. Add another warning in the main menu, because the initial warning is probably going to be ignored. The main menu points to some documentation on how to fix the problem. Note that this will only catch issues going forward, and won't catch any already saved config that has a problem. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a --- A Documentation/getting_started/fix_dot_config.md M src/Kconfig M src/mainboard/Kconfig 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33641/1 diff --git a/Documentation/getting_started/fix_dot_config.md b/Documentation/getting_started/fix_dot_config.md new file mode 100644 index 0000000..17d89d0 --- /dev/null +++ b/Documentation/getting_started/fix_dot_config.md @@ -0,0 +1,50 @@ +# How to repair your .config file + +## Overview +Many people rely on a saved .config file for building their +platform. This is reasonable, but can create unanticipated +problems. + +## TLDR +* Backup your .config: "cp .config .config_bak" +* Create the defconfig file: "make savedefconfig" +* Edit defconfig & delete unknown config lines: "vi defconfig" +* To just get rid of the warning about a bad .config, remove +* the CONFIG_MAINBOARD_CHECK line. +* The SMBIOS lines are probably incorrect as well. The ROM size +* is very suspect. Check the correct default for your platform. +* Save the defconfig +* Generate a new full config: +* "make -B defconfig KBUILD_DEFCONFIG=defconfig" + +## defconfig or "Mini config" +Instead of saving a "full" config, people should use a defconfig. +This is just the changes from a default coreboot configuration +file. It's significantly smaller, and when a new configuration option +gets added, it just takes the default value for that option when +expanded into a full .config. + +### Generating the defconfig file +To create the defconfig file, run "make savedefconfig". By default +this will generate the file in the root coreboot directory and call +it "defconfig". If there was already a file named "defconfig", this +will overwrite that file. + +### Contents of the defconfig file +As the defconfig file contains just the differences between the +platform and the default choices for the platform. For the current +default platform, the defconfig can actually be an empty file. + +Typically the defconfig will contain at least 2 lines - a +CONFIG_VENDOR_ line and a CONFIG_BOARD_ line. Again though, if you +are building the default board for any particular vendor, that line +may not be present. + +All additional lines in a defconfig file are options that the user +has specifically chosen to update in their config. + +### Generating a .config from a defconfig +To expand the defconfig so that can be used, run: + DFILE=defconfig; make -B defconfig KBUILD_DEFCONFIG=$DFILE + +You can point DFILE to any saved defconfig. diff --git a/src/Kconfig b/src/Kconfig index 72d826f..8eae329 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -16,6 +16,15 @@ mainmenu "coreboot configuration" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over, but if you want to try to repair the " +comment "file, see Documentation/getting_started/fix_dot_config.md " +comment "***********************************************************************" +endif + menu "General setup" config COREBOOT_BUILD @@ -1062,6 +1071,14 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config MAINBOARD_CHECK + string "Mainboard dir - Do not change manually" + default MAINBOARD_DIR + help + Check the platform. If this symbol doesn't match the currently + selected mainboard directory, give the user warnings that they're + probably doing something wrong. + endmenu diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index c88d317..d9216a9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,16 @@ comment "Important: Run 'make distclean' before switching boards" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over. " +comment "* *" +comment "If you ignore this warning and build anyway, you will almost certainly " +comment "get a bad rom with undefined results. " +comment "***********************************************************************" +endif + choice prompt "Mainboard vendor" default VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/33641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a Gerrit-Change-Number: 33641 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Console: Allow console UART to be enabled without serial console
by Martin Roth (Code Review) 26 Jan '20

26 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33380 Change subject: Console: Allow console UART to be enabled without serial console ...................................................................... Console: Allow console UART to be enabled without serial console Currently, when we disable serial console, the serial console uart remains uninitialized. This patch allows coreboot to still set up the UART, even if we're not sending the console to it. BUG=b:74392237 TEST=Verify UART still works, even with coreboot console disabled Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a --- M src/console/Kconfig M src/drivers/uart/Kconfig M src/include/console/uart.h 3 files changed, 28 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33380/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..da769d3 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -33,6 +33,7 @@ bool "Serial port console output" default y depends on DRIVERS_UART + select ENABLE_UART help Send coreboot debug output to a serial port. @@ -47,7 +48,7 @@ specific UART has to be used (e.g. when the platform code performs dangerous configurations). -if CONSOLE_SERIAL +if ENABLE_UART comment "I/O mapped, 8250-compatible" depends on DRIVERS_UART_8250IO @@ -79,13 +80,13 @@ Map the COM port number to the respective I/O port. comment "Serial port base address = 0x3f8" -depends on UART_FOR_CONSOLE = 0 +depends on UART_FOR_CONSOLE = 0 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2f8" -depends on UART_FOR_CONSOLE = 1 +depends on UART_FOR_CONSOLE = 1 && DRIVERS_UART_8250IO comment "Serial port base address = 0x3e8" -depends on UART_FOR_CONSOLE = 2 +depends on UART_FOR_CONSOLE = 2 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2e8" -depends on UART_FOR_CONSOLE = 3 +depends on UART_FOR_CONSOLE = 3 && DRIVERS_UART_8250IO config UART_OVERRIDE_BAUDRATE boolean @@ -156,7 +157,7 @@ default 3 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM -endif # CONSOLE_SERIAL +endif # ENABLE_UART config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1f23a19..9b242fd 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,6 +1,21 @@ config DRIVERS_UART bool +config ENABLE_UART + def_bool n + +config ENABLE_UART_WITHOUT_CONSOLE + bool "Always configure primary UART" + depends on DRIVERS_UART + select ENABLE_UART + help + The primary UART has previously only been set up when the serial console + is enabled. + Selecting this choice will configure the console UART even if the serial + console is disabled. + + Select the UART in the console menu + config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..6bd88ae 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -67,11 +67,16 @@ (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) -#if __CONSOLE_SERIAL_ENABLE__ +#if CONFIG(ENABLE_UART) static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +#else +static inline void __uart_init(void) {} +#endif + +#if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); @@ -81,7 +86,6 @@ uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else -static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a Gerrit-Change-Number: 33380 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 14

Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips
by Peter Lemenkov (Code Review) 24 Jan '20

24 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427 Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips ...................................................................... superio/nsc: Use common defines for NSC PC8xxxx chips * Some common NSC defines moved to superio/nsc/common * All NSC's pc8xxxx chips uses these common definitions * Lenovo T60/X60/Z61t/T400 docking updated to use these common defines * HP ProLiant DL165 G6 Fam10 updated to use this common code Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10 builds fine. Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/z61t/dock.c A src/superio/nsc/common/superio_defs.h D src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c D src/superio/nsc/pc87384/pc87384.h M src/superio/nsc/pc87384/superio.c D src/superio/nsc/pc87392/pc87392.h M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c 20 files changed, 219 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 6d2eed4..7f5411e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,6 +34,7 @@ #include <spd.h> #include <delay.h> #include <superio/serverengines/pilot/pilot.h> +#include <superio/nsc/common/superio_defs.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -50,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC) void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 6d1a80c..58788e7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87382/pc87382.h> +#include <superio/nsc/common/superio_defs.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> @@ -64,8 +64,8 @@ return 0; } -static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); -static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK); +static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO); static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { @@ -170,20 +170,18 @@ /* Docking station side. */ -#include <superio/nsc/pc87384/pc87384.h> - -static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1); static const struct pin_config remote_gpio[] = { - {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, + {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, }; static int pc87384_init(void) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818..cf5e71d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nsc/pc87392/pc87392.h> +#include <superio/nsc/common/superio_defs.h> static void dlpc_write_register(int reg, int value) { @@ -165,58 +165,58 @@ dock_write_register(0x61, 0x20); /* init GPIO pins */ - dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02); - dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* enable GPIO */ dock_write_register(0x30, 0x01); diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h new file mode 100644 index 0000000..cc35508 --- /dev/null +++ b/src/superio/nsc/common/superio_defs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H +#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H + +#define PC8XXXX_FDC 0x00 /* Floppy */ +#define PC8XXXX_PP 0x01 /* Parallel port */ +#define PC8XXXX_SP2 0x02 /* COM 2 / IR */ +#define PC8XXXX_SP1 0x03 /* COM 1 */ +#define PC8XXXX_SWC 0x04 /* System wakeup control */ +//#define PC8XXXX_PM 0x04 /* Power management */ +#define PC8XXXX_KBCM 0x05 /* Mouse */ +#define PC8XXXX_KBCK 0x06 /* Keyboard */ +#define PC8XXXX_GPIO 0x07 /* General purpose IO */ +//#define PC8XXXX_HM 0x08 +#define PC8XXXX_FSD 0x08 /* Fan speed device */ +#define PC8XXXX_ACB 0x08 +#define PC8XXXX_FSCM 0x09 +#define PC8XXXX_FMC 0x09 +#define PC8XXXX_WDT 0x0A +#define PC8XXXX_GMP 0x0B +#define PC8XXXX_MIDI 0x0C +#define PC8XXXX_VLM 0x0D +#define PC8XXXX_TMS 0x0E +#define PC8XXXX_XBUS 0x0F +#define PC8XXXX_RTC 0x10 +#define PC8XXXX_MHC 0x14 +#define PC8XXXX_DOCK 0x19 + +#define PC8XXXX_GPIO_PIN_OE 0x01 +#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC8XXXX_GPIO_PIN_PULLUP 0x04 +#define PC8XXXX_GPIO_PIN_LOCK 0x08 +#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20 +#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40 + +#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02 + +#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */ diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 458c501..f63bea9 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87309.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -28,7 +28,7 @@ return; switch (dev->path.pnp.device) { - case PC87309_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -43,14 +43,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index cf5c7ca..85f21a2 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87360.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87360_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index e1cba17..60e5e23 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87366.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87366_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h deleted file mode 100644 index 6826f45..0000000 --- a/src/superio/nsc/pc87382/pc87382.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87382_H -#define SUPERIO_NSC_PC87382_H - -#define PC87382_IR 0x02 -#define PC87382_SP1 0x03 -#define PC87382_GPIO 0x07 -#define PC87382_DOCK 0x19 -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 688f08c..6a21f51 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87382.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -27,10 +27,10 @@ return; switch (dev->path.pnp.device) { - case PC87382_DOCK: + case PC8XXXX_DOCK: break; - case PC87382_GPIO: + case PC8XXXX_GPIO: break; } } @@ -44,11 +44,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, - { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h deleted file mode 100644 index 2184584..0000000 --- a/src/superio/nsc/pc87384/pc87384.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87384_H -#define SUPERIO_NSC_PC87384_H - -#define PC87384_PP 0x01 -#define PC87384_SP2 0x02 -#define PC87384_SP1 0x03 -#define PC87384_GPIO 0x07 - -#define PC87384_GPIO_PIN_OE 0x01 -#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87384_GPIO_PIN_PULLUP 0x04 -#define PC87384_GPIO_PIN_LOCK 0x08 -#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87384_GPIO_PIN_TRIG_LOW 0x20 -#define PC87384_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index f34acd5..9548d2c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87384.h" +#include <superio/nsc/common/superio_defs.h> static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -29,10 +29,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h deleted file mode 100644 index 5832435..0000000 --- a/src/superio/nsc/pc87392/pc87392.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87392_H -#define SUPERIO_NSC_PC87392_H - -#define PC87392_FDC 0x00 -#define PC87392_PP 0x01 -#define PC87392_SP2 0x02 -#define PC87392_SP1 0x03 -#define PC87392_GPIO 0x07 -#define PC87392_WDT 0x0A - -#define PC87392_GPIO_PIN_OE 0x01 -#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87392_GPIO_PIN_PULLUP 0x04 -#define PC87392_GPIO_PIN_LOCK 0x08 -#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87392_GPIO_PIN_TRIG_LOW 0x20 -#define PC87392_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 -#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index edd4619..9971b5c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87392.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -36,13 +36,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, - { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index b50a920..e6c7f79 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -19,17 +19,6 @@ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H -#define PC87417_FDC 0x00 /* Floppy */ -#define PC87417_PP 0x01 /* Parallel Port */ -#define PC87417_SP2 0x02 /* Com2 */ -#define PC87417_SP1 0x03 /* Com1 */ -#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */ -#define PC87417_KBCM 0x05 /* Mouse */ -#define PC87417_KBCK 0x06 /* Keyboard */ -#define PC87417_GPIO 0x07 -#define PC87417_XBUS 0x0F -#define PC87417_RTC 0x10 - #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ /* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f0e0bb1..a4e8022 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -22,7 +22,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87417.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -30,7 +30,7 @@ return; switch (dev->path.pnp.device) { - case PC87417_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -45,17 +45,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87417_KBCM, PNP_IRQ0, }, - { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, - { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, + { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Gerrit-Change-Number: 31427 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: arch/x86: Add option for running Romstage out of RAM
by Martin Roth (Code Review) 23 Jan '20

23 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414 Change subject: arch/x86: Add option for running Romstage out of RAM ...................................................................... arch/x86: Add option for running Romstage out of RAM AMD's Picasso SOC brings up memory before releasing the X86 processor, and jumps directly to Romstage. Add a global config option to handle that. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034 --- M src/Kconfig M src/arch/x86/assembly_entry.S M src/arch/x86/memlayout.ld 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..bfa0b51 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -146,6 +146,16 @@ time spent decompressing. Doesn't work for XIP stages (assume all ARCH_X86 for now) for obvious reasons. +config ROMSTAGE_IN_RAM + bool + depends on ARCH_X86 + help + Some newer x86 processors come alive with memory enabled, and the + reset vector's physical address falling within DRAM. Select this + item to build romstage to execute in DRAM instead of XIP. Because + this is not a standard, the soc/ or cpu/ code must handle the reset + natively before jumping into the standard romstage code. + config COMPRESS_BOOTBLOCK bool help diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4ead9ea..01c0865 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -26,6 +26,16 @@ * variables that are stage specific. */ .section ".text._start", "ax", @progbits +#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM) +/* + * Systems that run romstage in DRAM, i.e. where romstage is the first + * executed code, are responsible for getting the processor into protected + * mode, setting the stack pointer, and jumping to this location. + */ +.global _romstage_in_ram_continue +_romstage_in_ram_continue: + +#else .global _start _start: @@ -34,6 +44,7 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp +#endif /* clear CAR_GLOBAL area as it is not shared */ cld diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cc72552..da63b05 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -57,6 +57,10 @@ #endif } +#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM) +#include <soc/romstage.ld> +#endif + #if ENV_BOOTBLOCK /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> -- To view, visit https://review.coreboot.org/c/coreboot/+/32414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034 Gerrit-Change-Number: 32414 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

8 40

Change in ...coreboot[master]: HACK PATCH: SDM845: Enable DFS mode for QUP
by mturney mturney (Code Review) 21 Jan '20

21 Jan '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33813 Change subject: HACK PATCH: SDM845: Enable DFS mode for QUP ...................................................................... HACK PATCH: SDM845: Enable DFS mode for QUP Enable DFS mode for QUP which are PORed with I2C & SPI use case in kernel. Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/mainboard/google/cheza/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33813/1 diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index 1a2e42a..a5d1bdb 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -82,6 +82,14 @@ qupv3_fw_init(); setup_usb(); i2c_init(QUPV3_1_SE4, I2C_SPEED_FAST); /* Speaker amp */ + write32((void *)0x117048, 0x21); + write32((void *)0x1172a8, 0x21); + write32((void *)0x1173d8, 0x21); + write32((void *)0x117638, 0x21); + write32((void *)0x11828c, 0x21); + write32((void *)0x1183bc, 0x21); + write32((void *)0x1184ec, 0x21); + write32((void *)0x11874c, 0x21); sdm845_sound_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa Gerrit-Change-Number: 33813 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: HACK fix upstream bug in util/cbfstool/fit.c
by mturney mturney (Code Review) 21 Jan '20

21 Jan '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33812 Change subject: HACK fix upstream bug in util/cbfstool/fit.c ...................................................................... HACK fix upstream bug in util/cbfstool/fit.c Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M util/cbfstool/fit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33812/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 4cd84f2..500e14f 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -601,7 +601,7 @@ name = "unknown"; } - printf(" %6zd %-20s 0x%08"PRIx64" 0x%08zx\n", i, name, + printf(" %6zd %-20s 0x%08zx 0x%08zx\n", i, name, fit->entries[i].address, fit_entry_size_bytes(&fit->entries[i])); } -- To view, visit https://review.coreboot.org/c/coreboot/+/33812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f Gerrit-Change-Number: 33812 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP lenovo/x230t: Add new mainboard
by Damien Zammit (Code Review) 20 Jan '20

20 Jan '20

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34361 ) Change subject: WIP lenovo/x230t: Add new mainboard ...................................................................... WIP lenovo/x230t: Add new mainboard This is a working port for x230t mostly using autoport. However, it should be made into a variant of x230. I don't have time to do that right now, so I'm pushing as is. gpios seem different between x230 and x230t, please check, but this plus the next commit (gpio33 corrected setting) works on x230t. Change-Id: I3e6b1de3c71bac548af9585f83293817d0576129 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/lenovo/x230t/Kconfig A src/mainboard/lenovo/x230t/Kconfig.name A src/mainboard/lenovo/x230t/Makefile.inc A src/mainboard/lenovo/x230t/acpi/ec.asl A src/mainboard/lenovo/x230t/acpi/platform.asl A src/mainboard/lenovo/x230t/acpi/superio.asl A src/mainboard/lenovo/x230t/acpi_tables.c A src/mainboard/lenovo/x230t/board_info.txt A src/mainboard/lenovo/x230t/cmos.default A src/mainboard/lenovo/x230t/cmos.layout A src/mainboard/lenovo/x230t/data.vbt A src/mainboard/lenovo/x230t/devicetree.cb A src/mainboard/lenovo/x230t/dsdt.asl A src/mainboard/lenovo/x230t/gma-mainboard.ads A src/mainboard/lenovo/x230t/gpio.c A src/mainboard/lenovo/x230t/hda_verb.c A src/mainboard/lenovo/x230t/mainboard.c A src/mainboard/lenovo/x230t/romstage.c A src/mainboard/lenovo/x230t/smihandler.c A src/mainboard/lenovo/x230t/thermal.h 20 files changed, 1,137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34361/1 diff --git a/src/mainboard/lenovo/x230t/Kconfig b/src/mainboard/lenovo/x230t/Kconfig new file mode 100644 index 0000000..f3154b5 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Kconfig @@ -0,0 +1,58 @@ +if BOARD_LENOVO_X230T + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select H8_HAS_BAT_TRESHOLDS_IMPL + select NO_UART_ON_SUPERIO + select BOARD_ROMSIZE_KB_12288 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_INT15 + select DRIVERS_RICOH_RCE822 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default lenovo/x230t + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X230 Tablet" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +endif # BOARD_LENOVO_X230T diff --git a/src/mainboard/lenovo/x230t/Kconfig.name b/src/mainboard/lenovo/x230t/Kconfig.name new file mode 100644 index 0000000..93cb151 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_X230T + bool "ThinkPad X230 Tablet" diff --git a/src/mainboard/lenovo/x230t/Makefile.inc b/src/mainboard/lenovo/x230t/Makefile.inc new file mode 100644 index 0000000..30cf715 --- /dev/null +++ b/src/mainboard/lenovo/x230t/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +smm-y += smihandler.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x230t/acpi/ec.asl b/src/mainboard/lenovo/x230t/acpi/ec.asl new file mode 100644 index 0000000..4b11e56 --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} + +#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/x230t/acpi/platform.asl b/src/mainboard/lenovo/x230t/acpi/platform.asl new file mode 100644 index 0000000..bf686f4 --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/platform.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/x230t/acpi/superio.asl b/src/mainboard/lenovo/x230t/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x230t/acpi_tables.c b/src/mainboard/lenovo/x230t/acpi_tables.c new file mode 100644 index 0000000..279674d --- /dev/null +++ b/src/mainboard/lenovo/x230t/acpi_tables.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/x230t/board_info.txt b/src/mainboard/lenovo/x230t/board_info.txt new file mode 100644 index 0000000..09ddde1 --- /dev/null +++ b/src/mainboard/lenovo/x230t/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/lenovo/x230t/cmos.default b/src/mainboard/lenovo/x230t/cmos.default new file mode 100644 index 0000000..979f132 --- /dev/null +++ b/src/mainboard/lenovo/x230t/cmos.default @@ -0,0 +1,16 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Disable diff --git a/src/mainboard/lenovo/x230t/cmos.layout b/src/mainboard/lenovo/x230t/cmos.layout new file mode 100644 index 0000000..27197fb --- /dev/null +++ b/src/mainboard/lenovo/x230t/cmos.layout @@ -0,0 +1,136 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 5 r 0 unused + +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/x230t/data.vbt b/src/mainboard/lenovo/x230t/data.vbt new file mode 100644 index 0000000..9bc06ee --- /dev/null +++ b/src/mainboard/lenovo/x230t/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/x230t/devicetree.cb b/src/mainboard/lenovo/x230t/devicetree.cb new file mode 100644 index 0000000..a3eebce --- /dev/null +++ b/src/mainboard/lenovo/x230t/devicetree.cb @@ -0,0 +1,190 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0x0 on end + device lapic 0xacac off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + register "pci_mmio_size" = "1024" + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x2203 + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x2203 + end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }" + + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + register "c2_latency" = "0x0065" + register "p_cnt_throttling_supported" = "1" + + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on + subsystemid 0x17aa 0x2203 + end # USB 3.0 Controller + device pci 16.0 on + subsystemid 0x17aa 0x2203 + end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21f3 + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x2203 + end # USB2 EHCI #2 + device pci 1b.0 on + subsystemid 0x17aa 0x2203 + end # High Definition Audio + device pci 1c.0 on + subsystemid 0x17aa 0x2203 + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x2203 + end + end + end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x2203 + end # PCIe Port #2 + device pci 1c.2 on + subsystemid 0x17aa 0x2203 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x2203 + end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + subsystemid 0x17aa 0x2203 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xe0" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0xf0" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on + subsystemid 0x17aa 0x2203 + end # SATA Controller 1 + device pci 1f.3 on + subsystemid 0x17aa 0x2203 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on + subsystemid 0x17aa 0x2203 + end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/x230t/dsdt.asl b/src/mainboard/lenovo/x230t/dsdt.asl new file mode 100644 index 0000000..1cb4add --- /dev/null +++ b/src/mainboard/lenovo/x230t/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/x230t/gma-mainboard.ads b/src/mainboard/lenovo/x230t/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/lenovo/x230t/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x230t/gpio.c b/src/mainboard/lenovo/x230t/gpio.c new file mode 100644 index 0000000..7e60e76 --- /dev/null +++ b/src/mainboard/lenovo/x230t/gpio.c @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/x230t/hda_verb.c b/src/mainboard/lenovo/x230t/hda_verb.c new file mode 100644 index 0000000..035bae0 --- /dev/null +++ b/src/mainboard/lenovo/x230t/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2203, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa2203), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x230t/mainboard.c b/src/mainboard/lenovo/x230t/mainboard.c new file mode 100644 index 0000000..29c15e0 --- /dev/null +++ b/src/mainboard/lenovo/x230t/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock (void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/x230t/romstage.c b/src/mainboard/lenovo/x230t/romstage.c new file mode 100644 index 0000000..10cddeb --- /dev/null +++ b/src/mainboard/lenovo/x230t/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + { 1, 1, 3 }, /* P2: dock, OC 3 */ + { 1, 1, -1 }, /* P3: wwan, no OC */ + { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 1, -1 }, /* P5: Expresscard, no OC */ + { 0, 0, -1 }, /* P6: Empty */ + { 1, 2, -1 }, /* P7: dock, no OC */ + { 1, 0, -1 }, + { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: webcam, no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd (&spd[0], 0x50, id_only); + read_spd (&spd[2], 0x51, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/lenovo/x230t/smihandler.c b/src/mainboard/lenovo/x230t/smihandler.c new file mode 100644 index 0000000..2425927 --- /dev/null +++ b/src/mainboard/lenovo/x230t/smihandler.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/x230t/thermal.h b/src/mainboard/lenovo/x230t/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/x230t/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e6b1de3c71bac548af9585f83293817d0576129 Gerrit-Change-Number: 34361 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230t: Use INPUT mode for gpio33 as per discussion
by Damien Zammit (Code Review) 20 Jan '20

20 Jan '20

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34362 ) Change subject: lenovo/x230t: Use INPUT mode for gpio33 as per discussion ...................................................................... lenovo/x230t: Use INPUT mode for gpio33 as per discussion Change-Id: Ieb262f38520aa04c65fb8da73e22c96ae510e3eb Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/lenovo/x230t/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34362/1 diff --git a/src/mainboard/lenovo/x230t/gpio.c b/src/mainboard/lenovo/x230t/gpio.c index 7e60e76..c84ba73 100644 --- a/src/mainboard/lenovo/x230t/gpio.c +++ b/src/mainboard/lenovo/x230t/gpio.c @@ -133,7 +133,7 @@ }; static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio33 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, -- To view, visit https://review.coreboot.org/c/coreboot/+/34362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb262f38520aa04c65fb8da73e22c96ae510e3eb Gerrit-Change-Number: 34362 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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