coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Create preprocessed __ROMCC__ bootblock source
by Kyösti Mälkki (Code Review) 06 Nov '19

06 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35602 ) Change subject: arch/x86: Create preprocessed __ROMCC__ bootblock source ...................................................................... arch/x86: Create preprocessed __ROMCC__ bootblock source Output file is used only as a debugging aid. Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35602/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d..055911c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -163,6 +163,8 @@ @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d + $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \ + $< > $(objgenerated)/bootblock_romcc.c $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ # bootblock.ld is part of $(bootblock-objs) -- To view, visit https://review.coreboot.org/c/coreboot/+/35602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca Gerrit-Change-Number: 35602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: drivers/intel/fsp2_0: Move Debug options to "Debugging"
by Arthur Heymans (Code Review) 06 Nov '19

06 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36165 ) Change subject: drivers/intel/fsp2_0: Move Debug options to "Debugging" ...................................................................... drivers/intel/fsp2_0: Move Debug options to "Debugging" TODO: Is verify HOBS really 'Debugging' and should this really be optional? Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/drivers/intel/fsp2_0/Kconfig 2 files changed, 40 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36165/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..80efb12 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,46 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP header information when the FSP file is found. + +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP HOBs which are provided for coreboot. + +config DISPLAY_UPD_DATA + bool "Display UPD data" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the user specified product data prior to memory + initialization. + +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + + + endmenu diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1e84dab..fee5de4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,32 +39,6 @@ Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. -config DISPLAY_FSP_CALLS_AND_STATUS - bool "Display the FSP calls and status" - default n - help - Display the FSP call entry point and parameters prior to calling FSP - and display the status upon return from FSP. - -config DISPLAY_FSP_HEADER - bool "Display the FSP header" - default n - help - Display the FSP header information when the FSP file is found. - -config DISPLAY_HOBS - bool "Display the hand-off-blocks" - default n - help - Display the FSP HOBs which are provided for coreboot. - -config DISPLAY_UPD_DATA - bool "Display UPD data" - default n - help - Display the user specified product data prior to memory - initialization. - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" depends on FSP_CAR @@ -161,13 +135,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config VERIFY_HOBS - bool "Verify the FSP hand-off-blocks" - default n - help - Verify that the HOBs required by coreboot are returned by FSP and - that the resource HOBs are in the correct order and position. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Gerrit-Change-Number: 36165 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/g/drallion: Override smbios enclosure type for drallion
by Mathew King (Code Review) 06 Nov '19

06 Nov '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36512 ) Change subject: mb/g/drallion: Override smbios enclosure type for drallion ...................................................................... mb/g/drallion: Override smbios enclosure type for drallion Drallion can be either a clamshell or convertible depending on the presence of the 360 sensor board. Set the smbios type 3 enclosure type to either CONVERTIBLE or LAPTOP accordingly. BUG=b:143701965 TEST='dmidecode -t 3' Type = Convertible with sensor board connected Type = Laptop with sensor board disconnected Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/google/drallion/variants/drallion/Makefile.inc A src/mainboard/google/drallion/variants/drallion/smbios.c 4 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36512/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 5edf3c6..261888f 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -492,7 +492,7 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } -u8 __weak smbios_mainboard_enclosure_type(void) +smbios_enclosure_type __weak smbios_mainboard_enclosure_type(void) { return CONFIG_SMBIOS_ENCLOSURE_TYPE; } diff --git a/src/include/smbios.h b/src/include/smbios.h index ef1c7de..d230fb2 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -65,7 +65,6 @@ const char *smbios_mainboard_asset_tag(void); u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); -u8 smbios_mainboard_enclosure_type(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -319,7 +318,7 @@ u8 eos[2]; } __packed; -enum { +typedef enum { SMBIOS_ENCLOSURE_OTHER = 0x01, SMBIOS_ENCLOSURE_UNKNOWN = 0x02, SMBIOS_ENCLOSURE_DESKTOP = 0x03, @@ -356,7 +355,7 @@ SMBIOS_ENCLOSURE_EMBEDDED_PC = 0x22, SMBIOS_ENCLOSURE_MINI_PC = 0x23, SMBIOS_ENCLOSURE_STICK_PC = 0x24, -}; +} smbios_enclosure_type; struct smbios_type3 { u8 type; @@ -798,5 +797,6 @@ struct smbios_type17 *t); smbios_board_type smbios_mainboard_board_type(void); +smbios_enclosure_type smbios_mainboard_enclosure_type(void); #endif diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index ccbcb08..7e4edc1 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -32,3 +32,5 @@ romstage-y += memory.c ramstage-y += sku.c + +ramstage-y += smbios.c diff --git a/src/mainboard/google/drallion/variants/drallion/smbios.c b/src/mainboard/google/drallion/variants/drallion/smbios.c new file mode 100644 index 0000000..f6c8491 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/smbios.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <variant/gpio.h> +#include <gpio.h> +#include <smbios.h> + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (gpio_get(SENSOR_DET_360) == 0) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + return SMBIOS_ENCLOSURE_LAPTOP; +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/36512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5 Gerrit-Change-Number: 36512 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/emulation/qemu: Add VBOOT support
by Patrick Rudolph (Code Review) 06 Nov '19

06 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35400 ) Change subject: mb/emulation/qemu: Add VBOOT support ...................................................................... mb/emulation/qemu: Add VBOOT support Add VBOOT support for testing purposes. Add a 16 MiB FMAP containing RO + RW_A. Tested on qemu. Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/cmos.layout A src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/cmos.layout A src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd 6 files changed, 81 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35400/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 3c5e325..4074fef 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,6 +12,22 @@ select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index bfa38ed..811630c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,6 +11,21 @@ select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_VBNV_CMOS + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-roa-16M.fmd" if VBOOT_SLOTS_RW_A + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2c config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index b238a37..247a6a0 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -7,6 +7,10 @@ 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 456 1 e 1 ECC_memory + +# VBOOT +464 128 r 0 vbnv + 1008 16 h 0 check_sum enumerations @@ -25,4 +29,4 @@ checksums -checksum 392 1007 1008 +checksum 392 463 1008 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd new file mode 100644 index 0000000..aa081b2 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-16M.fmd @@ -0,0 +1,20 @@ +FLASH@0xff000000 0x1000000 { + SI_BIOS 0x1000000 { + RW_SECTION_A 0x7c0000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) 0x74ffc0 + RW_FWID_A 0x40 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + + WP_RO 0x7ff000 { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS)@0x20000 0x7df000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a Gerrit-Change-Number: 35400 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mainboard/google: Rework Hatch so that SPD in CBFS is optional
by Edward O'Callaghan (Code Review) 06 Nov '19

06 Nov '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36250 ) Change subject: mainboard/google: Rework Hatch so that SPD in CBFS is optional ...................................................................... mainboard/google: Rework Hatch so that SPD in CBFS is optional All Hatch variants so far embed static SPD data encoded within the firmware image. However we wish the flexibility for romstage implementations that allow for reading the SPD data dynamically over SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name M src/mainboard/google/hatch/Makefile.inc R src/mainboard/google/hatch/romstage_spd_cbfs.c 4 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36250/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..278d009 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -58,6 +58,10 @@ int default 512 +config ROMSTAGE_SPD_CBFS + bool + default n + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fbc4c15..a2fea9f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -4,29 +4,35 @@ bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select ROMSTAGE_SPD_CBFS config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select ROMSTAGE_SPD_CBFS config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_CBFS config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select ROMSTAGE_SPD_CBFS config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE + select ROMSTAGE_SPD_CBFS config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select ROMSTAGE_SPD_CBFS diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 01a1eb8..3ed82e7 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -20,7 +20,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-y += romstage.c +romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage_spd_cbfs.c similarity index 100% rename from src/mainboard/google/hatch/romstage.c rename to src/mainboard/google/hatch/romstage_spd_cbfs.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b Gerrit-Change-Number: 36250 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

8 16

Change in coreboot[master]: ec/google/chromeec: Add EC driver support for software sync
by Tim Wawrzynczak (Code Review) 06 Nov '19

06 Nov '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36207 ) Change subject: ec/google/chromeec: Add EC driver support for software sync ...................................................................... ec/google/chromeec: Add EC driver support for software sync Quite a few new functions added here in order to support the use-case of performing EC software sync within coreboot. Most of these functions are related to retrieving the EC's hash, and writing a new image into the EC's flash. BUG=b:112198832 BRANCH=none TEST=With whole patch series, successfully performed EC software sync Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 333 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36207/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 7c294b6..0c9f3ab 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -33,6 +33,7 @@ #include "ec_commands.h" #define INVALID_HCMD 0xFF +#define EC_VER_MASK(version) BIT(version) /* * Map UHEPI masks to non UHEPI commands in order to support old EC FW @@ -498,6 +499,299 @@ return r.flags[feature / 32] & EC_FEATURE_MASK_0(feature); } +int google_chromeec_get_cmd_versions(int command, uint32_t *pmask) +{ + struct chromeec_command cmd; + struct ec_params_get_cmd_versions_v1 params = { + .cmd = command, + }; + struct ec_response_get_cmd_versions resp; + + *pmask = 0; + + cmd.cmd_code = EC_CMD_GET_CMD_VERSIONS; + cmd.cmd_version = 1; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(resp); + cmd.cmd_data_out = &resp; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + *pmask = resp.version_mask; + return 0; +} + +/** + * Return non-zero if the EC supports the command and version + * + * @param cmd Command to check + * @param ver Version to check + * @return non-zero if command version supported; 0 if not. + */ +static int cmd_version_supported(int cmd, int ver) +{ + uint32_t mask = 0; + + if (google_chromeec_get_cmd_versions(cmd, &mask)) + return 0; + + return (mask & EC_VER_MASK(ver)) ? 1 : 0; +} + +int google_chromeec_get_vboot_hash(u32 offset, + struct ec_response_vboot_hash *resp) +{ + struct chromeec_command cmd; + struct ec_params_vboot_hash params = { + .cmd = EC_VBOOT_HASH_GET, + .offset = offset, + }; + + cmd.cmd_code = EC_CMD_VBOOT_HASH; + cmd.cmd_version = 0; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(*resp); + cmd.cmd_data_out = resp; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_start_vboot_hash(enum ec_vboot_hash_type hash_type, + u32 hash_offset, + struct ec_response_vboot_hash *resp) +{ + struct chromeec_command cmd; + struct ec_params_vboot_hash params = { + .cmd = EC_VBOOT_HASH_START, + .hash_type = hash_type, + .nonce_size = 0, + .offset = hash_offset, + }; + + cmd.cmd_code = EC_CMD_VBOOT_HASH; + cmd.cmd_version = 0; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(*resp); + cmd.cmd_data_out = resp; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_protect(u32 mask, u32 flags, + struct ec_response_flash_protect *resp) +{ + struct chromeec_command cmd; + struct ec_params_flash_protect params = { + .mask = mask, + .flags = flags, + }; + + cmd.cmd_code = EC_CMD_FLASH_PROTECT; + cmd.cmd_version = EC_VER_FLASH_PROTECT; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(*resp); + cmd.cmd_data_out = resp; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_region_info(enum ec_flash_region region, u32 *offset, + u32 *size) +{ + struct chromeec_command cmd; + struct ec_params_flash_region_info params = { + .region = region, + }; + struct ec_response_flash_region_info resp; + + cmd.cmd_code = EC_CMD_FLASH_REGION_INFO; + cmd.cmd_version = EC_VER_FLASH_REGION_INFO; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(resp); + cmd.cmd_data_out = &resp; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + if (offset) + *offset = resp.offset; + if (size) + *size = resp.size; + + return 0; +} + +int google_chromeec_flash_erase(u32 region_offset, u32 region_size) +{ + struct chromeec_command cmd; + struct ec_params_flash_erase params = { + .offset = region_offset, + .size = region_size, + }; + + cmd.cmd_code = EC_CMD_FLASH_ERASE; + cmd.cmd_version = 0; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = 0; + cmd.cmd_data_out = NULL; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_info(struct ec_response_flash_info *info) +{ + struct chromeec_command cmd; + + cmd.cmd_code = EC_CMD_FLASH_INFO; + cmd.cmd_version = 0; + cmd.cmd_size_in = 0; + cmd.cmd_data_in = NULL; + cmd.cmd_size_out = sizeof(*info); + cmd.cmd_data_out = info; + cmd.cmd_dev_index = 0; + + if (google_chromeec_command(&cmd) != 0) + return -1; + + return 0; +} + +int google_chromeec_flash_write_burst_size(void) +{ + struct ec_response_flash_info info; + uint32_t pdata_max_size = (EC_LPC_HOST_PACKET_SIZE - + sizeof(struct ec_params_flash_write)) - + sizeof(struct ec_host_request); + + /* + * Determine whether we can use version 1 of the command with more + * data, or only version 0. + */ + if (!cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE)) + return EC_FLASH_WRITE_VER0_SIZE; + + /* + * Determine step size. This must be a multiple of the write block + * size, and must also fit into the host parameter buffer. + */ + if (google_chromeec_flash_info(&info)) + return 0; + + return (pdata_max_size / info.write_block_size) * info.write_block_size; +} + +/* Write a block into EC flash */ +int google_chromeec_flash_write_block(const u8 *data, u32 offset, u32 size) +{ + uint8_t *buf; + struct ec_params_flash_write *p; + uint32_t bufsize = sizeof(*p) + size; + int rv; + struct chromeec_command cmd; + + assert(data); + + /* Make sure request fits in the allowed packet size */ + if (bufsize > EC_LPC_HOST_PACKET_SIZE) + return -1; + + buf = crosec_get_buffer(bufsize, 0); + if (buf == NULL) + return -1; + + p = (struct ec_params_flash_write *)buf; + p->offset = offset; + p->size = size; + memcpy(p + 1, data, size); + + cmd.cmd_code = EC_CMD_FLASH_WRITE; + cmd.cmd_version = EC_VER_FLASH_WRITE; + cmd.cmd_size_in = bufsize; + cmd.cmd_data_in = buf; + cmd.cmd_size_out = 0; + cmd.cmd_data_out = NULL; + cmd.cmd_dev_index = 0; + + rv = google_chromeec_command(&cmd); + + return rv; +} + +/* EFS verification of flash */ +int google_chromeec_efs_verify(enum ec_flash_region region) +{ + struct chromeec_command cmd; + struct ec_params_efs_verify params = { + .region = region, + }; + int rv; + + cmd.cmd_code = EC_CMD_EFS_VERIFY; + cmd.cmd_version = 0; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = 0; + cmd.cmd_data_out = NULL; + cmd.cmd_dev_index = 0; + + /* It's okay if the EC doesn't support EFS */ + rv = google_chromeec_command(&cmd); + if (rv != 0 && (cmd.cmd_code == EC_RES_INVALID_COMMAND)) { + return 0; + } + + return rv; +} + +int google_chromeec_test(void) +{ + struct chromeec_command cmd; + struct ec_params_hello params = { + .in_data = 0x12345678, + }; + struct ec_response_hello resp = {}; + int rv; + + cmd.cmd_code = EC_CMD_HELLO; + cmd.cmd_version = 0; + cmd.cmd_size_in = sizeof(params); + cmd.cmd_data_in = &params; + cmd.cmd_size_out = sizeof(resp); + cmd.cmd_data_out = &resp; + cmd.cmd_dev_index = 0; + + rv = google_chromeec_command(&cmd); + if (rv || (resp.out_data != params.in_data + 0x01020304)) + return -1; + + return 0; +} + int google_chromeec_set_sku_id(u32 skuid) { struct chromeec_command cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 019f9c1..20e5bec 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -178,4 +178,43 @@ /* Log host events to eventlog based on the mask provided. */ void google_chromeec_log_events(uint64_t mask); +/* + * The following functions are for vboot EC software sync. + * They return 0 on success, non-zero for failure. + */ + +/* Protect/un-protect EC flash regions */ +int google_chromeec_flash_protect(u32 mask, u32 flags, + struct ec_response_flash_protect *resp); +/* Calculate image hash for vboot */ +int google_chromeec_start_vboot_hash(enum ec_vboot_hash_type hash_type, + u32 offset, + struct ec_response_vboot_hash *resp); +/* Return the vboot image hash */ +int google_chromeec_get_vboot_hash(u32 offset, + struct ec_response_vboot_hash *resp); +/* Get offset and size of the specified flash region */ +int google_chromeec_flash_region_info(enum ec_flash_region region, u32 *offset, + u32 *size); +/* Erase a region of flash */ +int google_chromeec_flash_erase(u32 region_offset, u32 region_size); + +/* Return information about the entire flash */ +int google_chromeec_flash_info(struct ec_response_flash_info *info); + +/* Verify flash using EFS if available */ +int google_chromeec_efs_verify(enum ec_flash_region region); + +/* Get available versions of the specified command */ +int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); + +/* Test if the EC is responding */ +int google_chromeec_test(void); + +/* Get the EC's flash write burst size */ +int google_chromeec_flash_write_burst_size(void); + +/* Write a block into EC flash */ +int google_chromeec_flash_write_block(const u8 *data, u32 offset, u32 size); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Gerrit-Change-Number: 36207 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

8 38

Change in coreboot[master]: soc/intel/common: Make native and FSP-T CAR init mutually exclusive
by Arthur Heymans (Code Review) 05 Nov '19

05 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36168 ) Change subject: soc/intel/common: Make native and FSP-T CAR init mutually exclusive ...................................................................... soc/intel/common: Make native and FSP-T CAR init mutually exclusive Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Makefile.inc 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36168/1 diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 3d6adce..c572928 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,10 +1,12 @@ +ifneq ($(CONFIG_FSP_CAR),y) bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S -bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c - postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S -postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S +else +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU)+= car/cache_as_ram_fsp.S +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car_fsp.S +endif +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Gerrit-Change-Number: 36168 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: vendorcode/eltan/security: align mboot with coreboot tpm
by Wim Vervoorn (Code Review) 05 Nov '19

05 Nov '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36483 ) Change subject: vendorcode/eltan/security: align mboot with coreboot tpm ...................................................................... vendorcode/eltan/security: align mboot with coreboot tpm Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest handled in a call. The pcr invalidation has been changed. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/romstage.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/mboot/mboot.h M src/vendorcode/eltan/security/mboot/mboot_func.c 4 files changed, 47 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36483/1 diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index c10e866..b6ea03f 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -78,7 +78,7 @@ CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int mb_crtm(void) { int status = TPM_E_IOERROR; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -91,9 +91,9 @@ tcgEventHdr.eventSize = sizeof(crtm_version); printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, &tcgEventHdr, - (uint8_t *)crtm_version, 0); + (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); } diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index bae377a..3799b8a 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -120,92 +120,37 @@ * Calculates the hash over the data and extends it in active PCR banks and * then logs them in the event log. * - * @param[in] activePcr bitmap of active PCR banks in TPM. - * @param[in] flags flags associated with hash data. Currently - * unused. + * @param[in] flags flags associated with hash data. Currently unused. * @param[in] hashData data to be hashed. * @param[in] hashDataLen length of the data to be hashed. * @param[in] newEventHdr event header in TCG_PCR_EVENT2 format. * @param[in] eventLog description of the event. - * @param[in] invalid invalidate the pcr * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid) +int mboot_hash_extend_log(uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog) { - int status; TPMT_HA *digest = NULL; - int digest_num = 0; - printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, - (size_t)hashDataLen); + printk(BIOS_DEBUG, "%s: Hash Data Length: %zu bytes\n", __func__, (size_t)hashDataLen); - if (invalid) { - digest = &(newEventHdr->digest.digests[digest_num]); - digest->hashAlg = TPM_ALG_ERROR; - digest_num++; + /* Generate SHA256 */ + digest = &(newEventHdr->digest.digests[0]); + if (flags & MBOOT_HASH_PROVIDED) { + /* The hash is provided as data */ + memcpy(digest->digest.sha256, (void *)hashData, hashDataLen); } else { - /* - * Generate SHA1 hash if SHA1 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA1) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha1, (void *)hashData, - VB2_SHA1_DIGEST_SIZE); - } else { - if (cb_sha_little_endian(VB2_HASH_SHA1, hashData, - hashDataLen, digest->digest.sha1)) - return TPM_E_IOERROR; - } - - digest->hashAlg = TPM_ALG_SHA1; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA1 Hash Digest:\n", __func__); - mboot_print_buffer(digest->digest.sha1, - VB2_SHA1_DIGEST_SIZE); - } - - /* - * Generate SHA256 hash if SHA256 PCR bank is active in TPM - * currently - */ - if (activePcr & EFI_TCG2_BOOT_HASH_ALG_SHA256) { - digest = &(newEventHdr->digest.digests[digest_num]); - if (flags & MBOOT_HASH_PROVIDED) { - /* The hash is provided as data */ - memcpy(digest->digest.sha256, - (void *)hashData, hashDataLen); - } else { - - if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, - hashDataLen, digest->digest.sha256)) - return TPM_E_IOERROR; - } - digest->hashAlg = TPM_ALG_SHA256; - digest_num++; - - printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", - __func__); - mboot_print_buffer(digest->digest.sha256, - VB2_SHA256_DIGEST_SIZE); - } + if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, hashDataLen, + digest->digest.sha256)) + return TPM_E_IOERROR; } - newEventHdr->digest.count = digest_num; + printk(BIOS_DEBUG, "%s: SHA256 Hash Digest:\n", __func__); + mboot_print_buffer(digest->digest.sha256, VB2_SHA256_DIGEST_SIZE); - status = tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), - NULL); - if (status != TPM_SUCCESS) - printk(BIOS_DEBUG, "%s: returned 0x%x\n", __func__, status); - - return status; + return (tlcl_extend(newEventHdr->pcrIndex, (uint8_t *)&(newEventHdr->digest), NULL)); } /* @@ -215,13 +160,11 @@ */ void invalidate_pcrs(void) { - int status, pcr; - TCG_PCR_EVENT2_HDR tcgEventHdr; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; - uint8_t invalidate; + int pcr; + int status; - ActivePcrs = tpm2_get_active_pcrs(); - invalidate = 1; + TCG_PCR_EVENT2_HDR tcgEventHdr; + uint8_t invalidate = 1; for (pcr = 0; pcr < 8; pcr++) { printk(BIOS_DEBUG, "%s: Invalidating PCR %d\n", __func__, pcr); @@ -230,10 +173,9 @@ tcgEventHdr.eventType = EV_NO_ACTION; tcgEventHdr.eventSize = (uint32_t) sizeof(invalidate); - status = mboot_hash_extend_log(ActivePcrs, 0, - (uint8_t *)&invalidate, tcgEventHdr.eventSize, - &tcgEventHdr, (uint8_t *)"Invalidate PCR", invalidate); - + status = mboot_hash_extend_log(0, (uint8_t *)&invalidate, + tcgEventHdr.eventSize, &tcgEventHdr, + (uint8_t *)"Invalidate PCR"); if (status != TPM_SUCCESS) printk(BIOS_DEBUG, "%s: invalidating pcr %d returned" " 0x%x\n", __func__, pcr, status); @@ -288,7 +230,6 @@ /* * measures and logs the specified cbfs file. * - * @param[in] activePcr bitmap of active PCR banks in TPM. * @param[in] name name of the cbfs file to measure * @param[in] type data type of the cbfs file. * @param[in] pcr pcr to extend. @@ -298,9 +239,8 @@ * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. */ -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg) +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -311,21 +251,18 @@ base = cbfs_boot_map_with_leak(name, type, &size); if (base == NULL) { - printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, - name); + printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, name); return VB2_ERROR_READ_FILE_OPEN; } - printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", - __func__, name); + printk(BIOS_DEBUG, "%s: CBFS locate success: %s\n", __func__, name); memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); tcgEventHdr.pcrIndex = pcr; tcgEventHdr.eventType = eventType; if (event_msg) tcgEventHdr.eventSize = (uint32_t) strlen(event_msg); - status = mboot_hash_extend_log(activePcr, 0, base, size, &tcgEventHdr, - (uint8_t *)event_msg, 0); + status = mboot_hash_extend_log(0, base, size, &tcgEventHdr, (uint8_t *)event_msg); return status; } @@ -440,18 +377,15 @@ int __attribute__((weak))mb_measure_log_start(void) { int status; - EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs; uint32_t i; - ActivePcrs = tpm2_get_active_pcrs(); - - if (ActivePcrs == 0x0) { - printk(BIOS_DEBUG, "%s: No Active PCR Bank in TPM.\n", + if ((tpm2_get_active_pcrs() & EFI_TCG2_BOOT_HASH_ALG_SHA256) == 0x0) { + printk(BIOS_DEBUG, "%s: SHA256 PCR Bank not active in TPM.\n", __func__); return TPM_E_IOERROR; } - status = mb_crtm(ActivePcrs); + status = mb_crtm(); if (status != TPM_SUCCESS) { printk(BIOS_DEBUG, "%s: Fail! CRTM Version can't be measured." " ABORTING!!!\n", __func__); @@ -462,7 +396,7 @@ /* Log the items defined by the mainboard */ for (i = 0; i < ARRAY_SIZE(mb_log_list); i++) { status = mb_measure_log_worker( - ActivePcrs, mb_log_list[i].cbfs_name, + mb_log_list[i].cbfs_name, mb_log_list[i].cbfs_type, mb_log_list[i].pcr, mb_log_list[i].eventType, mb_log_list[i].event_msg); @@ -494,12 +428,10 @@ * The function can be overridden at the mainboard level my simply creating a * function with the same name there. * - * @param[in] activePcr bitmap of the support - * * @retval TPM_SUCCESS Operation completed successfully. * @retval TPM_E_IOERROR Unexpected device behavior. **/ -int __attribute__((weak))mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int __attribute__((weak))mb_crtm(void) { int status; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -515,9 +447,8 @@ printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, - tcgEventHdr.eventSize, &tcgEventHdr, (uint8_t *)crtm_version, - 0); + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, + &tcgEventHdr, (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); @@ -540,8 +471,8 @@ msgPtr = NULL; tcgEventHdr.eventSize = 0; - status = mboot_hash_extend_log(activePcr, MBOOT_HASH_PROVIDED, hash, - sizeof(hash), &tcgEventHdr, msgPtr, 0); + status = mboot_hash_extend_log(MBOOT_HASH_PROVIDED, hash, sizeof(hash), &tcgEventHdr, + msgPtr); if (status) printk(BIOS_DEBUG, "Add ME hash returned 0x%x\n", status); diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 96375ab..43aca66 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -89,16 +89,14 @@ */ #define MBOOT_HASH_PROVIDED (0x00000001) - int is_zero_buffer(void *buffer, unsigned int size); -int mboot_hash_extend_log(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, - TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog, uint8_t invalid); +int mboot_hash_extend_log( uint64_t flags, uint8_t *hashData, uint32_t hashDataLen, + TCG_PCR_EVENT2_HDR *newEventHdr, uint8_t *eventLog); void mboot_print_buffer(uint8_t *buffer, uint32_t bufferSize); -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr); +int mb_crtm(void); typedef struct { const char *cbfs_name; @@ -108,9 +106,8 @@ const char *event_msg; } mboot_measure_item_t; -int mb_measure_log_worker(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr, - const char *name, uint32_t type, uint32_t pcr, - TCG_EVENTTYPE eventType, const char *event_msg); +int mb_measure_log_worker(const char *name, uint32_t type, uint32_t pcr, + TCG_EVENTTYPE eventType, const char *event_msg); int mb_measure_log_start(void); void invalidate_pcrs(void); @@ -122,7 +119,7 @@ int mb_measure(int wake_from_s3); int mb_entry(int wake_from_s3); -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs); +int log_efi_specid_event(void); int log_event_tcg_20_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); int log_event_tcg_12_format(TCG_PCR_EVENT2_HDR *EventHdr, uint8_t *EventLog); diff --git a/src/vendorcode/eltan/security/mboot/mboot_func.c b/src/vendorcode/eltan/security/mboot/mboot_func.c index ec66d34..6792204 100644 --- a/src/vendorcode/eltan/security/mboot/mboot_func.c +++ b/src/vendorcode/eltan/security/mboot/mboot_func.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,7 +15,7 @@ #include <mboot.h> -int log_efi_specid_event(EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrs) { +int log_efi_specid_event(void) { return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Gerrit-Change-Number: 36483 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: commonlib: Use __builtin_offsetof with supported compilers
by Alex James (Code Review) 05 Nov '19

05 Nov '19

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36249 ) Change subject: commonlib: Use __builtin_offsetof with supported compilers ...................................................................... commonlib: Use __builtin_offsetof with supported compilers Use __builtin_offsetof (which is treated as a constant expression) with Clang & GCC. This also allows check_member to work with Clang. Signed-off-by: Alex James <theracermaster(a)gmail.com> Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e --- M src/commonlib/include/commonlib/helpers.h 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/36249/1 diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index 4429ea4..b5e08b4 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -107,17 +107,15 @@ #define MHz (1000 * KHz) #define GHz (1000 * MHz) -#ifndef offsetof +#ifdef __ROMCC__ #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#else +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif -#if !defined(__clang__) #define check_member(structure, member, offset) _Static_assert( \ offsetof(struct structure, member) == offset, \ "`struct " #structure "` offset for `" #member "` is not " #offset) -#else -#define check_member(structure, member, offset) -#endif /** * container_of - cast a member of a structure out to the containing structure -- To view, visit https://review.coreboot.org/c/coreboot/+/36249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e Gerrit-Change-Number: 36249 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is un...
by Arthur Heymans (Code Review) 05 Nov '19

05 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35883 ) Change subject: pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined ...................................................................... pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if CONFIG_MMCONF_BASE_ADDRESS is not defined. Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/device/pci_mmio_cfg.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35883/1 diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 5567ed8..e3c5fe4 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -90,6 +90,10 @@ #if CONFIG(MMCONF_SUPPORT) +#if CONFIG_MMCONF_BASE_ADDRESS == 0 +#error "CONFIG_MMCONF_BASE_ADDRESS undefined!" +#endif + /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or * MMIO variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/35883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66 Gerrit-Change-Number: 35883 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019