coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: arch/x86: Remove EARLY_EBDA_INIT support
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36363 ) Change subject: arch/x86: Remove EARLY_EBDA_INIT support ...................................................................... arch/x86: Remove EARLY_EBDA_INIT support This is unused now. Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/ebda.c M src/arch/x86/include/arch/ebda.h M src/arch/x86/tables.c M src/device/device.c 6 files changed, 3 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36363/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 8ce5977..4ea11ea 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -141,15 +141,6 @@ help Increase this value if preram cbmem console is getting truncated -config EARLY_EBDA_INIT - bool - default n - help - Initialize BIOS EBDA area early in romstage to allow bootloader to - use this region for storing data which can be available across - various stages. If user is selecting this option then its users - responsibility to perform EBDA initialization call during romstage. - config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d..e3aa7fe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -226,7 +226,6 @@ romstage-y += cbmem.c romstage-y += cbfs_and_run.c romstage-y += cpu_common.c -romstage-$(CONFIG_EARLY_EBDA_INIT) += ebda.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S romstage-y += memcpy.c @@ -266,7 +265,6 @@ postcar-y += cbfs_and_run.c postcar-y += cbmem.c postcar-y += cpu_common.c -postcar-$(CONFIG_EARLY_EBDA_INIT) += ebda.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c postcar-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S postcar-y += exit_car.S diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index d1212f9..80909f6 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -39,43 +39,7 @@ * the top of conventional memory (below 1MB) */ -/* - * write_ebda_data is a wrapper function to write into EBDA area - * - * data = data to be written into EBDA area - * length = input data size. - */ -void write_ebda_data(const void *data, size_t length) -{ - void *ebda; - - if (!is_length_valid(length)) - die("Input data length is > EBDA default size (1KiB)!"); - - ebda = get_ebda_start(); - - memcpy(ebda, data, length); -} - -/* - * read_ebda_data is a wrapper function to read from EBDA area - * - * data = data read from EBDA area based on input size - * length = read data size. - */ -void read_ebda_data(void *data, size_t length) -{ - void *ebda; - - if (!is_length_valid(length)) - die("Input data length is > EBDA default size (1KiB)!"); - - ebda = get_ebda_start(); - - memcpy(data, ebda, length); -} - -void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) +static void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { u16 low_memory_kb; u16 ebda_kb; diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 534fb3d..6ee3332 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -27,27 +27,6 @@ #define DEFAULT_EBDA_SEGMENT 0xF600 #define DEFAULT_EBDA_SIZE 0x400 -void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size); void setup_default_ebda(void); -/* - * This read/write API only allows and assumes - * a single EBDA structure type for a platform. - */ - -/* - * write_ebda_data is a wrapper function to write into EBDA area - * - * data = data to be written into EBDA area - * length = input data size. - */ -void write_ebda_data(const void *data, size_t length); -/* - * read_ebda_data is a wrapper function to read from EBDA area - * - * data = data read from EBDA area based on input size - * length = read data size. - */ -void read_ebda_data(void *data, size_t length); - #endif diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index ddb0710..55a4dd6 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -194,41 +194,6 @@ #define FORWARDING_TABLE_ADDR ((uintptr_t)0x500) static uintptr_t forwarding_table = FORWARDING_TABLE_ADDR; -/* - * For EARLY_EBDA_INIT the BDA area will be wiped on the resume path which - * has the forwarding table entry. Therefore, when tables are written an - * entry is placed in cbmem that can be restored on OS resume to the proper - * location. - */ -static void stash_forwarding_table(uintptr_t addr, size_t sz) -{ - void *cbmem_addr = cbmem_add(CBMEM_ID_CBTABLE_FWD, sz); - - if (cbmem_addr == NULL) { - printk(BIOS_ERR, "Unable to allocate CBMEM forwarding entry.\n"); - return; - } - - memcpy(cbmem_addr, (void *)addr, sz); -} - -static void restore_forwarding_table(void *dest) -{ - const struct cbmem_entry *fwd_entry; - - fwd_entry = cbmem_entry_find(CBMEM_ID_CBTABLE_FWD); - - if (fwd_entry == NULL) { - printk(BIOS_ERR, "Unable to restore CBMEM forwarding entry.\n"); - return; - } - - memcpy(dest, cbmem_entry_start(fwd_entry), cbmem_entry_size(fwd_entry)); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - restore_forwarding_table, (void *)FORWARDING_TABLE_ADDR); - void arch_write_tables(uintptr_t coreboot_table) { size_t sz; diff --git a/src/device/device.c b/src/device/device.c index 333f1f0..5d9938f 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1165,13 +1165,8 @@ printk(BIOS_INFO, "Initializing devices...\n"); #if CONFIG(ARCH_X86) - /* - * Initialize EBDA area in ramstage if early - * initialization is not done. - */ - if (!CONFIG(EARLY_EBDA_INIT)) - /* Ensure EBDA is prepared before Option ROMs. */ - setup_default_ebda(); + /* Ensure EBDA is prepared before Option ROMs. */ + setup_default_ebda(); #endif /* First call the mainboard init. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8bc1d6761d66c5e1dda40c34c940cdba90646d2 Gerrit-Change-Number: 36363 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/icelake: Don't save tolum_base to ebda
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36361 ) Change subject: soc/intel/icelake: Don't save tolum_base to ebda ...................................................................... soc/intel/icelake: Don't save tolum_base to ebda Later stages don't need access to it anymore. Change-Id: Ib39d495262758fa884b5940a8deb7d2a34b2c498 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/icelake/memmap.c 1 file changed, 2 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36361/1 diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index d8cdb56..3b42801 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -14,7 +14,6 @@ */ #include <arch/romstage.h> -#include <arch/ebda.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> @@ -22,7 +21,6 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> -#include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> @@ -183,28 +181,11 @@ dram_base -= calculate_traditional_mem_size(dram_base, dev); /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; + dram_base = calculate_reserved_mem_size(dram_base, dev); return dram_base; } -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - size_t chipset_mem_size; - - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - /* * +-------------------------+ Top of RAM (aligned) * | System Management Mode | @@ -234,8 +215,6 @@ */ void *cbmem_top_romstage(void) { - struct ebda_config ebda_cfg; - /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the @@ -244,10 +223,7 @@ */ if (sa_get_tseg_base() == 0) return NULL; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)calculate_dram_base(); } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/36361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib39d495262758fa884b5940a8deb7d2a34b2c498 Gerrit-Change-Number: 36361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/cannonlake: Don't save tolum_base to ebda
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36360 ) Change subject: soc/intel/cannonlake: Don't save tolum_base to ebda ...................................................................... soc/intel/cannonlake: Don't save tolum_base to ebda Later stages don't need access to it anymore. Change-Id: Ic3b759f28f4969d4da2164ba61562f5cf53c5693 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/memmap.c 1 file changed, 3 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36360/1 diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 2a25940..dacc3ae 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -15,7 +15,6 @@ */ #include <arch/romstage.h> -#include <arch/ebda.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> @@ -23,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> -#include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> @@ -187,7 +185,7 @@ * the base registers from each other to determine sizes of the regions. In * other words, the memory map is in a fixed order no matter what. */ -static uintptr_t calculate_dram_base(size_t *reserved_mem_size) +static uintptr_t calculate_dram_base(void) { uintptr_t dram_base; const struct device *dev; @@ -204,28 +202,11 @@ dram_base -= calculate_traditional_mem_size(dram_base, dev); /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); - - dram_base -= *reserved_mem_size; + dram_base = calculate_reserved_mem_size(dram_base, dev); return dram_base; } -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - size_t chipset_mem_size; - - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - /* * +-------------------------+ Top of RAM (aligned) * | System Management Mode | @@ -255,8 +236,6 @@ */ void *cbmem_top_romstage(void) { - struct ebda_config ebda_cfg; - /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the @@ -266,9 +245,7 @@ if (sa_get_tseg_base() == 0) return NULL; - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_base; + return (void *)calculate_dram_base(); } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/36360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3b759f28f4969d4da2164ba61562f5cf53c5693 Gerrit-Change-Number: 36360 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/skylake: Pass on reserved_mem_size via cbmem
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36313 ) Change subject: soc/intel/skylake: Pass on reserved_mem_size via cbmem ...................................................................... soc/intel/skylake: Pass on reserved_mem_size via cbmem This uses common functions to pass on reserved_mem_size from romstage to ramstage over using EBDA, which is a more fragile area in memory. Change-Id: I6c750eecaf83b9c1fa94c7c22d9e11d7c830b8a2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/memmap.c 1 file changed, 12 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36313/1 diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 050cb25..e7de411 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -15,7 +15,6 @@ */ #include <arch/romstage.h> -#include <arch/ebda.h> #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> @@ -29,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <stdlib.h> +#include <romstage_handoff.h> #include "chip.h" @@ -217,34 +217,11 @@ return dram_base; } -/* - * SoC implementation - * - * SoC call to summarize all Intel Reserve MMIO size and report to SA - */ size_t soc_reserved_mmio_size(void) { - struct ebda_config cfg; - - retrieve_ebda_object(&cfg); - - /* Get Intel Reserved Memory Range Size */ - return cfg.reserved_mem_size; -} - -/* Fill up memory layout information */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - size_t chipset_mem_size; - - cfg->tolum_base = calculate_dram_base(&chipset_mem_size); - cfg->reserved_mem_size = chipset_mem_size; -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); + size_t reserve_mem_size; + get_romstage_info(&reserve_mem_size, sizeof(reserve_mem_size)); + return reserve_mem_size; } /* @@ -274,9 +251,13 @@ * | | * +-------------------------+ */ + void *cbmem_top_romstage(void) { - struct ebda_config ebda_cfg; + static uintptr_t dram_base; + size_t reserve_mem_size; + if (dram_base) + return (void *)dram_base; /* * Check if Tseg has been initialized, we will use this as a flag @@ -287,9 +268,9 @@ if (sa_get_tseg_base() == 0) return NULL; - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.tolum_base; + dram_base = calculate_dram_base(&reserve_mem_size); + save_romstage_info(&reserve_mem_size, sizeof(reserve_mem_size)); + return (void *)dram_base; } #if CONFIG(PLATFORM_USES_FSP2_0) -- To view, visit https://review.coreboot.org/c/coreboot/+/36313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c750eecaf83b9c1fa94c7c22d9e11d7c830b8a2 Gerrit-Change-Number: 36313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 10

Change in ...coreboot[master]: [WIP]mb/asus/p5ql-em: Add mainboard
by Arthur Heymans (Code Review) 09 Nov '19

09 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31323 Change subject: [WIP]mb/asus/p5ql-em: Add mainboard ...................................................................... [WIP]mb/asus/p5ql-em: Add mainboard Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 1067MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure macaddress in Kconfig) - PEG slot Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI TODO: - BSEL superio pins Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p5ql-em/Kconfig A src/mainboard/asus/p5ql-em/Kconfig.name A src/mainboard/asus/p5ql-em/Makefile.inc A src/mainboard/asus/p5ql-em/acpi/ec.asl A src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl A src/mainboard/asus/p5ql-em/acpi/platform.asl A src/mainboard/asus/p5ql-em/acpi/superio.asl A src/mainboard/asus/p5ql-em/acpi_tables.c A src/mainboard/asus/p5ql-em/board_info.txt A src/mainboard/asus/p5ql-em/cmos.default A src/mainboard/asus/p5ql-em/cmos.layout A src/mainboard/asus/p5ql-em/cstates.c A src/mainboard/asus/p5ql-em/data.vbt A src/mainboard/asus/p5ql-em/devicetree.cb A src/mainboard/asus/p5ql-em/dsdt.asl A src/mainboard/asus/p5ql-em/gma-mainboard.ads A src/mainboard/asus/p5ql-em/gpio.c A src/mainboard/asus/p5ql-em/hda_verb.c A src/mainboard/asus/p5ql-em/romstage.c 19 files changed, 811 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/31323/1 diff --git a/src/mainboard/asus/p5ql-em/Kconfig b/src/mainboard/asus/p5ql-em/Kconfig new file mode 100644 index 0000000..07af627 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_P5QL_EM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801JX + select SUPERIO_WINBOND_W83627DHG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select REALTEK_8168_RESET + +config MAINBOARD_DIR + string + default "asus/p5ql-em" + +config MAINBOARD_PART_NUMBER + string + default "P5QL EM" + +config MAX_CPUS + int + default 4 + +endif # BOARD_ASUS_P5QL_EM diff --git a/src/mainboard/asus/p5ql-em/Kconfig.name b/src/mainboard/asus/p5ql-em/Kconfig.name new file mode 100644 index 0000000..92ead65 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P5QL_EM + bool "P5QL EM" diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc new file mode 100644 index 0000000..6b3d94a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -0,0 +1,17 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-y += cstates.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/acpi/ec.asl b/src/mainboard/asus/p5ql-em/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000..861561a --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/ich10_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5ql-em/acpi/platform.asl b/src/mainboard/asus/p5ql-em/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5ql-em/acpi/superio.asl b/src/mainboard/asus/p5ql-em/acpi/superio.asl new file mode 100644 index 0000000..8f414f5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi/superio.asl @@ -0,0 +1 @@ +/* TODO */ diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c new file mode 100644 index 0000000..d609a0e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/acpi_tables.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/i82801jx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/asus/p5ql-em/board_info.txt b/src/mainboard/asus/p5ql-em/board_info.txt new file mode 100644 index 0000000..42d4812 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P5QC/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asus/p5ql-em/cmos.default b/src/mainboard/asus/p5ql-em/cmos.default new file mode 100644 index 0000000..ad822d5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout new file mode 100644 index 0000000..09ba5c5 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -0,0 +1,104 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 5 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +# coreboot config options: southbridge +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 4 e 11 gfx_uma_size +#436 548 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/p5ql-em/cstates.c b/src/mainboard/asus/p5ql-em/cstates.c new file mode 100644 index 0000000..aa7214d --- /dev/null +++ b/src/mainboard/asus/p5ql-em/cstates.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801jx/i82801jx.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/asus/p5ql-em/data.vbt b/src/mainboard/asus/p5ql-em/data.vbt new file mode 100644 index 0000000..5dd1803 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/data.vbt Binary files differ diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb new file mode 100644 index 0000000..e13d59b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -0,0 +1,169 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on # Host Bridge + subsystemid 0x1043 0x8336 + end + device pci 1.0 on # PEG + subsystemid 0x1043 0x8336 + end + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1043 0x8336 + end + device pci 2.1 on # Integrated graphics controller 2 + subsystemid 0x1043 0x8336 + end + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 off end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1a.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1b.0 on # Audio + subsystemid 0x1043 0x82fe + end + device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 on # PCIe 4 1394 controller + device pci 0.0 on + subsystemid 0x1043 0x8313 + end + end + device pci 1c.4 on # PCIe 5 Marvell IDE + device pci 0.0 on + subsystemid 0x1043 0x82a2 + end + end + device pci 1c.5 on # PCIe 6 Realtek LAN + device pci 0.0 on + subsystemid 0x1043 0x82c6 + end + end + device pci 1d.0 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.1 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.2 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1d.7 on # USB + subsystemid 0x1043 0x82d4 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1043 0x82d4 + chip superio/winbond/w83627dhg + device pnp 2e.0 on # Floppy + # global + irq 0x2c = 0x92 + #floppy + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + drq 0x74 = 0x02 + end + device pnp 2e.1 on # Parallel port + # parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard, mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xf0 = 0xf3 + irq 0xf1 = 0x0c + end + device pnp 2e.209 on # GPIO4 + irq 0xf4 = 0x06 + irq 0xf5 = 0x06 + end + device pnp 2e.309 on # GPIO5 + irq 0xe0 = 0xdf + irq 0xf3 = 0x09 # RSVD SUSLED settings + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front pannel LED + io 0x60 = 0x290 + irq 0x70 = 0 + end + device pnp 2e.c off end # PECI, SST + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1043 0x82d4 + end + device pci 1f.3 on # SMbus + subsystemid 0x1043 0x82d4 + end + device pci 1f.4 off end + device pci 1f.5 on # IDE + subsystemid 0x1043 0x82d4 + end + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p5ql-em/dsdt.asl b/src/mainboard/asus/p5ql-em/dsdt.asl new file mode 100644 index 0000000..d7ce26e --- /dev/null +++ b/src/mainboard/asus/p5ql-em/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801jx/i82801jx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00000001 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801jx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801jx/acpi/ich10.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801jx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/asus/p5ql-em/gma-mainboard.ads b/src/mainboard/asus/p5ql-em/gma-mainboard.ads new file mode 100644 index 0000000..43a7d89 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p5ql-em/gpio.c b/src/mainboard/asus/p5ql-em/gpio.c new file mode 100644 index 0000000..7bc8b9b --- /dev/null +++ b/src/mainboard/asus/p5ql-em/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c new file mode 100644 index 0000000..9e54df6 --- /dev/null +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0888, + 0x104382fe, // Subsystem ID + 13, // Number of entries + + /* Pin Widget Verb Table */ + + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x01012014), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862803, + 0x80860101, + 1, + + AZALIA_PIN_CFG(1, 0x03, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); +const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data); diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c new file mode 100644 index 0000000..da822ac --- /dev/null +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> +#include <superio/winbond/common/winbond.h> +#include <northbridge/intel/x4x/iomap.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich10_enable_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN + | COMA_LPC_EN); + /* HW EC */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); + /* TODO: FSB BSEL pins... */ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups + const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; + u8 s3_resume; + + /* Set southbridge and Super I/O GPIOs. */ + ich10_enable_lpc(); + mb_gpio_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + sdram_initialize(boot_path, spd_addrmap); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Gerrit-Change-Number: 31323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 40

Change in coreboot[master]: configs/config.facebookfbg1710: Add config file
by Frans Hendriks (Code Review) 08 Nov '19

08 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34343 ) Change subject: configs/config.facebookfbg1710: Add config file ...................................................................... configs/config.facebookfbg1710: Add config file BUG=N/A TEST=booting Embedded Linux 4.20 kernel on Facebook FBG1701 Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A configs/config.facebookfbg1710 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34343/1 diff --git a/configs/config.facebookfbg1710 b/configs/config.facebookfbg1710 new file mode 100644 index 0000000..be2e6d8 --- /dev/null +++ b/configs/config.facebookfbg1710 @@ -0,0 +1,10 @@ +CONFIG_VENDOR_FACEBOOK=y +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000 +CONFIG_ONBOARD_SAMSUNG_MEM=y +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 +CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC=0xfffe9000 +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_RUN_FSP_GOP=y +CONFIG_DISPLAY_HOBS=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_PAYLOAD_LINUX=y -- To view, visit https://review.coreboot.org/c/coreboot/+/34343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2cb3bb873b2d5e7e9031e5b249d86605d8e0945 Gerrit-Change-Number: 34343 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: Rangeley: Fix incorrect BCLK
by Name of user not set (Code Review) 07 Nov '19

07 Nov '19

hannah.williams(a)dell.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35348 ) Change subject: Rangeley: Fix incorrect BCLK ...................................................................... Rangeley: Fix incorrect BCLK Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR PSB_CLOCK_STS[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Signed-off-by: Hannah Williams <hannah.williams(a)dell.com> Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f --- M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h 2 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35348/1 diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 6672eab..d6177b6 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -154,6 +154,33 @@ return (int)power; } +static int get_core_frequency_mhz(int ratio) +{ + msr_t msr; + unsigned int cpu_bclk_hz[] = { + 83333333, + 100000000, + 133333333, + 116666666 + }; + int core_freq; + int index; + + /* Get BCLK - different SKUs can have different BCLK */ + msr = rdmsr(MSR_PSB_CLOCK_STS); + index = msr.lo & CPU_BCLK_MASK; + if (index >= ARRAY_SIZE(cpu_bclk_hz)) + index = 0; + + printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n", + msr.hi, msr.lo, cpu_bclk_hz[index], ratio); + core_freq = (cpu_bclk_hz[index] * ratio) / 1000000; + if ((cpu_bclk_hz[index] * ratio) % 1000000 > 500000) + core_freq++; + printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq); + return core_freq; +} + static void generate_P_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; @@ -177,7 +204,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * RANGELEY_BCLK; + clock_max = get_core_frequency_mhz(ratio_max); /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -240,7 +267,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * RANGELEY_BCLK; + clock = get_core_frequency_mhz(ratio); acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a9..dcfe914 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -15,8 +15,6 @@ #ifndef _CPU_INTEL_MODEL_406DX_H #define _CPU_INTEL_MODEL_406DX_H -/* Rangeley bus clock is fixed at 100MHz */ -#define RANGELEY_BCLK 100 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 @@ -27,6 +25,8 @@ #define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_PSB_CLOCK_STS 0xcd +#define CPU_BCLK_MASK 0x3 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Gerrit-Change-Number: 35348 Gerrit-PatchSet: 1 Gerrit-Owner: hannah.williams(a)dell.com Gerrit-MessageType: newchange

8 28

Change in ...coreboot[master]: cpu/intel/car/core2: Update microcode in CAR setup
by Arthur Heymans (Code Review) 07 Nov '19

07 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30775 Change subject: cpu/intel/car/core2: Update microcode in CAR setup ...................................................................... cpu/intel/car/core2: Update microcode in CAR setup This updates the BSP microcode during CAR setup. Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S 1 file changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30775/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..4fb8c66 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -111,6 +111,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Cache the whole rom to fetch microcode updates */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -131,15 +142,17 @@ invd movl %eax, %cr0 - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - xorl %eax, %eax - rep stosl +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif +cache_xip: post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ + /* Disable caching to set final MTRRs for speeding up XIP. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 @@ -165,8 +178,16 @@ /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd movl %eax, %cr0 + /* Clear the cache memory region. This will also fill up the cache. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Setup the stack. */ mov $_car_stack_end, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/30775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ecd1b99e18c7e73ae47f850fdc4870751dc6e8c Gerrit-Change-Number: 30775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: hatch: Create puff variant
by Edward O'Callaghan (Code Review) 07 Nov '19

07 Nov '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36452 ) Change subject: hatch: Create puff variant ...................................................................... hatch: Create puff variant Includes: - gpio mappings, - overridetree.cb, - kconfig adjustments for reading spd over smbus. BUG=b:141658115 TEST=util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/puff/Makefile.inc A src/mainboard/google/hatch/variants/puff/gpio.c A src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/puff/include/variant/ec.h A src/mainboard/google/hatch/variants/puff/include/variant/gpio.h A src/mainboard/google/hatch/variants/puff/overridetree.cb 8 files changed, 270 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36452/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e339693..8488762 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -93,6 +93,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Puff" if BOARD_GOOGLE_PUFF config MAINBOARD_VENDOR string @@ -118,6 +119,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "puff" if BOARD_GOOGLE_PUFF config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194b..2051e0f 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,9 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c new file mode 100644 index 0000000..baefcf2 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* E23 : TP1 */ + PAD_NC(GPP_E23, NONE), + /* H17 : TP2 */ + PAD_NC(GPP_H17, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb new file mode 100644 index 0000000..d82030d --- /dev/null +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on + chip drivers/i2c/generic + register "name" = ""PS175"" + register "desc" = ""PCON PS175"" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" + register "has_power_resource" = "1" + device i2c 15 on end # ????? + end + end # I2C #2 + device pci 15.3 on + chip drivers/i2c/generic + register "name" = ""RTD21"" + register "desc" = ""Realtek RTD2142"" + device i2c 4a on end # ????? + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323 Gerrit-Change-Number: 36452 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 9

Change in em100[master]: Update to upstream version 4.3.03
by Stefan Reinauer (Code Review) 06 Nov '19

06 Nov '19

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/36364 ) Change subject: Update to upstream version 4.3.03 ...................................................................... Update to upstream version 4.3.03 Update flash database to latest version 4.3.03 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I0974321543ad7f74767a99a7b3f9038a3c15fd95 --- M em100pro_chips.h 1 file changed, 1,957 insertions(+), 1,957 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/64/36364/1 diff --git a/em100pro_chips.h b/em100pro_chips.h index 43e3f0a..b46f65c 100644 --- a/em100pro_chips.h +++ b/em100pro_chips.h @@ -1,12 +1,12 @@ /* EM100Pro supported chips database created from - * Dediprog's EM100Pro utility version 4.3.01 + * Dediprog's EM100Pro utility version 4.3.03 */ #ifndef EM100PRO_CHIPS_H #define EM100PRO_CHIPS_H #include <stdint.h> -#define VERSION "4.3.01" +#define VERSION "4.3.03" #define NUM_INIT_ENTRIES 212 #define BYTES_PER_INIT_ENTRY 4 typedef struct { @@ -503,9 +503,9 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF010A (128 kB) */ + { /* Microchip/SST 25VF010 (128 kB) */ .vendor = "Microchip/SST", - .name = "25VF010A", + .name = "25VF010", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -652,9 +652,9 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF010 (128 kB) */ + { /* Microchip/SST 25VF010A (128 kB) */ .vendor = "Microchip/SST", - .name = "25VF010", + .name = "25VF010A", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -950,6 +950,155 @@ }, .init_len = 140, }, + { /* Microchip/SST 25VF020 (256 kB) */ + .vendor = "Microchip/SST", + .name = "25VF020", + .size = 0x40000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0xbf, 0x43 }, + { 0x23, 0x42, 0xbf, 0x43 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + }, + .init_len = 140, + }, { /* Microchip/SST 25VF020A (256 kB) */ .vendor = "Microchip/SST", .name = "25VF020A", @@ -1248,16 +1397,16 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF020 (256 kB) */ + { /* Microchip/SST 25VF032B (4096 kB) */ .vendor = "Microchip/SST", - .name = "25VF020", - .size = 0x40000, + .name = "25VF032B", + .size = 0x400000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0xbf, 0x43 }, - { 0x23, 0x42, 0xbf, 0x43 }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x4a, 0x4a }, + { 0x23, 0x42, 0xbf, 0x25 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, { 0x23, 0x48, 0x19, 0xc0 }, @@ -1397,16 +1546,16 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF032B (4096 kB) */ + { /* Microchip/SST 25VF040 (512 kB) */ .vendor = "Microchip/SST", - .name = "25VF032B", - .size = 0x400000, + .name = "25VF040", + .size = 0x80000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x4a, 0x4a }, - { 0x23, 0x42, 0xbf, 0x25 }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x53 }, + { 0x23, 0x40, 0xbf, 0x44 }, + { 0x23, 0x42, 0xbf, 0x44 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, { 0x23, 0x48, 0x19, 0xc0 }, @@ -1844,155 +1993,6 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF040 (512 kB) */ - .vendor = "Microchip/SST", - .name = "25VF040", - .size = 0x80000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x53 }, - { 0x23, 0x40, 0xbf, 0x44 }, - { 0x23, 0x42, 0xbf, 0x44 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - }, - .init_len = 140, - }, { /* Microchip/SST 25VF064C (8192 kB) */ .vendor = "Microchip/SST", .name = "25VF064C", @@ -2291,9 +2291,9 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF512A (64 kB) */ + { /* Microchip/SST 25VF512 (64 kB) */ .vendor = "Microchip/SST", - .name = "25VF512A", + .name = "25VF512", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -2440,9 +2440,9 @@ }, .init_len = 140, }, - { /* Microchip/SST 25VF512 (64 kB) */ + { /* Microchip/SST 25VF512A (64 kB) */ .vendor = "Microchip/SST", - .name = "25VF512", + .name = "25VF512A", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -2738,6 +2738,155 @@ }, .init_len = 140, }, + { /* Microchip/SST 25WF020 (256 kB) */ + .vendor = "Microchip/SST", + .name = "25WF020", + .size = 0x40000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0x03, 0x03 }, + { 0x23, 0x42, 0xbf, 0x25 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x06, 0x8f }, + { 0x11, 0x03, 0x04, 0x29 }, + { 0x11, 0x04, 0x07, 0x08 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + }, + .init_len = 140, + }, { /* Microchip/SST 25WF020A (256 kB) */ .vendor = "Microchip/SST", .name = "25WF020A", @@ -2887,15 +3036,15 @@ }, .init_len = 140, }, - { /* Microchip/SST 25WF020 (256 kB) */ + { /* Microchip/SST 25WF040 (512 kB) */ .vendor = "Microchip/SST", - .name = "25WF020", - .size = 0x40000, + .name = "25WF040", + .size = 0x80000, .init = { { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0x03, 0x03 }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x63 }, + { 0x23, 0x40, 0x04, 0x04 }, { 0x23, 0x42, 0xbf, 0x25 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -3257,155 +3406,6 @@ }, .init_len = 211, }, - { /* Microchip/SST 25WF040 (512 kB) */ - .vendor = "Microchip/SST", - .name = "25WF040", - .size = 0x80000, - .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x63 }, - { 0x23, 0x40, 0x04, 0x04 }, - { 0x23, 0x42, 0xbf, 0x25 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x06, 0x8f }, - { 0x11, 0x03, 0x04, 0x29 }, - { 0x11, 0x04, 0x07, 0x08 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - }, - .init_len = 140, - }, { /* Microchip/SST 25WF080 (1024 kB) */ .vendor = "Microchip/SST", .name = "25WF080", @@ -5011,9 +5011,9 @@ }, .init_len = 11, }, - { /* AMIC A25L010A (128 kB) */ + { /* AMIC A25L010 (128 kB) */ .vendor = "AMIC", - .name = "A25L010A", + .name = "A25L010", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5030,9 +5030,9 @@ }, .init_len = 11, }, - { /* AMIC A25L010 (128 kB) */ + { /* AMIC A25L010A (128 kB) */ .vendor = "AMIC", - .name = "A25L010", + .name = "A25L010A", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5068,6 +5068,25 @@ }, .init_len = 11, }, + { /* AMIC A25L020 (256 kB) */ + .vendor = "AMIC", + .name = "A25L020", + .size = 0x40000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0x12, 0x11 }, + { 0x23, 0x42, 0x37, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* AMIC A25L020B (256 kB) */ .vendor = "AMIC", .name = "A25L020B", @@ -5106,25 +5125,6 @@ }, .init_len = 11, }, - { /* AMIC A25L020 (256 kB) */ - .vendor = "AMIC", - .name = "A25L020", - .size = 0x40000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0x12, 0x11 }, - { 0x23, 0x42, 0x37, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* AMIC A25L032 (4096 kB) */ .vendor = "AMIC", .name = "A25L032", @@ -5201,9 +5201,9 @@ }, .init_len = 11, }, - { /* AMIC A25L080A (1024 kB) */ + { /* AMIC A25L080 (1024 kB) */ .vendor = "AMIC", - .name = "A25L080A", + .name = "A25L080", .size = 0x100000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5220,9 +5220,9 @@ }, .init_len = 11, }, - { /* AMIC A25L080 (1024 kB) */ + { /* AMIC A25L080A (1024 kB) */ .vendor = "AMIC", - .name = "A25L080", + .name = "A25L080A", .size = 0x100000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5391,9 +5391,9 @@ }, .init_len = 11, }, - { /* AMIC A25L512A (64 kB) */ + { /* AMIC A25L512 (64 kB) */ .vendor = "AMIC", - .name = "A25L512A", + .name = "A25L512", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5410,9 +5410,9 @@ }, .init_len = 11, }, - { /* AMIC A25L512 (64 kB) */ + { /* AMIC A25L512A (64 kB) */ .vendor = "AMIC", - .name = "A25L512", + .name = "A25L512A", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -5600,6 +5600,25 @@ }, .init_len = 11, }, + { /* Adesto AT25DF081 (1024 kB) */ + .vendor = "Adesto", + .name = "AT25DF081", + .size = 0x100000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x02, 0x00 }, + { 0x23, 0x42, 0x1f, 0x45 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x06, 0x8f }, + { 0x11, 0x03, 0x04, 0x2a }, + { 0x11, 0x04, 0x07, 0x08 }, + }, + .init_len = 11, + }, { /* Adesto AT25DF081A (1024 kB) */ .vendor = "Adesto", .name = "AT25DF081A", @@ -5749,25 +5768,6 @@ }, .init_len = 140, }, - { /* Adesto AT25DF081 (1024 kB) */ - .vendor = "Adesto", - .name = "AT25DF081", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x02, 0x00 }, - { 0x23, 0x42, 0x1f, 0x45 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x06, 0x8f }, - { 0x11, 0x03, 0x04, 0x2a }, - { 0x11, 0x04, 0x07, 0x08 }, - }, - .init_len = 11, - }, { /* Adesto AT25DF161 (2048 kB) */ .vendor = "Adesto", .name = "AT25DF161", @@ -5787,25 +5787,6 @@ }, .init_len = 11, }, - { /* Adesto AT25DF321A (4096 kB) */ - .vendor = "Adesto", - .name = "AT25DF321A", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x01, 0x00 }, - { 0x23, 0x42, 0x1f, 0x47 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x12, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Adesto AT25DF321 (4096 kB) */ .vendor = "Adesto", .name = "AT25DF321", @@ -5825,19 +5806,19 @@ }, .init_len = 11, }, - { /* Adesto AT25DF641A (8192 kB) */ + { /* Adesto AT25DF321A (4096 kB) */ .vendor = "Adesto", - .name = "AT25DF641A", - .size = 0x800000, + .name = "AT25DF321A", + .size = 0x400000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x00, 0x00 }, - { 0x23, 0x42, 0x1f, 0x48 }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x01, 0x00 }, + { 0x23, 0x42, 0x1f, 0x47 }, { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x02, 0x30 }, - { 0x23, 0x48, 0x01, 0xc0 }, + { 0x23, 0x46, 0x12, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, { 0x11, 0x02, 0x0b, 0x3f }, { 0x11, 0x03, 0x07, 0x08 }, { 0x11, 0x04, 0x0c, 0xe4 }, @@ -5863,6 +5844,25 @@ }, .init_len = 11, }, + { /* Adesto AT25DF641A (8192 kB) */ + .vendor = "Adesto", + .name = "AT25DF641A", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x00, 0x00 }, + { 0x23, 0x42, 0x1f, 0x48 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x02, 0x30 }, + { 0x23, 0x48, 0x01, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Adesto AT25DL161 (2048 kB) */ .vendor = "Adesto", .name = "AT25DL161", @@ -6034,25 +6034,6 @@ }, .init_len = 11, }, - { /* Adesto AT26DF041A (512 kB) */ - .vendor = "Adesto", - .name = "AT26DF041A", - .size = 0x80000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x63 }, - { 0x23, 0x40, 0x01, 0x00 }, - { 0x23, 0x42, 0x1f, 0x44 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x02, 0x30 }, - { 0x23, 0x48, 0x01, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Adesto AT26DF041 (512 kB) */ .vendor = "Adesto", .name = "AT26DF041", @@ -6072,6 +6053,25 @@ }, .init_len = 11, }, + { /* Adesto AT26DF041A (512 kB) */ + .vendor = "Adesto", + .name = "AT26DF041A", + .size = 0x80000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x63 }, + { 0x23, 0x40, 0x01, 0x00 }, + { 0x23, 0x42, 0x1f, 0x44 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x02, 0x30 }, + { 0x23, 0x48, 0x01, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Adesto AT26DF081A (1024 kB) */ .vendor = "Adesto", .name = "AT26DF081A", @@ -6091,15 +6091,15 @@ }, .init_len = 11, }, - { /* Adesto AT26DF161A (2048 kB) */ + { /* Adesto AT26DF161 (2048 kB) */ .vendor = "Adesto", - .name = "AT26DF161A", + .name = "AT26DF161", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, { 0x23, 0x3a, 0x00, 0x1f }, { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x01, 0x00 }, + { 0x23, 0x40, 0x00, 0x00 }, { 0x23, 0x42, 0x1f, 0x46 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x12, 0x30 }, @@ -6110,15 +6110,15 @@ }, .init_len = 11, }, - { /* Adesto AT26DF161 (2048 kB) */ + { /* Adesto AT26DF161A (2048 kB) */ .vendor = "Adesto", - .name = "AT26DF161", + .name = "AT26DF161A", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, { 0x23, 0x3a, 0x00, 0x1f }, { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x00, 0x00 }, + { 0x23, 0x40, 0x01, 0x00 }, { 0x23, 0x42, 0x1f, 0x46 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x12, 0x30 }, @@ -6186,9 +6186,9 @@ }, .init_len = 11, }, - { /* ATO ATO25Q16A (2048 kB) */ + { /* ATO ATO25Q16 (2048 kB) */ .vendor = "ATO", - .name = "ATO25Q16A", + .name = "ATO25Q16", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -6205,9 +6205,9 @@ }, .init_len = 11, }, - { /* ATO ATO25Q16 (2048 kB) */ + { /* ATO ATO25Q16A (2048 kB) */ .vendor = "ATO", - .name = "ATO25Q16", + .name = "ATO25Q16A", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -9365,6 +9365,25 @@ }, .init_len = 11, }, + { /* Eon EN25Q16 (2048 kB) */ + .vendor = "Eon", + .name = "EN25Q16", + .size = 0x200000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x1f }, + { 0x23, 0x38, 0x82, 0x65 }, + { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x42, 0x1c, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Eon EN25Q16A (2048 kB) */ .vendor = "Eon", .name = "EN25Q16A", @@ -9384,15 +9403,15 @@ }, .init_len = 11, }, - { /* Eon EN25Q16 (2048 kB) */ + { /* Eon EN25Q32 (4096 kB) */ .vendor = "Eon", - .name = "EN25Q16", - .size = 0x200000, + .name = "EN25Q32", + .size = 0x400000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x16, 0x15 }, { 0x23, 0x42, 0x1c, 0x30 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -9441,28 +9460,9 @@ }, .init_len = 11, }, - { /* Eon EN25Q32 (4096 kB) */ + { /* Eon EN25Q40 (512 kB) */ .vendor = "Eon", - .name = "EN25Q32", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x16, 0x15 }, - { 0x23, 0x42, 0x1c, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, - { /* Eon EN25Q40A (512 kB) */ - .vendor = "Eon", - .name = "EN25Q40A", + .name = "EN25Q40", .size = 0x80000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -9479,9 +9479,9 @@ }, .init_len = 11, }, - { /* Eon EN25Q40 (512 kB) */ + { /* Eon EN25Q40A (512 kB) */ .vendor = "Eon", - .name = "EN25Q40", + .name = "EN25Q40A", .size = 0x80000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -10800,25 +10800,6 @@ }, .init_len = 11, }, - { /* Eon EN25S80A (1024 kB) */ - .vendor = "Eon", - .name = "EN25S80A", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x14, 0x73 }, - { 0x23, 0x42, 0x1c, 0x38 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x06, 0x8f }, - { 0x11, 0x03, 0x04, 0x29 }, - { 0x11, 0x04, 0x07, 0x08 }, - }, - .init_len = 11, - }, { /* Eon EN25S80 (1024 kB) */ .vendor = "Eon", .name = "EN25S80", @@ -10838,6 +10819,25 @@ }, .init_len = 11, }, + { /* Eon EN25S80A (1024 kB) */ + .vendor = "Eon", + .name = "EN25S80A", + .size = 0x100000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x14, 0x73 }, + { 0x23, 0x42, 0x1c, 0x38 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x06, 0x8f }, + { 0x11, 0x03, 0x04, 0x29 }, + { 0x11, 0x04, 0x07, 0x08 }, + }, + .init_len = 11, + }, { /* Eon EN25SF80 (1024 kB) */ .vendor = "Eon", .name = "EN25SF80", @@ -10857,14 +10857,14 @@ }, .init_len = 11, }, - { /* Eon EN25T16A (2048 kB) */ + { /* Eon EN25T16 (2048 kB) */ .vendor = "Eon", - .name = "EN25T16A", + .name = "EN25T16", .size = 0x200000, .init = { { 0x23, 0x32, 0xfe, 0xff }, { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x82, 0x65 }, + { 0x23, 0x38, 0x86, 0x65 }, { 0x23, 0x40, 0x15, 0x14 }, { 0x23, 0x42, 0x1c, 0x51 }, { 0x23, 0x44, 0x03, 0x18 }, @@ -10876,14 +10876,14 @@ }, .init_len = 11, }, - { /* Eon EN25T16 (2048 kB) */ + { /* Eon EN25T16A (2048 kB) */ .vendor = "Eon", - .name = "EN25T16", + .name = "EN25T16A", .size = 0x200000, .init = { { 0x23, 0x32, 0xfe, 0xff }, { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x86, 0x65 }, + { 0x23, 0x38, 0x82, 0x65 }, { 0x23, 0x40, 0x15, 0x14 }, { 0x23, 0x42, 0x1c, 0x51 }, { 0x23, 0x44, 0x03, 0x18 }, @@ -11709,227 +11709,6 @@ }, .init_len = 11, }, - { /* Fudan FM25F02A (256 kB) */ - .vendor = "Fudan", - .name = "FM25F02A", - .size = 0x40000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0x12, 0x11 }, - { 0x23, 0x42, 0xa1, 0x31 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x1a, 0x30 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - /* PROT */ - { 0x23, 0xc4, 0x00, 0x01 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - }, - .init_len = 211, - }, { /* Fudan FM25F02 (256 kB) */ .vendor = "Fudan", .name = "FM25F02", @@ -11949,15 +11728,15 @@ }, .init_len = 11, }, - { /* Fudan FM25F04A (512 kB) */ + { /* Fudan FM25F02A (256 kB) */ .vendor = "Fudan", - .name = "FM25F04A", - .size = 0x80000, + .name = "FM25F02A", + .size = 0x40000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x63 }, - { 0x23, 0x40, 0x13, 0x12 }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0x12, 0x11 }, { 0x23, 0x42, 0xa1, 0x31 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -12189,6 +11968,227 @@ }, .init_len = 11, }, + { /* Fudan FM25F04A (512 kB) */ + .vendor = "Fudan", + .name = "FM25F04A", + .size = 0x80000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x63 }, + { 0x23, 0x40, 0x13, 0x12 }, + { 0x23, 0x42, 0xa1, 0x31 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x1a, 0x30 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + /* PROT */ + { 0x23, 0xc4, 0x00, 0x01 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + }, + .init_len = 211, + }, { /* Fidelix FM25M64A (8192 kB) */ .vendor = "Fidelix", .name = "FM25M64A", @@ -12410,6 +12410,25 @@ }, .init_len = 211, }, + { /* Fidelix FM25Q16 (2048 kB) */ + .vendor = "Fidelix", + .name = "FM25Q16", + .size = 0x200000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x1f }, + { 0x23, 0x38, 0x82, 0x65 }, + { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x42, 0xf8, 0x32 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Fidelix FM25Q16A (2048 kB) */ .vendor = "Fidelix", .name = "FM25Q16A", @@ -12448,174 +12467,6 @@ }, .init_len = 11, }, - { /* Fidelix FM25Q16 (2048 kB) */ - .vendor = "Fidelix", - .name = "FM25Q16", - .size = 0x200000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x15, 0x14 }, - { 0x23, 0x42, 0xf8, 0x32 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, - { /* Microchip/SST FM25Q32A (4096 kB) */ - .vendor = "Microchip/SST", - .name = "FM25Q32A", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x56 }, - { 0x23, 0x40, 0x16, 0x15 }, - { 0x23, 0x42, 0xf8, 0x32 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - }, - .init_len = 140, - }, { /* Fudan FM25Q32 (4096 kB) */ .vendor = "Fudan", .name = "FM25Q32", @@ -12837,6 +12688,155 @@ }, .init_len = 211, }, + { /* Microchip/SST FM25Q32A (4096 kB) */ + .vendor = "Microchip/SST", + .name = "FM25Q32A", + .size = 0x400000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x56 }, + { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x42, 0xf8, 0x32 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + }, + .init_len = 140, + }, { /* GigaDevice GD25B128C (16384 kB) */ .vendor = "GigaDevice", .name = "GD25B128C", @@ -15822,225 +15822,6 @@ }, .init_len = 11, }, - { /* GigaDevice GD25LQ64B (8192 kB) */ - .vendor = "GigaDevice", - .name = "GD25LQ64B", - .size = 0x800000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x17, 0x16 }, - { 0x23, 0x42, 0xc8, 0x60 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x06, 0x8f }, - { 0x11, 0x03, 0x04, 0x2a }, - { 0x11, 0x04, 0x07, 0x08 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - /* SRST */ - { 0x23, 0x4a, 0x8e, 0x65 }, - { 0x23, 0x4c, 0x00, 0x09 }, - { 0x23, 0x4e, 0xff, 0xff }, - /* PROT */ - { 0x23, 0xc4, 0x00, 0x01 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7e }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7c }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x78 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x70 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x60 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x40 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x01 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x03 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x07 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x0f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x1f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x3f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0xf0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0xe0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0xc0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x0f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x1f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x3f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x7f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x7f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x7f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - }, - .init_len = 208, - }, { /* GigaDevice GD25LQ64 (8192 kB) */ .vendor = "GigaDevice", .name = "GD25LQ64", @@ -16260,6 +16041,244 @@ }, .init_len = 208, }, + { /* GigaDevice GD25LQ64B (8192 kB) */ + .vendor = "GigaDevice", + .name = "GD25LQ64B", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0xc8, 0x60 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x06, 0x8f }, + { 0x11, 0x03, 0x04, 0x2a }, + { 0x11, 0x04, 0x07, 0x08 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + /* SRST */ + { 0x23, 0x4a, 0x8e, 0x65 }, + { 0x23, 0x4c, 0x00, 0x09 }, + { 0x23, 0x4e, 0xff, 0xff }, + /* PROT */ + { 0x23, 0xc4, 0x00, 0x01 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7e }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7c }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x78 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x70 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x60 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x40 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x01 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x03 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x07 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x0f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x1f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x3f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0xf0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0xe0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0xc0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x0f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x1f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x3f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x7f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x7f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x7f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + }, + .init_len = 208, + }, + { /* GigaDevice GD25LQ80 (1024 kB) */ + .vendor = "GigaDevice", + .name = "GD25LQ80", + .size = 0x100000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x14, 0x13 }, + { 0x23, 0x42, 0xc8, 0x60 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x06, 0x8f }, + { 0x11, 0x03, 0x04, 0x29 }, + { 0x11, 0x04, 0x07, 0x08 }, + }, + .init_len = 11, + }, { /* GigaDevice GD25LQ80C (1024 kB) */ .vendor = "GigaDevice", .name = "GD25LQ80C", @@ -16479,25 +16498,6 @@ }, .init_len = 208, }, - { /* GigaDevice GD25LQ80 (1024 kB) */ - .vendor = "GigaDevice", - .name = "GD25LQ80", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x14, 0x13 }, - { 0x23, 0x42, 0xc8, 0x60 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x06, 0x8f }, - { 0x11, 0x03, 0x04, 0x29 }, - { 0x11, 0x04, 0x07, 0x08 }, - }, - .init_len = 11, - }, { /* GigaDevice GD25Q10 (128 kB) */ .vendor = "GigaDevice", .name = "GD25Q10", @@ -17155,25 +17155,6 @@ }, .init_len = 208, }, - { /* GigaDevice GD25Q16B (2048 kB) */ - .vendor = "GigaDevice", - .name = "GD25Q16B", - .size = 0x200000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x15, 0x14 }, - { 0x23, 0x42, 0xc8, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* GigaDevice GD25Q16 (2048 kB) */ .vendor = "GigaDevice", .name = "GD25Q16", @@ -17393,6 +17374,25 @@ }, .init_len = 208, }, + { /* GigaDevice GD25Q16B (2048 kB) */ + .vendor = "GigaDevice", + .name = "GD25Q16B", + .size = 0x200000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x1f }, + { 0x23, 0x38, 0x82, 0x65 }, + { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x42, 0xc8, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* GigaDevice GD25Q20 (256 kB) */ .vendor = "GigaDevice", .name = "GD25Q20", @@ -17831,25 +17831,6 @@ }, .init_len = 208, }, - { /* GigaDevice GD25Q32B (4096 kB) */ - .vendor = "GigaDevice", - .name = "GD25Q32B", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x16, 0x15 }, - { 0x23, 0x42, 0xc8, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* GigaDevice GD25Q32 (4096 kB) */ .vendor = "GigaDevice", .name = "GD25Q32", @@ -18069,6 +18050,25 @@ }, .init_len = 208, }, + { /* GigaDevice GD25Q32B (4096 kB) */ + .vendor = "GigaDevice", + .name = "GD25Q32B", + .size = 0x400000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x42, 0xc8, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* GigaDevice GD25Q40 (512 kB) */ .vendor = "GigaDevice", .name = "GD25Q40", @@ -18307,6 +18307,25 @@ }, .init_len = 11, }, + { /* GigaDevice GD25Q64 (8192 kB) */ + .vendor = "GigaDevice", + .name = "GD25Q64", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0xc8, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* GigaDevice GD25Q64B (8192 kB) */ .vendor = "GigaDevice", .name = "GD25Q64B", @@ -18526,44 +18545,6 @@ }, .init_len = 208, }, - { /* GigaDevice GD25Q64 (8192 kB) */ - .vendor = "GigaDevice", - .name = "GD25Q64", - .size = 0x800000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x17, 0x16 }, - { 0x23, 0x42, 0xc8, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, - { /* GigaDevice GD25Q80B (1024 kB) */ - .vendor = "GigaDevice", - .name = "GD25Q80B", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x14, 0x13 }, - { 0x23, 0x42, 0xc8, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* GigaDevice GD25Q80 (1024 kB) */ .vendor = "GigaDevice", .name = "GD25Q80", @@ -18783,6 +18764,25 @@ }, .init_len = 208, }, + { /* GigaDevice GD25Q80B (1024 kB) */ + .vendor = "GigaDevice", + .name = "GD25Q80B", + .size = 0x100000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x14, 0x13 }, + { 0x23, 0x42, 0xc8, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* GigaDevice GD25T80 (1024 kB) */ .vendor = "GigaDevice", .name = "GD25T80", @@ -19639,225 +19639,6 @@ }, .init_len = 11, }, - { /* ISSI IS25WP064A (1024 kB) */ - .vendor = "ISSI", - .name = "IS25WP064A", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x17, 0x16 }, - { 0x23, 0x42, 0x9d, 0x70 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x1a, 0x30 }, - { 0x11, 0x02, 0x06, 0x40 }, - { 0x11, 0x03, 0x04, 0x28 }, - { 0x11, 0x04, 0x07, 0x08 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0x46, 0x53 }, - { 0x23, 0xc1, 0x50, 0x44 }, - { 0x23, 0xc1, 0x01, 0x06 }, - { 0x23, 0xc1, 0xff, 0x01 }, - { 0x23, 0xc1, 0x06, 0x00 }, - { 0x23, 0xc1, 0x10, 0x01 }, - { 0x23, 0xc1, 0x00, 0x30 }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0x05, 0x9d }, - { 0x23, 0xc1, 0x03, 0x01 }, - { 0x23, 0xc1, 0x00, 0x80 }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x20, 0xe5 }, - { 0x23, 0xc1, 0xff, 0xf9 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x03, 0xff }, - { 0x23, 0xc1, 0xeb, 0x44 }, - { 0x23, 0xc1, 0x6b, 0x08 }, - { 0x23, 0xc1, 0x3b, 0x08 }, - { 0x23, 0xc1, 0xbb, 0x80 }, - { 0x23, 0xc1, 0xff, 0xfe }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xeb, 0x44 }, - { 0x23, 0xc1, 0x20, 0x0c }, - { 0x23, 0xc1, 0x52, 0x0f }, - { 0x23, 0xc1, 0xd8, 0x10 }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0x32, 0x42 }, - { 0x23, 0xc1, 0x00, 0xa1 }, - { 0x23, 0xc1, 0xd8, 0x82 }, - { 0x23, 0xc1, 0xc3, 0x11 }, - { 0x23, 0xc1, 0x6b, 0xcc }, - { 0x23, 0xc1, 0x4b, 0x69 }, - { 0x23, 0xc1, 0x75, 0x7a }, - { 0x23, 0xc1, 0x75, 0x7a }, - { 0x23, 0xc1, 0xa4, 0xf7 }, - { 0x23, 0xc1, 0x6c, 0xd5 }, - { 0x23, 0xc1, 0xc2, 0x4a }, - { 0x23, 0xc1, 0xff, 0x2c }, - { 0x23, 0xc1, 0x30, 0xf0 }, - { 0x23, 0xc1, 0x80, 0xf8 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x19, 0x50 }, - { 0x23, 0xc1, 0x16, 0x50 }, - { 0x23, 0xc1, 0xf9, 0x9f }, - { 0x23, 0xc1, 0x64, 0xc0 }, - { 0x23, 0xc1, 0xec, 0x87 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - /* SRST */ - { 0x23, 0x4a, 0x80, 0x55 }, - { 0x23, 0x4c, 0x00, 0x06 }, - { 0x23, 0x4e, 0x00, 0xfc }, - /* PROT */ - { 0x23, 0xc4, 0x00, 0x01 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7e }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7c }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x78 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x70 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x60 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x40 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7e }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7c }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x78 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x70 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x60 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x40 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - }, - .init_len = 208, - }, { /* ISSI IS25WP064 (1024 kB) */ .vendor = "ISSI", .name = "IS25WP064", @@ -20079,6 +19860,225 @@ }, .init_len = 211, }, + { /* ISSI IS25WP064A (1024 kB) */ + .vendor = "ISSI", + .name = "IS25WP064A", + .size = 0x100000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0x9d, 0x70 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x1a, 0x30 }, + { 0x11, 0x02, 0x06, 0x40 }, + { 0x11, 0x03, 0x04, 0x28 }, + { 0x11, 0x04, 0x07, 0x08 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0x46, 0x53 }, + { 0x23, 0xc1, 0x50, 0x44 }, + { 0x23, 0xc1, 0x01, 0x06 }, + { 0x23, 0xc1, 0xff, 0x01 }, + { 0x23, 0xc1, 0x06, 0x00 }, + { 0x23, 0xc1, 0x10, 0x01 }, + { 0x23, 0xc1, 0x00, 0x30 }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0x05, 0x9d }, + { 0x23, 0xc1, 0x03, 0x01 }, + { 0x23, 0xc1, 0x00, 0x80 }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x20, 0xe5 }, + { 0x23, 0xc1, 0xff, 0xf9 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x03, 0xff }, + { 0x23, 0xc1, 0xeb, 0x44 }, + { 0x23, 0xc1, 0x6b, 0x08 }, + { 0x23, 0xc1, 0x3b, 0x08 }, + { 0x23, 0xc1, 0xbb, 0x80 }, + { 0x23, 0xc1, 0xff, 0xfe }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xeb, 0x44 }, + { 0x23, 0xc1, 0x20, 0x0c }, + { 0x23, 0xc1, 0x52, 0x0f }, + { 0x23, 0xc1, 0xd8, 0x10 }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0x32, 0x42 }, + { 0x23, 0xc1, 0x00, 0xa1 }, + { 0x23, 0xc1, 0xd8, 0x82 }, + { 0x23, 0xc1, 0xc3, 0x11 }, + { 0x23, 0xc1, 0x6b, 0xcc }, + { 0x23, 0xc1, 0x4b, 0x69 }, + { 0x23, 0xc1, 0x75, 0x7a }, + { 0x23, 0xc1, 0x75, 0x7a }, + { 0x23, 0xc1, 0xa4, 0xf7 }, + { 0x23, 0xc1, 0x6c, 0xd5 }, + { 0x23, 0xc1, 0xc2, 0x4a }, + { 0x23, 0xc1, 0xff, 0x2c }, + { 0x23, 0xc1, 0x30, 0xf0 }, + { 0x23, 0xc1, 0x80, 0xf8 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x19, 0x50 }, + { 0x23, 0xc1, 0x16, 0x50 }, + { 0x23, 0xc1, 0xf9, 0x9f }, + { 0x23, 0xc1, 0x64, 0xc0 }, + { 0x23, 0xc1, 0xec, 0x87 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + /* SRST */ + { 0x23, 0x4a, 0x80, 0x55 }, + { 0x23, 0x4c, 0x00, 0x06 }, + { 0x23, 0x4e, 0x00, 0xfc }, + /* PROT */ + { 0x23, 0xc4, 0x00, 0x01 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7e }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7c }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x78 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x70 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x60 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x40 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7e }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7c }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x78 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x70 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x60 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x40 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + }, + .init_len = 208, + }, { /* ISSI IS25WQ080 (1024 kB) */ .vendor = "ISSI", .name = "IS25WQ080", @@ -21995,6 +21995,25 @@ }, .init_len = 211, }, + { /* Macronix KH25L512 (64 kB) */ + .vendor = "Macronix", + .name = "KH25L512", + .size = 0x10000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x00 }, + { 0x23, 0x38, 0x82, 0x6a }, + { 0x23, 0x40, 0x10, 0x05 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix KH25L5121E (64 kB) */ .vendor = "Macronix", .name = "KH25L5121E", @@ -22216,25 +22235,6 @@ }, .init_len = 211, }, - { /* Macronix KH25L512 (64 kB) */ - .vendor = "Macronix", - .name = "KH25L512", - .size = 0x10000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x00 }, - { 0x23, 0x38, 0x82, 0x6a }, - { 0x23, 0x40, 0x10, 0x05 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix KH25L6405D (8192 kB) */ .vendor = "Macronix", .name = "KH25L6405D", @@ -24338,6 +24338,25 @@ }, .init_len = 11, }, + { /* SANYO LE25FW203 (256 kB) */ + .vendor = "SANYO", + .name = "LE25FW203", + .size = 0x40000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x86, 0x62 }, + { 0x23, 0x40, 0x00, 0x15 }, + { 0x23, 0x42, 0x62, 0x16 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x02, 0x30 }, + { 0x23, 0x48, 0x01, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* SANYO LE25FW203A (256 kB) */ .vendor = "SANYO", .name = "LE25FW203A", @@ -24487,25 +24506,6 @@ }, .init_len = 140, }, - { /* SANYO LE25FW203 (256 kB) */ - .vendor = "SANYO", - .name = "LE25FW203", - .size = 0x40000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x86, 0x62 }, - { 0x23, 0x40, 0x00, 0x15 }, - { 0x23, 0x42, 0x62, 0x16 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x02, 0x30 }, - { 0x23, 0x48, 0x01, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* SANYO LE25FW403A (512 kB) */ .vendor = "SANYO", .name = "LE25FW403A", @@ -25987,6 +25987,25 @@ }, .init_len = 208, }, + { /* Macronix MX25L1005 (128 kB) */ + .vendor = "Macronix", + .name = "MX25L1005", + .size = 0x20000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x01 }, + { 0x23, 0x38, 0x82, 0x61 }, + { 0x23, 0x40, 0x11, 0x10 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix MX25L1005A (128 kB) */ .vendor = "Macronix", .name = "MX25L1005A", @@ -26025,25 +26044,6 @@ }, .init_len = 11, }, - { /* Macronix MX25L1005 (128 kB) */ - .vendor = "Macronix", - .name = "MX25L1005", - .size = 0x20000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x01 }, - { 0x23, 0x38, 0x82, 0x61 }, - { 0x23, 0x40, 0x11, 0x10 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix MX25L1006E (128 kB) */ .vendor = "Macronix", .name = "MX25L1006E", @@ -28684,25 +28684,6 @@ }, .init_len = 211, }, - { /* Macronix MX25L1605A (2048 kB) */ - .vendor = "Macronix", - .name = "MX25L1605A", - .size = 0x200000, - .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x86, 0x65 }, - { 0x23, 0x40, 0x15, 0x14 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix MX25L1605 (2048 kB) */ .vendor = "Macronix", .name = "MX25L1605", @@ -28722,6 +28703,25 @@ }, .init_len = 11, }, + { /* Macronix MX25L1605A (2048 kB) */ + .vendor = "Macronix", + .name = "MX25L1605A", + .size = 0x200000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x1f }, + { 0x23, 0x38, 0x86, 0x65 }, + { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix MX25L1605D (2048 kB) */ .vendor = "Macronix", .name = "MX25L1605D", @@ -29531,25 +29531,6 @@ }, .init_len = 208, }, - { /* Macronix MX25L2005C (256 kB) */ - .vendor = "Macronix", - .name = "MX25L2005C", - .size = 0x40000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0x12, 0x11 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix MX25L2005 (256 kB) */ .vendor = "Macronix", .name = "MX25L2005", @@ -29569,6 +29550,25 @@ }, .init_len = 11, }, + { /* Macronix MX25L2005C (256 kB) */ + .vendor = "Macronix", + .name = "MX25L2005C", + .size = 0x40000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0x12, 0x11 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix MX25L2006E (256 kB) */ .vendor = "Macronix", .name = "MX25L2006E", @@ -29645,9 +29645,9 @@ }, .init_len = 11, }, - { /* Macronix MX25L2026C (256 kB) */ + { /* Macronix MX25L2026 (256 kB) */ .vendor = "Macronix", - .name = "MX25L2026C", + .name = "MX25L2026", .size = 0x40000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -29794,9 +29794,9 @@ }, .init_len = 140, }, - { /* Macronix MX25L2026 (256 kB) */ + { /* Macronix MX25L2026C (256 kB) */ .vendor = "Macronix", - .name = "MX25L2026", + .name = "MX25L2026C", .size = 0x40000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -32122,25 +32122,6 @@ }, .init_len = 208, }, - { /* Macronix MX25L3205A (4096 kB) */ - .vendor = "Macronix", - .name = "MX25L3205A", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x86, 0x66 }, - { 0x23, 0x40, 0x16, 0x15 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3e }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix MX25L3205 (4096 kB) */ .vendor = "Macronix", .name = "MX25L3205", @@ -32160,6 +32141,25 @@ }, .init_len = 11, }, + { /* Macronix MX25L3205A (4096 kB) */ + .vendor = "Macronix", + .name = "MX25L3205A", + .size = 0x400000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x86, 0x66 }, + { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix MX25L3205D (4096 kB) */ .vendor = "Macronix", .name = "MX25L3205D", @@ -34380,6 +34380,25 @@ }, .init_len = 208, }, + { /* Macronix MX25L512 (64 kB) */ + .vendor = "Macronix", + .name = "MX25L512", + .size = 0x10000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x00 }, + { 0x23, 0x38, 0x82, 0x60 }, + { 0x23, 0x40, 0x10, 0x05 }, + { 0x23, 0x42, 0xc2, 0x20 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Macronix MX25L5121E (64 kB) */ .vendor = "Macronix", .name = "MX25L5121E", @@ -34767,25 +34786,6 @@ }, .init_len = 11, }, - { /* Macronix MX25L512 (64 kB) */ - .vendor = "Macronix", - .name = "MX25L512", - .size = 0x10000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x00 }, - { 0x23, 0x38, 0x82, 0x60 }, - { 0x23, 0x40, 0x10, 0x05 }, - { 0x23, 0x42, 0xc2, 0x20 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Macronix MX25L512E (64 kB) */ .vendor = "Macronix", .name = "MX25L512E", @@ -45437,9 +45437,9 @@ }, .init_len = 211, }, - { /* Chingis Pm25LQ032C (4096 kB) */ + { /* Chingis Pm25LQ032 (4096 kB) */ .vendor = "Chingis", - .name = "Pm25LQ032C", + .name = "Pm25LQ032", .size = 0x400000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -45456,9 +45456,9 @@ }, .init_len = 11, }, - { /* Chingis Pm25LQ032 (4096 kB) */ + { /* Chingis Pm25LQ032C (4096 kB) */ .vendor = "Chingis", - .name = "Pm25LQ032", + .name = "Pm25LQ032C", .size = 0x400000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -45494,9 +45494,9 @@ }, .init_len = 11, }, - { /* Chingis Pm25LV010A (128 kB) */ + { /* Chingis Pm25LV010 (128 kB) */ .vendor = "Chingis", - .name = "Pm25LV010A", + .name = "Pm25LV010", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -45513,9 +45513,9 @@ }, .init_len = 11, }, - { /* Chingis Pm25LV010 (128 kB) */ + { /* Chingis Pm25LV010A (128 kB) */ .vendor = "Chingis", - .name = "Pm25LV010", + .name = "Pm25LV010A", .size = 0x20000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -45608,9 +45608,9 @@ }, .init_len = 11, }, - { /* Chingis Pm25LV512A (64 kB) */ + { /* Chingis Pm25LV512 (64 kB) */ .vendor = "Chingis", - .name = "Pm25LV512A", + .name = "Pm25LV512", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -45627,9 +45627,9 @@ }, .init_len = 11, }, - { /* Chingis Pm25LV512 (64 kB) */ + { /* Chingis Pm25LV512A (64 kB) */ .vendor = "Chingis", - .name = "Pm25LV512", + .name = "Pm25LV512A", .size = 0x10000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -50722,9 +50722,9 @@ }, .init_len = 208, }, - { /* Winbond W25Q16B (2048 kB) */ + { /* Winbond W25Q16 (2048 kB) */ .vendor = "Winbond", - .name = "W25Q16B", + .name = "W25Q16", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -50741,9 +50741,9 @@ }, .init_len = 11, }, - { /* Winbond W25Q16 (2048 kB) */ + { /* Winbond W25Q16B (2048 kB) */ .vendor = "Winbond", - .name = "W25Q16", + .name = "W25Q16B", .size = 0x200000, .init = { { 0x23, 0x32, 0xff, 0xff }, @@ -51893,16 +51893,16 @@ }, .init_len = 208, }, - { /* Winbond W25Q256JV (32768 kB) */ + { /* Winbond W25Q256JV-DTR (32768 kB) */ .vendor = "Winbond", - .name = "W25Q256JV", + .name = "W25Q256JV-DTR", .size = 0x2000000, .init = { { 0x23, 0x32, 0xff, 0xff }, { 0x23, 0x3a, 0x01, 0xff }, { 0x23, 0x38, 0x82, 0x69 }, { 0x23, 0x40, 0x19, 0x18 }, - { 0x23, 0x42, 0xef, 0x40 }, + { 0x23, 0x42, 0xef, 0x70 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, { 0x23, 0x48, 0x1a, 0x30 }, @@ -52112,16 +52112,16 @@ }, .init_len = 208, }, - { /* Winbond W25Q256JV-DTR (32768 kB) */ + { /* Winbond W25Q256JV (32768 kB) */ .vendor = "Winbond", - .name = "W25Q256JV-DTR", + .name = "W25Q256JV", .size = 0x2000000, .init = { { 0x23, 0x32, 0xff, 0xff }, { 0x23, 0x3a, 0x01, 0xff }, { 0x23, 0x38, 0x82, 0x69 }, { 0x23, 0x40, 0x19, 0x18 }, - { 0x23, 0x42, 0xef, 0x70 }, + { 0x23, 0x42, 0xef, 0x40 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, { 0x23, 0x48, 0x1a, 0x30 }, @@ -52550,6 +52550,25 @@ }, .init_len = 208, }, + { /* Winbond W25Q32 (4096 kB) */ + .vendor = "Winbond", + .name = "W25Q32", + .size = 0x400000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x42, 0xef, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25Q32BV (4096 kB) */ .vendor = "Winbond", .name = "W25Q32BV", @@ -52788,25 +52807,6 @@ }, .init_len = 11, }, - { /* Winbond W25Q32 (4096 kB) */ - .vendor = "Winbond", - .name = "W25Q32", - .size = 0x400000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x16, 0x15 }, - { 0x23, 0x42, 0xef, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25Q32DW (4096 kB) */ .vendor = "Winbond", .name = "W25Q32DW", @@ -53045,6 +53045,25 @@ }, .init_len = 208, }, + { /* Winbond W25Q40 (512 kB) */ + .vendor = "Winbond", + .name = "W25Q40", + .size = 0x80000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x63 }, + { 0x23, 0x40, 0x13, 0x12 }, + { 0x23, 0x42, 0xef, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25Q40B (512 kB) */ .vendor = "Winbond", .name = "W25Q40B", @@ -53521,25 +53540,6 @@ }, .init_len = 11, }, - { /* Winbond W25Q40 (512 kB) */ - .vendor = "Winbond", - .name = "W25Q40", - .size = 0x80000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x63 }, - { 0x23, 0x40, 0x13, 0x12 }, - { 0x23, 0x42, 0xef, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25Q40CL (512 kB) */ .vendor = "Winbond", .name = "W25Q40CL", @@ -53759,6 +53759,25 @@ }, .init_len = 208, }, + { /* Winbond W25Q64 (8192 kB) */ + .vendor = "Winbond", + .name = "W25Q64", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0xef, 0x40 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25Q64BV (8192 kB) */ .vendor = "Winbond", .name = "W25Q64BV", @@ -53978,25 +53997,6 @@ }, .init_len = 208, }, - { /* Winbond W25Q64 (8192 kB) */ - .vendor = "Winbond", - .name = "W25Q64", - .size = 0x800000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x17, 0x16 }, - { 0x23, 0x42, 0xef, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25Q64CV (8192 kB) */ .vendor = "Winbond", .name = "W25Q64CV", @@ -54673,6 +54673,225 @@ }, .init_len = 208, }, + { /* Winbond W25Q64JV-DTR (8192 kB) */ + .vendor = "Winbond", + .name = "W25Q64JV-DTR", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0xef, 0x70 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x1a, 0x30 }, + { 0x11, 0x02, 0x0b, 0x3e }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + /* SFDP */ + { 0x23, 0xc9, 0x00, 0x01 }, + { 0x23, 0xc1, 0x46, 0x53 }, + { 0x23, 0xc1, 0x50, 0x44 }, + { 0x23, 0xc1, 0x01, 0x05 }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0x05, 0x00 }, + { 0x23, 0xc1, 0x10, 0x01 }, + { 0x23, 0xc1, 0x00, 0x80 }, + { 0x23, 0xc1, 0xff, 0x00 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x20, 0xe5 }, + { 0x23, 0xc1, 0xff, 0xf9 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x03, 0xff }, + { 0x23, 0xc1, 0xeb, 0x44 }, + { 0x23, 0xc1, 0x6b, 0x08 }, + { 0x23, 0xc1, 0x3b, 0x08 }, + { 0x23, 0xc1, 0xbb, 0x42 }, + { 0x23, 0xc1, 0xff, 0xfe }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0x00, 0x00 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xeb, 0x40 }, + { 0x23, 0xc1, 0x20, 0x0c }, + { 0x23, 0xc1, 0x52, 0x0f }, + { 0x23, 0xc1, 0xd8, 0x10 }, + { 0x23, 0xc1, 0x00, 0x00 }, + { 0x23, 0xc1, 0x02, 0x36 }, + { 0x23, 0xc1, 0x00, 0xa6 }, + { 0x23, 0xc1, 0xea, 0x82 }, + { 0x23, 0xc1, 0xc4, 0x14 }, + { 0x23, 0xc1, 0x63, 0xe9 }, + { 0x23, 0xc1, 0x33, 0x76 }, + { 0x23, 0xc1, 0x75, 0x7a }, + { 0x23, 0xc1, 0x75, 0x7a }, + { 0x23, 0xc1, 0xa2, 0xf7 }, + { 0x23, 0xc1, 0x5c, 0xd5 }, + { 0x23, 0xc1, 0xf7, 0x19 }, + { 0x23, 0xc1, 0xff, 0x4d }, + { 0x23, 0xc1, 0x30, 0xe9 }, + { 0x23, 0xc1, 0x80, 0xf8 }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + { 0x23, 0xc1, 0xff, 0xff }, + /* SRST */ + { 0x23, 0x4a, 0x8e, 0x76 }, + { 0x23, 0x4c, 0x00, 0x09 }, + { 0x23, 0x4e, 0xfb, 0xff }, + /* PROT */ + { 0x23, 0xc4, 0x00, 0x01 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7e }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7c }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x78 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x70 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x60 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x40 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x01 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x03 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x07 }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x0f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x1f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x3f }, + { 0x23, 0xc5, 0xff, 0xff }, + { 0x23, 0xc5, 0x00, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0xf0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0xe0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0xc0, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x80, 0x7f }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x7f }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x0f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x0f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x1f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x3f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x7f, 0xff }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x00, 0x00 }, + { 0x23, 0xc5, 0x80, 0x00 }, + }, + .init_len = 208, + }, { /* Winbond W25Q64JV (8192 kB) */ .vendor = "Winbond", .name = "W25Q64JV", @@ -54892,224 +55111,24 @@ }, .init_len = 208, }, - { /* Winbond W25Q64JV-DTR (8192 kB) */ + { /* Winbond W25Q80 (1024 kB) */ .vendor = "Winbond", - .name = "W25Q64JV-DTR", - .size = 0x800000, + .name = "W25Q80", + .size = 0x100000, .init = { { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x17, 0x16 }, - { 0x23, 0x42, 0xef, 0x70 }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x14, 0x13 }, + { 0x23, 0x42, 0xef, 0x40 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x1a, 0x30 }, - { 0x11, 0x02, 0x0b, 0x3e }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, { 0x11, 0x03, 0x07, 0x08 }, { 0x11, 0x04, 0x0c, 0xe4 }, - /* SFDP */ - { 0x23, 0xc9, 0x00, 0x01 }, - { 0x23, 0xc1, 0x46, 0x53 }, - { 0x23, 0xc1, 0x50, 0x44 }, - { 0x23, 0xc1, 0x01, 0x05 }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0x05, 0x00 }, - { 0x23, 0xc1, 0x10, 0x01 }, - { 0x23, 0xc1, 0x00, 0x80 }, - { 0x23, 0xc1, 0xff, 0x00 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x20, 0xe5 }, - { 0x23, 0xc1, 0xff, 0xf9 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x03, 0xff }, - { 0x23, 0xc1, 0xeb, 0x44 }, - { 0x23, 0xc1, 0x6b, 0x08 }, - { 0x23, 0xc1, 0x3b, 0x08 }, - { 0x23, 0xc1, 0xbb, 0x42 }, - { 0x23, 0xc1, 0xff, 0xfe }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0x00, 0x00 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xeb, 0x40 }, - { 0x23, 0xc1, 0x20, 0x0c }, - { 0x23, 0xc1, 0x52, 0x0f }, - { 0x23, 0xc1, 0xd8, 0x10 }, - { 0x23, 0xc1, 0x00, 0x00 }, - { 0x23, 0xc1, 0x02, 0x36 }, - { 0x23, 0xc1, 0x00, 0xa6 }, - { 0x23, 0xc1, 0xea, 0x82 }, - { 0x23, 0xc1, 0xc4, 0x14 }, - { 0x23, 0xc1, 0x63, 0xe9 }, - { 0x23, 0xc1, 0x33, 0x76 }, - { 0x23, 0xc1, 0x75, 0x7a }, - { 0x23, 0xc1, 0x75, 0x7a }, - { 0x23, 0xc1, 0xa2, 0xf7 }, - { 0x23, 0xc1, 0x5c, 0xd5 }, - { 0x23, 0xc1, 0xf7, 0x19 }, - { 0x23, 0xc1, 0xff, 0x4d }, - { 0x23, 0xc1, 0x30, 0xe9 }, - { 0x23, 0xc1, 0x80, 0xf8 }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - { 0x23, 0xc1, 0xff, 0xff }, - /* SRST */ - { 0x23, 0x4a, 0x8e, 0x76 }, - { 0x23, 0x4c, 0x00, 0x09 }, - { 0x23, 0x4e, 0xfb, 0xff }, - /* PROT */ - { 0x23, 0xc4, 0x00, 0x01 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7e }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7c }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x78 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x70 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x60 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x40 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x01 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x03 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x07 }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x0f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x1f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x3f }, - { 0x23, 0xc5, 0xff, 0xff }, - { 0x23, 0xc5, 0x00, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0xf0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0xe0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0xc0, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x80, 0x7f }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x7f }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x0f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x0f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x1f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x3f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x7f, 0xff }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x00, 0x00 }, - { 0x23, 0xc5, 0x80, 0x00 }, }, - .init_len = 208, + .init_len = 11, }, { /* Winbond W25Q80BL (1024 kB) */ .vendor = "Winbond", @@ -55568,25 +55587,6 @@ }, .init_len = 11, }, - { /* Winbond W25Q80 (1024 kB) */ - .vendor = "Winbond", - .name = "W25Q80", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x14, 0x13 }, - { 0x23, 0x42, 0xef, 0x40 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25R128FV (16384 kB) */ .vendor = "Winbond", .name = "W25R128FV", @@ -56065,6 +56065,25 @@ }, .init_len = 11, }, + { /* Winbond W25X10 (128 kB) */ + .vendor = "Winbond", + .name = "W25X10", + .size = 0x20000, + .init = { + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x01 }, + { 0x23, 0x38, 0x82, 0x61 }, + { 0x23, 0x40, 0x11, 0x10 }, + { 0x23, 0x42, 0xef, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25X10A (128 kB) */ .vendor = "Winbond", .name = "W25X10A", @@ -56122,25 +56141,6 @@ }, .init_len = 11, }, - { /* Winbond W25X10 (128 kB) */ - .vendor = "Winbond", - .name = "W25X10", - .size = 0x20000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x01 }, - { 0x23, 0x38, 0x82, 0x61 }, - { 0x23, 0x40, 0x11, 0x10 }, - { 0x23, 0x42, 0xef, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25X10CL (128 kB) */ .vendor = "Winbond", .name = "W25X10CL", @@ -56160,6 +56160,25 @@ }, .init_len = 11, }, + { /* Winbond W25X16 (2048 kB) */ + .vendor = "Winbond", + .name = "W25X16", + .size = 0x200000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x1f }, + { 0x23, 0x38, 0x82, 0x65 }, + { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x42, 0xef, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25X16A (2048 kB) */ .vendor = "Winbond", .name = "W25X16A", @@ -56198,15 +56217,15 @@ }, .init_len = 11, }, - { /* Winbond W25X16 (2048 kB) */ + { /* Winbond W25X20 (256 kB) */ .vendor = "Winbond", - .name = "W25X16", - .size = 0x200000, + .name = "W25X20", + .size = 0x40000, .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x1f }, - { 0x23, 0x38, 0x82, 0x65 }, - { 0x23, 0x40, 0x15, 0x14 }, + { 0x23, 0x32, 0xff, 0xff }, + { 0x23, 0x3a, 0x00, 0x03 }, + { 0x23, 0x38, 0x82, 0x62 }, + { 0x23, 0x40, 0x12, 0x11 }, { 0x23, 0x42, 0xef, 0x30 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -56274,25 +56293,6 @@ }, .init_len = 11, }, - { /* Winbond W25X20 (256 kB) */ - .vendor = "Winbond", - .name = "W25X20", - .size = 0x40000, - .init = { - { 0x23, 0x32, 0xff, 0xff }, - { 0x23, 0x3a, 0x00, 0x03 }, - { 0x23, 0x38, 0x82, 0x62 }, - { 0x23, 0x40, 0x12, 0x11 }, - { 0x23, 0x42, 0xef, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25X20CL (256 kB) */ .vendor = "Winbond", .name = "W25X20CL", @@ -56480,6 +56480,25 @@ }, .init_len = 11, }, + { /* Winbond W25X32 (4096 kB) */ + .vendor = "Winbond", + .name = "W25X32", + .size = 0x400000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x3f }, + { 0x23, 0x38, 0x82, 0x66 }, + { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x42, 0xef, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25X32A (4096 kB) */ .vendor = "Winbond", .name = "W25X32A", @@ -56499,15 +56518,15 @@ }, .init_len = 11, }, - { /* Winbond W25X32 (4096 kB) */ + { /* Winbond W25X40 (512 kB) */ .vendor = "Winbond", - .name = "W25X32", - .size = 0x400000, + .name = "W25X40", + .size = 0x80000, .init = { { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x3f }, - { 0x23, 0x38, 0x82, 0x66 }, - { 0x23, 0x40, 0x16, 0x15 }, + { 0x23, 0x3a, 0x00, 0x07 }, + { 0x23, 0x38, 0x82, 0x63 }, + { 0x23, 0x40, 0x13, 0x12 }, { 0x23, 0x42, 0xef, 0x30 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -56575,25 +56594,6 @@ }, .init_len = 11, }, - { /* Winbond W25X40 (512 kB) */ - .vendor = "Winbond", - .name = "W25X40", - .size = 0x80000, - .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x07 }, - { 0x23, 0x38, 0x82, 0x63 }, - { 0x23, 0x40, 0x13, 0x12 }, - { 0x23, 0x42, 0xef, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* Winbond W25X40CL (512 kB) */ .vendor = "Winbond", .name = "W25X40CL", @@ -56762,6 +56762,25 @@ }, .init_len = 140, }, + { /* Winbond W25X64 (8192 kB) */ + .vendor = "Winbond", + .name = "W25X64", + .size = 0x800000, + .init = { + { 0x23, 0x32, 0xfe, 0xff }, + { 0x23, 0x3a, 0x00, 0x7f }, + { 0x23, 0x38, 0x82, 0x67 }, + { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x42, 0xef, 0x30 }, + { 0x23, 0x44, 0x03, 0x18 }, + { 0x23, 0x46, 0x1a, 0x30 }, + { 0x23, 0x48, 0x19, 0xc0 }, + { 0x11, 0x02, 0x0b, 0x3f }, + { 0x11, 0x03, 0x07, 0x08 }, + { 0x11, 0x04, 0x0c, 0xe4 }, + }, + .init_len = 11, + }, { /* Winbond W25X64A (8192 kB) */ .vendor = "Winbond", .name = "W25X64A", @@ -56781,15 +56800,15 @@ }, .init_len = 11, }, - { /* Winbond W25X64 (8192 kB) */ + { /* Winbond W25X80 (1024 kB) */ .vendor = "Winbond", - .name = "W25X64", - .size = 0x800000, + .name = "W25X80", + .size = 0x100000, .init = { { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x7f }, - { 0x23, 0x38, 0x82, 0x67 }, - { 0x23, 0x40, 0x17, 0x16 }, + { 0x23, 0x3a, 0x00, 0x0f }, + { 0x23, 0x38, 0x82, 0x64 }, + { 0x23, 0x40, 0x14, 0x13 }, { 0x23, 0x42, 0xef, 0x30 }, { 0x23, 0x44, 0x03, 0x18 }, { 0x23, 0x46, 0x1a, 0x30 }, @@ -56838,25 +56857,6 @@ }, .init_len = 11, }, - { /* Winbond W25X80 (1024 kB) */ - .vendor = "Winbond", - .name = "W25X80", - .size = 0x100000, - .init = { - { 0x23, 0x32, 0xfe, 0xff }, - { 0x23, 0x3a, 0x00, 0x0f }, - { 0x23, 0x38, 0x82, 0x64 }, - { 0x23, 0x40, 0x14, 0x13 }, - { 0x23, 0x42, 0xef, 0x30 }, - { 0x23, 0x44, 0x03, 0x18 }, - { 0x23, 0x46, 0x1a, 0x30 }, - { 0x23, 0x48, 0x19, 0xc0 }, - { 0x11, 0x02, 0x0b, 0x3f }, - { 0x11, 0x03, 0x07, 0x08 }, - { 0x11, 0x04, 0x0c, 0xe4 }, - }, - .init_len = 11, - }, { /* XMC XM25QH64A (8192 kB) */ .vendor = "XMC", .name = "XM25QH64A", -- To view, visit https://review.coreboot.org/c/em100/+/36364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I0974321543ad7f74767a99a7b3f9038a3c15fd95 Gerrit-Change-Number: 36364 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019