coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: intel/82801dx,ix: Rename SMM_ASEG functions
by Kyösti Mälkki (Code Review) 13 Nov '19

13 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35892 ) Change subject: intel/82801dx,ix: Rename SMM_ASEG functions ...................................................................... intel/82801dx,ix: Rename SMM_ASEG functions Static declarations for use with SMM_ASEG conflict those declared globally for use with SMM_TSEG. Change-Id: I8d2984cd8fe6208417b2eda0c10da8fc7bb76cf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/35892/1 diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 521b98d..dc53220 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -235,7 +235,7 @@ extern uint8_t smm_relocation_start, smm_relocation_end; static void *default_smm_area = NULL; -static void smm_relocate(void) +static void aseg_smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -318,7 +318,7 @@ outb(0x00, 0xb2); } -static void smm_install(void) +static void aseg_smm_install(void) { /* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, @@ -329,10 +329,10 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + aseg_smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); + aseg_smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 0a80dd2..5f73f41 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -45,7 +45,7 @@ extern uint8_t smm_relocation_start, smm_relocation_end; static void *default_smm_area = NULL; -static void smm_relocate(void) +static void aseg_smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -126,7 +126,7 @@ static int smm_handler_copied = 0; -static void smm_install(void) +static void aseg_smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all * of them. @@ -158,10 +158,10 @@ void smm_init(void) { /* Put SMM code to 0xa0000 */ - smm_install(); + aseg_smm_install(); /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); + aseg_smm_relocate(); /* We're done. Make sure SMIs can happen! */ smi_set_eos(); -- To view, visit https://review.coreboot.org/c/coreboot/+/35892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2984cd8fe6208417b2eda0c10da8fc7bb76cf1 Gerrit-Change-Number: 35892 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mainboard/google/hatch: Create helios_diskswap variant
by Alexis Savery (Code Review) 12 Nov '19

12 Nov '19

Alexis Savery has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36447 ) Change subject: mainboard/google/hatch: Create helios_diskswap variant ...................................................................... mainboard/google/hatch: Create helios_diskswap variant Created helios_diskswap as a variant of helios (hatch variant). BUG=b:143378037 BRANCH=None TEST=none Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Signed-off-by: Alexis Savery <asavery(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb 3 files changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/36447/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..6c4bb27 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -83,6 +83,7 @@ default "Dratini" if BOARD_GOOGLE_DRATINI default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS + default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU @@ -96,6 +97,7 @@ config OVERRIDE_DEVICETREE string + default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config TPM_TIS_ACPI_INTERRUPT @@ -108,6 +110,7 @@ default "dratini" if BOARD_GOOGLE_DRATINI default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS + default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 160194b..2268c9e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -32,3 +32,10 @@ select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 + +config BOARD_GOOGLE_HELIOS_DISKSWAP + bool "-> Helios_Diskswap" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb new file mode 100644 index 0000000..3bbf232 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -0,0 +1,209 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "13" + register "tdp_pl2_override" = "64" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Enable Root port 9(x2) for NVMe. + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # Enable Root port 11(x2) for NVMe. + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "10" + # ClkReq-to-ClkSrc mapping for CLK SRC 2 + register "PcieClkSrcClkReq[2]" = "1" + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | FP MCU | + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # No Type-A port + device usb 2.2 off end + end + chip drivers/usb/acpi + # No Type-A Port + device usb 2.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 3.4 off end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "500" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.enable_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 + + # I2C #2 unused + device pci 15.2 off end + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Left Speaker Amp"" + register "uid" = "2" + register "name" = ""WL"" + device i2c 3a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Woofer Right Speaker Amp"" + register "uid" = "3" + register "name" = ""WR"" + device i2c 3b on end + end + end #I2C #4 + + device pci 1d.0 on end # PCI Express Port 9 (X2 NVMe) + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Gerrit-Change-Number: 36447 Gerrit-PatchSet: 1 Gerrit-Owner: Alexis Savery <asavery(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33175 Change subject: [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... [WIP]northbridge/intel/sandybridge: Use C_ENVIRONMENT_BOOTBLOCK VERY WIP and UNTESTED Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc 15 files changed, 42 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33175/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index dbb8982..34b74b5 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -24,10 +24,6 @@ select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/model_206ax/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e1fa879..f0c263b 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -11,6 +11,11 @@ subdirs-y += ../microcode subdirs-y += ../turbo +bootblock-y += ../../x86/early_reset.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += bootblock.c + ramstage-y += acpi.c ramstage-y += common.c @@ -31,7 +36,6 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..197e94c 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -15,13 +15,11 @@ #include <stdint.h> #include <arch/cpu.h> -#include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> +#include <cpu/intel/car/bootblock.h> -#include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ @@ -32,35 +30,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - static void set_flex_ratio_to_tdp_nominal(void) { msr_t flex_ratio, msr; @@ -111,10 +80,8 @@ halt(); } -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..961aa7f 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +bootblock-y += early_init.c +romstage-y += early_init.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 97% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c index a5b0c81..4e416bd 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -27,8 +27,9 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <bootblock_common.h> -void pch_enable_lpc(void) +void bootblock_mainboard_early_init(void) { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -105,10 +106,6 @@ { } -void mainboard_config_superio(void) -{ -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index d5901da..ef87335 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_ACPI select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -68,16 +69,19 @@ int default 512 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 help The MRC blob requires it to be at 0xf0000000. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466..7e9c351 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,8 @@ ramstage-y += acpi.c +bootblock-y += bootblock.c + romstage-y += ram_calc.c ramstage-y += common.c diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..b4de3a4 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,11 +12,12 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> /* Just re-define this instead of including sandybridge.h. It blows up romcc. */ #define PCIEXBAR 0x60 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088..114cd6f 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -54,11 +54,11 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO, BARs, disable watchdog ... */ - early_pch_init(); + /* Init GPIO, ... */ + romstage_pch_init(); /* Initialize superio */ - mainboard_config_superio(); +// mainboard_config_superio(); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fc3e9fc..8b9f580 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -54,10 +54,6 @@ int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/bd82x6x/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b6023b0..7af3cec 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,12 +38,16 @@ romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c +bootblock-y += early_pch.c romstage-y += early_pch.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +bootblock-y += early_usb.c romstage-y += early_thermal.c early_me.c early_usb.c else romstage-y += early_me_mrc.c early_usb_mrc.c endif +bootblock-y += bootblock.c + endif diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0086fe3..1566faa 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> #include "pch.h" @@ -66,7 +67,7 @@ RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); enable_port80_on_lpc(); @@ -74,4 +75,6 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + bootblock_pch_init(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..0aa78ae 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,13 +258,15 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -void early_pch_init(void) +void bootblock_pch_init(void) { - pch_enable_lpc(); - pch_enable_bars(); pch_generic_setup(); +} +void romstage_pch_init(void) +{ setup_pch_gpios(&mainboard_gpio_map); } + diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 4369b5c..9d9570b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,7 +75,8 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -void early_pch_init(void); +void bootblock_pch_init(void); +void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f..6a5e636 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -31,6 +31,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +bootblock-y += pmbase.c verstage-y += pmbase.c romstage-y += pmbase.c ramstage-y += pmbase.c -- To view, visit https://review.coreboot.org/c/coreboot/+/33175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527b24e2e4bfd56a92ecd1bb1cebfe91f54b7fe0 Gerrit-Change-Number: 33175 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: northbridge/intel/sandybridge: Set up console on bootblock
by Arthur Heymans (Code Review) 12 Nov '19

12 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33187 Change subject: northbridge/intel/sandybridge: Set up console on bootblock ...................................................................... northbridge/intel/sandybridge: Set up console on bootblock The assmption is made that setting up southbridge gpio's is not needed for console in the bootblock. Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/Makefile.inc R src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/asrock/b75pro3-m/Makefile.inc R src/mainboard/asrock/b75pro3-m/early_init.c M src/mainboard/asus/h61m-cs/Makefile.inc R src/mainboard/asus/h61m-cs/early_init.c M src/mainboard/asus/maximus_iv_gene-z/Makefile.inc R src/mainboard/asus/maximus_iv_gene-z/early_init.c M src/mainboard/asus/p8h61-m_lx/Makefile.inc R src/mainboard/asus/p8h61-m_lx/early_init.c M src/mainboard/asus/p8h61-m_pro/Makefile.inc R src/mainboard/asus/p8h61-m_pro/early_init.c M src/mainboard/compulab/intense_pc/Makefile.inc R src/mainboard/compulab/intense_pc/early_init.c M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc R src/mainboard/gigabyte/ga-b75m-d3h/early_init.c M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc R src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c M src/mainboard/google/butterfly/Makefile.inc R src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/Makefile.inc R src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/Makefile.inc R src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/Makefile.inc R src/mainboard/google/stout/early_init.c M src/mainboard/hp/2570p/Makefile.inc R src/mainboard/hp/2570p/early_init.c M src/mainboard/hp/2760p/Makefile.inc R src/mainboard/hp/2760p/early_init.c M src/mainboard/hp/8460p/Makefile.inc R src/mainboard/hp/8460p/early_init.c M src/mainboard/hp/8470p/Makefile.inc R src/mainboard/hp/8470p/early_init.c M src/mainboard/hp/8770w/Makefile.inc R src/mainboard/hp/8770w/early_init.c M src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc R src/mainboard/hp/compaq_8200_elite_sff/early_init.c M src/mainboard/hp/folio_9470m/Makefile.inc R src/mainboard/hp/folio_9470m/early_init.c M src/mainboard/hp/revolve_810_g1/Makefile.inc R src/mainboard/hp/revolve_810_g1/early_init.c M src/mainboard/intel/dcp847ske/Makefile.inc R src/mainboard/intel/dcp847ske/early_init.c M src/mainboard/intel/emeraldlake2/Makefile.inc R src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/Makefile.inc R src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/l520/Makefile.inc R src/mainboard/lenovo/l520/early_init.c M src/mainboard/lenovo/s230u/Makefile.inc R src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t420/Makefile.inc R src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420s/Makefile.inc R src/mainboard/lenovo/t420s/early_init.c M src/mainboard/lenovo/t430/Makefile.inc R src/mainboard/lenovo/t430/early_init.c M src/mainboard/lenovo/t430s/Makefile.inc R src/mainboard/lenovo/t430s/early_init.c M src/mainboard/lenovo/t520/Makefile.inc R src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/t530/Makefile.inc R src/mainboard/lenovo/t530/early_init.c M src/mainboard/lenovo/x131e/Makefile.inc R src/mainboard/lenovo/x131e/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc R src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/lenovo/x220/Makefile.inc R src/mainboard/lenovo/x220/early_init.c M src/mainboard/lenovo/x230/Makefile.inc R src/mainboard/lenovo/x230/early_init.c M src/mainboard/msi/ms7707/Makefile.inc R src/mainboard/msi/ms7707/early_init.c M src/mainboard/roda/rv11/Makefile.inc R src/mainboard/roda/rv11/early_init.c M src/mainboard/samsung/lumpy/Makefile.inc R src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/Makefile.inc R src/mainboard/samsung/stumpy/early_init.c M src/mainboard/sapphire/pureplatinumh61/Makefile.inc R src/mainboard/sapphire/pureplatinumh61/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 86 files changed, 135 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33187/1 diff --git a/src/mainboard/apple/macbookair4_2/Makefile.inc b/src/mainboard/apple/macbookair4_2/Makefile.inc index a41ee25..b80d5da 100644 --- a/src/mainboard/apple/macbookair4_2/Makefile.inc +++ b/src/mainboard/apple/macbookair4_2/Makefile.inc @@ -6,3 +6,6 @@ spd.bin-type := spd ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/early_init.c similarity index 100% rename from src/mainboard/apple/macbookair4_2/romstage.c rename to src/mainboard/apple/macbookair4_2/early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc index 017967b..3ca89fb 100644 --- a/src/mainboard/asrock/b75pro3-m/Makefile.inc +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/early_init.c similarity index 100% rename from src/mainboard/asrock/b75pro3-m/romstage.c rename to src/mainboard/asrock/b75pro3-m/early_init.c diff --git a/src/mainboard/asus/h61m-cs/Makefile.inc b/src/mainboard/asus/h61m-cs/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/asus/h61m-cs/Makefile.inc +++ b/src/mainboard/asus/h61m-cs/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/early_init.c similarity index 100% rename from src/mainboard/asus/h61m-cs/romstage.c rename to src/mainboard/asus/h61m-cs/early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc index f81e828..dd91210 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c similarity index 100% rename from src/mainboard/asus/maximus_iv_gene-z/romstage.c rename to src/mainboard/asus/maximus_iv_gene-z/early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/Makefile.inc b/src/mainboard/asus/p8h61-m_lx/Makefile.inc index 7c1bf9e..0ef22db 100644 --- a/src/mainboard/asus/p8h61-m_lx/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_lx/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_lx/romstage.c rename to src/mainboard/asus/p8h61-m_lx/early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/Makefile.inc b/src/mainboard/asus/p8h61-m_pro/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/asus/p8h61-m_pro/Makefile.inc +++ b/src/mainboard/asus/p8h61-m_pro/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/early_init.c similarity index 100% rename from src/mainboard/asus/p8h61-m_pro/romstage.c rename to src/mainboard/asus/p8h61-m_pro/early_init.c diff --git a/src/mainboard/compulab/intense_pc/Makefile.inc b/src/mainboard/compulab/intense_pc/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/compulab/intense_pc/Makefile.inc +++ b/src/mainboard/compulab/intense_pc/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/early_init.c similarity index 100% rename from src/mainboard/compulab/intense_pc/romstage.c rename to src/mainboard/compulab/intense_pc/early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc index 07fc277..53aae3d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -20,3 +20,6 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-b75m-d3h/romstage.c rename to src/mainboard/gigabyte/ga-b75m-d3h/early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c rename to src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 8033e1c..9c6920e 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -22,3 +22,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/early_init.c similarity index 100% rename from src/mainboard/google/butterfly/romstage.c rename to src/mainboard/google/butterfly/early_init.c diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 89bb365..84e6e5e 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -41,3 +41,6 @@ spd.bin-file := $(SPD_BIN) spd.bin-type := spd romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/early_init.c similarity index 100% rename from src/mainboard/google/link/romstage.c rename to src/mainboard/google/link/early_init.c diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 393d582..9f057e5 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -20,3 +20,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/early_init.c similarity index 100% rename from src/mainboard/google/parrot/romstage.c rename to src/mainboard/google/parrot/early_init.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index be1f0fe..652dc6f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -25,3 +25,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/early_init.c similarity index 100% rename from src/mainboard/google/stout/romstage.c rename to src/mainboard/google/stout/early_init.c diff --git a/src/mainboard/hp/2570p/Makefile.inc b/src/mainboard/hp/2570p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2570p/Makefile.inc +++ b/src/mainboard/hp/2570p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/early_init.c similarity index 100% rename from src/mainboard/hp/2570p/romstage.c rename to src/mainboard/hp/2570p/early_init.c diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/2760p/Makefile.inc +++ b/src/mainboard/hp/2760p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/early_init.c similarity index 100% rename from src/mainboard/hp/2760p/romstage.c rename to src/mainboard/hp/2760p/early_init.c diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8460p/Makefile.inc +++ b/src/mainboard/hp/8460p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/early_init.c similarity index 100% rename from src/mainboard/hp/8460p/romstage.c rename to src/mainboard/hp/8460p/early_init.c diff --git a/src/mainboard/hp/8470p/Makefile.inc b/src/mainboard/hp/8470p/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/8470p/Makefile.inc +++ b/src/mainboard/hp/8470p/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/early_init.c similarity index 100% rename from src/mainboard/hp/8470p/romstage.c rename to src/mainboard/hp/8470p/early_init.c diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc index d57c9b5..b480ae4 100644 --- a/src/mainboard/hp/8770w/Makefile.inc +++ b/src/mainboard/hp/8770w/Makefile.inc @@ -14,3 +14,6 @@ ## romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/early_init.c similarity index 100% rename from src/mainboard/hp/8770w/romstage.c rename to src/mainboard/hp/8770w/early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc index ebe01ae..261e206 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc +++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc @@ -1,2 +1,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/early_init.c similarity index 100% rename from src/mainboard/hp/compaq_8200_elite_sff/romstage.c rename to src/mainboard/hp/compaq_8200_elite_sff/early_init.c diff --git a/src/mainboard/hp/folio_9470m/Makefile.inc b/src/mainboard/hp/folio_9470m/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/hp/folio_9470m/Makefile.inc +++ b/src/mainboard/hp/folio_9470m/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/early_init.c similarity index 100% rename from src/mainboard/hp/folio_9470m/romstage.c rename to src/mainboard/hp/folio_9470m/early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/Makefile.inc b/src/mainboard/hp/revolve_810_g1/Makefile.inc index 7a211f4..e5c8647 100644 --- a/src/mainboard/hp/revolve_810_g1/Makefile.inc +++ b/src/mainboard/hp/revolve_810_g1/Makefile.inc @@ -19,3 +19,6 @@ # FIXME: Other varients with same size onboard ram may exist. SPD_SOURCES = hynix_4g + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/early_init.c similarity index 100% rename from src/mainboard/hp/revolve_810_g1/romstage.c rename to src/mainboard/hp/revolve_810_g1/early_init.c diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 4d516f6..3803149 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -2,3 +2,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/early_init.c similarity index 100% rename from src/mainboard/intel/dcp847ske/romstage.c rename to src/mainboard/intel/dcp847ske/early_init.c diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index b3bf53f..f2d7b97 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/early_init.c similarity index 100% rename from src/mainboard/intel/emeraldlake2/romstage.c rename to src/mainboard/intel/emeraldlake2/early_init.c diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index ea035d3..5210d08 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1,3 +1,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/early_init.c similarity index 100% rename from src/mainboard/kontron/ktqm77/romstage.c rename to src/mainboard/kontron/ktqm77/early_init.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2aa7f0f..f1a1016 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -18,3 +18,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/early_init.c similarity index 100% rename from src/mainboard/lenovo/l520/romstage.c rename to src/mainboard/lenovo/l520/early_init.c diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index dea2e4e..0e4c5e8 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -15,3 +15,6 @@ SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/early_init.c similarity index 100% rename from src/mainboard/lenovo/s230u/romstage.c rename to src/mainboard/lenovo/s230u/early_init.c diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420/romstage.c rename to src/mainboard/lenovo/t420/early_init.c diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t420s/romstage.c rename to src/mainboard/lenovo/t420s/early_init.c diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index ada25f7..0ca0ecd 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -3,3 +3,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430/romstage.c rename to src/mainboard/lenovo/t430/early_init.c diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d70c22e..05763f9 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -19,3 +19,6 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/early_init.c similarity index 100% rename from src/mainboard/lenovo/t430s/romstage.c rename to src/mainboard/lenovo/t430s/early_init.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/early_init.c similarity index 100% rename from src/mainboard/lenovo/t520/romstage.c rename to src/mainboard/lenovo/t520/early_init.c diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 7187013..ccf810e 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/early_init.c similarity index 100% rename from src/mainboard/lenovo/t530/romstage.c rename to src/mainboard/lenovo/t530/early_init.c diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 7a00cce..9242841 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/early_init.c similarity index 100% rename from src/mainboard/lenovo/x131e/romstage.c rename to src/mainboard/lenovo/x131e/early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index ee08d78..5a83f28 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -19,3 +19,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c similarity index 100% rename from src/mainboard/lenovo/x1_carbon_gen1/romstage.c rename to src/mainboard/lenovo/x1_carbon_gen1/early_init.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..c988b80 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/early_init.c similarity index 100% rename from src/mainboard/lenovo/x220/romstage.c rename to src/mainboard/lenovo/x220/early_init.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 2dab950..1a4c50c 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/early_init.c similarity index 100% rename from src/mainboard/lenovo/x230/romstage.c rename to src/mainboard/lenovo/x230/early_init.c diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc index 3dae61e..ea30f64 100644 --- a/src/mainboard/msi/ms7707/Makefile.inc +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -1 +1,4 @@ romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/early_init.c similarity index 100% rename from src/mainboard/msi/ms7707/romstage.c rename to src/mainboard/msi/ms7707/early_init.c diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc index 5b5ca65..fd4c498 100644 --- a/src/mainboard/roda/rv11/Makefile.inc +++ b/src/mainboard/roda/rv11/Makefile.inc @@ -19,3 +19,6 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/early_init.c similarity index 100% rename from src/mainboard/roda/rv11/romstage.c rename to src/mainboard/roda/rv11/early_init.c diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 7f8f966..21c855f 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -30,3 +30,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/lumpy/romstage.c rename to src/mainboard/samsung/lumpy/early_init.c diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index a91a061..f50c637 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -18,3 +18,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/early_init.c similarity index 100% rename from src/mainboard/samsung/stumpy/romstage.c rename to src/mainboard/samsung/stumpy/early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc index 7c555f9..a584a16 100644 --- a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c similarity index 100% rename from src/mainboard/sapphire/pureplatinumh61/romstage.c rename to src/mainboard/sapphire/pureplatinumh61/early_init.c diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 336b47e..3f7bae2 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/common/gpio.h> #include <elog.h> static void early_pch_reset_pmcon(void) @@ -53,11 +54,8 @@ if (bist == 0) enable_lapic(); - /* Init LPC, GPIO ... */ - romstage_pch_init(); - - /* Initialize superio */ - mainboard_config_superio(); + /* Init GPIO */ + setup_pch_gpios(&mainboard_gpio_map); /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index ef64825..452fb4f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,7 +14,9 @@ */ #include <cpu/intel/car/bootblock.h> +#include <northbridge/intel/sandybridge/sandybridge.h> #include <device/pci_ops.h> +#include <bootblock_common.h> #include "pch.h" /* @@ -78,3 +80,10 @@ /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); } + +void bootblock_mainboard_early_init(void) +{ + pch_enable_lpc(); + + mainboard_config_superio(); +} diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index c166f79..5619133 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -264,10 +264,3 @@ pch_generic_setup(); } - -void romstage_pch_init(void) -{ - pch_enable_lpc(); - - setup_pch_gpios(&mainboard_gpio_map); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9d9570b..9102bb5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); void bootblock_pch_init(void); -void romstage_pch_init(void); void early_pch_init_native_dmi_pre(void); void early_pch_init_native_dmi_post(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/33187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b242e7cde0c5799f63331b817d863a0d6c00ab3 Gerrit-Change-Number: 33187 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 5

Change in coreboot[master]: vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded
by HAOUAS Elyes (Code Review) 12 Nov '19

12 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34536 ) Change subject: vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded ...................................................................... vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded This clean my .config from this symbol. Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/intel/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34536/1 diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 7b50995..d4f53e5 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -28,6 +28,7 @@ config UDK_2017_BINDING def_bool n +if (UEFI_2_4_BINDING || UDK_2015_BINDING || UDK_2017_BINDING) config UDK_2013_VERSION int default 2013 @@ -47,3 +48,4 @@ default UDK_2013_VERSION help UEFI Development Kit version for Platform +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb Gerrit-Change-Number: 34536 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/{cannonlake,skylake}: Remove unused 'rdmsr(MSR_CONFIG_TDP_NOMINAL)'
by HAOUAS Elyes (Code Review) 11 Nov '19

11 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36164 ) Change subject: soc/{cannonlake,skylake}: Remove unused 'rdmsr(MSR_CONFIG_TDP_NOMINAL)' ...................................................................... soc/{cannonlake,skylake}: Remove unused 'rdmsr(MSR_CONFIG_TDP_NOMINAL)' MSR_CONFIG_TDP_NOMINAL is used by 'cpu_get_tdp_nominal_ratio' to return the TDP Nominal Ratio. Change-Id: I4c8df7a4100c185c1430d993f7618ed00fc556ff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/skylake/cpu.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36164/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c58b9ad..b95d561 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -220,7 +220,6 @@ /* Use nominal TDP values for CPUs with configurable TDP */ if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; limit.lo = cpu_get_tdp_nominal_ratio(); wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1f9ecad..3acaa72 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -231,7 +231,6 @@ /* Use nominal TDP values for CPUs with configurable TDP */ if (cpu_config_tdp_levels()) { - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; limit.lo = cpu_get_tdp_nominal_ratio(); wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); -- To view, visit https://review.coreboot.org/c/coreboot/+/36164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8df7a4100c185c1430d993f7618ed00fc556ff Gerrit-Change-Number: 36164 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/mediatek: Add missing '#include <console/console.h>'
by HAOUAS Elyes (Code Review) 11 Nov '19

11 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36454 ) Change subject: soc/mediatek: Add missing '#include <console/console.h>' ...................................................................... soc/mediatek: Add missing '#include <console/console.h>' Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/mt8183/spm.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/36454/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index e58bb9c..1ca55ae 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -15,6 +15,7 @@ #include <string.h> #include <assert.h> +#include <console/console.h> #include <delay.h> #include <timer.h> #include <symbols.h> diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 669970f..9a08782 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -15,6 +15,7 @@ #include <assert.h> #include <cbfs.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <endian.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c Gerrit-Change-Number: 36454 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include <consol...
by HAOUAS Elyes (Code Review) 11 Nov '19

11 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36453 ) Change subject: mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include <console/console.h> ...................................................................... mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include <console/console.h> Change-Id: Ia4e496d359036591131c1ec0243d64c58823ca63 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/fizz/mainboard.c M src/mainboard/razer/blade_stealth_kbl/romstage.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/36453/1 diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6a7d452..9397786 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <chip.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <ec/ec.h> diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 89903ab..445f620 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -17,6 +17,7 @@ */ #include <assert.h> +#include <console/console.h> #include <soc/romstage.h> #include <spd_bin.h> #include "spd/spd.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/36453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4e496d359036591131c1ec0243d64c58823ca63 Gerrit-Change-Number: 36453 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: SMBIOS: Add 'CXL FLexbus 1.0' memory array location
by HAOUAS Elyes (Code Review) 11 Nov '19

11 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36427 ) Change subject: SMBIOS: Add 'CXL FLexbus 1.0' memory array location ...................................................................... SMBIOS: Add 'CXL FLexbus 1.0' memory array location Change-Id: Ib66616ddefe6254c7c64f223c4f3f7cc8d198bb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36427/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index ef1c7de..c69d48a 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -193,6 +193,7 @@ MEMORY_ARRAY_LOCATION_PC_98_C24_ADD_ON = 0xa1, MEMORY_ARRAY_LOCATION_PC_98_E_ADD_ON = 0xa2, MEMORY_ARRAY_LOCATION_PC_98_LOCAL_BUS_ADD_ON = 0xa3, + MEMORY_ARRAY_LOCATION_CXL_FLEXBUS_1_0_ADD_ON = 0xa4, } smbios_memory_array_location; typedef enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/36427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66616ddefe6254c7c64f223c4f3f7cc8d198bb7 Gerrit-Change-Number: 36427 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/x200: Add ThinkPad X301 as a variant
by Bill XIE (Code Review) 11 Nov '19

11 Nov '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36093 ) Change subject: mb/lenovo/x200: Add ThinkPad X301 as a variant ...................................................................... mb/lenovo/x200: Add ThinkPad X301 as a variant It is similar to X200s, with U-series CPU, slightly different gpio setup, and no docking support, thus no superio chip in dock. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/x301.md A Documentation/mainboard/lenovo/x301_kb_removed.jpg M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Kconfig.name M src/mainboard/lenovo/x200/Makefile.inc M src/mainboard/lenovo/x200/board_info.txt M src/mainboard/lenovo/x200/devicetree.cb A src/mainboard/lenovo/x200/variants/x200/board_info.txt R src/mainboard/lenovo/x200/variants/x200/dock.c R src/mainboard/lenovo/x200/variants/x200/gpio.c A src/mainboard/lenovo/x200/variants/x200/overridetree.cb A src/mainboard/lenovo/x200/variants/x301/board_info.txt A src/mainboard/lenovo/x200/variants/x301/dock.c A src/mainboard/lenovo/x200/variants/x301/gpio.c A src/mainboard/lenovo/x200/variants/x301/overridetree.cb M src/southbridge/intel/i82801ix/nvs.h 17 files changed, 294 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36093/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c9204f6..2aa2763 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -72,6 +72,10 @@ - [T410](lenovo/t410.md) +### GM45 series + +- [X301](lenovo/x301.md) + ### Sandy Bridge series - [T420](lenovo/t420.md) diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md new file mode 100644 index 0000000..5c6f771 --- /dev/null +++ b/Documentation/mainboard/lenovo/x301.md @@ -0,0 +1,27 @@ +# Lenovo X301 + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![x301_kb_removed](x301_kb_removed.jpg) + +* Battery pack +* Keyboard + +Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y9441… could be used as a guidance of disassembly. + +The WSON-8 flash chip (surrounded with red circle in the photo above, +already replaced with a SOIC-8 one) sits under a piece of insulating +tape. If solders between the chip and soldering pads fortunately +overflows beside the chip as tiny tin balls attached to soldering pads, +it will be possible to use a pomona 5250 clip to hold the chip, with +its metal tips just attached to tin balls, thus connecting the chip to +the programmer. Otherwise, it may be recommended to replace it with a +SOIC-8 one. (as what is done in the photo) + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/x301_kb_removed.jpg b/Documentation/mainboard/lenovo/x301_kb_removed.jpg new file mode 100644 index 0000000..b9f8090 --- /dev/null +++ b/Documentation/mainboard/lenovo/x301_kb_removed.jpg Binary files differ diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bc..fab8a88 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X200 +if BOARD_LENOVO_X200 || BOARD_LENOVO_X301 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,9 +28,19 @@ string default lenovo/x200 +config VARIANT_DIR + string + default "x200" if BOARD_LENOVO_X200 + default "x301" if BOARD_LENOVO_X301 + config MAINBOARD_PART_NUMBER string - default "ThinkPad X200" + default "ThinkPad X200" if BOARD_LENOVO_X200 + default "ThinkPad X301" if BOARD_LENOVO_X301 + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config USBDEBUG_HCD_INDEX int @@ -44,4 +54,4 @@ hex default 0x200000 -endif # BOARD_LENOVO_X200 +endif # BOARD_LENOVO_X200 || BOARD_LENOVO_X301 diff --git a/src/mainboard/lenovo/x200/Kconfig.name b/src/mainboard/lenovo/x200/Kconfig.name index 8e1dd43..54c7961 100644 --- a/src/mainboard/lenovo/x200/Kconfig.name +++ b/src/mainboard/lenovo/x200/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_X200 - bool "ThinkPad X200 / X200t" + bool "ThinkPad X200 / X200s / X200t" + +config BOARD_LENOVO_X301 + bool "ThinkPad X301" diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index ffd7cf2..f6c2c0c 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,10 +13,10 @@ ## GNU General Public License for more details. ## -ramstage-y += dock.c +ramstage-y += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index c9cc003..6f27955 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -1,5 +1,6 @@ Category: laptop -ROM package: SOIC-16 or SOIC-8 +Board name: ThinkPad X200 baseboard +ROM package: SOIC-16 or SOIC-8 or WSON8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 4efcc25..fdd69ec 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -73,12 +73,6 @@ # Set thermal throttling to 75%. register "throttle_duty" = "THTL_75_0" - # Enable PCIe ports 1,2,4 as slots (Mini * PCIe). - register "pcie_slot_implemented" = "0xb" - # Set power limits to 10 * 10^0 watts. - # Maybe we should set less for Mini PCIe. - register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen3_dec" = "0x001c1681" @@ -114,10 +108,7 @@ device pci 1c.2 on subsystemid 0x17aa 0x20f3 # UWB end # PCIe Port #3 - device pci 1c.3 on - subsystemid 0x17aa 0x20f3 # Expresscard - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + # PCIe Port #4 is configured in override tree. device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI @@ -154,7 +145,6 @@ device pnp ff.1 on # dummy end register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" end chip ec/lenovo/h8 @@ -192,22 +182,6 @@ register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" end - - chip superio/nsc/pc87382 - device pnp 164e.3 on # Digitizer - io 0x60 = 0x200 - irq 0x29 = 0xb0 - irq 0x70 = 0x5 - irq 0xf0 = 0x82 - end - # IR, not connected - device pnp 164e.2 off end - # GPIO, not connected - device pnp 164e.7 off end - # DLPC, not connected - device pnp 164e.19 off end - end - end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 diff --git a/src/mainboard/lenovo/x200/variants/x200/board_info.txt b/src/mainboard/lenovo/x200/variants/x200/board_info.txt new file mode 100644 index 0000000..c9cc003 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c similarity index 96% rename from src/mainboard/lenovo/x200/dock.c rename to src/mainboard/lenovo/x200/variants/x200/dock.c index d5f774b..019d079 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -26,11 +26,11 @@ #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> -#include "dock.h" +#include "../../dock.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) -void h8_mainboard_init_dock (void) +void h8_mainboard_init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/variants/x200/gpio.c similarity index 100% rename from src/mainboard/lenovo/x200/gpio.c rename to src/mainboard/lenovo/x200/variants/x200/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb new file mode 100644 index 0000000..dd08f1f --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb @@ -0,0 +1,38 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3,4 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0xf" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" + # Enable hotplug on PCIe port 4 (Express Card) + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 1c.3 on + subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 + + device pci 1f.0 on # LPC bridge + chip ec/lenovo/pmh7 + register "dock_event_enable" = "0x01" + end + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end + end + end + end +end diff --git a/src/mainboard/lenovo/x200/variants/x301/board_info.txt b/src/mainboard/lenovo/x200/variants/x301/board_info.txt new file mode 100644 index 0000000..6ee5df0 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c new file mode 100644 index 0000000..a180d64 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/dock.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <ec/lenovo/h8/h8.h> +#include "../../dock.h" + +void h8_mainboard_init_dock(void) +{ +} + +void dock_connect(void) +{ +} + +void dock_disconnect(void) +{ +} + +int dock_present(void) +{ + return 0; +} diff --git a/src/mainboard/lenovo/x200/variants/x301/gpio.c b/src/mainboard/lenovo/x200/variants/x301/gpio.c new file mode 100644 index 0000000..01421a9 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/gpio.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/x200/variants/x301/overridetree.cb b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb new file mode 100644 index 0000000..fafe5e9 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb @@ -0,0 +1,14 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x7" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }" + # x301 has no Express Card slot. + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + device pci 1c.3 off end # PCIe Port #4 + end + end +end diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 04e62db..607c225 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -13,6 +13,10 @@ * GNU General Public License for more details. */ +#ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#include <stdint.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -133,3 +137,5 @@ } __packed global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Gerrit-Change-Number: 36093 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

5 24

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019