coreboot-gerrit October 2019

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Change in coreboot[master]: cpu/x86: Move some PARALLEL_MP prototypes
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34152 ) Change subject: cpu/x86: Move some PARALLEL_MP prototypes ...................................................................... cpu/x86: Move some PARALLEL_MP prototypes The implementations live inside platform directories, but the function signatures must match those defined by PARALLEL_MP implementation. Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/smm/gen1/smi.h M src/include/cpu/x86/mp.h M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/skylake/include/soc/smm.h 8 files changed, 7 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34152/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cd8d5cb..2c52caf 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -160,13 +160,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Determine if HyperThreading is disabled. The variable is not valid until diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index 3d5149a..4c80230 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -24,11 +24,4 @@ bool cpu_has_alternative_smrr(void); /* parallel MP helper functions */ -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); void southbridge_smm_clear_state(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_relocate(void); -void smm_lock(void); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index c04252e..05f2471 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -154,4 +154,11 @@ /* Send SMI to self with single execution. */ void smm_initiate_relocation(void); +/* Parallel MP helper functions. */ +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); +void smm_initialize(void); +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); +void smm_relocate(void); +void smm_lock(void); + #endif /* _X86_MP_H_ */ diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index d3e1cdd..fe38dc9 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -53,13 +53,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index c0ab82f..5cf7407 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,12 +50,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 72aa7fa..a3400ff 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -54,13 +54,6 @@ return CONFIG_SMM_TSEG_SIZE; } -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); /* These helpers are for performing SMM relocation. */ void southbridge_trigger_smi(void); diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 991c593..9777599 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,12 +49,5 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 0c5e976..4dfa627 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,12 +48,5 @@ int smm_save_state_in_msrs; }; -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase); -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size); -void smm_initialize(void); -void smm_relocate(void); -void smm_lock(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2 Gerrit-Change-Number: 34152 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: device/hypertransport: Drop dev_find_slot() debugging
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704 Change subject: device/hypertransport: Drop dev_find_slot() debugging ...................................................................... device/hypertransport: Drop dev_find_slot() debugging Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device.c M src/device/device_const.c M src/include/device/device.h 3 files changed, 5 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1 diff --git a/src/device/device.c b/src/device/device.c index 20a4077..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,7 +1253,4 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); - - if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index 480ac76..cdae33d 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -177,15 +177,6 @@ * Work around the devicetree topology being manipulated on-the-fly * on systems with HyperTransport Support. */ - -static int ht_tree_needs_fixing, ht_tree_fixup_failed; - -void ht_report_devtree_sanity(void) -{ - printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", - ht_tree_needs_fixing, ht_tree_fixup_failed); -} - static const struct bus *ht_bus_reloc(const struct bus *parent, pci_devfn_t devfn) { @@ -222,34 +213,20 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { - DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; + const struct bus *root; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - dev = pcidev_path_behind(pci_domain->link_list, devfn); + root = pci_domain->link_list; /* Static devicetree with HyperTransport has whacky topology. */ - if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) - return dev; + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + root = ht_bus_reloc(root, devfn); - DEVTREE_CONST struct device *dev_fixup, *dev_old_method; - - const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); - dev_fixup = pcidev_path_behind(root, devfn); - dev_old_method = dev_find_slot(0, devfn); - - if (ENV_RAMSTAGE) { - if (dev != dev_old_method) - ht_tree_needs_fixing++; - - if (dev_fixup != dev_old_method) - ht_tree_fixup_failed++; - } - - return dev_old_method; + return pcidev_path_behind(root, devfn); } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/include/device/device.h b/src/include/device/device.h index 40a0f58..540b7e3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,7 +227,6 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); -void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432 Gerrit-Change-Number: 30704 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: device/hypertransport: Fix regression on dev_find_slot() removal
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30703 Change subject: device/hypertransport: Fix regression on dev_find_slot() removal ...................................................................... device/hypertransport: Fix regression on dev_find_slot() removal The regression is with the implementation of the functions introduced in commit ad7674e device: Introduce pcidev_on_root() and friends For these platforms, the first PCI node on devicetree is not the root of PCI bus hierarchy, and the topology (bus->children and dev->sibling links) are being manipulated during HyperTransport enumeration. This workaround reverts to old method of using dev_find_slot() while keeping track of whether the new method would give equivalent result. Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Makefile.inc M src/device/device.c M src/device/device_const.c M src/device/hypertransport.c M src/include/device/device.h M src/include/device/pci.h 6 files changed, 87 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30703/1 diff --git a/Makefile.inc b/Makefile.inc index 2741b19..24b5164 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -577,7 +577,10 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) + +ifneq ($(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT),y) smm-y+=$(DEVICETREE_STATIC_C) +endif ####################################################################### # Clean up rules diff --git a/src/device/device.c b/src/device/device.c index 7836af1..20a4077 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1253,4 +1253,7 @@ final_link(link); printk(BIOS_INFO, "Devices finalized\n"); + + if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + ht_report_devtree_sanity(); } diff --git a/src/device/device_const.c b/src/device/device_const.c index ec128e8..480ac76 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -173,6 +173,43 @@ return child; } +/*** + * Work around the devicetree topology being manipulated on-the-fly + * on systems with HyperTransport Support. + */ + +static int ht_tree_needs_fixing, ht_tree_fixup_failed; + +void ht_report_devtree_sanity(void) +{ + printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n", + ht_tree_needs_fixing, ht_tree_fixup_failed); +} + +static const struct bus *ht_bus_reloc(const struct bus *parent, + pci_devfn_t devfn) +{ + DEVTREE_CONST struct device *dev; + DEVTREE_CONST struct bus *bus; + + /* HyperTransport enumeration fixes up the whacky + * topology present in static devicetree. + */ + if (ENV_RAMSTAGE && (SCAN_COMPLETE == ht_scanning_status())) + return parent; + + if (devfn >= PCI_DEVFN(0x18, 0)) + return parent; + + /* One of the links is bus for devices 0:00.x to 0:17.x. */ + dev = pcidev_path_behind(parent, PCI_DEVFN(0x18, 0)); + for (bus = dev->link_list; bus; bus = bus->next) + if (bus->children) + return bus; + + return NULL; +} + DEVTREE_CONST struct device *pcidev_path_behind( const struct bus *parent, pci_devfn_t devfn) { @@ -185,12 +222,34 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn) { + DEVTREE_CONST struct device *dev; DEVTREE_CONST struct device *pci_domain; pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN); if (!pci_domain) return NULL; - return pcidev_path_behind(pci_domain->link_list, devfn); + + dev = pcidev_path_behind(pci_domain->link_list, devfn); + + /* Static devicetree with HyperTransport has whacky topology. */ + if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT)) + return dev; + + DEVTREE_CONST struct device *dev_fixup, *dev_old_method; + + const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn); + dev_fixup = pcidev_path_behind(root, devfn); + dev_old_method = dev_find_slot(0, devfn); + + if (ENV_RAMSTAGE) { + if (dev != dev_old_method) + ht_tree_needs_fixing++; + + if (dev_fixup != dev_old_method) + ht_tree_fixup_failed++; + } + + return dev_old_method; } DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index ed6b2dd..fd4961e 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -244,6 +244,13 @@ } } +static int ht_scan_chain_process = SCAN_NOT_STARTED; + +int ht_scanning_status(void) +{ + return ht_scan_chain_process; +} + static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unitid_base, @@ -276,6 +283,9 @@ /* Restore the hypertransport chain to it's uninitialized state. */ ht_collapse_early_enumeration(bus, offset_unitid); + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_IN_PROGRESS; + /* See which static device nodes I have. */ old_devices = bus->children; bus->children = 0; @@ -472,6 +482,9 @@ last_func->sibling = old_devices; } + if (bus->secondary == 0) + ht_scan_chain_process = SCAN_COMPLETE; + return next_unitid; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..40a0f58 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -227,6 +227,7 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char *msg); +void ht_report_devtree_sanity(void); /* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..41ad281 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -122,6 +122,13 @@ int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx); struct msix_entry *pci_msix_get_table(struct device *dev); +enum { + SCAN_NOT_STARTED = 0, + SCAN_IN_PROGRESS, + SCAN_COMPLETE +}; +int ht_scanning_status(void); + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) -- To view, visit https://review.coreboot.org/c/coreboot/+/30703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a54de542f97159266a1c127da32665957f58f9 Gerrit-Change-Number: 30703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] intel/fsp2_0: Restrict references to CAR
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35289 ) Change subject: [WIP] intel/fsp2_0: Restrict references to CAR ...................................................................... [WIP] intel/fsp2_0: Restrict references to CAR Change-Id: Ifb1e33d67722db086d9f9feff0e1d289f40d4ef5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 21 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35289/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index a916c9d..a4c7c07 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -185,24 +185,9 @@ return CB_SUCCESS; } -static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, - bool s3wake, uint32_t fsp_version, - const struct memranges *memmap) +static void cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, + bool s3wake, uint32_t fsp_version) { - /* - * FSP 2.1 version would use same stack as coreboot instead of - * setting up separate stack frame. FSP 2.1 would not relocate stack - * top and does not reinitialize stack pointer. The parameters passed - * as StackBase and StackSize are actually for temporary RAM and HOBs - * and are not related to FSP stack at all. - */ - if (CONFIG(FSP_USES_CB_STACK)) { - arch_upd->StackBase = temp_ram; - arch_upd->StackSize = sizeof(temp_ram); - } else if (setup_fsp_stack_frame(arch_upd, memmap)) { - return CB_ERR; - } - fsp_fill_mrc_cache(arch_upd, fsp_version); /* Configure bootmode */ @@ -226,8 +211,6 @@ } printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode); - - return CB_SUCCESS; } __weak @@ -292,11 +275,23 @@ /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); - /* Fill common settings on behalf of chipset. */ - if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, - memmap) != CB_SUCCESS) + /* + * FSP 2.1 version would use same stack as coreboot instead of + * setting up separate stack frame. FSP 2.1 would not relocate stack + * top and does not reinitialize stack pointer. The parameters passed + * as StackBase and StackSize are actually for temporary RAM and HOBs + * and are not related to FSP stack at all. + */ + if (CONFIG(FSP_USES_CB_STACK)) { + arch_upd->StackBase = temp_ram; + arch_upd->StackSize = sizeof(temp_ram); + } else if (setup_fsp_stack_frame(arch_upd, memmap)) { die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); + } + + /* Fill common settings on behalf of chipset. */ + fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); @@ -421,7 +416,10 @@ /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); - do_fsp_memory_init(&hdr, s3wake, &memmap); + if (CONFIG(FSP_USES_CB_STACK)) + do_fsp_memory_init(&hdr, s3wake, NULL); + else + do_fsp_memory_init(&hdr, s3wake, &memmap); timestamp_add_now(TS_AFTER_INITRAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb1e33d67722db086d9f9feff0e1d289f40d4ef5 Gerrit-Change-Number: 35289 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/qualcomm: Link cbmem.c only in romstage
by Arthur Heymans (Code Review) 14 Nov '19

14 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36368 ) Change subject: soc/qualcomm: Link cbmem.c only in romstage ...................................................................... soc/qualcomm: Link cbmem.c only in romstage Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/gale/mmu.c M src/mainboard/google/storm/mmu.c M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/cbmem.c 6 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/36368/1 diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index bf46f7a..7ac8b92 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -38,7 +38,8 @@ /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); + if (ENV_ROMSTAGE) + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 9750cc1..3f1515a 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -35,10 +35,9 @@ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); /* Map DMA memory */ mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); -#if ENV_ROMSTAGE - /* Mark cbmem backing store as ready. */ - ipq_cbmem_backing_store_ready(); -#endif + if (ENV_ROMSTAGE) + /* Mark cbmem backing store as ready. */ + ipq_cbmem_backing_store_ready(); } else { mmu_disable_range(DRAM_START, DRAM_SIZE); /* Map DMA memory */ diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 6447acf..b20ae24 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -16,7 +16,6 @@ ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) bootblock-y += clock.c -bootblock-y += cbmem.c bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c @@ -43,7 +42,6 @@ romstage-y += qup.c ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index bed6fce..2c4def6 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -31,7 +31,7 @@ * with components that utilize cbmem in romstage (e.g. vboot_locator * for loading ipq blobs before DRAM is initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL; return _memlayout_cbmem_top; diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 1fd134a..67d54d2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -42,7 +42,6 @@ romstage-y += qup.c ramstage-y += blobs_init.c -ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += lcc.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index 564f538..38f3d73 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -32,7 +32,7 @@ * (e.g. vboot_locator for loading ipq blobs before DRAM is * initialized). */ - if (ENV_ROMSTAGE && (cbmem_backing_store_ready == 0)) + if (cbmem_backing_store_ready == 0) return NULL; return _memlayout_cbmem_top; -- To view, visit https://review.coreboot.org/c/coreboot/+/36368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8 Gerrit-Change-Number: 36368 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: ec/google/chromeec: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 14 Nov '19

14 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32142 Change subject: ec/google/chromeec: Remove redundant use of ACPI offset operator ...................................................................... ec/google/chromeec: Remove redundant use of ACPI offset operator Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32142/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 962988e..b6c2231 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -41,7 +41,6 @@ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte @@ -54,7 +53,6 @@ TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number // DFUD must be 0 for the other 31 values to be valid - Offset (0x0a), DFUD, 1, // Device Features Undefined FLSH, 1, // Flash commands present PFAN, 1, // PWM Fan control present @@ -88,7 +86,6 @@ RWSG, 1, // EC has RWSIG task enabled DEVE, 1, // EC supports device events // make sure we're within our space envelope - Offset (0x0e), Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 982ec5b..77b4708 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -17,7 +17,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */ -Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8 Gerrit-Change-Number: 32142 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: soc/sifive/fu540: add support boot from sdcard
by Xiang Wang (Code Review) 14 Nov '19

14 Nov '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35119 ) Change subject: soc/sifive/fu540: add support boot from sdcard ...................................................................... soc/sifive/fu540: add support boot from sdcard Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/mainboard/sifive/hifive-unleashed/Kconfig M src/mainboard/sifive/hifive-unleashed/media.c M src/soc/sifive/fu540/include/soc/memlayout.ld 3 files changed, 98 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35119/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 2453178..fc9bc1e 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_32768 select MISSING_BOARD_RESET select FLATTENED_DEVICE_TREE + select SPI_SDCARD config HEAP_SIZE default 0x10000 diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index b0198a7..29cca08 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -15,15 +15,91 @@ */ #include <boot_device.h> +#include <symbols.h> +#include <cbfs.h> +#include <arch/mmio.h> +#include <soc/addressmap.h> #include <soc/spi.h> +#include <soc/clock.h> +#include <console/console.h> +#include <string.h> +#include <spi_sdcard.h> + +static struct spi_sdcard card; /* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = +static struct mem_region_device spi_mdev = MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); +static ssize_t unleashed_sd_readat(const struct region_device *rdev, void *dest, + size_t offset, size_t count) +{ + size_t start_block_address = offset / 512; + size_t end_block_address = (offset + count - 1) / 512; + size_t has_begin = !!(offset % 512); + size_t has_end = !!((offset + count) % 512); + + if (start_block_address == end_block_address) { + uint8_t tmp[512]; + size_t o = offset % 512; + size_t l = count; + spi_sdcard_single_read(&card, start_block_address, tmp); + memcpy(dest, tmp + o, l); + return count; + } + + if (has_begin) { + uint8_t tmp[512]; + size_t o = offset % 512; + size_t l = 512 - o; + spi_sdcard_single_read(&card, start_block_address, tmp); + memcpy(dest, tmp + o, l); + } + + if (start_block_address + has_begin <= end_block_address - has_end) { + size_t start_lba = start_block_address + has_begin; + size_t end_lba = end_block_address - has_end; + size_t o = has_begin ? 512 - offset % 512 : 0; + if (start_lba < end_lba) + spi_sdcard_multiple_read(&card, + start_lba, end_lba, dest + o); + else + spi_sdcard_single_read(&card, start_lba, dest + o); + } + + if (has_end) { + uint8_t tmp[512]; + size_t o = 0; + size_t l = (offset + count) % 512; + spi_sdcard_single_read(&card, end_block_address, tmp); + memcpy(dest + count - l, tmp + o, l); + } + + return count; +} + +static const struct region_device_ops unleashed_sd_ops = { + .mmap = mmap_helper_rdev_mmap, + .munmap = mmap_helper_rdev_munmap, + .readat = unleashed_sd_readat, +}; + + +static struct mmap_helper_region_device sd_mdev = + MMAP_HELPER_REGION_INIT(&unleashed_sd_ops, 0, CONFIG_ROM_SIZE); + const struct region_device *boot_device_ro(void) { - return &mdev.rdev; + + switch (read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + return &spi_mdev.rdev; + case 11: + return &sd_mdev.rdev; + } + return NULL; } const static struct fu540_spi_mmap_config spi_mmap_config = { @@ -40,10 +116,22 @@ void boot_device_init(void) { struct spi_slave slave; + switch (read32((uint32_t *)FU540_MSEL)) { + case 6: + case 10: + case 15: + /* initialize spi controller */ + spi_setup_slave(0, 0, &slave); - /* initialize spi controller */ - spi_setup_slave(0, 0, &slave); - - /* map flash to memory space */ - fu540_spi_mmap(&slave, &spi_mmap_config); + /* map flash to memory space */ + fu540_spi_mmap(&slave, &spi_mmap_config); + break; + case 11: + spi_sdcard_init(&card, 2, 0); + mmap_helper_device_init(&sd_mdev, + _cbfs_cache, REGION_SIZE(cbfs_cache)); + break; + default: + die("Wrong configuration of MSEL"); + } } diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index b9b9c47..81a7f9b 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -28,9 +28,11 @@ CAR_STACK(FU540_L2LIM + 64K, 20K) PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) ROMSTAGE(FU540_L2LIM + 128K, 128K) + PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) RAMSTAGE(FU540_DRAM, 256K) MEM_STACK(FU540_DRAM + 256K, 20K) + POSTRAM_CBFS_CACHE(FU540_DRAM + 512K, 32M - 512K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84 Gerrit-Change-Number: 35119 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

6 35

Change in coreboot[master]: drivers/spi: add drivers for sdcard mounted on the spi bus
by Xiang Wang (Code Review) 14 Nov '19

14 Nov '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35118 ) Change subject: drivers/spi: add drivers for sdcard mounted on the spi bus ...................................................................... drivers/spi: add drivers for sdcard mounted on the spi bus Currently supports initialization, read, write, and erase operations. Tested on HiFive Uneashed Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.inc A src/drivers/spi/spi_sdcard.c A src/include/spi_sdcard.h 4 files changed, 768 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35118/1 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index b15a502..dab6d0e 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -30,6 +30,13 @@ Select this option if your chipset driver needs to store certain data in the SPI flash. +config SPI_SDCARD + bool + default n + help + Select this option if your chipset driver needs to store certain + data in the SPI sdcard. + if SPI_FLASH # Keep at 0 because lots of boards assume this default. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index e55233e..6dbc43a 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -15,6 +15,7 @@ $(1)-y += bitbang.c $(1)-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c $(1)-$(CONFIG_SPI_FLASH) += spi_flash.c +$(1)-$(CONFIG_SPI_SDCARD) += spi_sdcard.c $(1)-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP$(2)) += boot_device_rw_nommap.c $(1)-$(CONFIG_CONSOLE_SPI_FLASH) += flashconsole.c $(1)-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c new file mode 100644 index 0000000..7fc6afd --- /dev/null +++ b/src/drivers/spi/spi_sdcard.c @@ -0,0 +1,706 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <spi-generic.h> +#include <spi_sdcard.h> +#include <commonlib/helpers.h> +#include <console/console.h> + +//#define SPI_SDCARD_DEBUG + +#ifdef SPI_SDCARD_DEBUG +#define dprintk(fmt, args...) \ + printk(BIOS_DEBUG, fmt, ##args) +#else +#define dprintk(fmt, args...) \ + do {} while (0) +#endif + +#define SDCARD_TYPE_SDSC 1 +#define SDCARD_TYPE_SDHC 2 +#define SDCARD_TYPE_SDXC 3 + +/* CMD */ +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define SWITCH_FUNC 6 +#define SEND_IF_COND 8 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_TRANSMISSION 12 +#define SEND_STATUS 13 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define READ_MULTIPLEBLOCK 18 +#define WRITE_BLOCK 24 +#define WRITE_MULTIPLEBLOCK 25 +#define PROGRAM_CSD 27 +#define SET_WRITE_PROT 28 +#define CLR_WRITE_PROT 29 +#define SEND_WRITE_PROT 30 +#define ERASE_WR_BLK_START_ADDR 32 +#define ERASE_WR_BLK_END_ADDR 33 +#define ERASE 38 +#define LOCK_UNLOCK 42 +#define APP_CMD 55 +#define GEN_CMD 56 +#define READ_OCR 58 +#define CRC_ON_OFF 59 + +/* ACMD */ +#define SD_STATUS 13 +#define SEND_NUM_WR_BLOCKS 22 +#define SET_WR_BLK_ERASE_COUNT 23 +#define SD_SEND_OP_COND 41 +#define SET_CLR_CARD_DETECT 42 +#define SEND_SCR 51 + +/* control tokens */ +#define CT_BLOCK_START 0xFE +#define CT_MULTIPLE_BLOCK_START 0xFC +#define CT_MULTIPLE_BLOCK_STOP 0xFD +#define CT_RESPONSE_MASK 0x1F +#define CT_RESPONSE_ACCEPTED 0x05 +#define CT_RESPONSE_REJECTED_CRC 0x0B +#define CT_RESPONSE_REJECTED_WRITE_ERR 0x0D + +/* response type */ +#define RSP_R1 0 +#define RSP_R1b 1 +#define RSP_R2 2 +#define RSP_R3 3 +#define RSP_R4 4 +#define RSP_R5 5 +#define RSP_R7 7 + +#define RSP_ERR_CARD_IS_LOCKED (1 << 0) +#define RSP_ERR_WP_ERASE_SKIP (1 << 1) +#define RSP_ERR_GENERAL (1 << 2) +#define RSP_ERR_CC (1 << 3) +#define RSP_ERR_ECC (1 << 4) +#define RSP_ERR_WP_VIOLATION (1 << 5) +#define RSP_ERR_ERASE_PARAM (1 << 6) +#define RSP_ERR_OUT_OF_RANGE (1 << 7) +#define RSP_ERR_IN_IDLE (1 << 8) +#define RSP_ERR_ERASE_RESET (1 << 9) +#define RSP_ERR_ILLEGAL_COMMAND (1 << 10) +#define RSP_ERR_COM_CRC (1 << 11) +#define RSP_ERR_ERASE_SEQUENCE (1 << 12) +#define RSP_ERR_ADDRESS (1 << 13) +#define RSP_ERR_PARAMETER (1 << 14) + +static const uint8_t crc7_table[256] = { + 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, + 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77, + 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26, + 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e, + 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d, + 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45, + 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14, + 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c, + 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b, + 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13, + 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42, + 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a, + 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69, + 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21, + 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70, + 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38, + 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e, + 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36, + 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67, + 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f, + 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c, + 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, + 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55, + 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d, + 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a, + 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52, + 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03, + 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b, + 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28, + 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60, + 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31, + 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79 +}; + +static uint8_t crc7_byte(uint8_t crc, uint8_t data) +{ + return crc7_table[(crc << 1) ^ data]; +} + +static const uint16_t crc16_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, +}; + +static uint16_t crc16_byte(uint16_t prev, uint8_t in) +{ + return crc16_tab[((prev >> 8) ^ in) & 0xff] ^ (prev << 8); +} + +static unsigned long long extract_bits(uint8_t *buff, + int width, int start, int end) +{ + unsigned long long r = 0; + for (int i = end; i >= start; i--) { + int bitpos = width - i - 1; + int b = bitpos / 8; + int shift = 7 - bitpos % 8; + r = (r << 1) | ((buff[b] >> shift) & 1); + } + return r; +} + +static void spi_sdcard_sendbyte(const struct spi_sdcard *card, uint8_t b) +{ + dprintk("sdcard -> %#x\n", b); + spi_xfer(&card->slave, &b, 1, NULL, 0); +} + +static uint8_t spi_sdcard_recvbyte(const struct spi_sdcard *card) +{ + uint8_t b, t = 0xff; + spi_xfer(&card->slave, &t, 1, &b, 1); + dprintk("sdcard <- %#x\n", b); + return b; +} + +static uint8_t spi_sdcard_calculate_command_crc(uint8_t cmd, uint32_t argument) +{ + uint8_t crc = 0; + crc = crc7_byte(crc, (cmd | 0x40) & 0x7f); + crc = crc7_byte(crc, (argument >> (3 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (2 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (1 * 8)) & 0xff); + crc = crc7_byte(crc, (argument >> (0 * 8)) & 0xff); + return (crc << 1) | 1; +} + +static int lookup_cmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case 0: + case 1: + case 6: + case 9: + case 10: + case 16: + case 17: + case 18: + case 24: + case 25: + case 27: + case 30: + case 32: + case 33: + case 42: + case 55: + case 56: + case 59: + return RSP_R1; + case 12: + case 28: + case 29: + case 38: + return RSP_R1b; + case 13: + return RSP_R2; + case 58: + return RSP_R3; + case 8: + return RSP_R7; + } + return -1; +} + +static int lookup_acmd_response_type(uint8_t cmd) +{ + switch (cmd) { + case 22: + case 23: + case 41: + case 42: + case 51: + return RSP_R1; + case 13: + return RSP_R2; + } + return -1; +} + +static int lookup_response_length(int response_type) +{ + switch (response_type) { + case RSP_R1: + case RSP_R1b: + return 1; + case RSP_R2: + return 2; + case RSP_R3: + case RSP_R7: + return 5; + } + return -1; +} + +static int response_resolve(int response_type, uint8_t *response, + uint32_t *out_register) +{ + __unused static const char * const sd_err[] = { + "Card is locked", + "wp erase skip | lock/unlok cmd failed", + "error", + "CC error", + "card err failed", + "wp violation", + "erase param", + "out of range | csd overwrite", + "in idle state", + "erase reset", + "illegal command", + "com crc error", + "erase sequence error", + "address error", + "parameter error" + }; + uint8_t r1 = 0, r2 = 0; + + if ((response_type == RSP_R1) + || (response_type == RSP_R1b) + || (response_type == RSP_R2) + || (response_type == RSP_R3) + || (response_type == RSP_R7)) + r1 = response[0]; + + if (response_type == RSP_R2) + r2 = response[1]; + + if (((response_type == RSP_R3) || (response_type == RSP_R7)) + && (out_register != NULL)) { + *out_register = 0; + *out_register = (*out_register << 8) | response[1]; + *out_register = (*out_register << 8) | response[2]; + *out_register = (*out_register << 8) | response[3]; + *out_register = (*out_register << 8) | response[4]; + } + + if (r1 != 0 || r2 != 0) { + int i = 0; + uint16_t r = (r1 << 8) | r2; + while (r) { + if (r & 1) + dprintk("SDCARD ERROR: %s\n", sd_err[i]); + r = r >> 1; + i++; + } + return (r1 << 8) | r2; + } + + return 0; +} + +static int spi_sdcard_do_command_help(const struct spi_sdcard *card, + int is_acmd, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + int ret, type, length; + uint8_t crc, c, response[5]; + + /* calculate crc for command */ + crc = spi_sdcard_calculate_command_crc(cmd, argument); + + if (is_acmd) + dprintk("\nsdcard execute acmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + else + dprintk("\nsdcard execute cmd%d, argument = %#x, crc = %#x\n", + cmd, argument, crc); + + /* lookup response type of command */ + type = lookup_cmd_response_type(cmd); + if (is_acmd) + type = lookup_acmd_response_type(cmd); + + /* lookup response length of command */ + length = lookup_response_length(type); + + /* enable CS to communicate */ + spi_claim_bus(&card->slave); + + spi_sdcard_recvbyte(card); + + /* send command */ + spi_sdcard_sendbyte(card, (cmd | 0x40) & 0x7f); + /* send argument */ + spi_sdcard_sendbyte(card, (argument >> (8 * 3)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 2)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 1)) & 0xff); + spi_sdcard_sendbyte(card, (argument >> (8 * 0)) & 0xff); + /* send crc */ + spi_sdcard_sendbyte(card, crc); + + /* waitting for response */ + while ((c = spi_sdcard_recvbyte(card)) & 0x80) + ; + + /* obtain response */ + response[0] = c; + for (int i = 1; i < length; i++) + response[i] = spi_sdcard_recvbyte(card); + + if (type == RSP_R1b) + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* waitting done */ + + + ret = response_resolve(type, response, out_register); + if (ret) + /* disable CS if the command fail to execute */ + spi_release_bus(&card->slave); + + return ret; +} + +static int spi_sdcard_do_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + return spi_sdcard_do_command_help(card, 0, cmd, argument, out_register); +} + +static int spi_sdcard_do_app_command(const struct spi_sdcard *card, + uint8_t cmd, + uint32_t argument, + uint32_t *out_register) +{ + /* CMD55 */ + spi_sdcard_do_command(card, APP_CMD, 0, NULL); + return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register); +} + + +size_t spi_sdcard_size(const struct spi_sdcard *card) +{ + uint8_t csd[16]; + uint16_t c = 0; + + /* CMD9, send csd (128bits register) */ + if (spi_sdcard_do_command(card, SEND_CSD, 0, NULL)) { + spi_release_bus(&card->slave); + return -1; + } + + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + + for (int i = 0; i < 16; i++) { + csd[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, csd[i]); + } + + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + + if (extract_bits(csd, 128, 126, 127) == 0) { + /* csd version 1.0 */ + size_t c_size = extract_bits(csd, 128, 62, 73); + size_t mult = extract_bits(csd, 128, 47, 49); + size_t read_bl_len = extract_bits(csd, 128, 80, 83); + return (c_size + 1) * mult * (1 << read_bl_len); + } + + if (extract_bits(csd, 128, 126, 127) == 1) { + /* csd version 2.0 */ + size_t c_size = extract_bits(csd, 128, 48, 69); + return (c_size + 1) * 512 * 1024; + } + + return -1; +} + +int spi_sdcard_init(struct spi_sdcard *card, + unsigned int bus, unsigned int cs) +{ + int resolve; + uint32_t ocr; + + /* initialize spi controller */ + spi_setup_slave(bus, cs, &card->slave); + + spi_release_bus(&card->slave); + for (int i = 0; i < 10; i++) + spi_sdcard_sendbyte(card, 0xff); + + /* CMD0, reset sdcard */ + while (spi_sdcard_do_command(card, GO_IDLE_STATE, 0, NULL) + != RSP_ERR_IN_IDLE) + ; + + /* CMD8 */ + resolve = spi_sdcard_do_command(card, SEND_IF_COND, 0x1aa, NULL); + if (resolve & RSP_ERR_ILLEGAL_COMMAND) + /* ACMD41, initialize card */ + while (spi_sdcard_do_app_command(card, SD_SEND_OP_COND, + 0, NULL)) + ; + else + /* ACMD41, initialize card */ + while (spi_sdcard_do_app_command(card, SD_SEND_OP_COND, + 0x40000000, NULL)) + ; + + /* CMD58, read ocr register */ + if (spi_sdcard_do_command(card, READ_OCR, 0, &ocr)) + return -1; + + /* CMD16, set block length to 512 bytes */ + if (spi_sdcard_do_command(card, SET_BLOCKLEN, 512, NULL)) + return -1; + + /* CCS is bit30 of ocr register + * CCS = 0 -> SDSC + * CCS = 1 -> SDHC/SDXC + * */ + if ((ocr & 0x40000000) == 0) + card->type = SDCARD_TYPE_SDSC; + else { + /* size > 32G -> SDXC */ + if (spi_sdcard_size(card) > 32LL * 1024 * 1024 * 1024) + card->type = SDCARD_TYPE_SDXC; + else + card->type = SDCARD_TYPE_SDHC; + } + + return 0; +} + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + uint16_t c = 0; + + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + /* CMD17, start single block read */ + if (spi_sdcard_do_command(card, READ_SINGLE_BLOCK, block_address, NULL)) + return -1; + + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + for (int i = 0; i < 512; i++) { + ((uint8_t *)buff)[i] = spi_sdcard_recvbyte(card); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + + return 0; +} + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + /* CMD18, start multiple block read */ + if (spi_sdcard_do_command(card, + READ_MULTIPLEBLOCK, start_block_address, NULL)) + return -1; + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + while (spi_sdcard_recvbyte(card) != CT_BLOCK_START) + ; + for (int k = 0; k < 512; k++) { + uint8_t tmp = spi_sdcard_recvbyte(card); + ((uint8_t *)buff)[512 * i + k] = tmp; + c = crc16_byte(c, tmp); + } + if (((c >> 8) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + if (((c >> 0) & 0xff) != spi_sdcard_recvbyte(card)) { + spi_release_bus(&card->slave); + return -1; + } + } + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + return 0; +} + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff) +{ + uint16_t c = 0; + if (card->type == SDCARD_TYPE_SDSC) + block_address = block_address * 512; + + if (spi_sdcard_do_command(card, WRITE_BLOCK, block_address, NULL)) + return -1; + + spi_sdcard_sendbyte(card, CT_BLOCK_START); + for (int i = 0; i < 512; i++) { + spi_sdcard_sendbyte(card, ((uint8_t *)buff)[i]); + c = crc16_byte(c, ((uint8_t *)buff)[i]); + } + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + while (((c = spi_sdcard_recvbyte(card)) & 0x11) != 0x01) + ; + if ((c & CT_RESPONSE_MASK) == CT_RESPONSE_ACCEPTED) { + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* wait for complete */ + return 0; + } + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + + return -1; +} + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff) +{ + int ret = 0; + int block_num = end_block_address - start_block_address + 1; + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + if (spi_sdcard_do_command(card, WRITE_MULTIPLEBLOCK, + start_block_address, NULL)) + return -1; + + for (int i = 0; i < block_num; i++) { + uint16_t c = 0; + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_START); + for (int k = 0; k < 512; k++) { + spi_sdcard_sendbyte(card, + ((uint8_t *)buff)[512 * i + k]); + c = crc16_byte(c, ((uint8_t *)buff)[512 * i + k]); + } + spi_sdcard_sendbyte(card, 0xff & (c >> 8)); + spi_sdcard_sendbyte(card, 0xff & (c >> 0)); + + while (((c = spi_sdcard_recvbyte(card)) & 0x11) != 0x01) + ; + if ((c & CT_RESPONSE_MASK) != CT_RESPONSE_ACCEPTED) { + ret = -1; + break; + } + while (spi_sdcard_recvbyte(card) != 0xff) + ;/* wait for complete */ + } + spi_sdcard_sendbyte(card, CT_MULTIPLE_BLOCK_STOP); + + if (spi_sdcard_do_command(card, STOP_TRANSMISSION, 0, NULL)) + return -1; + + return ret; +} + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address) +{ + if (card->type == SDCARD_TYPE_SDSC) { + start_block_address = start_block_address * 512; + end_block_address = end_block_address * 512; + } + + /* CMD32, set erase start address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_START_ADDR, + start_block_address, NULL)) + return -1; + + /* CMD33, set erase end address */ + if (spi_sdcard_do_command(card, ERASE_WR_BLK_END_ADDR, + end_block_address, NULL)) + return -1; + + /* CMD38, erase */ + if (spi_sdcard_do_command(card, ERASE, 0, NULL)) + return -1; + + return 0; +} + +int spi_sdcard_erase_all(const struct spi_sdcard *card) +{ + return spi_sdcard_erase(card, 0, spi_sdcard_size(card) / 512); +} diff --git a/src/include/spi_sdcard.h b/src/include/spi_sdcard.h new file mode 100644 index 0000000..40d351d --- /dev/null +++ b/src/include/spi_sdcard.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SPI_SDCARD_H_ +#define _SPI_SDCARD_H_ + +struct spi_sdcard { + int type; + struct spi_slave slave; +}; + +int spi_sdcard_init(struct spi_sdcard *card, + unsigned int bus, + unsigned int cs); + +int spi_sdcard_single_read(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_multiple_read(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_single_write(const struct spi_sdcard *card, + size_t block_address, + void *buff); + +int spi_sdcard_multiple_write(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address, + void *buff); + +int spi_sdcard_erase(const struct spi_sdcard *card, + size_t start_block_address, + size_t end_block_address); + +int spi_sdcard_erase_all(const struct spi_sdcard *card); + +size_t spi_sdcard_size(const struct spi_sdcard *card); + +#endif /* _SPI_SDCARD_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a Gerrit-Change-Number: 35118 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: Fix sarien depthcharge make build
by Selma Bensaid (Code Review) 14 Nov '19

14 Nov '19

Selma Bensaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36336 ) Change subject: Fix sarien depthcharge make build ...................................................................... Fix sarien depthcharge make build CONFIG_MAINBOARD_DEPTHCHARGE is set to "" for boards not configuring it. Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.com> Change-Id: If61a1371ad8baf165b09ce045fc1a6c205c2c0ae --- M payloads/external/Makefile.inc 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/36336/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f6417fd..d3d10f8 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -30,9 +30,11 @@ PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),) - BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE) -else - BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) + ifeq ($(CONFIG_MAINBOARD_DEPTHCHARGE),"") + BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) + else + BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE) + endif endif #TODO: Figure out version endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If61a1371ad8baf165b09ce045fc1a6c205c2c0ae Gerrit-Change-Number: 36336 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newchange

2 8

Change in em100[master]: Fix whitespace error
by Patrick Rudolph (Code Review) 14 Nov '19

14 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/36051 ) Change subject: Fix whitespace error ...................................................................... Fix whitespace error Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I5b2492668b1b41afb4c32b24cbf9554783767311 --- M em100.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/51/36051/1 diff --git a/em100.c b/em100.c index a20dc7d..6a348d3 100644 --- a/em100.c +++ b/em100.c @@ -642,7 +642,7 @@ " -c|--set CHIP: select chip emulation\n" " -d|--download FILE: download FILE into EM100pro\n" " -a|--start address: only works with -d (E.g. -d file.bin -a 0x300000)\n" - " -u|--upload FILE: upload from EM100pro into FILE\n" + " -u|--upload FILE: upload from EM100pro into FILE\n" " -r|--start: em100 shall run\n" " -s|--stop: em100 shall stop\n" " -v|--verify: verify EM100 content matches the file\n" -- To view, visit https://review.coreboot.org/c/em100/+/36051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I5b2492668b1b41afb4c32b24cbf9554783767311 Gerrit-Change-Number: 36051 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019