coreboot-gerrit October 2019

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Change in coreboot[master]: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
by Arthur Heymans (Code Review) 17 Nov '19

17 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35722 ) Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR ...................................................................... [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR Totest: Does it still boot? Are romstage timestamps affected (does caching work)? Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/romstage.c A src/cpu/intel/car/set_mtrr.S A src/cpu/intel/car/set_mtrr.h M src/cpu/intel/socket_LGA775/Makefile.inc 4 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b121..eee3412 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -15,12 +15,17 @@ #include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <arch/symbols.h> #include <commonlib/helpers.h> #include <program_loading.h> #include <timestamp.h> +#include <symbols.h> +#include <lib.h> +#include "../car/set_mtrr.h" /* If we do not have a constrained _car_stack region size, use the following as a guideline for acceptable stack usage. */ @@ -51,6 +56,15 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + u32 program_size = _eprogram - _program; + program_size = 1 << log2_ceil(program_size); + msr_t mtrr_phys_mask; + mtrr_phys_mask.lo = ~(program_size - 1) | MTRR_PHYS_MASK_VALID; + mtrr_phys_mask.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + + set_mtrr_asm(1, ALIGN_DOWN((u32)_program, program_size) | MTRR_TYPE_WRPROT, + mtrr_phys_mask); + mainboard_romstage_entry(); /* Check the stack. */ diff --git a/src/cpu/intel/car/set_mtrr.S b/src/cpu/intel/car/set_mtrr.S new file mode 100644 index 0000000..de8a242 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.S @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.global set_mtrr_asm + /* ARG0: MTRR_NUM to use (1 dword) + * ARG1: BASE_ARG (1 dword) + * ARG2: MASK_ARG (2 dwords) + * All arguments assume sanity from the caller + */ +.code32 +set_mtrr_asm: + push %ebp + movl %esp, %ebp + push %edi + push %esi + push %ebx + movl (%ebp), %ecx // MTRR_NUM + movl 4(%ebp), %edi // BASE + movl 8(%ebp), %esi // MASK_LO + movl 12(%ebp), %ebx // MASK_HI + + /* Enable Cache-as-RAM mode by disabling cache. + Assume fetching from stack does not work */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + imul $2, %ecx, %ecx + addl $MTRR_PHYS_BASE(0), %ecx + + // MTRR_PHYS_BASE + xorl %edx, %edx + movl %edi, %eax + wrmsr + + // MTRR_PHYS_MASK + addl $1, %ecx + movl %esi, %eax + movl %ebx, %edx + wrmsr + + /* Enable cache again. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + movl %eax, %cr0 + + /* restore regs */ + pop %ebx + pop %esi + pop %edi + pop %ebp + ret diff --git a/src/cpu/intel/car/set_mtrr.h b/src/cpu/intel/car/set_mtrr.h new file mode 100644 index 0000000..41bc430 --- /dev/null +++ b/src/cpu/intel/car/set_mtrr.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SET_MTRR_H +#define _SET_MTRR_H + +#include <cpu/x86/msr.h> + +void set_mtrr_asm(int num_mtrr, u32 phys_base, msr_t phys_mask); + +#endif diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c..fd0d642 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,6 +14,7 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +romstage-y += ../car/set_mtrr.S postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde Gerrit-Change-Number: 35722 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: vboot: Unify options to force display init
by Nico Huber (Code Review) 16 Nov '19

16 Nov '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34622 ) Change subject: vboot: Unify options to force display init ...................................................................... vboot: Unify options to force display init We used to let implementations for display init that honor display_init_required() explicitly declare that by selecting VBOOT_MUST_REQUEST_DISPLAY. However, to allow the user to force display initialization, it's simpler to invert this Kconfig option. The new Kconfig VBOOT_FORCE_DISPLAY_INIT has the same effect as ALWAYS_RUN_OPROM for VGA OpRoms. Thus, we can also remove the latter. The inversion adds a little Kconfig noise. However, this can be reduced in the future by honoring display_init_required() where it should be. Change-Id: I52288b0d5f33cd11d84e609e039dc4ea16ff7bdf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/pci_device.c M src/drivers/aspeed/ast2050/Kconfig M src/drivers/emulation/qemu/Kconfig M src/drivers/xgi/z9s/Kconfig M src/lib/bootmode.c M src/mainboard/google/daisy/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/peach_pit/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/x4x/Kconfig M src/security/vboot/Kconfig M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/sdm845/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/Kconfig 33 files changed, 51 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34622/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..d1037da 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -139,13 +139,6 @@ are needed for the kernel's display driver to know how a piece of hardware is configured to be used. -config ALWAYS_RUN_OPROM - def_bool n - depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM - help - Always uncondtionally run the option regardless of other - policies. - config ON_DEVICE_ROM_LOAD bool "Load Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..98ec6fc 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -707,11 +707,6 @@ if (should_run >= 0) return should_run; - if (CONFIG(ALWAYS_RUN_OPROM)) { - should_run = 1; - return should_run; - } - /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. */ diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 337b181..137abd7 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -3,3 +3,10 @@ select DRIVERS_ASPEED_AST_COMMON select HAVE_VGA_TEXT_FRAMEBUFFER select MAINBOARD_HAS_NATIVE_VGA_INIT + +if DRIVERS_ASPEED_AST2050 + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + +endif diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 58daaa44..5ab487f 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -13,14 +13,19 @@ vga (cirrus) is *not* supported, so you have to pick another one explicitly via 'qemu -vga $card'. +if DRIVERS_EMULATION_QEMU_BOCHS + config DRIVERS_EMULATION_QEMU_BOCHS_XRES int "bochs vga xres" default 800 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS config DRIVERS_EMULATION_QEMU_BOCHS_YRES int "bochs vga yres" default 600 depends on LINEAR_FRAMEBUFFER - depends on DRIVERS_EMULATION_QEMU_BOCHS + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT + +endif diff --git a/src/drivers/xgi/z9s/Kconfig b/src/drivers/xgi/z9s/Kconfig index b8000c1..98ad1a1 100644 --- a/src/drivers/xgi/z9s/Kconfig +++ b/src/drivers/xgi/z9s/Kconfig @@ -1,3 +1,10 @@ config DRIVERS_XGI_Z9S bool select DRIVERS_XGI_Z79_COMMON + +if DRIVERS_XGI_Z9S + +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + +endif diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 2465966..69ac520 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -35,10 +35,6 @@ { /* For vboot, always honor VBOOT_WD_FLAG_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { - /* Must always select MUST_REQUEST_DISPLAY when using this - function. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - dead_code(); return vboot_get_working_data()->flags & VBOOT_WD_FLAG_DISPLAY_INIT; } diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 55e0978..b1e8bd8 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -32,6 +32,7 @@ select MAINBOARD_HAS_TPM1 config VBOOT + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_EC config MAINBOARD_DIR diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index b675f33..7437edc 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -17,7 +17,6 @@ bool select SOC_AMD_STONEYRIDGE_FT4 select ALWAYS_LOAD_OPROM - select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID @@ -101,6 +100,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_LID_SWITCH config VBOOT_VBNV_OFFSET diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index c383fa4..99d206c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -46,6 +46,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_FLASH config MAINBOARD_DIR diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 75f0f0a..6dc414f 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -30,6 +30,7 @@ select MISSING_BOARD_RESET config VBOOT + select VBOOT_FORCE_DISPLAY_INIT select VBOOT_VBNV_EC config MAINBOARD_DIR diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index c3d2482..d3b7a9b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -51,4 +51,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 3678cb8..9937e99 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -44,7 +44,7 @@ and back to the RW region after the binary is done. config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK config VGA_BIOS_ID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index b151e8f..4a7b2a8 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -90,4 +90,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_DO_NATIVE_VGA_INIT + endif diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 02b6e80..2b3b2a1 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -54,4 +54,7 @@ hex default 0x10000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 37959dd..bf5cafa 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -50,4 +50,7 @@ hex default 0x80000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 53725ca..d7810c8 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -26,6 +26,7 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT select VBOOT_STARTS_IN_ROMSTAGE config USE_NATIVE_RAMINIT diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index ce43936..703e2133 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -51,4 +51,7 @@ hex default 0x100000 +config VBOOT + select VBOOT_FORCE_DISPLAY_INIT if MAINBOARD_USE_LIBGFXINIT + endif diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index ea1f738..7c06ce5 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -154,15 +154,15 @@ reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms. -config VBOOT_MUST_REQUEST_DISPLAY - bool - default y if VGA_ROM_RUN - default n +config VBOOT_FORCE_DISPLAY_INIT + bool "Force display initialization" + default y if !CHROMEOS help - Set this option to indicate to vboot that this platform will skip its - display initialization on a normal (non-recovery, non-developer) boot. - Unless display is specifically requested, the video option ROM is not - loaded, and any other native display initialization code is not run. + Set this option to indicate to vboot that display initialization shall + always be performed, even on a normal (non-recovery, non-developer) + boot. Without this option, unless display is specifically requested, + the video option ROM is not loaded, and any other native display + initialization code is not run. config VBOOT_HAS_REC_HASH_SPACE bool diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2468f5f..165facc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -359,7 +359,7 @@ ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Mainboard/SoC always initializes display. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + if (CONFIG(VBOOT_FORCE_DISPLAY_INIT)) ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; /* Do early init (set up secdata and NVRAM, load GBB) */ diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index cf3d244..796d406 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -117,7 +117,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4b816a2..2a576ce 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -42,7 +42,6 @@ select CPU_HAS_L2_ENABLE_MSR config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config BOOTBLOCK_CPU_INIT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7887156..6afaf9b 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -63,7 +63,6 @@ default 0x8000 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE config MMCONF_BASE_ADDRESS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bf6b78c..bfe9519 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -81,7 +81,6 @@ and back to the RW region after the binary is done. config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK config MMCONF_BASE_ADDRESS diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..77f589e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -244,7 +244,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 99000bb..e43feb1 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -156,7 +156,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..e253596 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -108,7 +108,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 6476d42..958d41f 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -14,7 +14,6 @@ if SOC_MEDIATEK_MT8173 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index c60cdea..dd710a8 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -12,7 +12,6 @@ if SOC_MEDIATEK_MT8183 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index c962aea..cc06486 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -16,7 +16,6 @@ if SOC_NVIDIA_TEGRA124 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 0e1efd7..1c99bd6 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -16,7 +16,6 @@ config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index dbe025e..e2eadbb 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -15,7 +15,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK config SDM845_QSPI diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3aebab9..01c3f95 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -33,7 +33,6 @@ if SOC_ROCKCHIP_RK3288 config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 7e3c44b..0424664 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -17,7 +17,6 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK config PMIC_BUS -- To view, visit https://review.coreboot.org/c/coreboot/+/34622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52288b0d5f33cd11d84e609e039dc4ea16ff7bdf Gerrit-Change-Number: 34622 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] intel/skylake: Implement PCIe RP devicetree update based on DID
by Nico Huber (Code Review) 16 Nov '19

16 Nov '19

Hello Arthur Heymans, Michael Niewöhner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35985 to review the following change. Change subject: [WIP] intel/skylake: Implement PCIe RP devicetree update based on DID ...................................................................... [WIP] intel/skylake: Implement PCIe RP devicetree update based on DID Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip_fsp20.c A src/soc/intel/skylake/include/soc/pcie_rp.h A src/soc/intel/skylake/pcie_rp.c 4 files changed, 159 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35985/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..691bdbc 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 55fedd3..83e3be5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -15,13 +15,10 @@ #include <bootmode.h> #include <bootstate.h> -#include <device/pci.h> #include <fsp/api.h> #include <arch/acpi.h> -#include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> -#include <device/pci_ids.h> #include <fsp/util.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> @@ -37,135 +34,13 @@ #include <soc/irq.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie_rp.h> #include <soc/ramstage.h> #include <soc/systemagent.h> #include <string.h> #include "chip.h" -struct pcie_entry { - unsigned int devfn; - unsigned int func_count; -}; - -/* - * According to table 2-2 in doc#546717: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA110 - 0xA117 - * D29:[F0 - F7] 0xA118 - 0xA11F - * D27:[F0 - F3] 0xA167 - 0xA16A - */ -static const struct pcie_entry pcie_table_skl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 4}, -}; - -/* - * According to table 2-2 in doc#564464: - * PCI bus[function] ID - * D28:[F0 - F7] 0xA290 - 0xA297 - * D29:[F0 - F7] 0xA298 - 0xA29F - * D27:[F0 - F7] 0xA2E7 - 0xA2EE - */ -static const struct pcie_entry pcie_table_kbl_pch_h[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 8}, - {PCH_DEVFN_PCIE17, 8}, -}; - -/* - * According to table 2-2 in doc#567995/545659: - * PCI bus[function] ID - * D28:[F0 - F7] 0x9D10 - 0x9D17 - * D29:[F0 - F3] 0x9D18 - 0x9D1B - */ -static const struct pcie_entry pcie_table_skl_pch_lp[] = { - {PCH_DEVFN_PCIE1, 8}, - {PCH_DEVFN_PCIE9, 4}, -}; - -/* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. - */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) -{ - struct device *func0; - unsigned int devfn, devfn0; - int i, group; - unsigned int inc = PCI_DEVFN(0, 1); - - for (group = 0; group < pci_groups; group++) { - devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); - if (func0 == NULL) - continue; - - /* No more functions if function 0 is disabled. */ - if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) - continue; - - devfn = devfn0 + inc; - - /* - * Increase function by 1. - * Then find first enabled device to replace func0 - * as that port was move to func0. - */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); - if (dev == NULL || !dev->enabled) - continue; - - /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); - func0->path.pci.devfn = dev->path.pci.devfn; - dev->path.pci.devfn = devfn0; - break; - } - } -} - -static void pcie_override_devicetree_after_silicon_init(void) -{ - uint16_t id, id_mask; - - id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); - /* - * We may read an ID other than func 0 after FSP-S. - * Strip out 4 least significant bits. - */ - id_mask = id & ~0xf; - printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); - if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_lp[0], - ARRAY_SIZE(pcie_table_skl_pch_lp)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "KBL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_kbl_pch_h[0], - ARRAY_SIZE(pcie_table_kbl_pch_h)); - } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { - printk(BIOS_INFO, "SKL PCH-H SKU\n"); - pcie_update_device_tree(&pcie_table_skl_pch_h[0], - ARRAY_SIZE(pcie_table_skl_pch_h)); - } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); - return; - } -} - void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a @@ -179,7 +54,7 @@ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* swap enabled PCI ports in device tree if needed */ - pcie_override_devicetree_after_silicon_init(); + pcie_rp_update_devicetree(); } void soc_fsp_load(void) diff --git a/src/soc/intel/skylake/include/soc/pcie_rp.h b/src/soc/intel/skylake/include/soc/pcie_rp.h new file mode 100644 index 0000000..2bc7095 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/pcie_rp.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_SKYLAKE_PCIE_RP_H +#define SOC_INTEL_SKYLAKE_PCIE_RP_H + +void pcie_rp_update_devicetree(void); + +#endif /* SOC_INTEL_SKYLAKE_PCIE_RP_H */ diff --git a/src/soc/intel/skylake/pcie_rp.c b/src/soc/intel/skylake/pcie_rp.c new file mode 100644 index 0000000..5882dea --- /dev/null +++ b/src/soc/intel/skylake/pcie_rp.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> + +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> +#include <soc/pcie_rp.h> + +/* negative if disabled, new function number otherwise */ +static int pcie_rp_fn_mapping[24]; + +/* The original DEVFN in the `devicetree.cb` is supposed to map directly to RPx. */ +static int pcie_rp_idx_from_devfn(const struct device *const dev) +{ + int rp_idx = PCI_FUNC(dev->path.pci.devfn); + switch (PCI_SLOT(dev->path.pci.devfn)) { + case 0x1c: + break; + case 0x1d: + rp_idx += 8; + break; + case 0x1b: + rp_idx += 16; + break; + default: + printk(BIOS_WARNING, + "Unexpected DEVFN for PCIe Root Port: %s.\n", + dev_path(dev)); + rp_idx = -1; + } + + return rp_idx; +} + +/* Check which RP (identified by its DID) has the given DEVFN assigned now. */ +static int pcie_rp_idx_from_did(const pci_devfn_t dev) +{ + unsigned int rp_idx; + + const uint16_t did = pci_s_read_config16(dev, PCI_DEVICE_ID); + + switch (did & ~0xf) { + case PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1: /* Fall through. */ + case PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1: /* Fall through. */ + case PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1: + rp_idx = did & 0xf; + break; + /* DIDs in the third groups on PCH-H are not aligned: */ + case PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17: + rp_idx = 16 + did - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17; + break; + case PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17: + rp_idx = 16 + did - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17; + break; + default: + printk(BIOS_WARNING, + "Unexpected DID for PCIe Root Port %02x.%x: %04x.\n", + PCI_SLOT(PCI_DEV2DEVFN(dev)), PCI_FUNC(PCI_DEV2DEVFN(dev)), did); + /* Fall through. */ + case 0xffff: + rp_idx = -1; + } + + return rp_idx; +} + +static void pcie_rp_register_group(const unsigned int devnum) +{ + unsigned int fn; + + /* Reconstruct current mapping */ + for (fn = 0; fn < 7; ++fn) { + const int rp_idx = pcie_rp_idx_from_did(PCI_DEV(0, devnum, fn)); + if (rp_idx < 0) { + if (fn == 0) + break; + else + continue; + } + pcie_rp_fn_mapping[rp_idx] = fn; + } +} + +static void pcie_rp_update_dev(struct device *const dev) +{ + const int rp_idx = pcie_rp_idx_from_devfn(dev); + if (rp_idx < 0) + return; + + const int fn = pcie_rp_fn_mapping[rp_idx]; + if (fn < 0) + dev->enabled = 0; + else + dev->path.pci.devfn = PCI_DEVFN(PCI_SLOT(dev->path.pci.devfn), fn); +} + +void pcie_rp_update_devicetree(void) +{ + const struct bus *const root = pci_root_bus(); + if (!root) + return; + + pcie_rp_register_group(0x1c); + pcie_rp_register_group(0x1d); + if (CONFIG(SKYLAKE_SOC_PCH_H)) + pcie_rp_register_group(0x1b); + + struct device *dev; + for (dev = root->children; dev; dev = dev->sibling) { + if (dev->path.type != DEVICE_PATH_PCI) + continue; + + if (PCI_SLOT(dev->path.pci.devfn) != 0x1c && + PCI_SLOT(dev->path.pci.devfn) != 0x1d && + (!CONFIG(SKYLAKE_SOC_PCH_H) || PCI_SLOT(dev->path.pci.devfn) != 0x1b)) + continue; + + pcie_rp_update_dev(dev); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Gerrit-Change-Number: 35985 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-MessageType: newchange

7 92

Change in coreboot[master]: sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbol
by Arthur Heymans (Code Review) 16 Nov '19

16 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36438 ) Change subject: sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbol ...................................................................... sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbol All code in southbridge/intel/common is now properly guarded by a Kconfig symbol, making SOUTHBRIDGE_INTEL_COMMON obsolete. Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_rangeley/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 13 files changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36438/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b118636..5856ef1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -18,7 +18,6 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 8f682ff..dc01092 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,7 +12,6 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 4a56005..f561fe5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -24,7 +24,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 5674c2f..f44145b 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,17 +1,12 @@ -config SOUTHBRIDGE_INTEL_COMMON - def_bool n - config SOUTHBRIDGE_INTEL_COMMON_RESET def_bool n select HAVE_CF9_RESET config SOUTHBRIDGE_INTEL_COMMON_RTC def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON config SOUTHBRIDGE_INTEL_COMMON_PMCLIB def_bool n - depends on SOUTHBRIDGE_INTEL_COMMON depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_PMBASE @@ -86,7 +81,6 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool - depends on SOUTHBRIDGE_INTEL_COMMON depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE if SOUTHBRIDGE_INTEL_COMMON_FINALIZE diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index d8091f7..68e423a 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,8 +25,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) - all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE) += pmbase.c @@ -54,5 +52,3 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c - -endif diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index a25c430..56c02b5 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -29,7 +29,6 @@ select PCIEXP_COMMON_CLOCK select SPI_FLASH select INTEL_DESCRIPTOR_MODE_CAPABLE - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f725926..f5b5f4e 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 7cf7b97..916560a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -20,7 +20,6 @@ select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 37b5e6d..b0cdfd4 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index f1bfcfc..9f821ae 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801IX bool - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 7a49e57..eeb843e 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_INTEL_I82801JX bool - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 99fc2cd..9976cb1 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -27,7 +27,6 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ac2a8f7..95b9f62 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -21,7 +21,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT -- To view, visit https://review.coreboot.org/c/coreboot/+/36438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e Gerrit-Change-Number: 36438 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in em100[master]: em100: Detect emulated flash chip
by Patrick Rudolph (Code Review) 15 Nov '19

15 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/35947 ) Change subject: em100: Detect emulated flash chip ...................................................................... em100: Detect emulated flash chip It's not clear why uploads (EM100 to host) generate a 64MiB ROM file. It turns out that the flash chip needs to be specified at the command line, which isn't intentional. Detect the currently emulated SPI and use the size as defined in flashchips. Tested on EM100Pro, will now upload ROM files matching the currently emulated target even without specifying the flash chip on the command line. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Ia3fb3034a195313b8d3bb4ce24dc1779058fd08f --- M em100.c 1 file changed, 56 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/47/35947/1 diff --git a/em100.c b/em100.c index 1548450..a20dc7d 100644 --- a/em100.c +++ b/em100.c @@ -567,6 +567,51 @@ return !result; } +static int get_chip_init_val(const chipdesc *desc, + const uint8_t reg1, + const uint8_t reg2, + uint16_t *out) +{ + int i; + for (i = 0; i < desc->init_len; i++) { + if (desc->init[i][0] == reg1 && desc->init[i][1] == reg2) { + *out = (desc->init[i][2] << 8) | desc->init[i][3]; + return 1; + } + } + return 0; +} + +static int get_chip_type(struct em100 *em100, const chipdesc **out) +{ + uint16_t manu; + uint16_t vend; + + /* Read manufacturer and vendor id from FPGA */ + if (!read_fpga_register(em100, 0x42, &manu)) + return 1; + if (!read_fpga_register(em100, 0x40, &vend)) + return 1; + + const chipdesc *chip = chips; + do { + uint16_t comp; + if (!get_chip_init_val(chip, 0x23, 0x40, &comp) || vend != comp) + continue; + if (!get_chip_init_val(chip, 0x23, 0x42, &comp) || manu != comp) + continue; + + break; + } while ((++chip)->name); + if (!chip->name) + return 1; + + printf("Configured to emulate %s\n", chip->name); + *out = chip; + + return 0; +} + static const struct option longopts[] = { {"set", 1, 0, 'c'}, {"download", 1, 0, 'd'}, @@ -822,8 +867,17 @@ } if (read_filename) { - /* largest size - 64MB */ - int maxlen = desiredchip ? chip->size : 0x4000000; + int maxlen = 0x4000000; /* largest size - 64MB */ + + if (!desiredchip) { + /* Read configured SPI emulation from EM100 */ + const chipdesc *current; + if (!get_chip_type(&em100, &current)) + maxlen = current->size; + } else { + maxlen = chip->size; + } + void *data = malloc(maxlen); if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); -- To view, visit https://review.coreboot.org/c/em100/+/35947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ia3fb3034a195313b8d3bb4ce24dc1779058fd08f Gerrit-Change-Number: 35947 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mainboard/facebook/fbg1701: Add IFD and ME binary
by Frans Hendriks (Code Review) 15 Nov '19

15 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34448 ) Change subject: mainboard/facebook/fbg1701: Add IFD and ME binary ...................................................................... mainboard/facebook/fbg1701: Add IFD and ME binary Use IFD and ME binary to generate complete SPI image BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34448/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 95d8f6c..dce315e 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -19,6 +19,8 @@ def_bool y select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES + select HAVE_IFD_BIN + select HAVE_ME_BIN select HAVE_OPTION_TABLE select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 @@ -94,4 +96,12 @@ hex "C Bootblock Size" default 0x4000 +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + endif # BOARD_FACEBOOK_FBG1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/34448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db Gerrit-Change-Number: 34448 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME
by Frans Hendriks (Code Review) 15 Nov '19

15 Nov '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34442 ) Change subject: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME ...................................................................... 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME Upgrade to blobs version with descriptor and Intel ME binary BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34442/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd..c7dc4f2 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit c7dc4f25229fd3c022afdb410264b02f292ddca6 -- To view, visit https://review.coreboot.org/c/coreboot/+/34442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c Gerrit-Change-Number: 34442 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: vboot: use vboot persistent context
by Joel Kitching (Code Review) 15 Nov '19

15 Nov '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36300 ) Change subject: vboot: use vboot persistent context ...................................................................... vboot: use vboot persistent context vb2_context object is now stored on the workbuf as part of vb2_shared_data. Use vboot's new API functions vb2api_init and vb2api_reinit to create and restore the context object respectively. BUG=b:124141368, chromium:994060 TEST=Build locally BRANCH=none Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa Signed-off-by: Joel Kitching <kitching(a)google.com> --- M 3rdparty/blobs M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/security/vboot/bootmode.c M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/vboot_logic.c 7 files changed, 64 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36300/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 62aa0e0..678b4c4 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04 +Subproject commit 678b4c4a81069bb6e10e2e59f5374b83d727cd2b diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index 0eb311b..00571ed 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -95,8 +95,8 @@ * and the value from the TPM would be wrong anyway since the verstage * read would have cleared the value on the TPM. * - * The TPM recovery request is passed between stages through the - * vboot_get_shared_data or cbmem depending on stage. + * The TPM recovery request is passed between stages through vboot data + * or cbmem depending on stage. */ if (ENV_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 6643d9b..bdd414c 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -93,8 +93,8 @@ * and the value from the TPM would be wrong anyway since the verstage * read would have cleared the value on the TPM. * - * The TPM recovery request is passed between stages through the - * vboot_get_shared_data or cbmem depending on stage. + * The TPM recovery request is passed between stages through vboot data + * or cbmem depending on stage. */ if (ENV_VERSTAGE && tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS && diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 4625bcd..25650b4 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -26,7 +26,8 @@ static int vboot_get_recovery_reason_shared_data(void) { - struct vb2_shared_data *sd = vboot_get_shared_data(); + struct vb2_shared_data *sd = + (struct vb2_shared_data *)vboot_get_workbuf(); assert(sd); return sd->recovery_reason; } diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 626fbc5..421c7a7 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -40,40 +40,40 @@ return wd; } -void vboot_init_work_context(struct vb2_context *ctx) +struct vb2_context *vboot_get_context(void) { + static struct vb2_context *ctx; struct vboot_working_data *wd; - /* First initialize the working data region. */ + /* Return if context has already been restored / initialized. */ + if (ctx) + return ctx; + wd = vboot_get_working_data(); - memset(wd, 0, VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE); + + /* Restore context from a previous stage. */ + if (wd->buffer_offset == ALIGN_UP(sizeof(*wd), 16)) { + assert(vb2api_reinit(vboot_get_workbuf(), &ctx)); + return ctx; + } /* * vboot prefers 16-byte alignment. This takes away 16 bytes * from the VBOOT2_WORK region, but the vboot devs said that's okay. */ + memset(wd, 0, sizeof(*wd)); wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); wd->buffer_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - wd->buffer_offset; - /* Initialize the vb2_context. */ - memset(ctx, 0, sizeof(*ctx)); - ctx->workbuf = (void *)vboot_get_shared_data(); - ctx->workbuf_size = wd->buffer_size; + /* Initialize vb2_shared_data and friends. */ + assert(vb2api_init(vboot_get_workbuf(), wd->buffer_size, &ctx) + == VB2_SUCCESS); + + return ctx; } -void vboot_finalize_work_context(struct vb2_context *ctx) -{ - /* - * Shrink buffer_size so that vboot_migrate_cbmem knows how - * much of vboot_working_data needs to be copied into CBMEM - * (if applicable), and so that downstream users know how much - * of the workbuf is currently used. - */ - vboot_get_working_data()->buffer_size = ctx->workbuf_used; -} - -struct vb2_shared_data *vboot_get_shared_data(void) +void *vboot_get_workbuf(void) { struct vboot_working_data *wd = vboot_get_working_data(); return (void *)((uintptr_t)wd + wd->buffer_offset); @@ -128,7 +128,8 @@ { const struct vboot_working_data *wd_preram = (struct vboot_working_data *)_vboot2_work; - size_t cbmem_size = wd_preram->buffer_offset + wd_preram->buffer_size; + /* TODO: We don't know the workbuf size with the current API... */ + size_t cbmem_size = VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE; struct vboot_working_data *wd_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wd_cbmem != NULL); diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 1458354..c64214b 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -54,9 +54,8 @@ * Source: security/vboot/common.c */ struct vboot_working_data *vboot_get_working_data(void); -void vboot_init_work_context(struct vb2_context *ctx); -void vboot_finalize_work_context(struct vb2_context *ctx); -struct vb2_shared_data *vboot_get_shared_data(void); +struct vb2_context *vboot_get_context(void); +void *vboot_get_workbuf(void); /* Returns 0 on success. < 0 on failure. */ int vboot_get_selected_region(struct region *region); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index da6231a..5110147 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -319,17 +319,17 @@ */ void verstage_main(void) { - struct vb2_context ctx; + struct vb2_context *ctx; struct region_device fw_main; vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); /* Set up context and work buffer */ - vboot_init_work_context(&ctx); + ctx = vboot_get_context(); /* Initialize and read nvdata from non-volatile storage. */ - vbnv_init(ctx.nvdata); + vbnv_init(ctx->nvdata); /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform @@ -337,51 +337,51 @@ * the same slot that it booted from. */ if (CONFIG(RESUME_PATH_SAME_AS_BOOT) && vboot_platform_is_resuming()) - ctx.flags |= VB2_CONTEXT_S3_RESUME; + ctx->flags |= VB2_CONTEXT_S3_RESUME; /* Read secdata from TPM. Initialize TPM if secdata not found. We don't * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ timestamp_add_now(TS_START_TPMINIT); - if (vboot_setup_tpm(&ctx) == TPM_SUCCESS) - antirollback_read_space_firmware(&ctx); + if (vboot_setup_tpm(ctx) == TPM_SUCCESS) + antirollback_read_space_firmware(ctx); timestamp_add_now(TS_END_TPMINIT); /* Enable measured boot mode */ if (CONFIG(VBOOT_MEASURED_BOOT) && - !(ctx.flags & VB2_CONTEXT_S3_RESUME)) { + !(ctx->flags & VB2_CONTEXT_S3_RESUME)) { if (vboot_init_crtm() != VB2_SUCCESS) die_with_post_code(POST_INVALID_ROM, "Initializing measured boot mode failed!"); } if (get_recovery_mode_switch()) { - ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY)) - ctx.flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; + ctx->flags |= VB2_CONTEXT_DISABLE_DEVELOPER_MODE; } if (CONFIG(VBOOT_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch()) - ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE; + ctx->flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE; if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) - ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + ctx->flags |= VB2_CONTEXT_NOFAIL_BOOT; /* Mainboard/SoC always initializes display. */ if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; + ctx->flags |= VB2_CONTEXT_DISPLAY_INIT; /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); - rv = vb2api_fw_phase1(&ctx); + rv = vb2api_fw_phase1(ctx); /* Jot down some information from vboot which may be required later on in coreboot boot flow. */ - if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + if (ctx->flags & VB2_CONTEXT_DISPLAY_INIT) /* Mainboard/SoC should initialize display. */ vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; - if (ctx.flags & VB2_CONTEXT_DEVELOPER_MODE) + if (ctx->flags & VB2_CONTEXT_DEVELOPER_MODE) vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DEVELOPER_MODE; if (rv) { @@ -393,58 +393,58 @@ */ if (rv == VB2_ERROR_API_PHASE1_RECOVERY) { printk(BIOS_INFO, "Recovery requested (%x)\n", rv); - save_if_needed(&ctx); - extend_pcrs(&ctx); /* ignore failures */ + save_if_needed(ctx); + extend_pcrs(ctx); /* ignore failures */ goto verstage_main_exit; } printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); - rv = vb2api_fw_phase2(&ctx); + rv = vb2api_fw_phase2(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } /* Try that slot (verify its keyblock and preamble) */ printk(BIOS_INFO, "Phase 3\n"); timestamp_add_now(TS_START_VERIFY_SLOT); - rv = vb2api_fw_phase3(&ctx); + rv = vb2api_fw_phase3(ctx); timestamp_add_now(TS_END_VERIFY_SLOT); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } printk(BIOS_INFO, "Phase 4\n"); - rv = locate_firmware(&ctx, &fw_main); + rv = locate_firmware(ctx, &fw_main); if (rv) die_with_post_code(POST_INVALID_ROM, "Failed to read FMAP to locate firmware"); - rv = hash_body(&ctx, &fw_main); - save_if_needed(&ctx); + rv = hash_body(ctx, &fw_main); + save_if_needed(ctx); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); vboot_reboot(); } /* Only extend PCRs once on boot. */ - if (!(ctx.flags & VB2_CONTEXT_S3_RESUME)) { + if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) { timestamp_add_now(TS_START_TPMPCR); - rv = extend_pcrs(&ctx); + rv = extend_pcrs(ctx); if (rv) { printk(BIOS_WARNING, "Failed to extend TPM PCRs (%#x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); - save_if_needed(&ctx); + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_U_ERROR, rv); + save_if_needed(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMPCR); @@ -456,8 +456,8 @@ rv = antirollback_lock_space_firmware(); if (rv) { printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); - save_if_needed(&ctx); + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); + save_if_needed(ctx); vboot_reboot(); } timestamp_add_now(TS_END_TPMLOCK); @@ -468,14 +468,14 @@ if (rv) { printk(BIOS_INFO, "Failed to lock rec hash space(%x)\n", rv); - vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, + vb2api_fail(ctx, VB2_RECOVERY_RO_TPM_REC_HASH_L_ERROR, 0); - save_if_needed(&ctx); + save_if_needed(ctx); vboot_reboot(); } } - printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B'); + printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(ctx) ? 'A' : 'B'); vboot_set_selected_region(region_device_region(&fw_main)); verstage_main_exit: @@ -487,6 +487,5 @@ /* Save recovery reason in case of unexpected reboots on x86. */ vboot_save_recovery_reason_vbnv(); - vboot_finalize_work_context(&ctx); timestamp_add_now(TS_END_VBOOT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I051be1e47bf79b15a1689d49a5d4c031e9363dfa Gerrit-Change-Number: 36300 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

7 49

Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [WIP] Documentation: PCI resource allocations
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36493 ) Change subject: [WIP] Documentation: PCI resource allocations ...................................................................... [WIP] Documentation: PCI resource allocations Change-Id: I5479c4a60c3d8c7545759c0f48aa9f5d628d65f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A Documentation/device/pci_resource.md 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36493/1 diff --git a/Documentation/device/pci_resource.md b/Documentation/device/pci_resource.md new file mode 100644 index 0000000..0fa2a51 --- /dev/null +++ b/Documentation/device/pci_resource.md @@ -0,0 +1,26 @@ +PCI resource allocation rules +============================= + +Definition: To opt-out from PCI resource allocation for a specific PCI device is to enter payload with the *PCI COMMAND* register having a defined state where *IO* and *MEMORY* spaces and *BUS_MASTER* bits are cleared, while all the *PCI standard BARs* are in an undefined state. + +1. #### Rule A +PCI devices that do not bind to PCI drivers can always implicitly opt-out, because PCI subsystem code itself will not address register banks or buffers behind standard BARs. + +1. Most external/add-on PCIe devices located behind PCIe bridges will hit `Rule A`. This includes the troublesome PCIe graphics with large *PREFMEM* resources. + +1. With the recursive nature of how *.read_resources* already works, upstream PCIe bridges will implicitly opt-out in the case all the secondary side devices have opted-out. + +1. Within PCI drivers, *.init* is the only callback where resource assignment may be required. + +1. #### Rule B +For cases where *.init* is not implemented at all, we can implicitly opt-out. + +1. #### Rule C +If .init does not call any *find_resource()*, we can explicitly opt-out by using alternative *.read_resources()* implementation with a conditional *MINIMAL_PCI_RESOURCES* check in it. + +1. #### Rule D +If *.init* does call *find_resource()*, it's likely for the reason that it does configurations that are dependent of either some *KConfig* option or *devicetree.cb*. Or it could be a static chipset configuration that is not easy to delay to payload. These devices can rarely opt-out, but it could be done explicitly using custom *.read_resources* like *Rule C*. + +1. Platforms with blobbed chipset initialisation would currently likely hit *Rule C*, but it might be possible to have them hit *Rule B* instead. + +1. If choice of payload is capable of completing the resource allocation, possibly extending to 64-bit MMIO space, it may be desirable to leave as many resources as possible unallocated and potentially even unallocate the ones that had been assigned. -- To view, visit https://review.coreboot.org/c/coreboot/+/36493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5479c4a60c3d8c7545759c0f48aa9f5d628d65f3 Gerrit-Change-Number: 36493 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019