coreboot-gerrit October 2019

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Change in coreboot[master]: mainboard/amd: Remove AMD Torpedo mainboard
by Name of user not set (Code Review) 20 Nov '19

20 Nov '19

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36173 ) Change subject: mainboard/amd: Remove AMD Torpedo mainboard ...................................................................... mainboard/amd: Remove AMD Torpedo mainboard This also permits removal of vc/amd/agesa/f12, as it was the only mainboard using it. That will in turn allow resolving some unique Coverity issues reported against that source. Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> --- D src/mainboard/amd/torpedo/BiosCallOuts.c D src/mainboard/amd/torpedo/Kconfig D src/mainboard/amd/torpedo/Kconfig.name D src/mainboard/amd/torpedo/Makefile.inc D src/mainboard/amd/torpedo/Oem.h D src/mainboard/amd/torpedo/OemCustomize.c D src/mainboard/amd/torpedo/OptionsIds.h D src/mainboard/amd/torpedo/acpi/ide.asl D src/mainboard/amd/torpedo/acpi/routing.asl D src/mainboard/amd/torpedo/acpi/sata.asl D src/mainboard/amd/torpedo/acpi/usb.asl D src/mainboard/amd/torpedo/acpi_tables.c D src/mainboard/amd/torpedo/board_info.txt D src/mainboard/amd/torpedo/buildOpts.c D src/mainboard/amd/torpedo/cmos.layout D src/mainboard/amd/torpedo/devicetree.cb D src/mainboard/amd/torpedo/dsdt.asl D src/mainboard/amd/torpedo/fadt.c D src/mainboard/amd/torpedo/gpio.c D src/mainboard/amd/torpedo/gpio.h D src/mainboard/amd/torpedo/irq_tables.c D src/mainboard/amd/torpedo/mainboard.c D src/mainboard/amd/torpedo/mptable.c D src/mainboard/amd/torpedo/platform_cfg.h D src/mainboard/amd/torpedo/pmio.h D src/mainboard/amd/torpedo/romstage.c 26 files changed, 0 insertions(+), 7,601 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/36173/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f570f01fcb5ba0e306508a569ea97f432596b3 Gerrit-Change-Number: 36173 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: Remove MIPS architecture
by Julius Werner (Code Review) 20 Nov '19

20 Nov '19

Hello Hung-Te Lin, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34919 to review the following change. Change subject: Remove MIPS architecture ...................................................................... Remove MIPS architecture The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code, MIPS-speicfic hacks and any board and SoC code depending on it. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M .gitignore M Documentation/contributing/project_ideas.md M Documentation/util.md M MAINTAINERS M Makefile.inc M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc D payloads/libpayload/arch/mips/Kconfig D payloads/libpayload/arch/mips/Makefile.inc D payloads/libpayload/arch/mips/cache.c D payloads/libpayload/arch/mips/coreboot.c D payloads/libpayload/arch/mips/dummy_media.c D payloads/libpayload/arch/mips/exception.c D payloads/libpayload/arch/mips/exception_asm.S D payloads/libpayload/arch/mips/gdb.c D payloads/libpayload/arch/mips/head.S D payloads/libpayload/arch/mips/libpayload.ldscript D payloads/libpayload/arch/mips/main.c D payloads/libpayload/arch/mips/selfboot.c D payloads/libpayload/arch/mips/string.c D payloads/libpayload/arch/mips/sysinfo.c D payloads/libpayload/arch/mips/timer.c D payloads/libpayload/arch/mips/util.S M payloads/libpayload/bin/lpgcc D payloads/libpayload/configs/defconfig-mips M payloads/libpayload/drivers/Makefile.inc M payloads/libpayload/drivers/timer/Kconfig D payloads/libpayload/drivers/timer/img_pistachio.c D payloads/libpayload/include/mips/arch/byteorder.h D payloads/libpayload/include/mips/arch/cache.h D payloads/libpayload/include/mips/arch/cpu.h D payloads/libpayload/include/mips/arch/exception.h D payloads/libpayload/include/mips/arch/io.h D payloads/libpayload/include/mips/arch/stdint.h D payloads/libpayload/include/mips/arch/types.h D payloads/libpayload/include/mips/arch/virtual.h D payloads/libpayload/libc/64bit_div.c M payloads/libpayload/libc/Makefile.inc M payloads/libpayload/sample/Makefile D src/arch/mips/Kconfig D src/arch/mips/Makefile.inc D src/arch/mips/ashldi3.c D src/arch/mips/boot.c D src/arch/mips/bootblock.S D src/arch/mips/bootblock_simple.c D src/arch/mips/cache.c D src/arch/mips/include/arch/bootblock_common.h D src/arch/mips/include/arch/byteorder.h D src/arch/mips/include/arch/cache.h D src/arch/mips/include/arch/cbconfig.h D src/arch/mips/include/arch/cpu.h D src/arch/mips/include/arch/early_variables.h D src/arch/mips/include/arch/exception.h D src/arch/mips/include/arch/header.ld D src/arch/mips/include/arch/hlt.h D src/arch/mips/include/arch/memlayout.h D src/arch/mips/include/arch/mmio.h D src/arch/mips/include/arch/mmu.h D src/arch/mips/include/arch/pci_ops.h D src/arch/mips/include/arch/stages.h D src/arch/mips/include/arch/types.h D src/arch/mips/mmu.c D src/arch/mips/stages.c D src/arch/mips/tables.c M src/console/vtxprintf.c M src/cpu/Makefile.inc M src/drivers/spi/cbfs_spi.c M src/include/rules.h D src/mainboard/google/urara/Kconfig D src/mainboard/google/urara/Kconfig.name D src/mainboard/google/urara/Makefile.inc D src/mainboard/google/urara/board_info.txt D src/mainboard/google/urara/boardid.c D src/mainboard/google/urara/bootblock.c D src/mainboard/google/urara/chromeos.c D src/mainboard/google/urara/chromeos.fmd D src/mainboard/google/urara/devicetree.cb D src/mainboard/google/urara/mainboard.c D src/mainboard/google/urara/memlayout.ld D src/mainboard/google/urara/urara_boardid.h D src/soc/imgtec/Kconfig D src/soc/imgtec/pistachio/Kconfig D src/soc/imgtec/pistachio/Makefile.inc D src/soc/imgtec/pistachio/bootblock.c D src/soc/imgtec/pistachio/cbmem.c D src/soc/imgtec/pistachio/clocks.c D src/soc/imgtec/pistachio/ddr2_init.c D src/soc/imgtec/pistachio/ddr3_init.c D src/soc/imgtec/pistachio/include/soc/clocks.h D src/soc/imgtec/pistachio/include/soc/cpu.h D src/soc/imgtec/pistachio/include/soc/ddr_init.h D src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h D src/soc/imgtec/pistachio/include/soc/gpio.h D src/soc/imgtec/pistachio/include/soc/memlayout.ld D src/soc/imgtec/pistachio/include/soc/spi.h D src/soc/imgtec/pistachio/monotonic_timer.c D src/soc/imgtec/pistachio/reset.c D src/soc/imgtec/pistachio/romstage.c D src/soc/imgtec/pistachio/soc.c D src/soc/imgtec/pistachio/spi.c D src/soc/imgtec/pistachio/uart.c M src/vendorcode/google/chromeos/Makefile.inc M toolchain.inc M util/README.md D util/bimgtool/Makefile D util/bimgtool/bimgtool.c D util/bimgtool/description.md M util/cbfstool/cbfs.h M util/crossgcc/Makefile M util/crossgcc/Makefile.inc M util/crossgcc/README M util/crossgcc/buildgcc M util/docker/coreboot.org-status/board-status.html/tohtml.sh M util/release/genrelnotes M util/xcompile/xcompile 116 files changed, 15 insertions(+), 7,486 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/34919/1 diff --git a/.gitignore b/.gitignore index 6ce8cb7..77db961 100644 --- a/.gitignore +++ b/.gitignore @@ -84,7 +84,6 @@ util/*/.test util/amdfwtool/amdfwtool util/archive/archive -util/bimgtool/bimgtool util/bincfg/bincfg util/board_status/board-status util/bucts/bucts diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 21a756d..5bc4cac 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -64,7 +64,7 @@ ### Mentors * Timothy Pearson <tpearson(a)raptorengineering.com> -## Support QEMU AArch64 or MIPS +## Support QEMU AArch64 Having QEMU support for the architectures coreboot can boot helps with some (limited) compatibility testing: While QEMU generally doesn't need much hardware init, any CPU state changes in the boot flow will likely @@ -105,7 +105,7 @@ ### Mentors * Werner Zeh <werner.zeh(a)gmx.net> -## Port payloads to ARM, AArch64, MIPS or RISC-V +## Port payloads to ARM, AArch64 or RISC-V While we have a rather big set of payloads for x86 based platforms, all other architectures are rather limited. Improve the situation by porting a payload to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore, diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1..38a5329 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -11,9 +11,6 @@ platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` -* __bimgtool__ - A simple tool which generates and verifies boot images -in the BIMG format, used in systems designed by Imagination -Technologies, for example the Pistachio SoC. `C` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` `Yacc` * __board_status__ - Tools to collect logs and upload them to the board diff --git a/MAINTAINERS b/MAINTAINERS index 030ed7a..1ca2c7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -472,12 +472,6 @@ F: util/exynos/ F: util/ipqheader/ -MIPS ARCHITECTURE -F: src/arch/mips/ -F: src/cpu/mips/ -F: src/soc/imgtec/ -F: util/bimgtool/ - X86 ARCHITECTURE F: src/arch/x86/ F: src/cpu/x86/ diff --git a/Makefile.inc b/Makefile.inc index c275d1e..d46e45e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -479,7 +479,7 @@ additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ - $(objutil)/cbootimage $(objutil)/bimgtool + $(objutil)/cbootimage export $(COREBOOT_EXPORTS) @@ -572,11 +572,6 @@ subdirs-y += util/nvidia -BIMGTOOL:=$(objutil)/bimgtool/bimgtool -$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< - $(obj)/config.h: $(objutil)/kconfig/conf ####################################################################### diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 97b970b..d216f61 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -114,11 +114,6 @@ help Support the ARM64 architecture -config ARCH_MIPS - bool "MIPS" - help - Support the MIPS architecture - endchoice config MULTIBOOT @@ -147,12 +142,11 @@ hex "Base address" default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 - default 0x00000000 if ARCH_MIPS default 0x00100000 if ARCH_X86 help This is the base address for the payload. - If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS, + If unsure, set to 0x00100000 on x86, 0x04000000 on ARM or 0x80100000 on ARM64. endmenu @@ -452,5 +446,4 @@ source "arch/arm/Kconfig" source "arch/arm64/Kconfig" -source "arch/mips/Kconfig" source "arch/x86/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1..0121c27 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -95,7 +95,6 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 ARCH-y := $(ARCHDIR-y) @@ -105,7 +104,6 @@ ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips # Three cases where we don't need fully populated $(obj) lists: # 1. when no .config exists diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index f0aaa27..d4bfaff 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -33,7 +33,6 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install diff --git a/payloads/libpayload/arch/mips/Kconfig b/payloads/libpayload/arch/mips/Kconfig deleted file mode 100644 index b6e326b..0000000 --- a/payloads/libpayload/arch/mips/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# This file is part of the libpayload project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - - -if ARCH_MIPS - -config ARCH_SPECIFIC_OPTIONS # dummy - def_bool y - select LITTLE_ENDIAN - -endif diff --git a/payloads/libpayload/arch/mips/Makefile.inc b/payloads/libpayload/arch/mips/Makefile.inc deleted file mode 100644 index 2bd112f..0000000 --- a/payloads/libpayload/arch/mips/Makefile.inc +++ /dev/null @@ -1,33 +0,0 @@ -# -# This file is part of the libpayload project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -############################################################################### -CFLAGS += -march=mips32r2 -mxgot - -head.o-y += head.S - -libc-y += cache.c -libc-y += coreboot.c -libc-y += dummy_media.c -libc-y += exception_asm.S -libc-y += exception.c -libc-y += gdb.c -libc-y += main.c -libc-y += selfboot.c -libc-y += sysinfo.c -libc-y += string.c -libc-y += timer.c -libc-y += util.S diff --git a/payloads/libpayload/arch/mips/cache.c b/payloads/libpayload/arch/mips/cache.c deleted file mode 100644 index 4338415..0000000 --- a/payloads/libpayload/arch/mips/cache.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> - - -void dcache_clean_all(void) -{ - /* TODO */ -} - -void dcache_invalidate_all(void) -{ - /* TODO */ -} -void dcache_clean_invalidate_all(void) -{ - /* TODO */ -} - -void tlb_invalidate_all(void) -{ - /* TODO */ -} - -unsigned int dcache_line_bytes(void) -{ - /* TO DO */ - return 0; -} - -void dcache_mmu_disable(void) -{ - /* TODO */ -} - -void dcache_mmu_enable(void) -{ - /* TODO */ -} - -void cache_sync_instructions(void) -{ - /* TODO */ -} - -void mmu_init(void) -{ - /* TODO */ -} - -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) -{ - /* TODO */ -} -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy) -{ - /* TODO */ -} diff --git a/payloads/libpayload/arch/mips/coreboot.c b/payloads/libpayload/arch/mips/coreboot.c deleted file mode 100644 index e2b5557..0000000 --- a/payloads/libpayload/arch/mips/coreboot.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <libpayload-config.h> -#include <libpayload.h> -#include <coreboot_tables.h> - -/* This pointer gets set in head.S and is passed in from coreboot. */ -void *cb_header_ptr; - -static void cb_parse_dma(void *ptr) -{ - struct lb_range *dma = (struct lb_range *)ptr; - init_dma_memory(bus_to_virt(dma->range_start), dma->range_size); -} - -/* Architecture specific */ -int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) -{ - switch (rec->tag) { - case CB_TAG_DMA: - cb_parse_dma(rec); - break; - default: - return 0; - } - return 1; - -} - -int get_coreboot_info(struct sysinfo_t *info) -{ - return cb_parse_header(cb_header_ptr, 1, info); -} - -void *get_cb_header_ptr(void) -{ - return cb_header_ptr; -} diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c deleted file mode 100644 index 112d7fe..0000000 --- a/payloads/libpayload/arch/mips/dummy_media.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#define LIBPAYLOAD - -#include <cbfs.h> - -/* The generic cbfs code relies on the libpayload_init_default_cbfs_media - * symbol. Therefore, provide an implementation that just throws an error. */ - -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) -{ - return -1; -} diff --git a/payloads/libpayload/arch/mips/exception.c b/payloads/libpayload/arch/mips/exception.c deleted file mode 100644 index e488f2e..0000000 --- a/payloads/libpayload/arch/mips/exception.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/exception.h> -#include <exception.h> -#include <libpayload.h> -#include <stdint.h> - -u32 exception_stack[0x400] __attribute__((aligned(8))); -struct exception_state_t exception_state; - -static const char *names[EXC_COUNT] = { - [EXC_CACHE_ERROR] = "Cache error exception", - [EXC_TLB_REFILL_AND_ALL] = "TLB refill or general exception", - [EXC_INTERRUPT] = "Interrupt", - [EXC_EJTAG_DEBUG] = "EJTAG debug exception" -}; - -static void dump_exception_state(void) -{ - printf("%s exception!\n", names[exception_state_ptr->vector]); - printf("\nRegisters:\n"); - printf("ZERO:\t0x%08x\n", exception_state_ptr->regs.zero); - printf("AT:\t0x%08x\n", exception_state_ptr->regs.at); - printf("V0:\t0x%08x\n", exception_state_ptr->regs.v0); - printf("V1:\t0x%08x\n", exception_state_ptr->regs.v1); - printf("A0:\t0x%08x\n", exception_state_ptr->regs.a0); - printf("A1:\t0x%08x\n", exception_state_ptr->regs.a1); - printf("A2:\t0x%08x\n", exception_state_ptr->regs.a2); - printf("A3:\t0x%08x\n", exception_state_ptr->regs.a3); - printf("T0:\t0x%08x\n", exception_state_ptr->regs.t0); - printf("T1:\t0x%08x\n", exception_state_ptr->regs.t1); - printf("T2:\t0x%08x\n", exception_state_ptr->regs.t2); - printf("T3:\t0x%08x\n", exception_state_ptr->regs.t3); - printf("T4:\t0x%08x\n", exception_state_ptr->regs.t4); - printf("T5:\t0x%08x\n", exception_state_ptr->regs.t5); - printf("T6:\t0x%08x\n", exception_state_ptr->regs.t6); - printf("T7:\t0x%08x\n", exception_state_ptr->regs.t7); - printf("S0:\t0x%08x\n", exception_state_ptr->regs.s0); - printf("S1:\t0x%08x\n", exception_state_ptr->regs.s1); - printf("S2:\t0x%08x\n", exception_state_ptr->regs.s2); - printf("S3:\t0x%08x\n", exception_state_ptr->regs.s3); - printf("S4:\t0x%08x\n", exception_state_ptr->regs.s4); - printf("S5:\t0x%08x\n", exception_state_ptr->regs.s5); - printf("S6:\t0x%08x\n", exception_state_ptr->regs.s6); - printf("S7:\t0x%08x\n", exception_state_ptr->regs.s7); - printf("T8:\t0x%08x\n", exception_state_ptr->regs.t8); - printf("T9:\t0x%08x\n", exception_state_ptr->regs.t9); - printf("K0:\t0x%08x\n", exception_state_ptr->regs.k0); - printf("K1:\t0x%08x\n", exception_state_ptr->regs.k1); - printf("GP:\t0x%08x\n", exception_state_ptr->regs.gp); - printf("SP:\t0x%08x\n", exception_state_ptr->regs.sp); - printf("FP:\t0x%08x\n", exception_state_ptr->regs.fp); - printf("RA:\t0x%08x\n", exception_state_ptr->regs.ra); -} - -static void dump_stack(uintptr_t addr, size_t bytes) -{ - int i, j; - const int words_per_line = 8; - int words_to_print; - uint32_t *ptr = (uint32_t *) - (addr & ~(words_per_line * sizeof(*ptr) - 1)); - - printf("Dumping stack:\n"); - words_to_print = bytes/sizeof(*ptr); - for (i = words_to_print; i >= 0; i -= words_per_line) { - printf("%p: ", ptr + i); - for (j = i; j < i + words_per_line; j++) - printf("%08x ", *(ptr + j)); - printf("\n"); - } -} - - -void exception_dispatch(void) -{ - u32 vec = exception_state_ptr->vector; - die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u", vec); - - dump_exception_state(); - dump_stack(exception_state_ptr->regs.sp, 512); - halt(); -} - -void exception_init(void) -{ - exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack); - exception_state_ptr = &exception_state; - exception_init_asm(); -} diff --git a/payloads/libpayload/arch/mips/exception_asm.S b/payloads/libpayload/arch/mips/exception_asm.S deleted file mode 100644 index 118c12d..0000000 --- a/payloads/libpayload/arch/mips/exception_asm.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define STATUS_REGISTER $12,0 -#define BOOT_EXC_VECTOR_MASK (1 << 22) -#define EBASE_REGISTER $15,1 -#define EXCEPTION_BASE_MASK (0xFFFFF000) - - /* Don't reorder instructions */ - .set noreorder - .set noat - - .align 4 - .global exception_stack_end -exception_stack_end: - .word 0 - - .global exception_state_ptr -exception_state_ptr: - .word 0 - -/* Temporary variables. */ -ret_addr: - .word 0 -exception_sp: - .word 0 -vector: - .word 0 - -/* Cache error */ -.org 0x100 - li $v0, 0x0 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* TLB refill and all others */ -.org 0x180 - li $v0, 0x1 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* Interrupt */ -.org 0x200 - li $v0, 0x2 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -/* EJTAG debug exception */ -.org 0x480 - li $v0, 0x3 - la $at, vector - sw $v0, 0x00($at) - b exception_common - nop - -exception_common: - /* Obtain return address of exception */ - la $v0, ret_addr - sw $ra, 0x00($v0) - - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw $gp, 0($ra) - - la $at, exception_sp - sw $sp, 0x00($at) - lw $sp, exception_state_ptr - - /* Save all registers */ - sw $zero, 0x00($sp) - sw $at, 0x04($sp) - sw $v0, 0x08($sp) - sw $v1, 0x0C($sp) - sw $a0, 0x10($sp) - sw $a1, 0x14($sp) - sw $a2, 0x18($sp) - sw $a3, 0x1C($sp) - sw $t0, 0x20($sp) - sw $t1, 0x34($sp) - sw $t2, 0x28($sp) - sw $t3, 0x2C($sp) - sw $t4, 0x30($sp) - sw $t5, 0x34($sp) - sw $t6, 0x38($sp) - sw $t7, 0x3C($sp) - sw $s0, 0x40($sp) - sw $s1, 0x44($sp) - sw $s2, 0x48($sp) - sw $s3, 0x4C($sp) - sw $s4, 0x50($sp) - sw $s5, 0x54($sp) - sw $s6, 0x58($sp) - sw $s7, 0x5C($sp) - sw $t8, 0x60($sp) - sw $t9, 0x64($sp) - sw $k0, 0x68($sp) - sw $k1, 0x6C($sp) - sw $gp, 0x70($sp) - lw $v0, exception_sp - sw $v0, 0x74($sp) - sw $fp, 0x78($sp) - lw $v0, ret_addr - sw $v0, 0x7C($sp) - lw $v0, vector - sw $v0, 0x80($sp) - - /* Point SP to the stack for C code */ - lw $sp, exception_stack_end - /* Give control to exception dispatch */ - la $a2, exception_dispatch - jalr $a2 - nop - lw $sp, exception_state_ptr - /* Restore registers */ - lw $zero, 0x00($sp) - lw $at, 0x04($sp) - lw $v0, 0x08($sp) - lw $v1, 0x0C($sp) - lw $a0, 0x10($sp) - lw $a1, 0x14($sp) - lw $a2, 0x18($sp) - lw $a3, 0x1C($sp) - lw $t0, 0x20($sp) - lw $t1, 0x24($sp) - lw $t2, 0x28($sp) - lw $t3, 0x2C($sp) - lw $t4, 0x30($sp) - lw $t5, 0x34($sp) - lw $t6, 0x38($sp) - lw $t7, 0x3C($sp) - lw $s0, 0x40($sp) - lw $s1, 0x44($sp) - lw $s2, 0x48($sp) - lw $s3, 0x4C($sp) - lw $s4, 0x50($sp) - lw $s5, 0x54($sp) - lw $s6, 0x58($sp) - lw $s7, 0x5C($sp) - lw $t8, 0x60($sp) - lw $t9, 0x64($sp) - lw $k0, 0x68($sp) - sw $k1, 0x6C($sp) - sw $gp, 0x70($sp) - sw $fp, 0x78($sp) - sw $ra, 0x7C($sp) - /* Return */ - eret - - .global exception_init_asm -exception_init_asm: - .set push - /* Make sure boot exception vector is 1 before writing EBASE */ - mfc0 $t0, STATUS_REGISTER - li $t1, BOOT_EXC_VECTOR_MASK - or $t0, $t0, $t1 - mtc0 $t0, STATUS_REGISTER - - /*Prepare base address */ - la $t1, exception_stack_end - li $t2, EXCEPTION_BASE_MASK - and $t1, $t1, $t2 - - /* Prepare EBASE register value */ - mfc0 $t0, EBASE_REGISTER - li $t2, ~(EXCEPTION_BASE_MASK) - and $t0, $t0, $t2 - /* Filling base address */ - or $t0, $t0, $t1 - mtc0 $t0, EBASE_REGISTER - - /* Clear boot exception vector bit for EBASE value to take effect */ - mfc0 $t0, STATUS_REGISTER - li $t1, ~BOOT_EXC_VECTOR_MASK - and $t0, $t0, $t1 - mtc0 $t0, STATUS_REGISTER - - .set pop - /* Return */ - jr $ra diff --git a/payloads/libpayload/arch/mips/gdb.c b/payloads/libpayload/arch/mips/gdb.c deleted file mode 100644 index 7fd741a..0000000 --- a/payloads/libpayload/arch/mips/gdb.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <gdb.h> -#include <libpayload.h> - - -void gdb_arch_init(void) -{ -} - -void gdb_arch_enter(void) -{ -} diff --git a/payloads/libpayload/arch/mips/head.S b/payloads/libpayload/arch/mips/head.S deleted file mode 100644 index 203e0ae..0000000 --- a/payloads/libpayload/arch/mips/head.S +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> - - /* Disable interrupts and mark the kernel mode */ - .macro setup_c0_status clr - .set push - mfc0 $t0, $CP0_STATUS - or $t0, ST0_CU0 | 0x1f | \clr - xor $t0, 0x1f | \clr - mtc0 $t0, $CP0_STATUS - .set noreorder - sll $zero, 3 - .set pop - .endm - - /* Don't reorder instructions */ - .set noreorder - - .align 4 - - .global cb_header_ptr -cb_header_ptr: - .word 0 - - .global old_sp -old_sp: - .word 0 - - - .global _entry, _leave - .text - -/* Our entry point */ -_entry: - - /* - * This function saves off the previous stack and switches us to our - * own execution environment. - */ - - /* Clear watch and cause registers */ - mtc0 $zero, $CP0_WATCHLO - mtc0 $zero, $CP0_WATCHHI - mtc0 $zero, $CP0_CAUSE - - /* Disable interrupts */ - setup_c0_status 0 - - /* Don't use at in synthetic instr. */ - .set noat - - /* Init timer */ - mtc0 $zero, $CP0_COUNT - mtc0 $zero, $CP0_COMPARE - - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw $gp, 0($ra) - - /* Save off the location of the coreboot tables */ - la $at, cb_header_ptr - sw $a0, 0x00($at) - - /* Save old stack pointer */ - la $at, old_sp - sw $sp, 0x00($at) - - /* Setup new stack */ - la $sp, _stack - - /* Let's rock */ - la $a2, start_main - jalr $a2 - nop -_leave: - /* Restore old stack. */ - lw $sp, old_sp - /* Return to the original context. */ - eret diff --git a/payloads/libpayload/arch/mips/libpayload.ldscript b/payloads/libpayload/arch/mips/libpayload.ldscript deleted file mode 100644 index 351c225..0000000 --- a/payloads/libpayload/arch/mips/libpayload.ldscript +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/arm/ramstage.ld: - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -OUTPUT_ARCH(mips) - -ENTRY(_entry) - -SECTIONS -{ - . = CONFIG_LP_BASE_ADDRESS; - - . = ALIGN(16); - _start = .; - - .text : { - *(.text._entry) - *(.text) - *(.text.*) - } - - .rodata : { - *(.rodata) - *(.rodata.*) - } - - .data : { - *(.data) - *(.data.*) - } - - _edata = .; - - .sdata : { - *(.srodata) - *(.sdata) - } - - _bss = .; - .bss : { - *(.sbss) - *(.sbss.*) - *(.bss) - *(.bss.*) - *(COMMON) - - /* Stack and heap */ - - . = ALIGN(16); - _heap = .; - . += CONFIG_LP_HEAP_SIZE; - . = ALIGN(16); - _eheap = .; - - _estack = .; - . += CONFIG_LP_STACK_SIZE; - . = ALIGN(16); - _stack = .; - } - _ebss = .; - - _end = .; - - /DISCARD/ : { - *(.comment) - *(.note*) - *(.reginfo) - - } -} diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c deleted file mode 100644 index 7a71f90..0000000 --- a/payloads/libpayload/arch/mips/main.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <exception.h> -#include <libpayload.h> - -/* The argc value to pass to main() */ -int main_argc; -/* The argv value to pass to main() */ -char *main_argv[MAX_ARGC_COUNT]; - -/* - * This is our C entry function - set up the system - * and jump into the payload entry point. - */ -void start_main(void); -void start_main(void) -{ - extern int main(int argc, char **argv); - - /* Gather system information. */ - lib_get_sysinfo(); - - /* Optionally set up the consoles. */ -#if !CONFIG(LP_SKIP_CONSOLE_INIT) - console_init(); -#endif - - exception_init(); - /* - * Any other system init that has to happen before the - * user gets control goes here - */ - - /* - * Go to the entry point. - * In the future we may care about the return value. - */ - - (void) main(main_argc, (main_argc != 0) ? main_argv : NULL); - - /* - * Returning here will go to the _leave function to return - * us to the original context. - */ -} diff --git a/payloads/libpayload/arch/mips/selfboot.c b/payloads/libpayload/arch/mips/selfboot.c deleted file mode 100644 index c695831..0000000 --- a/payloads/libpayload/arch/mips/selfboot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> - -extern void *cb_header_ptr; - -void selfboot(void *entry) -{ - void (*entry_func)(void *) = entry; - entry_func(cb_header_ptr); -} diff --git a/payloads/libpayload/arch/mips/string.c b/payloads/libpayload/arch/mips/string.c deleted file mode 100644 index 79cc8d2..0000000 --- a/payloads/libpayload/arch/mips/string.c +++ /dev/null @@ -1,77 +0,0 @@ - /* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include "string.h" - -/* - * Alternative string functions to the default ones are added - * because there is no guarantee that the provided source and - * destination addresses are properly aligned; - * The default string functions work with multiple of 4 bytes - * (sizeof(unsinged long)); MIPS will use LW/SW instructions - * for these operations and if the source and destination - * addresses are not aligned it will trigger an exception. - */ - -void *memcpy(void *dest, const void *src, size_t n) -{ - u8 *ptr_d = dest; - const u8 *ptr_s = src; - size_t i; - - for (i = 0; i < n; i++) - *ptr_d++ = *ptr_s++; - - return dest; -} - -void *memmove(void *dest, const void *src, size_t n) -{ - if ((src < dest) && (dest - src < n)) { - u8 *ptr_d = dest; - const u8 *ptr_s = src; - - /* copy backwards */ - while (n--) - ptr_d[n] = ptr_s[n]; - - return dest; - } - - /* copy forwards */ - return memcpy(dest, src, n); -} - -void *memset(void *s, int c, size_t n) -{ - u8 *ptr = s; - size_t i; - - for (i = 0; i < n; i++) - *ptr++ = c; - - return s; -} - -int memcmp(const void *s1, const void *s2, size_t n) -{ - size_t i; - - for (i = 0; i < n; i++) - if (((u8 *)s1)[i] != ((u8 *)s2)[i]) - return ((u8 *)s1)[i] - ((u8 *)s2)[i]; - return 0; -} diff --git a/payloads/libpayload/arch/mips/sysinfo.c b/payloads/libpayload/arch/mips/sysinfo.c deleted file mode 100644 index 49c6c84..0000000 --- a/payloads/libpayload/arch/mips/sysinfo.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <libpayload-config.h> -#include <libpayload.h> -#include <coreboot_tables.h> -#include <multiboot_tables.h> - -/* - * This is a global structure that is used through the library - we set it - * up initially with some dummy values - hopefully they will be overridden. - */ -struct sysinfo_t lib_sysinfo = { - .cpu_khz = 200, -}; - -int lib_get_sysinfo(void) -{ - int ret; - - /* Get the CPU speed (for delays). */ - lib_sysinfo.cpu_khz = get_cpu_speed(); - - /* Get information from the coreboot tables, - * if they exist */ - ret = get_coreboot_info(&lib_sysinfo); - - /* If we can't get a good memory range, use the default. */ - if (!lib_sysinfo.n_memranges) { - lib_sysinfo.n_memranges = 1; - lib_sysinfo.memrange[0].base = 0; - lib_sysinfo.memrange[0].size = 1024 * 1024; - lib_sysinfo.memrange[0].type = CB_MEM_RAM; - } - - return ret; -} diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c deleted file mode 100644 index a066f67..0000000 --- a/payloads/libpayload/arch/mips/timer.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <libpayload.h> -#include <arch/cpu.h> -#include <arch/io.h> - -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 - -/** - * @ingroup arch - * Global variable containing the speed of the processor in KHz. - */ -u32 cpu_khz; - -/** - * Calculate the speed of the processor for use in delays. - * - * @return The CPU speed in kHz. - */ -unsigned int get_cpu_speed(void) -{ - if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - cpu_khz = 50000; /* FPGA board */ - else { - /* If MIPS PLL external bypass bit is set, it means - * that the MIPS PLL is already set up to work at a - * frequency of 550 MHz; otherwise, the crystal is - * used with a frequency of 52 MHz - */ - if (read32(PISTACHIO_CLOCK_SWITCH) & - MIPS_EXTERN_PLL_BYPASS_MASK) - cpu_khz = 550000; - else - cpu_khz = 52000; - } - - return cpu_khz; -} diff --git a/payloads/libpayload/arch/mips/util.S b/payloads/libpayload/arch/mips/util.S deleted file mode 100644 index 986a34c..0000000 --- a/payloads/libpayload/arch/mips/util.S +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .global halt - .text - .align 4 - .type halt, function -halt: - j halt - nop diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342..2c214dd 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -80,12 +80,6 @@ _ARCHEXTRA="" _ARCH=arm64 fi -if [ "$CONFIG_LP_ARCH_MIPS" = "y" ]; then - _ARCHINCDIR=$_INCDIR/mips - _ARCHLIBDIR=$_LIBDIR/mips - _ARCHEXTRA="" - _ARCH=mips -fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 @@ -170,9 +164,6 @@ $DEFAULT_CC $CMDLINE $_CFLAGS else - if [ -z "${CONFIG_LP_ARCH_MIPS}" ]; then - _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name` - fi if [ -f $_ARCHLIBDIR/head.o ]; then HEAD_O=$_ARCHLIBDIR/head.o elif [ -f $BASE/../build/head.o ]; then diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips deleted file mode 100644 index 4a0a914..0000000 --- a/payloads/libpayload/configs/defconfig-mips +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_LP_ARCH_MIPS=y -CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_TIMER_IMG_PISTACHIO=y -# CONFIG_LP_USB_EHCI is not set -# CONFIG_LP_USB_XHCI is not set diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e7594..a391670 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -54,7 +54,6 @@ libc-y += timer/generic.c endif libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c -libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c # Video console drivers diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 5a61dfa..e3bd0e9 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -50,9 +50,6 @@ config TIMER_RK3399 bool "Timer for Rockchip RK3399" -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - config TIMER_MTK bool "Timer for MediaTek" diff --git a/payloads/libpayload/drivers/timer/img_pistachio.c b/payloads/libpayload/drivers/timer/img_pistachio.c deleted file mode 100644 index d11c3ff..0000000 --- a/payloads/libpayload/drivers/timer/img_pistachio.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <libpayload.h> -#include <arch/cpu.h> - -uint64_t timer_hz(void) -{ - return (uint64_t)lib_sysinfo.cpu_khz * 1000; -} - -uint64_t timer_raw_value(void) -{ - static uint64_t total_ticks = 0; - uint8_t overflow = 0; - uint32_t current_ticks = read_c0_count() * 2; - - /* It assumes only one overflow happened since the last call */ - if (current_ticks <= (uint32_t)total_ticks) - overflow = 1; - /* The least significant part(32 bits) of total_ticks will always - * become equal to current ticks */ - total_ticks = (((total_ticks >> 32) + overflow) << 32) + - current_ticks; - return total_ticks; -} diff --git a/payloads/libpayload/include/mips/arch/byteorder.h b/payloads/libpayload/include/mips/arch/byteorder.h deleted file mode 100644 index 40412d2..0000000 --- a/payloads/libpayload/include/mips/arch/byteorder.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_BYTEORDER_H__ -#define __MIPS_ARCH_BYTEORDER_H__ - -#include <stdint.h> -#include <swab.h> - -#ifndef __ORDER_LITTLE_ENDIAN__ -#error "What endian are you!?" -#endif - -#define cpu_to_le64(x) ((uint64_t)(x)) -#define le64_to_cpu(x) ((uint64_t)(x)) -#define cpu_to_le32(x) ((uint32_t)(x)) -#define le32_to_cpu(x) ((uint32_t)(x)) -#define cpu_to_le16(x) ((uint16_t)(x)) -#define le16_to_cpu(x) ((uint16_t)(x)) -#define cpu_to_be64(x) swab64(x) -#define be64_to_cpu(x) swab64(x) -#define cpu_to_be32(x) swab32((x)) -#define be32_to_cpu(x) swab32((x)) -#define cpu_to_be16(x) swab16((x)) -#define be16_to_cpu(x) swab16((x)) - -#endif /* __MIPS_ARCH_BYTEORDER_H__ */ diff --git a/payloads/libpayload/include/mips/arch/cache.h b/payloads/libpayload/include/mips/arch/cache.h deleted file mode 100644 index e65a2a0..0000000 --- a/payloads/libpayload/include/mips/arch/cache.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CACHE_H__ -#define __MIPS_ARCH_CACHE_H__ - - -#include <stddef.h> -#include <stdint.h> - - -/* - * Sync primitives - */ - -/* data memory barrier */ -static inline void dmb(void) -{ - /* TODO */ -} - -/* data sync barrier */ -static inline void dsb(void) -{ - /* TODO */ -} - -/* instruction sync barrier */ -static inline void isb(void) -{ - /* TODO */ -} - - -/* - * Cache maintenance API - */ - -/* dcache clean and invalidate all */ -void dcache_clean_invalidate_all(void); - -/* dcache clean all */ -void dcache_clean_all(void); - -/* dcache invalidate all (on current level given by CCSELR) */ -void dcache_invalidate_all(void); - -/* returns number of bytes per cache line */ -unsigned int dcache_line_bytes(void); - -/* dcache and MMU disable */ -void dcache_mmu_disable(void); - -/* dcache and MMU enable */ -void dcache_mmu_enable(void); - -/* perform all icache/dcache maintenance needed after loading new code */ -void cache_sync_instructions(void); - -/* tlb invalidate all */ -void tlb_invalidate_all(void); - -/* - * Generalized setup/init functions - */ - -/* mmu initialization (set page table address, set permissions, etc) */ -void mmu_init(void); - -enum dcache_policy { - DCACHE_OFF, - DCACHE_WRITEBACK, - DCACHE_WRITETHROUGH, -}; - -/* disable the mmu for a range. Primarily useful to lock out address 0. */ -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); -/* mmu range configuration (set dcache policy) */ -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy); - -#endif /* __MIPS_ARCH_CACHE_H__ */ diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h deleted file mode 100644 index 93e42ea..0000000 --- a/payloads/libpayload/include/mips/arch/cpu.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MIPS_ARCH_CPU_H__ -#define __MIPS_ARCH_CPU_H__ - -/* - * Reading at this address allows to identify the platform the code is running - * on - */ - -/* - * This register holds the FPGA image version - * If we're not working on the FPGA this will be 0 - */ -#define PRIMARY_FPGA_VERSION 0xB8149060 -#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION) -#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ -#define IMG_PLATFORM_ID_SILICON 0 - -#define CP0_COUNT 9 -#define CP0_COMPARE 11 -#define CP0_STATUS 12 -#define CP0_CAUSE 13 -#define CP0_WATCHLO 18 -#define CP0_WATCHHI 19 - -/* coprocessor 0 enable */ -#define ST0_CU0 (1 << 28) -#define C0_CAUSE_DC (1 << 27) - -/*************************************************************************** - * The following section was copied from arch/mips/include/asm/mipsregs.h in - * the 3.14 kernel tree. - */ - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* Shortcuts to access various internal registers, keep adding as needed. */ -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) -/***************************************************************************/ - -#endif /* __MIPS_ARCH_CPU_H__ */ diff --git a/payloads/libpayload/include/mips/arch/exception.h b/payloads/libpayload/include/mips/arch/exception.h deleted file mode 100644 index 27f0b64..0000000 --- a/payloads/libpayload/include/mips/arch/exception.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EXCEPTION_H__ -#define __MIPS_ARCH_EXCEPTION_H__ - -#include <stdint.h> - -void exception_init_asm(void); -void exception_dispatch(void); - -struct exception_state_t { - struct { - /* Always 0: just to keep the series complete */ - u32 zero; - /* Reserved for the assembler */ - /* TODO: is this actually needed here? */ - u32 at; - /* v0-v1: expression evaluation */ - u32 v0; - u32 v1; - /* a0-a3: Arguments */ - u32 a0; - u32 a1; - u32 a2; - u32 a3; - /* t0-t3: Temporary registers for expression evaluation */ - u32 t0; - u32 t1; - u32 t2; - u32 t3; - u32 t4; - u32 t5; - u32 t6; - u32 t7; - /* s0-s7: Saved registers */ - u32 s0; - u32 s1; - u32 s2; - u32 s3; - u32 s4; - u32 s5; - u32 s6; - u32 s7; - /* t8-t9: Temporary registers for expression evaluation */ - u32 t8; - u32 t9; - /* k0-k1: reserved for SO kernel */ - u32 k0; - u32 k1; - /* Global pointer */ - u32 gp; - /* Stack pointer */ - u32 sp; - /* Frame pointer */ - u32 fp; - /* Return address */ - u32 ra; - } regs; - u32 vector; -} __packed; - -extern struct exception_state_t *exception_state_ptr; -extern u32 *exception_stack_end; - -enum { - EXC_CACHE_ERROR = 0, - EXC_TLB_REFILL_AND_ALL = 1, - EXC_INTERRUPT = 2, - EXC_EJTAG_DEBUG = 3, - EXC_COUNT -}; - -#endif /* __MIPS_ARCH_EXCEPTION_H__ */ diff --git a/payloads/libpayload/include/mips/arch/io.h b/payloads/libpayload/include/mips/arch/io.h deleted file mode 100644 index f86f45f..0000000 --- a/payloads/libpayload/include/mips/arch/io.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on arch/armv7/include/arch/io.h: - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_IO_H__ -#define __MIPS_ARCH_IO_H__ - -#include <arch/types.h> -#include <arch/cache.h> -#include <arch/byteorder.h> - -#define read8(a) (*(volatile uint8_t *) (a)) -#define read16(a) (*(volatile uint16_t *) (a)) -#define read32(a) (*(volatile uint32_t *) (a)) - -#define write8(v, a) (*(volatile uint8_t *) (a) = (v)) -#define write16(v, a) (*(volatile uint16_t *) (a) = (v)) -#define write32(v, a) (*(volatile uint32_t *) (a) = (v)) - - -/* - * Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define out_arch(type, endian, a, v) write##type(cpu_to_##endian(v), a) -#define in_arch(type, endian, a) endian##_to_cpu(read##type(a)) - -#define readb(a) read8(a) -#define readw(a) read16(a) -#define readl(a) read32(a) - -#define inb(a) read8(a) -#define inw(a) read16(a) -#define inl(a) read32(a) - -#define writeb(v, a) write8(v, a) -#define writew(v, a) write16(v, a) -#define writel(v, a) write32(v, a) - -#define outb(v, a) write8(v, a) -#define outw(v, a) write16(v, a) -#define outl(v, a) write32(v, a) - -#endif /* __MIPS_ARCH_IO_H__ */ diff --git a/payloads/libpayload/include/mips/arch/stdint.h b/payloads/libpayload/include/mips/arch/stdint.h deleted file mode 100644 index 18fa54f..0000000 --- a/payloads/libpayload/include/mips/arch/stdint.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Based on src/arch/armv7/include/stdint.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_STDINT_H__ -#define __MIPS_STDINT_H__ - -#if defined(__GNUC__) -#define __HAVE_LONG_LONG__ 1 -#else -#define __HAVE_LONG_LONG__ 0 -#endif - -/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; - -typedef unsigned short uint16_t; -typedef signed short int16_t; - -typedef unsigned int uint32_t; -typedef signed int int32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint64_t; -typedef signed long long int64_t; -#endif - -/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; - -typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; - -typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_least64_t; -typedef signed long long int_least64_t; -#endif - -/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; - -typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; - -typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; - -#if __HAVE_LONG_LONG__ -typedef unsigned long long uint_fast64_t; -typedef signed long long int_fast64_t; -#endif - -/* Largest integral types */ -#if __HAVE_LONG_LONG__ -typedef long long int intmax_t; -typedef unsigned long long uintmax_t; -#else -typedef long int intmax_t; -typedef unsigned long int uintmax_t; -#endif - -typedef uint8_t u8; -typedef uint16_t u16; -typedef uint32_t u32; -#if __HAVE_LONG_LONG__ -typedef uint64_t u64; -#endif -typedef int8_t s8; -typedef int16_t s16; -typedef int32_t s32; - -#undef __HAVE_LONG_LONG__ - -#endif /* __MIPS_STDINT_H__ */ diff --git a/payloads/libpayload/include/mips/arch/types.h b/payloads/libpayload/include/mips/arch/types.h deleted file mode 100644 index afa3a37..0000000 --- a/payloads/libpayload/include/mips/arch/types.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/armv7/include/arch/types.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_TYPES_H -#define __MIPS_ARCH_TYPES_H - -#include <arch/stdint.h> - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -typedef long time_t; -typedef long suseconds_t; - -#ifndef NULL -#define NULL ((void *)0) -#endif - -#endif /* __MIPS_ARCH_TYPES_H */ diff --git a/payloads/libpayload/include/mips/arch/virtual.h b/payloads/libpayload/include/mips/arch/virtual.h deleted file mode 100644 index da791ee..0000000 --- a/payloads/libpayload/include/mips/arch/virtual.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_VIRTUAL_H -#define __MIPS_ARCH_VIRTUAL_H - -#define KSEG0_BASE 0x80000000 -#define KSEG1_BASE 0xA0000000 - -#define kseg0_to_phys(virt) ((unsigned long)(virt) - KSEG0_BASE) -#define phys_to_kseg0(phys) ((void *)((unsigned long)(phys) + KSEG0_BASE)) - -#define kseg1_to_phys(virt) ((unsigned long)(virt) - KSEG1_BASE) -#define phys_to_kseg1(phys) ((void *)((unsigned long)(phys) + KSEG1_BASE)) - -#define virt_to_phys(virt) ((unsigned long)(virt)) -#define phys_to_virt(phys) ((void *)(unsigned long)(phys)) - -#define virt_to_bus(virt) kseg1_to_phys(virt) -#define bus_to_virt(phys) phys_to_kseg1(phys) - -#endif diff --git a/payloads/libpayload/libc/64bit_div.c b/payloads/libpayload/libc/64bit_div.c deleted file mode 100644 index 5cd5bc5..0000000 --- a/payloads/libpayload/libc/64bit_div.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload-config.h> -#include <stdlib.h> - -#if !CONFIG(LP_LITTLE_ENDIAN) -#error this code is for little endian only -#endif - -union overlay64 { - uint64_t longw; - struct { - uint32_t lower; - uint32_t higher; - } words; -}; - - -uint64_t __ashldi3(uint64_t num, unsigned shift) -{ - union overlay64 output; - - output.longw = num; - if (shift >= 32) { - output.words.higher = output.words.lower << (shift - 32); - output.words.lower = 0; - } else { - if (!shift) - return num; - output.words.higher = (output.words.higher << shift) | - (output.words.lower >> (32 - shift)); - output.words.lower = output.words.lower << shift; - } - return output.longw; -} - -uint64_t __lshrdi3(uint64_t num, unsigned shift) -{ - union overlay64 output; - - output.longw = num; - if (shift >= 32) { - output.words.lower = output.words.higher >> (shift - 32); - output.words.higher = 0; - } else { - if (!shift) - return num; - output.words.lower = output.words.lower >> shift | - (output.words.higher << (32 - shift)); - output.words.higher = output.words.higher >> shift; - } - return output.longw; -} - -#define MAX_32BIT_UINT ((((uint64_t)1) << 32) - 1) - -static uint64_t _64bit_divide(uint64_t dividend, - uint64_t divider, uint64_t *rem_p) -{ - uint64_t result = 0; - - /* - * If divider is zero - let the rest of the system care about the - * exception. - */ - if (!divider) - return 1/(uint32_t)divider; - - /* As an optimization, let's not use 64 bit division unless we must. */ - if (dividend <= MAX_32BIT_UINT) { - if (divider > MAX_32BIT_UINT) { - result = 0; - if (rem_p) - *rem_p = divider; - } else { - result = (uint32_t) dividend / (uint32_t) divider; - if (rem_p) - *rem_p = (uint32_t) dividend % - (uint32_t) divider; - } - return result; - } - - while (divider <= dividend) { - uint64_t locald = divider; - uint64_t limit = __lshrdi3(dividend, 1); - int shifts = 0; - - while (locald <= limit) { - shifts++; - locald = locald + locald; - } - result |= __ashldi3(1, shifts); - dividend -= locald; - } - - if (rem_p) - *rem_p = dividend; - - return result; -} - -uint64_t __udivdi3(uint64_t num, uint64_t den) -{ - return _64bit_divide(num, den, NULL); -} - -uint64_t __umoddi3(uint64_t num, uint64_t den) -{ - uint64_t v = 0; - - _64bit_divide(num, den, &v); - return v; -} diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index edef62c..348dc11 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -39,7 +39,3 @@ libc-$(CONFIG_LP_LIBC) += die.c libc-$(CONFIG_LP_LIBC) += coreboot.c libc-$(CONFIG_LP_LIBC) += fmap.c - -ifeq ($(CONFIG_LP_ARCH_MIPS),y) -libc-$(CONFIG_LP_LIBC) += 64bit_div.c -endif diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile index 18121df..b67d876 100644 --- a/payloads/libpayload/sample/Makefile +++ b/payloads/libpayload/sample/Makefile @@ -34,7 +34,6 @@ ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 -ARCH-$(CONFIG_LP_ARCH_MIPS) := mips CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig deleted file mode 100644 index b8570c1..0000000 --- a/src/arch/mips/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config ARCH_MIPS - bool - -if ARCH_MIPS - -config ARCH_BOOTBLOCK_MIPS - bool - default n - select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK - -config ARCH_VERSTAGE_MIPS - bool - default n - -config ARCH_ROMSTAGE_MIPS - bool - default n - -config ARCH_RAMSTAGE_MIPS - bool - default n - -endif # if ARCH_MIPS diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc deleted file mode 100644 index cd474ee..0000000 --- a/src/arch/mips/Makefile.inc +++ /dev/null @@ -1,95 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -############################################################################### -# MIPS specific options -############################################################################### - -ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) -check-ramstage-overlap-regions += stack -endif - -############################################################################### -# bootblock -############################################################################### - -ifeq ($(CONFIG_ARCH_BOOTBLOCK_MIPS),y) - -bootblock-y += boot.c -bootblock-y += bootblock.S -bootblock-y += bootblock_simple.c -bootblock-y += cache.c -bootblock-y += mmu.c -bootblock-y += stages.c -bootblock-y += ../../lib/memcpy.c -bootblock-y += ../../lib/memmove.c -bootblock-y += ../../lib/memset.c - -# Much of the assembly code is generated by the compiler, and may contain -# terms which the preprocessor will happily go on to replace. For example -# "mips" would be replaced with "1". Clear all the built in definitions to -# prevent that. -bootblock-S-ccopts += -undef - -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group - -endif # CONFIG_ARCH_BOOTBLOCK_MIPS - -############################################################################### -# romstage -############################################################################### - -ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y) - -romstage-y += boot.c -romstage-y += cache.c -romstage-y += mmu.c -romstage-y += stages.c -romstage-y += ../../lib/memcpy.c -romstage-y += ../../lib/memmove.c -romstage-y += ../../lib/memset.c - -$(objcbfs)/romstage.debug: $$(romstage-objs) - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group - -endif # CONFIG_ARCH_ROMSTAGE_MIPS - -############################################################################### -# ramstage -############################################################################### - -ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y) - -ramstage-y += ashldi3.c -ramstage-y += boot.c -ramstage-y += cache.c -ramstage-y += mmu.c -ramstage-y += stages.c -ramstage-y += tables.c -ramstage-y += ../../lib/memcpy.c -ramstage-y += ../../lib/memmove.c -ramstage-y += ../../lib/memset.c - -ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) - -$(objcbfs)/ramstage.debug: $$(ramstage-objs) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group - -endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c deleted file mode 100644 index f68d78e..0000000 --- a/src/arch/mips/ashldi3.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google, Inc. - * - * Based on linux arch/mips/lib/ashldi3.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ORDER_LITTLE_ENDIAN__ -#errror "What endian are you!?" -#endif - -typedef unsigned int word_type; -long long __ashldi3(long long u, word_type b); - -struct DWstruct { - int low, high; -}; -typedef union { - struct DWstruct s; - long long ll; -} DWunion; - -long long __ashldi3(long long u, word_type b) -{ - DWunion uu, w; - word_type bm; - - if (b == 0) - return u; - - uu.ll = u; - bm = 32 - b; - - if (bm <= 0) { - w.s.low = 0; - w.s.high = (unsigned int) uu.s.low << -bm; - } else { - const unsigned int carries = (unsigned int) uu.s.low >> bm; - - w.s.low = (unsigned int) uu.s.low << b; - w.s.high = ((unsigned int) uu.s.high << b) | carries; - } - - return w.ll; -} diff --git a/src/arch/mips/boot.c b/src/arch/mips/boot.c deleted file mode 100644 index 5ab36ec..0000000 --- a/src/arch/mips/boot.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/stages.h> -#include <program_loading.h> - -void arch_prog_run(struct prog *prog) -{ - void *cb_tables = prog_entry_arg(prog); - void (*doit)(void *) = prog_entry(prog); - - doit(cb_tables); -} diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S deleted file mode 100644 index f8049c9..0000000 --- a/src/arch/mips/bootblock.S +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -.set noreorder /* Prevent assembler from "optimizing" this code. */ - -.section ".text._start", "ax", %progbits -.globl _start -_start: - /* Set the stack pointer */ - la $sp, _estack - - /* - * Initialise the stack to a known value, used later to check for - * overflow. - */ - la $t0, _stack - addi $t1, $sp, -4 - li $t2, 0xdeadbeef -1: sw $t2, 0($t0) - bne $t0, $t1, 1b - addi $t0, $t0, 4 - - /* Run main */ - b mips_main - - /* - * Should never return from main. Make sure there is no branch in the - * branch delay slot. - */ -2: nop - b 2b - nop /* Make sure there is no branch after this either. */ diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c deleted file mode 100644 index e195b6a..0000000 --- a/src/arch/mips/bootblock_simple.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/bootblock_common.h> -#include <console/console.h> -#include <halt.h> -#include <program_loading.h> - -/* called from assembly in bootblock.S */ -void mips_main(void); - -void mips_main(void) -{ - bootblock_cpu_init(); - - /* Mainboard basic init */ - bootblock_mainboard_init(); - -#if CONFIG(BOOTBLOCK_CONSOLE) - console_init(); -#endif - - bootblock_mmu_init(); - - if (init_extra_hardware()) - printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n"); - else - run_romstage(); - - halt(); -} diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c deleted file mode 100644 index 62c20f3..0000000 --- a/src/arch/mips/cache.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/cpu.h> -#include <console/console.h> -#include <program_loading.h> -#include <symbols.h> - -/* cache_op: issues cache operation for specified address */ -#define cache_op(op, addr) \ -({ \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips32\n\t" \ - "cache %0, %1\n\t" \ - ".set mips0\n\t" \ - ".set pop\n\t" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))); \ -}) - -#define MIPS_CONFIG1_DL_SHIFT 10 -#define MIPS_CONFIG1_DL_MASK (0x00000007) -#define MIPS_CONFIG1_IL_SHIFT 19 -#define MIPS_CONFIG1_IL_MASK (0x00000007) -#define MIPS_CONFIG2_SL_SHIFT 4 -#define MIPS_CONFIG2_SL_MASK (0x0000000F) - -/* - * get_cache_line_size: - * Read config register - * Isolate instruction cache line size - * Interpret value as per MIPS manual: 2 << value - * Return cache line size - */ -static int get_cache_line_size(uint8_t type) -{ - switch (type) { - case ICACHE: - return 2 << ((read_c0_config1() >> MIPS_CONFIG1_IL_SHIFT) & - MIPS_CONFIG1_IL_MASK); - case DCACHE: - return 2 << ((read_c0_config1() >> MIPS_CONFIG1_DL_SHIFT) & - MIPS_CONFIG1_DL_MASK); - case L2CACHE: - return 2 << ((read_c0_config2() >> MIPS_CONFIG2_SL_SHIFT) & - MIPS_CONFIG2_SL_MASK); - default: - printk(BIOS_ERR, "%s: Error: unsupported cache type.\n", - __func__); - return 0; - } - return 0; -} - -void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation) -{ - u32 line_size, line_mask; - uintptr_t end; - - line_size = get_cache_line_size((operation >> CACHE_TYPE_SHIFT) & - CACHE_TYPE_MASK); - if (!line_size) - return; - line_mask = ~(line_size-1); - end = (start + (line_size - 1) + size) & line_mask; - start &= line_mask; - if ((operation & L2CACHE) == L2CACHE) - write_c0_l23taglo(0); - while (start < end) { - switch (operation) { - case CACHE_CODE(ICACHE, WB_INVD): - cache_op(CACHE_CODE(ICACHE, WB_INVD), start); - break; - case CACHE_CODE(DCACHE, WB_INVD): - cache_op(CACHE_CODE(DCACHE, WB_INVD), start); - break; - case CACHE_CODE(L2CACHE, WB_INVD): - cache_op(CACHE_CODE(L2CACHE, WB_INVD), start); - break; - default: - return; - } - start += line_size; - } - asm("sync"); -} - -void cache_invalidate_all(uintptr_t start, size_t size) -{ - perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD)); - perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD)); - perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD)); -} - -void arch_segment_loaded(uintptr_t start, size_t size, int flags) -{ - cache_invalidate_all(start, size); - if (flags & SEG_FINAL) - cache_invalidate_all((uintptr_t)_cbfs_cache, - REGION_SIZE(cbfs_cache)); -} diff --git a/src/arch/mips/include/arch/bootblock_common.h b/src/arch/mips/include/arch/bootblock_common.h deleted file mode 100644 index f5c11ba..0000000 --- a/src/arch/mips/include/arch/bootblock_common.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -} -#endif diff --git a/src/arch/mips/include/arch/byteorder.h b/src/arch/mips/include/arch/byteorder.h deleted file mode 100644 index 35d444b..0000000 --- a/src/arch/mips/include/arch/byteorder.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_BYTEORDER_H -#define __MIPS_ARCH_BYTEORDER_H - -#ifndef __ORDER_LITTLE_ENDIAN__ -#errror "What endian are you!?" -#endif - -#define __LITTLE_ENDIAN 1234 - -#endif /* __MIPS_ARCH_BYTEORDER_H */ diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h deleted file mode 100644 index 61a3e7c..0000000 --- a/src/arch/mips/include/arch/cache.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CACHE_H -#define __MIPS_ARCH_CACHE_H - -#include <stddef.h> -#include <stdint.h> - -#define CACHE_TYPE_SHIFT (0) -#define CACHE_OP_SHIFT (2) -#define CACHE_TYPE_MASK (0x3) -#define CACHE_OP_MASK (0x7) - -/* Cache type */ -#define ICACHE 0x00 -#define DCACHE 0x01 -#define L2CACHE 0x03 - -/* Cache operation*/ -#define WB_INVD 0x05 - -#define CACHE_CODE(type, op) ((((type) & (CACHE_TYPE_MASK)) << \ - (CACHE_TYPE_SHIFT)) | \ - (((op) & (CACHE_OP_MASK)) << (CACHE_OP_SHIFT))) - -/* Perform cache operation on cache lines for target addresses */ -void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation); -/* Invalidate all caches: instruction, data, L2 data */ -void cache_invalidate_all(uintptr_t start, size_t size); - -/* TODO: Global cache API. Implement properly once we finally have a MIPS board - again where we can figure out what exactly these should be doing. */ -static inline void dcache_clean_all(void) {} -static inline void dcache_invalidate_all(void) {} -static inline void dcache_clean_invalidate_all(void) {} - -#endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/mips/include/arch/cbconfig.h b/src/arch/mips/include/arch/cbconfig.h deleted file mode 100644 index 9467f52..0000000 --- a/src/arch/mips/include/arch/cbconfig.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ARCH_CBCONFIG_H_ -#define _ARCH_CBCONFIG_H_ - -/* - * Instead of using Kconfig variables for internal coreboot infrastructure - * variables that are architecture dependent land those things in this file. - * If it's not obvious all variables that are used in the common code need - * to have the same name across all architectures. - */ - -#define COREBOOT_TABLE_SIZE 0x2000 - -#endif diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h deleted file mode 100644 index 8e35908..0000000 --- a/src/arch/mips/include/arch/cpu.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_CPU_H -#define __MIPS_ARCH_CPU_H - -#define asmlinkage - -#ifndef __PRE_RAM__ - -#include <device/device.h> - -struct cpu_driver { - struct device_operations *ops; - const struct cpu_device_id *id_table; -}; - -struct thread; - -struct cpu_info { - struct device *cpu; - unsigned long index; -}; - -#endif /* !__PRE_RAM__ */ - -/*************************************************************************** - * The following section was copied from arch/mips/include/asm/mipsregs.h in - * the 3.14 kernel tree. - */ - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* Shortcuts to access various internal registers, keep adding as needed. */ -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, (val)) - -#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, (val)) - -#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, (val)) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, (val)) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, (val)) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val)) - -#define read_c0_entryhi() __read_32bit_c0_register($10, 0) -#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, (val)) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val)) - -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val)) - -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val)) - -#define read_c0_l23taglo() __read_32bit_c0_register($28, 4) -#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val)) - - -#define C0_ENTRYLO_PFN_SHIFT 6 - -#define C0_ENTRYLO_COHERENCY_MASK 0x00000038 -#define C0_ENTRYLO_COHERENCY_SHIFT 3 -/* Cacheable, write-back, non-coherent */ -#define C0_ENTRYLO_COHERENCY_WB (0x3 << C0_ENTRYLO_COHERENCY_SHIFT) -/* Uncached, non-coherent */ -#define C0_ENTRYLO_COHERENCY_UC (0x2 << C0_ENTRYLO_COHERENCY_SHIFT) - -/* Writeable */ -#define C0_ENTRYLO_D (0x1 << 2) -/* Valid */ -#define C0_ENTRYLO_V (0x1 << 1) -/* Global */ -#define C0_ENTRYLO_G (0x1 << 0) - -#define C0_PAGEMASK_SHIFT 13 -#define C0_PAGEMASK_MASK 0xffff - -#define C0_WIRED_MASK 0x3f - -#define C0_CAUSE_DC (1 << 27) - -#define C0_CONFIG1_MMUSIZE_SHIFT 25 -#define C0_CONFIG1_MMUSIZE_MASK 0x3f - -/* Hazard handling */ -static inline void __nop(void) -{ - __asm__ __volatile__("nop"); -} - -static inline void __ssnop(void) -{ - __asm__ __volatile__("sll\t$0, $0, 1"); -} - -#define mtc0_tlbw_hazard() \ -do { \ - __nop(); \ - __nop(); \ -} while (0) - -#define tlbw_use_hazard() \ -do { \ - __nop(); \ - __nop(); \ - __nop(); \ -} while (0) - -#define tlb_probe_hazard() \ -do { \ - __nop(); \ - __nop(); \ - __nop(); \ -} while (0) - -#define back_to_back_c0_hazard() \ -do { \ - __ssnop(); \ - __ssnop(); \ - __ssnop(); \ -} while (0) -/**************************************************************************/ - -#endif /* __MIPS_ARCH_CPU_H */ diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h deleted file mode 100644 index 61f4653..0000000 --- a/src/arch/mips/include/arch/early_variables.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EARLY_VARIABLES_H -#define __MIPS_ARCH_EARLY_VARIABLES_H - -#define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) - -static inline void *car_get_var_ptr(void *var) { return var; } -#define car_get_var(var) (var) -#define car_sync_var(var) (var) -#define car_set_var(var, val) { (var) = (val); } - -#endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/mips/include/arch/exception.h b/src/arch/mips/include/arch/exception.h deleted file mode 100644 index e70d396..0000000 --- a/src/arch/mips/include/arch/exception.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_EXCEPTION_H -#define __MIPS_ARCH_EXCEPTION_H - -static inline void exception_init(void) {} - -#endif /* __MIPS_ARCH_EXCEPTION_H */ diff --git a/src/arch/mips/include/arch/header.ld b/src/arch/mips/include/arch/header.ld deleted file mode 100644 index 1d84a4e..0000000 --- a/src/arch/mips/include/arch/header.ld +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_ARCH(mips) - -PHDRS -{ - to_load PT_LOAD; -} - -#ifdef __BOOTBLOCK__ -ENTRY(_start) -#else -ENTRY(stage_entry) -#endif diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h deleted file mode 100644 index 703773b..0000000 --- a/src/arch/mips/include/arch/hlt.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_HLT_H -#define __MIPS_ARCH_HLT_H - -static inline __always_inline void hlt(void) -{ - for (;;) - ; -} - -#endif /* __MIPS_ARCH_HLT_H */ diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h deleted file mode 100644 index fe05bd8..0000000 --- a/src/arch/mips/include/arch/memlayout.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __ARCH_MEMLAYOUT_H -#define __ARCH_MEMLAYOUT_H - -/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ -/* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) \ - REGION(stack, addr, size, 8) \ - _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); - -#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) - -#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4) - -#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/mmio.h deleted file mode 100644 index c491b51..0000000 --- a/src/arch/mips/include/arch/mmio.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on arch/armv7/include/arch/io.h: - * Copyright 2013 Google Inc. - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_MMIO_H__ -#define __ARCH_MMIO_H__ - -#include <types.h> -#include <arch/cache.h> -#include <endian.h> - -static inline uint8_t read8(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint8_t *)addr; -} - -static inline uint16_t read16(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint16_t *)addr; -} - -static inline uint32_t read32(const volatile void *addr) -{ - asm("sync"); - return *(volatile uint32_t *)addr; -} - -static inline void write8(volatile void *addr, uint8_t val) -{ - asm("sync"); - *(volatile uint8_t *)addr = val; - asm("sync"); -} - -static inline void write16(volatile void *addr, uint16_t val) -{ - asm("sync"); - *(volatile uint16_t *)addr = val; - asm("sync"); -} - -static inline void write32(volatile void *addr, uint32_t val) -{ - asm("sync"); - *(volatile uint32_t *)addr = val; - asm("sync"); -} - -/* Fixing soc/imgtech/pistachio seemed painful at the time. */ -#define read32_x(addr) read32((void *)(addr)) -#define write32_x(addr, val) write32((void *)(addr), (val)) - -#endif /* __MIPS_ARCH_IO_H */ diff --git a/src/arch/mips/include/arch/mmu.h b/src/arch/mips/include/arch/mmu.h deleted file mode 100644 index 8997e27..0000000 --- a/src/arch/mips/include/arch/mmu.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_MMU_H -#define __MIPS_ARCH_MMU_H - -#include <arch/cpu.h> -#include <stddef.h> -#include <stdint.h> - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline uint32_t get_max_pagesize(void) -{ - uint32_t max_pgsize; - - write_c0_pagemask(C0_PAGEMASK_MASK << C0_PAGEMASK_SHIFT); - back_to_back_c0_hazard(); - max_pgsize = (((read_c0_pagemask() >> C0_PAGEMASK_SHIFT) & - C0_PAGEMASK_MASK) + 1) * 4 * KiB; - - return max_pgsize; -} - -static inline uint32_t get_tlb_size(void) -{ - uint32_t tlbsize; - - tlbsize = ((read_c0_config1() >> C0_CONFIG1_MMUSIZE_SHIFT) & - C0_CONFIG1_MMUSIZE_MASK) + 1; - - return tlbsize; -} - -int identity_map(uint32_t start, size_t len, uint32_t coherency); - -#endif /* __MIPS_ARCH_MMU_H */ diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h deleted file mode 100644 index 7bfcbdd..0000000 --- a/src/arch/mips/include/arch/pci_ops.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_MIPS_PCI_OPS_H -#define ARCH_MIPS_PCI_OPS_H - -#include <stdint.h> -#include <device/pci_type.h> - -#ifdef __SIMPLE_DEVICE__ -u8 pci_read_config8(pci_devfn_t dev, unsigned int where); -u16 pci_read_config16(pci_devfn_t dev, unsigned int where); -u32 pci_read_config32(pci_devfn_t dev, unsigned int where); -void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val); -void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val); -void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val); -#endif - -#endif diff --git a/src/arch/mips/include/arch/stages.h b/src/arch/mips/include/arch/stages.h deleted file mode 100644 index 802199f..0000000 --- a/src/arch/mips/include/arch/stages.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_STAGES_H -#define __MIPS_ARCH_STAGES_H - -#include <main_decl.h> - -void stage_entry(void); - -#endif /* __MIPS_ARCH_STAGES_H */ diff --git a/src/arch/mips/include/arch/types.h b/src/arch/mips/include/arch/types.h deleted file mode 100644 index 31a2f9f..0000000 --- a/src/arch/mips/include/arch/types.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * Based on src/arch/armv7/include/arch/types.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MIPS_ARCH_TYPES_H -#define __MIPS_ARCH_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __MIPS_ARCH_TYPES_H */ diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c deleted file mode 100644 index b144fd3..0000000 --- a/src/arch/mips/mmu.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/mmu.h> -#include <console/console.h> -#include <stddef.h> -#include <stdint.h> -#include <stdlib.h> - -#define MIN_PAGE_SIZE (4 * KiB) - -static int add_wired_tlb_entry(uint32_t entrylo0, uint32_t entrylo1, - uint32_t entryhi, uint32_t pgsize) -{ - uint32_t tlbindex; - - tlbindex = read_c0_wired(); - if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) { - printk(BIOS_ERR, "Ran out of TLB entries\n"); - return -1; - } - write_c0_wired(tlbindex + 1); - write_c0_index(tlbindex); - write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT); - write_c0_entryhi(entryhi); - write_c0_entrylo0(entrylo0); - write_c0_entrylo1(entrylo1); - mtc0_tlbw_hazard(); - tlb_write_indexed(); - tlbw_use_hazard(); - - return 0; -} - -static uint32_t pick_pagesize(uint32_t start, uint32_t len) -{ - uint32_t pgsize, max_pgsize; - - max_pgsize = get_max_pagesize(); - for (pgsize = max_pgsize; - pgsize >= MIN_PAGE_SIZE; - pgsize = pgsize / 4) { - /* - * Each TLB entry maps a pair of virtual pages. To avoid - * aliasing, pick the largest page size that is at most - * half the size of the region we're trying to map. - */ - if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len)) - break; - } - - return pgsize; -} - -/* - * Identity map the memory from [start,start+len] in the TLB using the - * largest suitable page size so as to conserve TLB entries. - */ -int identity_map(uint32_t start, size_t len, uint32_t coherency) -{ - uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1; - - coherency &= C0_ENTRYLO_COHERENCY_MASK; - while (len > 0) { - pgsize = pick_pagesize(start, len); - entryhi = start; - pfn = start >> 12; - entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency | - C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; - start += pgsize; - len -= MIN(len, pgsize); - if (len >= pgsize) { - pfn = start >> 12; - entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) | - coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | - C0_ENTRYLO_G; - start += pgsize; - len -= MIN(len, pgsize); - } else { - entrylo1 = 0; - } - if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize)) - return -1; - } - - return 0; -} diff --git a/src/arch/mips/stages.c b/src/arch/mips/stages.c deleted file mode 100644 index e940faa..0000000 --- a/src/arch/mips/stages.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/stages.h> -#include <arch/cache.h> - -void stage_entry(void) -{ - main(); -} diff --git a/src/arch/mips/tables.c b/src/arch/mips/tables.c deleted file mode 100644 index 50d2a55..0000000 --- a/src/arch/mips/tables.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Based on src/arch/armv7/tables.c: - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2005 Steve Magnani - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootmem.h> -#include <boot/tables.h> -#include <boot/coreboot_tables.h> - -void arch_write_tables(uintptr_t coreboot_table) -{ -} - -void bootmem_arch_add_ranges(void) -{ -} - -void lb_arch_add_records(struct lb_header *header) -{ -} diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index f34c91b..c1e218d 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -22,10 +22,6 @@ #define call_tx(x) tx_byte(x, data) -#if !CONFIG(ARCH_MIPS) -#define SUPPORT_64BIT_INTS -#endif - #define ZEROPAD 1 /* pad with zero */ #define SIGN 2 /* unsigned/signed long */ #define PLUS 4 /* show plus */ diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 66ee2f9..bf857f8 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += allwinner subdirs-y += amd subdirs-y += armltd -subdirs-y += imgtec subdirs-y += intel subdirs-y += ti subdirs-y += via diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index ad282c6..52006ae 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -55,7 +55,7 @@ u64 speed; /* KiB/s */ int bps; /* Bits per second */ - speed = size * 1000 / usecs; + speed = size * (u64)1000 / usecs; bps = speed * 8; printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..2df0caf 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -173,7 +173,6 @@ #define ENV_ARMV7 0 #endif #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -189,19 +188,6 @@ #else #define ENV_ARMV8 0 #endif -#define ENV_MIPS 0 -#define ENV_RISCV 0 -#define ENV_X86 0 -#define ENV_X86_32 0 -#define ENV_X86_64 0 - -#elif defined(__ARCH_mips__) -#define ENV_ARM 0 -#define ENV_ARM64 0 -#define ENV_ARMV4 0 -#define ENV_ARMV7 0 -#define ENV_ARMV8 0 -#define ENV_MIPS 1 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 @@ -213,7 +199,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 1 #define ENV_X86 0 #define ENV_X86_32 0 @@ -225,7 +210,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 1 @@ -237,7 +221,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 1 #define ENV_X86_32 0 @@ -249,7 +232,6 @@ #define ENV_ARMV4 0 #define ENV_ARMV7 0 #define ENV_ARMV8 0 -#define ENV_MIPS 0 #define ENV_RISCV 0 #define ENV_X86 0 #define ENV_X86_32 0 diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig deleted file mode 100644 index 19d5c41..0000000 --- a/src/mainboard/google/urara/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -if BOARD_GOOGLE_URARA - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_512 - select SPI_FLASH_WINBOND - select CPU_IMGTEC_PISTACHIO - select COMMON_CBFS_SPI_WRAPPER - select SPI_FLASH - -config MAINBOARD_DIR - string - default "google/urara" - -config MAINBOARD_PART_NUMBER - string - default "ImgTec Pistachio Virtual Platform" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/google/urara/bootblock.c" - -config DRAM_SIZE_MB - int - default 256 - -config TTYS0_LCS - int - default 3 - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on DRIVERS_UART - default 0xB8101500 - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 1 - -config GBB_HWID - string - depends on CHROMEOS - default "Urara TEST 1" -endif diff --git a/src/mainboard/google/urara/Kconfig.name b/src/mainboard/google/urara/Kconfig.name deleted file mode 100644 index edc935a..0000000 --- a/src/mainboard/google/urara/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_URARA - bool "Urara" diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc deleted file mode 100644 index 7ad779d..0000000 --- a/src/mainboard/google/urara/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright 2014 Imagination Technologies Ltd. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-y += boardid.c -ramstage-y += boardid.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += mainboard.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt deleted file mode 100644 index 0458abd..0000000 --- a/src/mainboard/google/urara/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Vendor name: Google -Board name: Urara Imgtec Pistachio reference board -Category: eval -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c deleted file mode 100644 index 9a6b64e..0000000 --- a/src/mainboard/google/urara/boardid.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <string.h> - -#include <boardid.h> -#include <cbfs.h> -#include <console/console.h> - -#include "mainboard/google/urara/urara_boardid.h" - -/* Name of the CBFS file were the board ID string is read from. */ -#define CBFS_BOARD_ID_FILE_NAME "board_id" - -const struct bid_map { - const char *board_name; - uint8_t board_id; - struct board_hw hardware; -} board_id_map[] = { - {"urara", URARA_BOARD_ID_BUB, {0} }, - {"buranku", URARA_BOARD_ID_BURANKU, {3} }, - {"derwent", URARA_BOARD_ID_DERWENT, {3} }, - {"jaguar", URARA_BOARD_ID_JAGUAR, {3} }, - {"kennet", URARA_BOARD_ID_KENNET, {3} }, - {"space", URARA_BOARD_ID_SPACE, {3} }, -}; - -static int cached_board_id = -1; - -static uint8_t retrieve_board_id(void) -{ - const char *board_id_file_name = CBFS_BOARD_ID_FILE_NAME; - char *file_contents; - int i; - size_t length; - - file_contents = cbfs_boot_map_with_leak(board_id_file_name, - CBFS_TYPE_RAW, &length); - - if (!file_contents) { - printk(BIOS_WARNING, - "board_id: failed to locate file '%s'\n", - board_id_file_name); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - const struct bid_map *entry = board_id_map + i; - - if ((strlen(entry->board_name) == length) && - !strncmp(entry->board_name, file_contents, length)) { - printk(BIOS_INFO, "board_id: name '%s', ID %d\n", - entry->board_name, entry->board_id); - return entry->board_id; - } - } - - printk(BIOS_WARNING, "board_id: no match for board name '%.*s'\n", - length, file_contents); - printk(BIOS_WARNING, "board_id: will use default board ID 0\n"); - - return 0; -} - -const struct board_hw *board_get_hw(void) -{ - int i; - uint8_t bid = board_id(); - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - if (bid == board_id_map[i].board_id) - return &(board_id_map[i].hardware); - } - - return 0; -} - -uint32_t board_id(void) -{ - if (cached_board_id == -1) - cached_board_id = retrieve_board_id(); - - return cached_board_id; -} diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c deleted file mode 100644 index 16e7580..0000000 --- a/src/mainboard/google/urara/bootblock.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/mmio.h> -#include <stdint.h> -#include <soc/clocks.h> -#include <assert.h> -#include <boardid.h> - -#include "urara_boardid.h" - -#define PADS_FUNCTION_SELECT0_ADDR (0xB8101C00 + 0xC0) - -#define GPIO_BIT_EN_ADDR(bank) (0xB8101C00 + 0x200 + (0x24 * (bank))) -#define PAD_DRIVE_STRENGTH_ADDR(bank) (0xB8101C00 + 0x120 + (0x4 * (bank))) -#define MAX_NO_MFIOS 89 -#define PAD_DRIVE_STRENGTH_LENGTH 2 -#define PAD_DRIVE_STRENGTH_MASK 0x3 - -typedef enum { - DRIVE_STRENGTH_2mA = 0, - DRIVE_STRENGTH_4mA = 1, - DRIVE_STRENGTH_8mA = 2, - DRIVE_STRENGTH_12mA = 3 -} drive_strength; - -/* MFIO definitions for UART1 */ -#define UART1_RXD_MFIO 59 -#define UART1_TXD_MFIO 60 - -/* MFIO definitions for SPIM */ -#define SPIM1_D0_TXD_MFIO 5 -#define SPIM1_D1_RXD_MFIO 4 -#define SPIM1_MCLK_MFIO 3 -#define SPIM1_D2_MFIO 6 -#define SPIM1_D3_MFIO 7 -#define SPIM1_CS0_MFIO 0 - -/* MFIO definitions for I2C */ -#define I2C_DATA_MFIO(i) (28 + (2*(i))) -#define I2C_CLK_MFIO(i) (29 + (2*(i))) -#define I2C_DATA_FUNCTION_OFFSET(i) (20 + (2*(i))) -#define I2C_CLK_FUNCTION_OFFSET(i) (21 + (2*(i))) -#define I2C_DATA_FUNCTION_MASK 0x1 -#define I2C_CLK_FUNCTION_MASK 0x1 - -static void pad_drive_strength(u32 pad, drive_strength strength) -{ - u32 reg, drive_strength_shift; - - assert(pad <= MAX_NO_MFIOS); - assert(!(strength & ~(PAD_DRIVE_STRENGTH_MASK))); - - /* Set drive strength value */ - drive_strength_shift = (pad % 16) * PAD_DRIVE_STRENGTH_LENGTH; - reg = read32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16)); - reg &= ~(PAD_DRIVE_STRENGTH_MASK << drive_strength_shift); - reg |= strength << drive_strength_shift; - write32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg); -} - -static void uart1_mfio_setup(void) -{ - u32 reg, mfio_mask; - - /* - * Disable GPIO for UART1 MFIOs - * All UART MFIOs have MFIO/16 = 3, therefore we use GPIO pad 3 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(3)); - mfio_mask = 1 << (UART1_RXD_MFIO % 16); - mfio_mask |= 1 << (UART1_TXD_MFIO % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(3), reg); -} - -static void spim1_mfio_setup(void) -{ - u32 reg, mfio_mask; - /* - * Disable GPIO for SPIM1 MFIOs - * All SPFI1 MFIOs have MFIO/16 = 0, therefore we use GPIO pad 0 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(0)); - - /* Disable GPIO for SPIM1 MFIOs */ - mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D1_RXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_MCLK_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D2_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D3_MFIO % 16); - mfio_mask |= 1 << (SPIM1_CS0_MFIO % 16); - - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(0), reg); - - /* Set drive strength to maximum for these MFIOs */ - pad_drive_strength(SPIM1_CS0_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D1_RXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D0_TXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D2_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D3_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_MCLK_MFIO, DRIVE_STRENGTH_12mA); -} - -static void i2c_mfio_setup(int interface) -{ - u32 reg, mfio_mask; - - assert(interface < 4); - /* - * Disable GPIO for I2C MFIOs - */ - reg = read32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16)); - mfio_mask = 1 << (I2C_DATA_MFIO(interface) % 16); - mfio_mask |= 1 << (I2C_CLK_MFIO(interface) % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg); - - /* for I2C0 and I2C1: - * Set bits to 0 (clear) which is the primary function - * for these MFIOs; those bits will all be set to 1 by - * default. - * There is no need to do that for I2C2 and I2C3 - */ - if (interface > 1) - return; - reg = read32_x(PADS_FUNCTION_SELECT0_ADDR); - reg &= ~(I2C_DATA_FUNCTION_MASK << - I2C_DATA_FUNCTION_OFFSET(interface)); - reg &= ~(I2C_CLK_FUNCTION_MASK << - I2C_CLK_FUNCTION_OFFSET(interface)); - write32_x(PADS_FUNCTION_SELECT0_ADDR, reg); -} - -static void bootblock_mainboard_init(void) -{ - int ret; - - /* System PLL divided by 2 -> 350 MHz */ - /* The same frequency will be the input frequency for the SPFI block */ - system_clk_setup(1); - - /* MIPS CPU dividers: division by 1 -> 546 MHz - * This is set up as we cannot make any assumption about - * the values set or not by the boot ROM code */ - mips_clk_setup(0, 0); - - /* Setup system PLL at 700 MHz */ - ret = sys_pll_setup(2, 1, 13, 350); - if (ret != CLOCKS_OK) - return; - /* Setup MIPS PLL at 546 MHz */ - ret = mips_pll_setup(2, 1, 1, 21); - if (ret != CLOCKS_OK) - return; - - /* - * Move peripheral clock control from RPU to MIPS. - * The RPU gate register is not managed in Linux so disable its default - * values and assign MIPS gate register the default values. - * *Note*: All unused clocks will be gated by Linux - */ - setup_clk_gate_defaults(); - - /* Setup SPIM1 MFIOs */ - spim1_mfio_setup(); - /* Setup UART1 clock and MFIOs - * System PLL divided by 5 divided by 76 -> 1.8421 Mhz - */ - uart1_clk_setup(4, 75); - uart1_mfio_setup(); -} - - -static int init_extra_hardware(void) -{ - const struct board_hw *hardware; - - /* Obtain information about current board */ - hardware = board_get_hw(); - if (!hardware) { - printk(BIOS_ERR, "%s: Invalid hardware information.\n", - __func__); - return -1; - } - - /* Setup USB clock - * System clock divided by 7 -> 50 MHz - */ - if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) { - printk(BIOS_ERR, "%s: Failed to set up USB clock.\n", - __func__); - return -1; - } - - /* Setup I2C clocks and MFIOs - * System clock divided by 4 divided by 3 -> 29.1(6) MHz - */ - i2c_clk_setup(3, 2, hardware->i2c_interface); - i2c_mfio_setup(hardware->i2c_interface); - - /* Ethernet clocks setup: ENET as clock source */ - eth_clk_setup(0, 6); - /* ROM clock setup: system clock divided by 2 -> 175 MHz */ - /* Hash accelerator is driven from the ROM clock */ - rom_clk_setup(1); - - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c deleted file mode 100644 index 3f7ec32..0000000 --- a/src/mainboard/google/urara/chromeos.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <bootmode.h> -#include <console/console.h> -#include <gpio.h> - -int get_write_protect_state(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); -} - -int get_recovery_mode_switch(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.fmd b/src/mainboard/google/urara/chromeos.fmd deleted file mode 100644 index 4bc0db4..0000000 --- a/src/mainboard/google/urara/chromeos.fmd +++ /dev/null @@ -1,32 +0,0 @@ -FLASH@0x0 0x200000 { - WP_RO@0x0 0x100000 { - RO_SECTION@0x0 0xf0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x60000 - FMAP@0xe0000 0x1000 - GBB@0xe1000 0xef00 - RO_FRID@0xeff00 0x100 - } - RO_VPD(PRESERVE)@0xf0000 0x10000 - } - RW_SECTION_A@0x100000 0x70000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x6df00 - RW_FWID_A@0x6ff00 0x100 - } - RW_SHARED@0x170000 0x2000 { - SHARED_DATA@0x0 0x2000 - } - RW_GPT@0x172000 0x2000 { - RW_GPT_PRIMARY@0x0 0x1000 - RW_GPT_SECONDARY@0x1000 0x1000 - } - RW_ELOG(PRESERVE)@0x174000 0x4000 - RW_VPD(PRESERVE)@0x178000 0x8000 - RW_SECTION_B@0x180000 0x70000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x6df00 - RW_FWID_B@0x6ff00 0x100 - } - RW_NVRAM(PRESERVE)@0x1f0000 0x10000 -} diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb deleted file mode 100644 index d865add..0000000 --- a/src/mainboard/google/urara/devicetree.cb +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -chip soc/imgtec/pistachio - device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end -end diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c deleted file mode 100644 index 7bf8b90..0000000 --- a/src/mainboard/google/urara/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <symbols.h> -#include <console/console.h> -#include <device/device.h> -#include <boot/coreboot_tables.h> - -#include <vendorcode/google/chromeos/chromeos.h> - -static void mainboard_init(struct device *dev) -{ -#if CONFIG(CHROMEOS) - /* Copy WIFI calibration data into CBMEM. */ - cbmem_add_vpd_calibration_data(); -#endif -} - -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Enable Pistachio device...\n"); - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAG_DMA; - dma->size = sizeof(*dma); - dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = REGION_SIZE(dma_coherent); - -#if CONFIG(CHROMEOS) - /* Retrieve the switch interface MAC addresses. */ - lb_table_add_macs_from_vpd(header); -#endif -} diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld deleted file mode 100644 index 14703291..0000000 --- a/src/mainboard/google/urara/memlayout.ld +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h deleted file mode 100644 index fbd9179..0000000 --- a/src/mainboard/google/urara/urara_boardid.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ -#define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ - -#include <stdint.h> - -/* - * List of URARA derivatives board ID definitions. They are stored in uint8_t - * across the code, using #defines here not to imply any specific size. - */ -#define URARA_BOARD_ID_BUB 0 -#define URARA_BOARD_ID_BURANKU 1 -#define URARA_BOARD_ID_DERWENT 2 -#define URARA_BOARD_ID_JAGUAR 3 -#define URARA_BOARD_ID_KENNET 4 -#define URARA_BOARD_ID_SPACE 5 - -struct board_hw { - uint8_t i2c_interface; -}; - -const struct board_hw *board_get_hw(void); - -#endif diff --git a/src/soc/imgtec/Kconfig b/src/soc/imgtec/Kconfig deleted file mode 100644 index 18c6ba1..0000000 --- a/src/soc/imgtec/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# Load all chipsets -source "src/soc/imgtec/*/Kconfig" diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig deleted file mode 100644 index 30d7bee..0000000 --- a/src/soc/imgtec/pistachio/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config CPU_IMGTEC_PISTACHIO - select ARCH_MIPS - select ARCH_BOOTBLOCK_MIPS - select ARCH_VERSTAGE_MIPS - select ARCH_ROMSTAGE_MIPS - select ARCH_RAMSTAGE_MIPS - select HAVE_UART_SPECIAL - select GENERIC_GPIO_LIB - select UART_OVERRIDE_REFCLK - bool - -if CPU_IMGTEC_PISTACHIO - -config BOOTBLOCK_CPU_INIT - string - default "soc/imgtec/pistachio/bootblock.c" - -endif diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc deleted file mode 100644 index 6e8d539..0000000 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y) - -# We enable CBFS_SPI_WRAPPER for Pistachio targets. -bootblock-y += clocks.c -bootblock-y += spi.c -romstage-y += spi.c -ramstage-y += spi.c - -bootblock-y += uart.c -romstage-y += uart.c -ramstage-y += uart.c - -bootblock-y += monotonic_timer.c - -ramstage-y += cbmem.c -ramstage-y += monotonic_timer.c -ramstage-y += soc.c -ramstage-y += reset.c - -romstage-y += cbmem.c -romstage-y += ddr2_init.c -romstage-y += ddr3_init.c -romstage-y += romstage.c -romstage-y += monotonic_timer.c - -CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ - -# Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL) - @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" - $(BIMGTOOL) $< $@ $(call loadaddr,bootblock) - -endif diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c deleted file mode 100644 index ac4a740..0000000 --- a/src/soc/imgtec/pistachio/bootblock.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/mmu.h> -#include <assert.h> -#include <stdint.h> -#include <symbols.h> - -static void bootblock_cpu_init(void) -{ - uint32_t cause; - - /* - * Make sure the count register is counting by clearing the "Disable - * Counter" bit, in case it is set. - */ - cause = read_c0_cause(); - if (cause & C0_CAUSE_DC) - write_c0_cause(cause & ~(C0_CAUSE_DC)); - - /* And make sure that it starts from zero. */ - write_c0_count(0); -} - -static void bootblock_mmu_init(void) -{ - uint32_t null_guard_size = 1 * MiB; - uint32_t dram_base, dram_size; - - write_c0_wired(0); - - dram_base = (uint32_t)_dram; - dram_size = CONFIG_DRAM_SIZE_MB * MiB; - - /* - * To be able to catch NULL pointer dereference attempts, lets not map - * memory close to zero. - */ - if (dram_base < null_guard_size) { - dram_base += null_guard_size; - dram_size -= null_guard_size; - } - assert(!identity_map((uint32_t)_sram, REGION_SIZE(sram), - C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map((uint32_t)_soc_registers, - REGION_SIZE(soc_registers), C0_ENTRYLO_COHERENCY_UC)); -} diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c deleted file mode 100644 index 112df7c..0000000 --- a/src/soc/imgtec/pistachio/cbmem.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stdlib.h> -#include <symbols.h> - -void *cbmem_top(void) -{ - return _dram + (CONFIG_DRAM_SIZE_MB << 20); -} diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c deleted file mode 100644 index aa54ebc..0000000 --- a/src/soc/imgtec/pistachio/clocks.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <assert.h> -#include <delay.h> -#include <soc/clocks.h> -#include <timer.h> - -/* Definitions for PLL enable */ -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 - -#define SYS_EXTERN_PLL_BYPASS_MASK 0x00002000 -#define SYS_PLL_CTRL4_ADDR 0xB8144048 -#define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 -#define SYS_PLL_DACPD_ADDR 0xB8144044 -#define SYS_PLL_DACPD_MASK 0x00000002 -#define SYS_PLL_DSMPD_ADDR 0xB8144044 -#define SYS_PLL_DSMPD_MASK 0x00000004 - -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 -#define MIPS_PLL_CTRL2_ADDR 0xB8144008 -#define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 -#define MIPS_PLL_DSMPD_ADDR 0xB8144004 -#define MIPS_PLL_DSMPD_MASK 0x02000000 - -/* Definitions for PLL dividers */ -#define SYS_PLL_POSTDIV_ADDR 0xB8144040 -#define SYS_PLL_POSTDIV1_MASK 0x07000000 -#define SYS_PLL_POSTDIV1_SHIFT 24 -#define SYS_PLL_POSTDIV2_MASK 0x38000000 -#define SYS_PLL_POSTDIV2_SHIFT 27 -#define SYS_PLL_STATUS_ADDR 0xB8144038 -#define SYS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define SYS_PLL_REFDIV_ADDR 0xB814403C -#define SYS_PLL_REFDIV_MASK 0x0000003F -#define SYS_PLL_REFDIV_SHIFT 0 -#define SYS_PLL_FEEDBACK_ADDR 0xB814403C -#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 -#define SYS_PLL_FEEDBACK_SHIFT 6 - -#define MIPS_PLL_POSTDIV_ADDR 0xB8144004 -#define MIPS_PLL_POSTDIV1_MASK 0x001C0000 -#define MIPS_PLL_POSTDIV1_SHIFT 18 -#define MIPS_PLL_POSTDIV2_MASK 0x00E00000 -#define MIPS_PLL_POSTDIV2_SHIFT 21 -#define MIPS_PLL_STATUS_ADDR 0xB8144000 -#define MIPS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define MIPS_REFDIV_ADDR 0xB8144004 -#define MIPS_REFDIV_MASK 0x0000003F -#define MIPS_REFDIV_SHIFT 0 -#define MIPS_FEEDBACK_ADDR 0xB8144004 -#define MIPS_FEEDBACK_MASK 0x0003FFC0 -#define MIPS_FEEDBACK_SHIFT 6 - -/* Definitions for system clock setup */ -#define SYSCLKINTERNAL_CTRL_ADDR 0xB8144244 -#define SYSCLKINTERNAL_MASK 0X00000007 - -/* Definitions for MIPS clock setup */ -#define MIPSCLKINTERNAL_CTRL_ADDR 0xB8144204 -#define MIPSCLKINTERNAL_MASK 0x00000003 -#define MIPSCLKOUT_CTRL_ADDR 0xB8144208 -#define MIPSCLKOUT_MASK 0x000000FF - -/* Peripheral Clock gate reg */ -#define MIPS_CLOCK_GATE_ADDR 0xB8144900 -#define RPU_CLOCK_GATE_ADDR 0xB8144904 -#define MIPS_CLOCK_GATE_ALL_ON 0x3fff -#define RPU_CLOCK_GATE_ALL_OFF 0x0 - -/* Definitions for USB clock setup */ -#define USBPHYCLKOUT_CTRL_ADDR 0xB814422C -#define USBPHYCLKOUT_MASK 0X0000003F -#define USBPHYCONTROL1_ADDR 0xB8149004 -#define USBPHYCONTROL1_FSEL_SHIFT 2 -#define USBPHYCONTROL1_FSEL_MASK 0x1C -#define USBPHYSTRAPCTRL_ADDR 0xB8149010 -#define USBPHYSTRAPCTRL_REFCLKSEL_SHIFT 4 -#define USBPHYSTRAPCTRL_REFCLKSEL_MASK 0x30 -#define USBPHYSTATUS_ADDR 0xB8149014 -#define USBPHYSTATUS_RX_PHY_CLK_MASK 0x200 -#define USBPHYSTATUS_RX_UTMI_CLK_MASK 0x100 -#define USBPHYSTATUS_VBUS_FAULT_MASK 0x80 - -/* Definitions for UART0/1 setup */ -#define UART0CLKINTERNAL_CTRL_ADDR 0xB8144234 -#define UART0CLKINTERNAL_MASK 0x00000007 -#define UART0CLKOUT_CTRL_ADDR 0xB8144238 -#define UART0CLKOUT_MASK 0x000003FF -#define UART1CLKINTERNAL_CTRL_ADDR 0xB814423C -#define UART1CLKINTERNAL_MASK 0x00000007 -#define UART1CLKOUT_CTRL_ADDR 0xB8144240 -#define UART1CLKOUT_MASK 0x000003FF - -/* Definitions for I2C setup */ -#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144800 + 0x013C + (2*(i)*4)) -#define I2CCLKDIV1_MASK 0x0000007F -#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144800 + 0x0140 + (2*(i)*4)) -#define I2CCLKOUT_MASK 0x0000007F - -/* Definitions for ROM clock setup */ -#define ROMCLKOUT_CTRL_ADDR 0xB814490C -#define ROMCLKOUT_MASK 0x0000007F - -/* Definitions for ETH clock setup */ -#define ENETCLKMUX_MASK 0x00004000 -#define ENETCLKDIV_CTRL_ADDR 0xB8144230 -#define ENETCLKDIV_MASK 0x0000003F - -/* Definitions for timeout values */ -#define PLL_TIMEOUT_VALUE_US 20000 -#define USB_TIMEOUT_VALUE_US 200000 -#define SYS_CLK_LOCK_DELAY 3 - -struct pll_parameters { - u32 external_bypass_mask; - u32 ctrl_addr; - u32 internal_bypass_mask; - u32 power_down_ctrl_addr; - u32 power_down_ctrl_mask; - u32 dacpd_addr; - u32 dacpd_mask; - u32 dsmpd_addr; - u32 dsmpd_mask; - u32 postdiv_addr; - u32 postdiv1_shift; - u32 postdiv1_mask; - u32 postdiv2_shift; - u32 postdiv2_mask; - u32 status_addr; - u32 status_lock_mask; - u32 refdivider; - u32 refdiv_addr; - u32 refdiv_shift; - u32 refdiv_mask; - u32 feedback; - u32 feedback_addr; - u32 feedback_shift; - u32 feedback_mask; -}; - -enum plls { - SYS_PLL = 0, - MIPS_PLL = 1 -}; - -static struct pll_parameters pll_params[] = { - [SYS_PLL] = { - .external_bypass_mask = SYS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = SYS_PLL_CTRL4_ADDR, - .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, - /* Noise cancellation */ - .dacpd_addr = SYS_PLL_DACPD_ADDR, - .dacpd_mask = SYS_PLL_DACPD_MASK, - .dsmpd_addr = SYS_PLL_DSMPD_ADDR, - /* 0 - Integer mode - * SYS_PLL_DSMPD_MASK - Fractional mode - */ - .dsmpd_mask = 0, - .postdiv_addr = SYS_PLL_POSTDIV_ADDR, - .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, - .postdiv2_shift = SYS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = SYS_PLL_POSTDIV2_MASK, - .status_addr = SYS_PLL_STATUS_ADDR, - .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = SYS_PLL_REFDIV_ADDR, - .refdiv_shift = SYS_PLL_REFDIV_SHIFT, - .refdiv_mask = SYS_PLL_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = SYS_PLL_FEEDBACK_ADDR, - .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, - .feedback_mask = SYS_PLL_FEEDBACK_MASK - }, - - [MIPS_PLL] = { - .external_bypass_mask = MIPS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = MIPS_PLL_CTRL2_ADDR, - .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, - .dacpd_addr = 0, - .dacpd_mask = 0, - .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, - .dsmpd_mask = MIPS_PLL_DSMPD_MASK, - .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, - .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, - .postdiv2_shift = MIPS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = MIPS_PLL_POSTDIV2_MASK, - .status_addr = MIPS_PLL_STATUS_ADDR, - .status_lock_mask = MIPS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = MIPS_REFDIV_ADDR, - .refdiv_shift = MIPS_REFDIV_SHIFT, - .refdiv_mask = MIPS_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = MIPS_FEEDBACK_ADDR, - .feedback_shift = MIPS_FEEDBACK_SHIFT, - .feedback_mask = MIPS_FEEDBACK_MASK - } -}; - -static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!((divider1 << param->postdiv1_shift) & - ~(param->postdiv1_mask))); - assert(!((divider2 << param->postdiv2_shift) & - ~(param->postdiv2_mask))); - - /* Temporary bypass PLL (select XTAL as clock input) */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg &= ~(param->external_bypass_mask); - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - /* Un-bypass PLL's internal bypass */ - reg = read32_x(param->ctrl_addr); - reg &= ~(param->internal_bypass_mask); - write32_x(param->ctrl_addr, reg); - - /* Disable power down */ - reg = read32_x(param->power_down_ctrl_addr); - reg &= ~(param->power_down_ctrl_mask); - write32_x(param->power_down_ctrl_addr, reg); - - /* Noise cancellation */ - if (param->dacpd_addr) { - reg = read32_x(param->dacpd_addr); - reg &= ~(param->dacpd_mask); - write32_x(param->dacpd_addr, reg); - } - - /* Functional mode */ - if (param->dsmpd_addr) { - reg = read32_x(param->dsmpd_addr); - reg &= ~(param->dsmpd_mask); - write32_x(param->dsmpd_addr, reg); - } - - if (param->feedback_addr) { - assert(!((param->feedback << param->feedback_shift) & - ~(param->feedback_mask))); - reg = read32_x(param->feedback_addr); - reg &= ~(param->feedback_mask); - reg |= (param->feedback << param->feedback_shift) & - param->feedback_mask; - write32_x(param->feedback_addr, reg); - } - - if (param->refdiv_addr) { - assert(!((param->refdivider << param->refdiv_shift) & - ~(param->refdiv_mask))); - reg = read32_x(param->refdiv_addr); - reg &= ~(param->refdiv_mask); - reg |= (param->refdivider << param->refdiv_shift) & - param->refdiv_mask; - write32_x(param->refdiv_addr, reg); - } - - /* Read postdivider register value */ - reg = read32_x(param->postdiv_addr); - /* Set divider 1 */ - reg &= ~(param->postdiv1_mask); - reg |= (divider1 << param->postdiv1_shift) & - param->postdiv1_mask; - /* Set divider 2 */ - reg &= ~(param->postdiv2_mask); - reg |= (divider2 << param->postdiv2_shift) & - param->postdiv2_mask; - /* Write back to register */ - write32_x(param->postdiv_addr, reg); - - /* Waiting for PLL to lock*/ - stopwatch_init_usecs_expire(&sw, PLL_TIMEOUT_VALUE_US); - while (!(read32_x(param->status_addr) & param->status_lock_mask)) { - if (stopwatch_expired(&sw)) - return PLL_TIMEOUT; - } - - /* Start using PLL */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= param->external_bypass_mask; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - return CLOCKS_OK; -} - -int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[SYS_PLL].refdivider = refdivider; - pll_params[SYS_PLL].feedback = feedback; - return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); -} - -int mips_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[MIPS_PLL].refdivider = refdivider; - pll_params[MIPS_PLL].feedback = feedback; - return pll_setup(&(pll_params[MIPS_PLL]), divider1, divider2); -} - -/* - * uart1_clk_setup: sets up clocks for UART1 - * divider1: 3-bit divider value - * divider2: 10-bit divider value - */ -void uart1_clk_setup(u8 divider1, u16 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(UART1CLKINTERNAL_MASK))); - assert(!(divider2 & ~(UART1CLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(UART1CLKINTERNAL_CTRL_ADDR); - reg &= ~UART1CLKINTERNAL_MASK; - reg |= divider1 & UART1CLKINTERNAL_MASK; - write32_x(UART1CLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(UART1CLKOUT_CTRL_ADDR); - reg &= ~UART1CLKOUT_MASK; - reg |= divider2 & UART1CLKOUT_MASK; - write32_x(UART1CLKOUT_CTRL_ADDR, reg); -} - -/* - * i2c_clk_setup: sets up clocks for I2C - * divider1: 7-bit divider value - * divider2: 7-bit divider value - */ -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(I2CCLKDIV1_MASK))); - assert(!(divider2 & ~(I2CCLKOUT_MASK))); - assert(interface < 4); - /* Set divider 1 */ - reg = read32_x(I2CCLKDIV1_CTRL_ADDR(interface)); - reg &= ~I2CCLKDIV1_MASK; - reg |= divider1 & I2CCLKDIV1_MASK; - write32_x(I2CCLKDIV1_CTRL_ADDR(interface), reg); - - /* Set divider 2 */ - reg = read32_x(I2CCLKOUT_CTRL_ADDR(interface)); - reg &= ~I2CCLKOUT_MASK; - reg |= divider2 & I2CCLKOUT_MASK; - write32_x(I2CCLKOUT_CTRL_ADDR(interface), reg); -} - -/* system_clk_setup: sets up the system (peripheral) clock */ -void system_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(SYSCLKINTERNAL_MASK))); - - /* Set system clock divider */ - reg = read32_x(SYSCLKINTERNAL_CTRL_ADDR); - reg &= ~SYSCLKINTERNAL_MASK; - reg |= divider & SYSCLKINTERNAL_MASK; - write32_x(SYSCLKINTERNAL_CTRL_ADDR, reg); - - /* Small delay to cover a maximum lock time of 1500 cycles */ - udelay(SYS_CLK_LOCK_DELAY); -} - -void mips_clk_setup(u8 divider1, u8 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(MIPSCLKINTERNAL_MASK))); - assert(!(divider2 & ~(MIPSCLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(MIPSCLKINTERNAL_CTRL_ADDR); - reg &= ~MIPSCLKINTERNAL_MASK; - reg |= divider1 & MIPSCLKINTERNAL_MASK; - write32_x(MIPSCLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(MIPSCLKOUT_CTRL_ADDR); - reg &= ~MIPSCLKOUT_MASK; - reg |= divider2 & MIPSCLKOUT_MASK; - write32_x(MIPSCLKOUT_CTRL_ADDR, reg); -} - -/* usb_clk_setup: sets up USB clock */ -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!(divider & ~(USBPHYCLKOUT_MASK))); - assert(!((refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - ~(USBPHYSTRAPCTRL_REFCLKSEL_MASK))); - assert(!((fsel << USBPHYCONTROL1_FSEL_SHIFT) & - ~(USBPHYCONTROL1_FSEL_MASK))); - - /* Set USB divider */ - reg = read32_x(USBPHYCLKOUT_CTRL_ADDR); - reg &= ~USBPHYCLKOUT_MASK; - reg |= divider & USBPHYCLKOUT_MASK; - write32_x(USBPHYCLKOUT_CTRL_ADDR, reg); - - /* Set REFCLKSEL */ - reg = read32_x(USBPHYSTRAPCTRL_ADDR); - reg &= ~USBPHYSTRAPCTRL_REFCLKSEL_MASK; - reg |= (refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - USBPHYSTRAPCTRL_REFCLKSEL_MASK; - write32_x(USBPHYSTRAPCTRL_ADDR, reg); - - /* Set FSEL */ - reg = read32_x(USBPHYCONTROL1_ADDR); - reg &= ~USBPHYCONTROL1_FSEL_MASK; - reg |= (fsel << USBPHYCONTROL1_FSEL_SHIFT) & - USBPHYCONTROL1_FSEL_MASK; - write32_x(USBPHYCONTROL1_ADDR, reg); - - /* Waiting for USB clock status */ - stopwatch_init_usecs_expire(&sw, USB_TIMEOUT_VALUE_US); - while (1) { - reg = read32_x(USBPHYSTATUS_ADDR); - if (reg & USBPHYSTATUS_VBUS_FAULT_MASK) - return USB_VBUS_FAULT; - if (stopwatch_expired(&sw)) - return USB_TIMEOUT; - /* Check if USB is set up properly */ - if ((reg & USBPHYSTATUS_RX_PHY_CLK_MASK) && - (reg & USBPHYSTATUS_RX_UTMI_CLK_MASK)) - break; - } - - return CLOCKS_OK; -} - -void rom_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameter */ - assert(!(divider & ~(ROMCLKOUT_MASK))); - - /* Set ROM divider */ - reg = read32_x(ROMCLKOUT_CTRL_ADDR); - reg &= ~ROMCLKOUT_MASK; - reg |= divider & ROMCLKOUT_MASK; - write32_x(ROMCLKOUT_CTRL_ADDR, reg); -} - -void eth_clk_setup(u8 mux, u8 divider) -{ - - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(ENETCLKDIV_MASK))); - /* This can be either 0 or 1, selecting between - * ENET and system clock as clocksource */ - assert(!(mux & ~(0x1))); - - /* Set ETH divider */ - reg = read32_x(ENETCLKDIV_CTRL_ADDR); - reg &= ~ENETCLKDIV_MASK; - reg |= divider & ENETCLKDIV_MASK; - write32_x(ENETCLKDIV_CTRL_ADDR, reg); - - /* Select source */ - if (mux) { - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= ENETCLKMUX_MASK; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - } -} - -void setup_clk_gate_defaults(void) -{ - write32_x(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); - write32_x(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); -} diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c deleted file mode 100644 index 39b553d..0000000 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <soc/ddr_init.h> -#include <soc/ddr_private_reg.h> -#include <stdint.h> - -#define BL8 0 - -/* - * Configuration for the Winbond W972GG6JB-25 part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr2(void) -{ - - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - note must be done together, - * not sequentially - */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* - * Dummy read to fence the access between the reset above - * and thw DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 0 = 4 1 = 8 - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 0 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, - 0x00060000 | (BL8 ? 0x1 : 0x0)); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR2 2 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); - /* Generate to use with PHY and PCTL - * MR0 : MR Register, bits 12:0 imported dfrom MR - * 2:0 BL 8 011 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (101) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); - /* MR1 : EMR Register - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 1 DIC Output Driver Imp Ctl 0 Full, 1 Half - * 6,2 ODT 0 Disable, 1 75R, 2 150R, 3 50R; LSB: 2, MSB: 6 - * 5:3 AL = 0 - * 9:7 OCD = 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 RDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); - /* MR2 : EMR2 Register - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 DDC NA 0 - * 6:4 RSVD - * 7 SFR 0 - * 15:8 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 0 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 2 - * 4:2 tRTP 3 - * 7:5 tWTR 3 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 18 - * 24:21 tRRD 4 - * 30:25 tRC 24 (23) - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 4 Bank Act 45ns = 18 18 - * 10:9 tMOD DDR3 Only 0 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 195ns 78 def 131 78d - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 200, 200d - * 14:10 tXP PD Exit Del 8 3 - * 18:15 tCKE CKE Min pulse 3 - * 28:19 tDLLK DLL Lock time 200d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880 - * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : use PHY for DRAM Init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra tRPall 8 bank 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* - * TRAS : Activate to Precharge cmd time - * Range 8 to 24: 45ns / 2.5ns = 18d - */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); - /* - * TRC : Min. ROW cycle time - * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); - /* - * TRCD : Row to Column Delay - * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* - * TWTR : Write to read turn around time - * Range 2 to 4: 7.3ns / 2.5ns = 3 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); - /* - * TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* - * TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* - * TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* - * TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001)) - return DDR_TIMEOUT; - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 0 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 4 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - if (BL8) - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - else - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c deleted file mode 100644 index 7392525..0000000 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/mmio.h> -#include <soc/ddr_init.h> -#include <soc/ddr_private_reg.h> - -/* - * Configuration for the Winbond W631GG6KB part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr3(void) -{ - uint32_t temp_rw_val; - - temp_rw_val = read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Set CLK_EN = 1 */ - temp_rw_val |= 0x2; - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - */ - /* Drive the 3 resets low */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* And release */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* Dummy read to fence the access between the reset above and - * the DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 1 -> 8 fixed - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 1 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR3 3 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B); - /* Generate to use with PHY and PCTL - * MR0 : DDR3 mode register 0 - * 1:0 BL 8 fixed 00 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4,2 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (010) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520); - /* MR1 : DDR3 mode register 1 - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 5,1 DIC Output Driver RZQ/6 - * 9,6,2 ODT RZQ/4 - * 4:3 AL = 0 - * 7 write leveling enabled 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 TDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004); - /* MR2 : DDR3 mode register 2 - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 CWL 000 (5) tck = 22.5ns - * 6 auto self-refresh 1 - * 7 SRT normal 0 - * 8 RSVD - * 10:9 dynamic ODT 10 RZQ/2 - * 31:11 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440); - /* MR3: DDR3 mode register 3 - * 1:0 MPRLOC 00 - * 2 MPR 0 - */ - write32_x(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000); - /* DTAR : Data Training Register - * 11:0 Data Training Column Address - * 27:12 Data Training Row Address - * 30:28 Data Training Bank Address - * 31 Data Training Use MPR (DDR3 Only) - */ - write32_x(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 1 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 0 - * 4:2 tRTP 2 - * 7:5 tWTR 4 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 15 - * 24:21 tRRD 4 for x16 - * 30:25 tRC 21 - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 20 Clk - * 10:9 tMOD DDR3 Only 15 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 160ns 64 ref 131 - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 512d - * 14:10 tXP PD Exit Del 8 5 - * 18:15 tCKE CKE Min pulse 5 - * 28:19 tDLLK DLL Lock time 512d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40 - * 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : PHY controlled init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : controller DRAM initialization */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F)) - return DDR_TIMEOUT; - /********************************************************************/ - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra DDR3 - value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F); - /* TRC : Min. ROW cycle time 21 - * 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015); - /* TRCD : Row to Column Delay # Range 3 to 7 (TCL = TRCD) - * 12.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6 - * 2K Page 10ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* TWTR : Write to read turn around time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200); - /* TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /* TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004); - /* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */ - write32_x(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F); - /* TZQCS : SDRAM ZQ Calibration Short Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040); - /* TZQCL : SDRAM ZQ Calibration Long Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* TREFI_MEM_DDR3 */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30); - - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 1 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 0 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000); - - /* Memory initialization */ - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - /* MCMD: MR2 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403)) - return DDR_TIMEOUT; - /* MCMD: MR3 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003)) - return DDR_TIMEOUT; - /* MCMD: MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043)) - return DDR_TIMEOUT; - /* MCMD: MR0 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203)) - return DDR_TIMEOUT; - /* MCMD: ZQS cmd, long 5 short 4 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A)) - return DDR_TIMEOUT; - - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* STAT : Wait for Switch INIT to Config State */ - write32_x(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* Use PHY for DRAM init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h deleted file mode 100644 index 27ba6d6..0000000 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ -#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ - -#include <stdint.h> - -/* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); -int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); - -/* Peripheral divider setting */ -void system_clk_setup(u8 divider); -void mips_clk_setup(u8 divider1, u8 divider2); -void uart1_clk_setup(u8 divider1, u16 divider2); -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); -void rom_clk_setup(u8 divider); -void eth_clk_setup(u8 mux, u8 divider); -void setup_clk_gate_defaults(void); -enum { - CLOCKS_OK = 0, - PLL_TIMEOUT = -1, - USB_TIMEOUT = -2, - USB_VBUS_FAULT = -3 -}; - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h deleted file mode 100644 index c22dceb..0000000 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_DANUBE_CPU_H__ -#define __SOC_IMGTEC_DANUBE_CPU_H__ - -#include <device/mmio.h> - -#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 -#define IMG_SPIM1_BASE_ADDRESS 0xB8101000 - -/* - * This register holds the FPGA image version - * If we're not working on the FPGA this will be 0 - */ -#define PRIMARY_FPGA_VERSION 0xB8149060 -#define IMG_PLATFORM_ID() read32_x(PRIMARY_FPGA_VERSION) -#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ -#define IMG_PLATFORM_ID_SILICON 0 - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_init.h b/src/soc/imgtec/pistachio/include/soc/ddr_init.h deleted file mode 100644 index d8b5b19..0000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_init.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ - -#define DDR_TIMEOUT -1 - -int init_ddr2(void); -int init_ddr3(void); - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h deleted file mode 100644 index eab5b3a..0000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ - -#include <device/mmio.h> -#include <timer.h> - -#define MAX_WAIT_MICROS 100000 - -#define TOPLEVEL_REGS 0xB8149000 - -#define DDR_CTRL_OFFSET (0x0020) -#define DDR_CLK_EN_MASK (0x00000002) -#define DDR_CLK_EN_SHIFT (1) -#define DDR_CLK_EN_LENGTH (1) - -#define DDR_PCTL 0xB8180000 -#define DDR_PCTL_SCFG_OFFSET (0x0000) -#define DDR_PCTL_SCTL_OFFSET (0x0004) -#define DDR_PCTL_STAT_OFFSET (0x0008) -#define DDR_PCTL_MCMD_OFFSET (0x0040) -#define DDR_PCTL_POWCTL_OFFSET (0x0044) -#define DDR_PCTL_POWSTAT_OFFSET (0x0048) -#define DDR_PCTL_CMDTSTAT_OFFSET (0x004C) -#define DDR_PCTL_CMDTSTATEN_OFFSET (0x0050) -#define DDR_PCTL_MCFG1_OFFSET (0x007C) -#define DDR_PCTL_MCFG_OFFSET (0x0080) -#define DDR_PCTL_MSTAT_OFFSET (0x0088) -#define DDR_PCTL_DTUAWDT_OFFSET (0x00B0) -#define DDR_PCTL_TOGCNT1U_OFFSET (0x00C0) -#define DDR_PCTL_TINIT_OFFSET (0x00C4) -#define DDR_PCTL_TRSTH_OFFSET (0x00C8) -#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET (0x00CC) -#define DDR_PCTL_TREFI_OFFSET (0x00D0) -#define DDR_PCTL_TMRD_OFFSET (0x00D4) -#define DDR_PCTL_TRFC_OFFSET (0x00D8) -#define DDR_PCTL_TRP_OFFSET (0x00DC) -#define DDR_PCTL_TRTW_OFFSET (0x00E0) -#define DDR_PCTL_TAL_OFFSET (0x00E4) -#define DDR_PCTL_TCL_OFFSET (0x00E8) -#define DDR_PCTL_TCWL_OFFSET (0x00EC) -#define DDR_PCTL_TRAS_OFFSET (0x00F0) -#define DDR_PCTL_TRC_OFFSET (0x00F4) -#define DDR_PCTL_TRCD_OFFSET (0x00F8) -#define DDR_PCTL_TRRD_OFFSET (0x00FC) -#define DDR_PCTL_TRTP_OFFSET (0x0100) -#define DDR_PCTL_TWR_OFFSET (0x0104) -#define DDR_PCTL_TWTR_OFFSET (0x0108) -#define DDR_PCTL_TEXSR_OFFSET (0x010C) -#define DDR_PCTL_TXP_OFFSET (0x0110) -#define DDR_PCTL_TXPDLL_OFFSET (0x0114) -#define DDR_PCTL_TZQCS_OFFSET (0x0118) -#define DDR_PCTL_TDQS_OFFSET (0x0120) -#define DDR_PCTL_TCKE_OFFSET (0x012C) -#define DDR_PCTL_TMOD_OFFSET (0x0130) -#define DDR_PCTL_TZQCL_OFFSET (0x0138) -#define DDR_PCTL_TCKESR_OFFSET (0x0140) -#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET (0x0148) -#define DDR_PCTL_DTUWACTL_OFFSET (0x0200) -#define DDR_PCTL_DTURACTL_OFFSET (0x0204) -#define DDR_PCTL_DTUCFG_OFFSET (0x0208) -#define DDR_PCTL_DTUECTL_OFFSET (0x020C) -#define DDR_PCTL_DTUWD0_OFFSET (0x0210) -#define DDR_PCTL_DTUWD1_OFFSET (0x0214) -#define DDR_PCTL_DTUWD2_OFFSET (0x0218) -#define DDR_PCTL_DTUWD3_OFFSET (0x021C) -#define DDR_PCTL_DFIODTCFG_OFFSET (0x0244) -#define DDR_PCTL_DFIODTCFG1_OFFSET (0x0248) -#define DDR_PCTL_DFITPHYWRDATA_OFFSET (0x0250) -#define DDR_PCTL_DFIWRLAT_OFFSET (0x0254) -#define DDR_PCTL_DFITRDDATAEN_OFFSET (0x0260) -#define DDR_PCTL_DFITPHYRDLAT_OFFSET (0x0264) -#define DDR_PCTL_DFIUPDCFG_OFFSET (0x0290) -#define DDR_PCTL_DFISTAT0_OFFSET (0x02C0) -#define DDR_PCTL_DFISTCFG0_OFFSET (0x02C4) -#define DDR_PCTL_DFISTCFG1_OFFSET (0x02C8) -#define DDR_PCTL_DFISTCFG2_OFFSET (0x02D8) -#define DDR_PCTL_DFILPCFG0_OFFSET (0x02F0) -#define DDR_PCTL_PCFG0_OFFSET (0x0400) -#define DDR_PCTL_CCFG_OFFSET (0x0480) -#define DDR_PCTL_DCFG_OFFSET (0x0484) -#define DDR_PCTL_CCFG1_OFFSET (0x048C) - -#define DDR_PHY 0xB8180800 -#define DDRPHY_PIR_OFFSET (0x0004) -#define DDRPHY_PGCR_OFFSET (0x0008) -#define DDRPHY_PGSR_OFFSET (0x000C) -#define DDRPHY_DLLGCR_OFFSET (0x0010) -#define DDRPHY_PTR0_OFFSET (0x0018) -#define DDRPHY_PTR1_OFFSET (0x001C) -#define DDRPHY_DXCCR_OFFSET (0x0028) -#define DDRPHY_DSGCR_OFFSET (0x002C) -#define DDRPHY_DCR_OFFSET (0x0030) -#define DDRPHY_DTPR0_OFFSET (0x0034) -#define DDRPHY_DTPR1_OFFSET (0x0038) -#define DDRPHY_DTPR2_OFFSET (0x003C) -#define DDRPHY_MR_OFFSET (0x0040) -#define DDRPHY_EMR_OFFSET (0x0044) -#define DDRPHY_EMR2_OFFSET (0x0048) -#define DDRPHY_EMR3_OFFSET (0x004C) -#define DDRPHY_DTAR_OFFSET (0x0054) -#define DDRPHY_BISTRR_OFFSET (0x0100) -#define DDRPHY_BISTWCR_OFFSET (0x010C) -#define DDRPHY_BISTAR0_OFFSET (0x0114) -#define DDRPHY_BISTAR1_OFFSET (0x0118) -#define DDRPHY_BISTAR2_OFFSET (0x011C) -#define DDRPHY_BISTUDPR_OFFSET (0x0120) -#define DDRPHY_BISTGSR_OFFSET (0x0124) -#define DDRPHY_ZQ0CR0_OFFSET (0x0180) -#define DDRPHY_ZQ1CR0_OFFSET (0x0190) - -#define DDR_TIMEOUT_VALUE_US 100000 - -static int wait_for_completion(u32 reg, u32 exp_val) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US); - while (read32_x(reg) != exp_val) { - if (stopwatch_expired(&sw)) - return DDR_TIMEOUT; - } - return 0; -} - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h deleted file mode 100644 index f2427f24..0000000 --- a/src/soc/imgtec/pistachio/include/soc/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__ -#define __SOC_IMGTECH_PISTACHIO_GPIO_H__ - -typedef unsigned gpio_t; - -#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__ diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld deleted file mode 100644 index cd81093..0000000 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* SRAM memory is mapped in two different locations. Define regions in both for - * full overlap checking and use this to guarantee they're kept in sync. */ -#define ASSERT_MIRRORED(r1, r2) \ - _ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \ - (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \ - STR(r1 and r2 do not match!)); - -SECTIONS -{ - /* - * All of DRAM (other than the DMA coherent area) is accessed through - * the identity mapping. - */ - DRAM_START(0x00000000) - /* DMA coherent area: accessed via KSEG1. */ - DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 512K) - RAMSTAGE(0x00280000, 128K) - - /* 0x18100000 -> 0x18540000 */ - SOC_REGISTERS(0x18100000, 0x440000) - /* - * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock - * and then through the identity mapping in ROM stage. - */ - SRAM_START(0x1a000000) - REGION(gram_bootblock, 0x1a000000, 28K, 1) - ROMSTAGE(0x1a007000, 60K) - VBOOT2_WORK(0x1a016000, 12K) - VBOOT2_TPM_LOG(0x1a019000, 2K) - PRERAM_CBFS_CACHE(0x1a019800, 46K) - SRAM_END(0x1a066000) - - /* Bootblock executes out of KSEG0 and sets up the identity mapping. - * This is identical to SRAM above, and thus also limited 64K and - * needs to avoid conflicts with items set up above. - */ - BOOTBLOCK(0x9a000000, 28K) - REGION(kseg0_romstage, 0x9a007000, 60K, 1) - - /* - * Let's use SRAM for stack and CBMEM console. Always accessed - * through KSEG0. - */ - STACK(0x9b000000, 8K) - PRERAM_CBMEM_CONSOLE(0x9b002000, 8K) - -} - -ASSERT_MIRRORED(bootblock, gram_bootblock) -ASSERT_MIRRORED(romstage, kseg0_romstage) diff --git a/src/soc/imgtec/pistachio/include/soc/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h deleted file mode 100644 index f23cca5..0000000 --- a/src/soc/imgtec/pistachio/include/soc/spi.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef __SOC_IMGTEC_DANUBE_SPI_H__ -#define __SOC_IMGTEC_DANUBE_SPI_H__ - -#include <arch/types.h> - -#define spi_read_reg_field(regval, field) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (regval) : \ - (((regval) & (field##_MASK)) >> (field##_SHIFT))\ -) - -#define spi_write_reg_field(regval, field, val) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (val) : \ - (((regval) & ~(field##_MASK)) | \ - (((val) << (field##_SHIFT)) & (field##_MASK))) \ -) - -/* - * Parameter register - * Each of these corresponds to a single port (ie CS line) in the interface - * Fields Name Description - * ====== ==== =========== - * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz - * b23:16 CS_SETUP Chip Select setup = (40 * value) ns - * b15:8 CS_HOLD Chip Select hold = (40 * value) ns - * b7:0 CS_DELAY Chip Select delay = (40 * value) ns - */ - -#define SPIM_CLK_DIVIDE_MASK (0xFF000000) -#define SPIM_CS_SETUP_MASK (0x00FF0000) -#define SPIM_CS_HOLD_MASK (0x0000FF00) -#define SPIM_CS_DELAY_MASK (0x000000FF) -#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \ - | SPIM_CS_HOLD_MASK \ - | SPIM_CS_DELAY_MASK) - -#define SPIM_CLK_DIVIDE_SHIFT (24) -#define SPIM_CS_SETUP_SHIFT (16) -#define SPIM_CS_HOLD_SHIFT (8) -#define SPIM_CS_DELAY_SHIFT (0) -#define SPIM_CS_PARAM_SHIFT (0) - -/* Control register */ - -#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000) -#define SPFI_MEMORY_IF_MASK (0x00008000) -#define SPIM_BYTE_DELAY_MASK (0x00004000) -#define SPIM_CS_DEASSERT_MASK (0x00002000) -#define SPIM_CONTINUE_MASK (0x00001000) -#define SPIM_SOFT_RESET_MASK (0x00000800) -#define SPIM_SEND_DMA_MASK (0x00000400) -#define SPIM_GET_DMA_MASK (0x00000200) -#define SPIM_EDGE_TX_RX_MASK (0x00000100) -#define SPFI_TRNSFR_MODE_MASK (0x000000e0) -#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c) -#define SPFI_TX_RX_MASK (0x00000002) -#define SPFI_EN_MASK (0x00000001) - -#define SPFI_DRIBBLE_COUNT_SHIFT (17) -#define SPFI_MEMORY_IF_SHIFT (15) -#define SPIM_BYTE_DELAY_SHIFT (14) -#define SPIM_CS_DEASSERT_SHIFT (13) -#define SPIM_CONTINUE_SHIFT (12) -#define SPIM_SOFT_RESET_SHIFT (11) -#define SPIM_SEND_DMA_SHIFT (10) -#define SPIM_GET_DMA_SHIFT (9) -#define SPIM_EDGE_TX_RX_SHIFT (8) -#define SPFI_TRNSFR_MODE_SHIFT (5) -#define SPFI_TRNSFR_MODE_DQ_SHIFT (2) -#define SPFI_TX_RX_SHIFT (1) -#define SPFI_EN_SHIFT (0) - -/* Transaction register */ - -#define SPFI_TSIZE_MASK (0xffff0000) -#define SPFI_CMD_LENGTH_MASK (0x0000e000) -#define SPFI_ADDR_LENGTH_MASK (0x00001c00) -#define SPFI_DUMMY_LENGTH_MASK (0x000003e0) -#define SPFI_PI_LENGTH_MASK (0x0000001c) - -#define SPFI_TSIZE_SHIFT (16) -#define SPFI_CMD_LENGTH_SHIFT (13) -#define SPFI_ADDR_LENGTH_SHIFT (10) -#define SPFI_DUMMY_LENGTH_SHIFT (5) -#define SPFI_PI_LENGTH_SHIFT (2) - -/* Port state register */ - -#define SPFI_PORT_SELECT_MASK (0x00700000) -/* WARNING the following bits are reversed */ -#define SPFI_CLOCK0_IDLE_MASK (0x000f8000) -#define SPFI_CLOCK0_PHASE_MASK (0x00007c00) -#define SPFI_CS0_IDLE_MASK (0x000003e0) -#define SPFI_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_CLOCK0_IDLE_MASK (0x000f8000) -#define SPIM_CLOCK0_PHASE_MASK (0x00007c00) -#define SPIM_CS0_IDLE_MASK (0x000003e0) -#define SPIM_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_PORT0_MASK (0x00084210) - -#define SPFI_PORT_SELECT_SHIFT (20) -/* WARNING the following bits are reversed, bit 0 is highest */ -#define SPFI_CLOCK0_IDLE_SHIFT (19) -#define SPFI_CLOCK0_PHASE_SHIFT (14) -#define SPFI_CS0_IDLE_SHIFT (9) -#define SPFI_DATA0_IDLE_SHIFT (4) - -#define SPIM_CLOCK0_IDLE_SHIFT (19) -#define SPIM_CLOCK0_PHASE_SHIFT (14) -#define SPIM_CS0_IDLE_SHIFT (9) -#define SPIM_DATA0_IDLE_SHIFT (4) - - -/* - * Interrupt registers - * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls - * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls - */ -#define SPFI_IACCESS_MASK (0x00001000) -#define SPFI_GDEX8BIT_MASK (0x00000800) -#define SPFI_ALLDONE_MASK (0x00000200) -#define SPFI_GDFUL_MASK (0x00000100) -#define SPFI_GDHF_MASK (0x00000080) -#define SPFI_GDEX32BIT_MASK (0x00000040) -#define SPFI_GDTRIG_MASK (0x00000020) -#define SPFI_SDFUL_MASK (0x00000008) -#define SPFI_SDHF_MASK (0x00000004) -#define SPFI_SDE_MASK (0x00000002) -#define SPFI_SDTRIG_MASK (0x00000001) - -#define SPFI_IACCESS_SHIFT (12) -#define SPFI_GDEX8BIT_SHIFT (11) -#define SPFI_ALLDONE_SHIFT (9) -#define SPFI_GDFUL_SHIFT (8) -#define SPFI_GDHF_SHIFT (7) -#define SPFI_GDEX32BIT_SHIFT (6) -#define SPFI_GDTRIG_SHIFT (5) -#define SPFI_SDFUL_SHIFT (3) -#define SPFI_SDHF_SHIFT (2) -#define SPFI_SDE_SHIFT (1) -#define SPFI_SDTRIG_SHIFT (0) - - -/* SPFI register block */ - -#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00) -#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04) -#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08) -#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C) -#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10) -#define SPFI_CONTROL_REG_OFFSET (0x14) -#define SPFI_TRANSACTION_REG_OFFSET (0x18) -#define SPFI_PORT_STATE_REG_OFFSET (0x1C) - -#define SPFI_SEND_LONG_REG_OFFSET (0x20) -#define SPFI_SEND_BYTE_REG_OFFSET (0x24) -#define SPFI_GET_LONG_REG_OFFSET (0x28) -#define SPFI_GET_BYTE_REG_OFFSET (0x2C) - -#define SPFI_INT_STATUS_REG_OFFSET (0x30) -#define SPFI_INT_ENABLE_REG_OFFSET (0x34) -#define SPFI_INT_CLEAR_REG_OFFSET (0x38) - -#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c) - -#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48) -#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C) - -#define IMG_FALSE 0 -#define IMG_TRUE 1 - -/* Number of SPIM interfaces*/ -#define SPIM_NUM_BLOCKS 2 -/* Number of chip select lines supported by the SPI master port. */ -#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS) -/* Maximum transfer size (in bytes) for the SPI master port. */ -#define SPIM_MAX_TRANSFER_BYTES (0xFFFF) -/* Maximum size of a flash command: command bytes+address_bytes. */ -#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8) -/* Write operation to fifo done in blocks of 16 words (64 bytes) */ -#define SPIM_MAX_BLOCK_BYTES (0x40) -/* Number of tries until timeout error is returned*/ -#define SPI_TIMEOUT_VALUE_US 500000 - -/* SPIM initialisation function return value.*/ -enum spim_return { - /* Initialisation parameters are valid. */ - SPIM_OK = 0, - /* Mode parameter is invalid. */ - SPIM_INVALID_SPI_MODE, - /* Chip select idle level is invalid. */ - SPIM_INVALID_CS_IDLE_LEVEL, - /* Data idle level is invalid. */ - SPIM_INVALID_DATA_IDLE_LEVEL, - /* Chip select line parameter is invalid. */ - SPIM_INVALID_CS_LINE, - /* Transfer size parameter is invalid. */ - SPIM_INVALID_SIZE, - /* Read/write parameter is invalid. */ - SPIM_INVALID_READ_WRITE, - /* Continue parameter is invalid. */ - SPIM_INVALID_CONTINUE, - /* Invalid block index */ - SPIM_INVALID_BLOCK_INDEX, - /* Extended error values */ - /* Invalid bit rate */ - SPIM_INVALID_BIT_RATE, - /* Invalid CS hold value */ - SPIM_INVALID_CS_HOLD_VALUE, - /* API function called before API is initialised */ - SPIM_API_NOT_INITIALISED, - /* SPI driver initialisation failed */ - SPIM_DRIVER_INIT_ERROR, - /* Invalid transfer description */ - SPIM_INVALID_TRANSFER_DESC, - /* Timeout */ - SPIM_TIMEOUT - -}; - -/* This type defines the SPI Mode.*/ -enum spim_mode { - /* Mode 0 (clock idle low, data valid on first clock transition). */ - SPIM_MODE_0 = 0, - /* Mode 1 (clock idle low, data valid on second clock transition). */ - SPIM_MODE_1, - /* Mode 2 (clock idle high, data valid on first clock transition). */ - SPIM_MODE_2, - /* Mode 3 (clock idle high, data valid on second clock transition). */ - SPIM_MODE_3 - -}; - -/* This type defines the SPIM device numbers (chip select lines). */ -enum spim_device { - /* Device 0 (CS0). */ - SPIM_DEVICE0 = 0, - /* Device 1 (CS1). */ - SPIM_DEVICE1, - /* Device 2 (CS2). */ - SPIM_DEVICE2, - /* Device 3 (CS3). */ - SPIM_DEVICE3, - /* Device 4 (CS4). */ - SPIM_DEVICE4, - /* Dummy chip select. */ - SPIM_DUMMY_CS - -}; - -/* This structure defines communication parameters for a slave device */ -struct spim_device_parameters { - /* Bit rate value.*/ - unsigned char bitrate; - /* - * Chip select set up time. - * Time taken between chip select going active and activity occurring - * on the clock, calculated by dividing the desired set up time in ns - * by the Input clock period. (setup time / Input clock freq) - */ - unsigned char cs_setup; - /* - * Chip select hold time. - * Time after the last clock pulse before chip select goes inactive, - * calculated by dividing the desired hold time in ns by the - * Input clock period (hold time / Input clock freq). - */ - unsigned char cs_hold; - /* - * Chip select delay time (CS minimum inactive time). - * Minimum time after chip select goes inactive before chip select - * can go active again, calculated by dividing the desired delay time - * in ns by the Input clock period (delay time / Input clock freq). - */ - unsigned char cs_delay; - /* SPI Mode. */ - enum spim_mode spi_mode; - /* Chip select idle level (0=low, 1=high, Others=invalid). */ - unsigned int cs_idle_level; - /* Data idle level (0=low, 1=high, Others=invalid). */ - unsigned int data_idle_level; - -}; - -/* Command transfer mode */ -enum command_mode { - /* Command, address, dummy and PI cycles are transferred on sio0 */ - SPIM_CMD_MODE_0 = 0, - /* - * Command and Address are transferred on sio0 port only but dummy - * cycles and PI is transferred on all the interface ports. - */ - SPIM_CMD_MODE_1, - /* - * Command is transferred on sio0 port only but address, dummy - * and PI is transferred on all the interface portS - */ - SPIM_CMD_MODE_2, - /* - * Command, address, dummy and PI bytes are transferred on all - * the interfaces - */ - SPIM_CMD_MODE_3 -}; - -/* Data transfer mode */ -enum transfer_mode { - /* Transfer data in single mode */ - SPIM_DMODE_SINGLE = 0, - /* Transfer data in dual mode */ - SPIM_DMODE_DUAL, - /* Transfer data in quad mode */ - SPIM_DMODE_QUAD -}; - -/* This structure contains parameters that describe an SPIM operation. */ -struct spim_buffer { - /* The buffer to read from or write to. */ - unsigned char *buffer; - - /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */ - unsigned int size; - - /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/ - int isread; - - /* - * ByteDelay select. - * Selects whether or not a delay is inserted between bytes. - * 0 - Minimum inter-byte delay - * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk. - */ - int inter_byte_delay; -}; - -#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */ diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c deleted file mode 100644 index bbcd8a1..0000000 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <device/mmio.h> -#include <soc/cpu.h> -#include <stdint.h> -#include <timer.h> - -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 - -static int get_count_mhz_freq(void) -{ - static unsigned count_mhz_freq; - - if (!count_mhz_freq) { - if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - count_mhz_freq = 25; /* FPGA board */ - else { - /* If MIPS PLL external bypass bit is set, it means - * that the MIPS PLL is already set up to work at a - * frequency of 550 MHz; otherwise, the crystal is - * used with a frequency of 52 MHz - */ - if (read32_x(PISTACHIO_CLOCK_SWITCH) & - MIPS_EXTERN_PLL_BYPASS_MASK) - /* Half MIPS PLL freq. */ - count_mhz_freq = 275; - else - /* Half Xtal freq. */ - count_mhz_freq = 26; - } - } - return count_mhz_freq; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq()); -} diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c deleted file mode 100644 index cc56337..0000000 --- a/src/soc/imgtec/pistachio/reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <reset.h> - -#define PISTACHIO_WD_ADDR 0xB8102100 -#define PISTACHIO_WD_SW_RST_OFFSET 0x0000 - -void do_board_reset(void) -{ - /* Generate system reset */ - write32_x(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); -} diff --git a/src/soc/imgtec/pistachio/romstage.c b/src/soc/imgtec/pistachio/romstage.c deleted file mode 100644 index 8e44ea8..0000000 --- a/src/soc/imgtec/pistachio/romstage.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <console/console.h> -#include <halt.h> -#include <program_loading.h> -#include <soc/ddr_init.h> - -void main(void) -{ - int error; - console_init(); - error = init_ddr2(); - - if (!error) { - /* - * When romstage is running it's always on the reboot path and - * never a resume path where cbmem recovery is required. - * Therefore, always initialize the cbmem area to be empty. - */ - cbmem_initialize_empty(); - run_ramstage(); - } - halt(); -} diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c deleted file mode 100644 index 156d1de..0000000 --- a/src/soc/imgtec/pistachio/soc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 The Chromium OS Authors. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <symbols.h> - -static void soc_read_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)_dram / KiB, - (CONFIG_DRAM_SIZE_MB * MiB) / KiB); -} - -static void soc_init(struct device *dev) -{ - printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .init = soc_init, -}; - -static void enable_soc_dev(struct device *dev) -{ - dev->ops = &soc_ops; -} - -struct chip_operations soc_imgtec_pistachio_ops = { - CHIP_NAME("SOC: Imgtec Pistachio") - .enable_dev = enable_soc_dev, -}; diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c deleted file mode 100644 index acbbd90..0000000 --- a/src/soc/imgtec/pistachio/spi.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/mmio.h> -#include <soc/cpu.h> -#include <soc/spi.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <stdlib.h> -#include <string.h> -#include <timer.h> - -/* Imgtec controller uses 16 bit packet length. */ -#define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) - -struct img_spi_slave { - /* SPIM instance device parameters */ - struct spim_device_parameters device_parameters; - /* SPIM instance base address */ - u32 base; - /* Boolean property that is TRUE if API has been initialised */ - int initialised; -}; - -/* Allocate memory for the maximum number of devices */ -static struct -img_spi_slave img_spi_slaves[SPIM_NUM_BLOCKS*SPIM_NUM_PORTS_PER_BLOCK]; - -/* - * Wait for the bit at the shift position to be set in reg - * If the bit is not set in SPI_TIMEOUT_VALUE_US return with error - */ -static int wait_status(u32 reg, u32 shift) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_VALUE_US); - while (!(read32_x(reg) & (1 << shift))) { - if (stopwatch_expired(&sw)) - return -SPIM_TIMEOUT; - } - return SPIM_OK; -} - -static struct img_spi_slave *get_img_slave(const struct spi_slave *slave) -{ - return img_spi_slaves + slave->bus * SPIM_NUM_PORTS_PER_BLOCK + - slave->cs; -} - -/* Transmitter function. Fills TX FIFO with data before enabling SPIM */ -static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 blocksize, base, write_data; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - while (size) { - /* Wait until FIFO empty */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK); - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_SDE_SHIFT); - if (ret) - return ret; - - /* - * Write to FIFO in blocks of 16 words (64 bytes) - * Do 32bit writes first. - */ - blocksize = SPIM_MAX_BLOCK_BYTES; - while ((size >= sizeof(u32)) && blocksize) { - memcpy(&write_data, buffer, sizeof(u32)); - write32_x(base + SPFI_SEND_LONG_REG_OFFSET, write_data); - buffer += sizeof(u32); - size -= sizeof(u32); - blocksize -= sizeof(u32); - } - while (size && blocksize) { - write32_x(base + SPFI_SEND_BYTE_REG_OFFSET, *buffer); - buffer++; - size--; - blocksize--; - } - } - return SPIM_OK; -} - -/* Receiver function */ -static int receivedata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 read_data, base; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - /* - * Do 32bit reads first. Clear status GDEX32BIT here so that the first - * status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - while (size >= sizeof(u32)) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX32BIT_SHIFT); - if (ret) - return ret; - read_data = read32_x(base + SPFI_GET_LONG_REG_OFFSET); - memcpy(buffer, &read_data, sizeof(u32)); - buffer += sizeof(u32); - size -= sizeof(u32); - /* Clear interrupt status on GDEX32BITL */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - } - - /* - * Do the remaining 8bit reads. Clear status GDEX8BIT here so that - * the first status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - while (size) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX8BIT_SHIFT); - if (ret) - return ret; - *buffer = read32_x(base + SPFI_GET_BYTE_REG_OFFSET); - buffer++; - size--; - /* Clear interrupt status on SPFI_GDEX8BIT */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - } - return SPIM_OK; -} - -/* Sets port parameters in port state register. */ -static void setparams(const struct spi_slave *slave, u32 port, - struct spim_device_parameters *params) -{ - u32 spim_parameters, port_state, base; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - spim_parameters = 0; - port_state = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - port_state &= ~((SPIM_PORT0_MASK>>port)|SPFI_PORT_SELECT_MASK); - port_state |= params->cs_idle_level<<(SPIM_CS0_IDLE_SHIFT-port); - port_state |= - params->data_idle_level<<(SPIM_DATA0_IDLE_SHIFT-port); - - /* Clock idle level and phase */ - switch (params->spi_mode) { - case SPIM_MODE_0: - break; - case SPIM_MODE_1: - port_state |= (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - case SPIM_MODE_2: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)); - break; - case SPIM_MODE_3: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)) | - (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - } - /* Set port state register */ - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, port_state); - - /* Set up values to be written to device parameter register */ - spim_parameters |= params->bitrate << SPIM_CLK_DIVIDE_SHIFT; - spim_parameters |= params->cs_setup << SPIM_CS_SETUP_SHIFT; - spim_parameters |= params->cs_hold << SPIM_CS_HOLD_SHIFT; - spim_parameters |= params->cs_delay << SPIM_CS_DELAY_SHIFT; - - write32_x(base + SPFI_PORT_0_PARAM_REG_OFFSET + 4 * port, - spim_parameters); -} - -/* Sets up transaction register */ -static u32 transaction_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg = 0; - - /* 2nd transfer exists? */ - if (second) { - /* - * If second transfer exists, it's a "command followed by data" - * type of transfer and first transfer is defined by - * CMD_LENGTH, ADDR_LENGTH, DUMMY_LENGTH... fields of - * transaction register - */ - reg = spi_write_reg_field(reg, SPFI_CMD_LENGTH, 1); - reg = spi_write_reg_field(reg, SPFI_ADDR_LENGTH, - first->size - 1); - reg = spi_write_reg_field(reg, SPFI_DUMMY_LENGTH, 0); - /* Set data size (size of the second transfer) */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, second->size); - } else { - /* Set data size, in this case size of the 1st transfer */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, first->size); - } - return reg; -} - -/* Sets up control register */ -static u32 control_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg; - - /* Enable SPFI */ - reg = SPFI_EN_MASK; - reg |= first->inter_byte_delay ? SPIM_BYTE_DELAY_MASK : 0; - - /* Set up the transfer mode */ - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE_DQ, SPIM_CMD_MODE_0); - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE, SPIM_DMODE_SINGLE); - reg = spi_write_reg_field(reg, SPIM_EDGE_TX_RX, 1); - - if (second) { - /* Set TX bit if the 2nd transaction is 'send' */ - reg = spi_write_reg_field(reg, SPFI_TX_RX, - second->isread ? 0 : 1); - /* - * Set send/get DMA for both transactions - * (first is always 'send') - */ - reg = spi_write_reg_field(reg, SPIM_SEND_DMA, 1); - if (second->isread) - reg = spi_write_reg_field(reg, SPIM_GET_DMA, 1); - - } else { - /* Set TX bit if the 1st transaction is 'send' */ - reg |= first->isread ? 0 : SPFI_TX_RX_MASK; - /* Set send/get DMA */ - reg |= first->isread ? SPIM_GET_DMA_MASK : SPIM_SEND_DMA_MASK; - } - return reg; -} - -/* Checks the given buffer information */ -static int check_buffers(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second){ - - struct img_spi_slave *img_slave = get_img_slave(slave); - - if (!(img_slave->initialised)) - return -SPIM_API_NOT_INITIALISED; - /* - * First operation must always be defined - * It can be either a read or a write and its size cannot be bigge - * than SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (!first) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (first->isread > 1) - return -SPIM_INVALID_READ_WRITE; - /* Check operation parameters for 'second' */ - if (second) { - /* - * If the second operation is defined it must be a read - * operation and its size must not be bigger than - * SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (second->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (!second->isread) - return -SPIM_INVALID_READ_WRITE; - /* - * If the second operations is defined, the first operation - * must be a write and its size cannot be bigger than - * SPIM_MAX_FLASH_COMMAND_BYTES(8): command size (1) + - * address size (7). - */ - if (first->isread) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_FLASH_COMMAND_BYTES) - return -SPIM_INVALID_SIZE; - - } - return SPIM_OK; -} - -/* Checks the set bitrate */ -static int check_bitrate(u32 rate) -{ - /* Bitrate must be 1, 2, 4, 8, 16, 32, 64, or 128 */ - switch (rate) { - case 1: - case 2: - case 4: - case 8: - case 16: - case 32: - case 64: - case 128: - return SPIM_OK; - default: - return -SPIM_INVALID_BIT_RATE; - } - return -SPIM_INVALID_BIT_RATE; -} - -/* Checks device parameters for errors */ -static int check_device_params(struct spim_device_parameters *pdev_param) -{ - if (pdev_param->spi_mode < SPIM_MODE_0 || - pdev_param->spi_mode > SPIM_MODE_3) - return -SPIM_INVALID_SPI_MODE; - if (check_bitrate(pdev_param->bitrate) != SPIM_OK) - return -SPIM_INVALID_BIT_RATE; - if (pdev_param->cs_idle_level > 1) - return -SPIM_INVALID_CS_IDLE_LEVEL; - if (pdev_param->data_idle_level > 1) - return -SPIM_INVALID_DATA_IDLE_LEVEL; - return SPIM_OK; -} - -/* Function that carries out read/write operations */ -static int spim_io(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg, base; - int i, trans_count, ret; - struct spim_buffer *transaction[2]; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - - ret = check_buffers(slave, first, second); - if (ret) - return ret; - - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - /* Port state register */ - reg = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - reg = spi_write_reg_field(reg, SPFI_PORT_SELECT, slave->cs); - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, reg); - /* Set transaction register */ - reg = transaction_reg_setup(first, second); - write32_x(base + SPFI_TRANSACTION_REG_OFFSET, reg); - /* Clear status */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, 0xffffffff); - /* Set control register */ - reg = control_reg_setup(first, second); - write32_x(base + SPFI_CONTROL_REG_OFFSET, reg); - /* First transaction always exists */ - transaction[0] = first; - trans_count = 1; - /* Is there a second transaction? */ - if (second) { - transaction[1] = second; - trans_count++; - } - /* Now write/read FIFO's */ - for (i = 0; i < trans_count; i++) - /* Which transaction to execute, "Send" or "Get"? */ - if (transaction[i]->isread) { - /* Get */ - ret = receivedata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: receive data failed.\n", - __func__); - return ret; - } - } else { - /* Send */ - ret = transmitdata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: transmit data failed.\n", - __func__); - return ret; - } - } - - /* Wait for end of the transaction */ - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_ALLDONE_SHIFT); - if (ret) - return ret; - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - - return SPIM_OK; -} - -/* Claim the bus and prepare it for communication */ -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - int ret; - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - img_slave = get_img_slave(slave); - if (img_slave->initialised) - return SPIM_OK; - /* Check device parameters */ - ret = check_device_params(&(img_slave->device_parameters)); - if (ret) { - printk(BIOS_ERR, "%s: Error: incorrect device parameters.\n", - __func__); - return ret; - } - /* Set device parameters */ - setparams(slave, slave->cs, &(img_slave->device_parameters)); - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); - img_slave->initialised = IMG_TRUE; - return SPIM_OK; -} - -/* Release the SPI bus */ -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return; - } - img_slave = get_img_slave(slave); - img_slave->initialised = IMG_FALSE; - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); -} - -/* SPI transfer */ -static int do_spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - struct spim_buffer buff_0; - struct spim_buffer buff_1; - - /* If we only have a read or a write operation - * the parameters for it will be put in the first buffer - */ - buff_0.buffer = (dout) ? (void *)dout : (void *)din; - buff_0.size = (dout) ? bytesout : bytesin; - buff_0.isread = (dout) ? IMG_FALSE : IMG_TRUE; - buff_0.inter_byte_delay = 0; - - if (dout && din) { - /* Set up the read buffer to receive our data */ - buff_1.buffer = din; - buff_1.size = bytesin; - buff_1.isread = IMG_TRUE; - buff_1.inter_byte_delay = 0; - } - return spim_io(slave, &buff_0, (dout && din) ? &buff_1 : NULL); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - unsigned int in_sz, out_sz; - int ret; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - if (!dout && !din) { - printk(BIOS_ERR, "%s: Error: both buffers are NULL.\n", - __func__); - return -SPIM_INVALID_TRANSFER_DESC; - } - - while (bytesin || bytesout) { - in_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesin); - out_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesout); - - ret = do_spi_xfer(slave, dout, out_sz, din, in_sz); - if (ret) - return ret; - - bytesin -= in_sz; - bytesout -= out_sz; - - if (bytesin) - din += in_sz; - else - din = NULL; - - if (bytesout) - dout += out_sz; - else - dout = NULL; - } - - return SPIM_OK; -} - -static int spi_ctrlr_setup(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave = NULL; - struct spim_device_parameters *device_parameters; - u32 base; - - switch (slave->bus) { - case 0: - base = IMG_SPIM0_BASE_ADDRESS; - break; - case 1: - base = IMG_SPIM1_BASE_ADDRESS; - break; - default: - printk(BIOS_ERR, "%s: Error: unsupported bus.\n", - __func__); - return -1; - } - if (slave->cs > SPIM_DEVICE4) { - printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", - __func__); - return -1; - } - - img_slave = get_img_slave(slave); - device_parameters = &(img_slave->device_parameters); - - img_slave->base = base; - - device_parameters->bitrate = 64; - device_parameters->cs_setup = 0; - device_parameters->cs_hold = 0; - device_parameters->cs_delay = 0; - device_parameters->spi_mode = SPIM_MODE_0; - device_parameters->cs_idle_level = 1; - device_parameters->data_idle_level = 0; - img_slave->initialised = IMG_FALSE; - - return 0; -} - -static const struct spi_ctrlr spi_ctrlr = { - .setup = spi_ctrlr_setup, - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 1, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c deleted file mode 100644 index a39f2ec..0000000 --- a/src/soc/imgtec/pistachio/uart.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <boot/coreboot_tables.h> -#include <console/uart.h> -#include <device/device.h> -#include <delay.h> -#include <drivers/uart/uart8250reg.h> - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -#define UART_SHIFT 2 - -#define GEN_ACCESSOR(name, idx) \ -static inline uint8_t read_##name(unsigned base_port) \ -{ \ - return read8((void *)(base_port + (idx << UART_SHIFT))); \ -} \ - \ -static inline void write_##name(unsigned base_port, uint8_t val) \ -{ \ - write8((void *)(base_port + (idx << UART_SHIFT)), val); \ -} - -GEN_ACCESSOR(rbr, UART8250_RBR) -GEN_ACCESSOR(tbr, UART8250_TBR) -GEN_ACCESSOR(ier, UART8250_IER) -GEN_ACCESSOR(fcr, UART8250_FCR) -GEN_ACCESSOR(lcr, UART8250_LCR) -GEN_ACCESSOR(mcr, UART8250_MCR) -GEN_ACCESSOR(lsr, UART8250_LSR) -GEN_ACCESSOR(dll, UART8250_DLL) -GEN_ACCESSOR(dlm, UART8250_DLM) - -static int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read_lsr(base_port) & UART8250_LSR_THRE; -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); - write_tbr(base_port, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT)) - udelay(1); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read_lsr(base_port) & UART8250_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read_rbr(base_port); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write_ier(base_port, 0x0); - /* Enable FIFOs */ - write_fcr(base_port, UART8250_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS); - - /* DLAB on */ - write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS); - - write_dll(base_port, divisor & 0xFF); - write_dlm(base_port, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write_lcr(base_port, CONFIG_TTYS0_LCS); -} - -unsigned int uart_platform_refclk(void) -{ - /* 1.8433179 MHz */ - return 1843318; -} - -void uart_init(int idx) -{ - u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - if (!base) - return; - - unsigned int div; - div = uart_baudrate_divisor(get_uart_baudrate(), - uart_platform_refclk(), 16); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - uart8250_mem_tx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS, data); -} - -unsigned char uart_rx_byte(int idx) -{ - return uart8250_mem_rx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -void uart_tx_flush(int idx) -{ - uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -#ifndef __PRE_RAM__ -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - serial.baud = get_uart_baudrate(); - serial.regwidth = 1 << UART_SHIFT; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..a7528bc 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -22,8 +22,7 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c -ifeq ($(CONFIG_ARCH_MIPS),) + bootblock-y += watchdog.c verstage-y += watchdog.c ramstage-y += watchdog.c -endif diff --git a/toolchain.inc b/toolchain.inc index 875cb20..9fd39bd 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -56,12 +56,10 @@ ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv -ARCHDIR-mips := mips ARCHDIR-ppc64 := ppc64 CFLAGS_arm += CFLAGS_arm64 += -mgeneral-regs-only -CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone @@ -83,7 +81,6 @@ ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_arm += -Wstack-usage=1536 CFLAGS_arm64 += -Wstack-usage=1536 -CFLAGS_mips += -Wstack-usage=1536 CFLAGS_riscv += -Wstack-usage=1536 CFLAGS_ppc64 += -Wstack-usage=1536 endif diff --git a/util/README.md b/util/README.md index 470013e..55bcaab 100644 --- a/util/README.md +++ b/util/README.md @@ -9,9 +9,6 @@ platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` -* __bimgtool__ - A simple tool which generates and verifies boot images -in the BIMG format, used in systems designed by Imagination -Technologies, for example the Pistachio SoC. `C` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` `Yacc` * __board_status__ - Tools to collect logs and upload them to the board diff --git a/util/bimgtool/Makefile b/util/bimgtool/Makefile deleted file mode 100644 index 05ddf7d..0000000 --- a/util/bimgtool/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -obj ?= $(CURDIR) - -HOSTCC ?= gcc -CFLAGS ?= -g -CFLAGS += -D_7ZIP_ST -CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow -Werror - -all: $(obj)/bimgtool - -clean: - rm -f $(obj)/bimgtool - -$(obj)/bimgtool: bimgtool.c - $(HOSTCC) $(CFLAGS) -o $@ $^ diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c deleted file mode 100644 index 518674c..0000000 --- a/util/bimgtool/bimgtool.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Imagination Technologies Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <errno.h> -#include <stdint.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <sys/stat.h> -#include <sys/types.h> - -struct bimg_header { - uint32_t magic; - uint16_t ver_major; - uint16_t ver_minor; - uint32_t data_size; - uint32_t entry_addr; - uint32_t flags; - uint32_t data_crc; - uint32_t crc; -} __attribute__((packed)); - -struct bimg_data_header { - uint32_t size; - uint32_t dest_addr; - uint16_t dummy; - uint16_t crc; -} __attribute__((packed)); - -struct crc_t { - uint16_t (*crc_f)(uint16_t crc, void *void_buf, size_t size); - uint32_t crc_init; - uint16_t ver_major; - uint16_t ver_minor; -}; - - -#define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ - -#define BIMG_OP_MASK (0xf << 0) -#define BIMG_OP_EXEC_RETURN (0x1 << 0) -#define BIMG_OP_EXEC_NO_RETURN (0x2 << 0) -#define BIMG_DATA_CHECKSUM (0x1 << 4) - -/* Typical use case for this utility. */ -#define BIMG_FLAGS (BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM) - -#define MAX_RECORD_BYTES 0x8000 - -#define CRC_16 - -#define error(msg...) fprintf(stderr, "ERROR: " msg) - -#define error_ret(ret, msg...) { \ - error(msg); \ - return ret; \ -} - -#if defined(CRC_X25) -static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) -{ - static const uint16_t crc_table[16] = { - 0x0000, 0x1021, 0x2042, 0x3063, - 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, - 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 4)) & 0xf]; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 0)) & 0xf]; - } - - return crc; -} -#endif - -#if defined(CRC_16) -static uint16_t crc_16(uint16_t crc, void *void_buf, size_t size) -{ - /* - * CRC table for the CRC-16. - * The poly is 0x8005 (x^16 + x^15 + x^2 + 1) - */ - static const uint16_t crc16_table[256] = { - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff]; - } - - return crc; -} -#endif - -static const struct crc_t crc_type = { -#if defined(CRC_16) - .crc_f = crc_16, - .crc_init = 0, - .ver_major = 2, - .ver_minor = 0 -#elif defined(CRC_X25) - .crc_f = crc_x25, - .crc_init = 0xffff, - .ver_major = 1, - .ver_minor = 0 -#endif -}; - -static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) -{ - static uint8_t file_buf[MAX_RECORD_BYTES]; - struct bimg_data_header data_hdr = { 0 }; - size_t n_written; - - data_hdr.dest_addr = hdr->entry_addr; - - /* - * The read binary data has to be split in chunks of max 64KiB - 1 byte - * (SPI controller limitation). Each chunk will have its own header in - * order to respect the BIMG format. - */ - while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", - errno); - - n_written = fwrite(file_buf, 1, data_hdr.size, out); - if (n_written != data_hdr.size) - error_ret(-EIO, "Failed to write to output file: %d\n", - errno); - - data_hdr.dest_addr += n_written; - hdr->data_size += sizeof(data_hdr) + n_written; - hdr->data_crc = crc_type.crc_f(hdr->data_crc, - file_buf, n_written); - } - - if (ferror(in)) - error_ret(-EIO, "Failed to read input file\n"); - - return 0; -} - -static int write_final(FILE *out, struct bimg_header *hdr) -{ - struct bimg_data_header data_hdr = { - .size = 0, - .dest_addr = ~0, - }; - - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", errno); - - hdr->data_size += sizeof(data_hdr); - - return 0; -} - -static const char *help_message = - "Usage: bimgtool <input> [<output> <base-address>]\n" - "\n" - "This is a simple tool which generates and verifies boot images in\n" - "the BIMG format, used in systems designed by Imagination\n" - "Technologies, for example the Pistachio SoC. This version of the\n" - "tool works with BIMG images version %d.\n" - "\n" - " input: The binary file to be converted to a BIMG\n" - " or verified\n" - " output: The name of the output BIMG file\n" - " base-address: The address in memory at which you wish the " - " input binary to be loaded.\n"; - -static void usage(FILE *f) -{ - fprintf(f, help_message, crc_type.ver_major); -} - -static int verify_file(FILE *f) -{ - struct bimg_header file_header; - struct bimg_data_header data_header; - char *file_pointer; - char *file_data; - struct stat buf; - int data_size; - int fd = fileno(f); - uint32_t data_crc = crc_type.crc_init; - uint32_t crc_result; - - if (fread(&file_header, 1, sizeof(struct bimg_header), f) != - sizeof(struct bimg_header)) { - perror("Problems trying to read input file header\n"); - return -1; - } - - if (fstat(fd, &buf)) { - perror("Problems trying to stat input file\n"); - return -1; - } - - if (file_header.magic != BIMG_MAGIC) { - fprintf(stderr, "Wrong magic value %#x\n", file_header.magic); - return -1; - } - - crc_result = crc_type.crc_f(crc_type.crc_init, &file_header, - sizeof(file_header) - - sizeof(file_header.crc)); - if (file_header.crc != crc_result) { - fprintf(stderr, "File header CRC mismatch\n"); - return -1; - } - - if ((file_header.data_size + sizeof(struct bimg_header)) > - buf.st_size) { - fprintf(stderr, "Data size too big: %d > %zd\n", - file_header.data_size, buf.st_size); - return -1; - } - - if (file_header.ver_major != crc_type.ver_major) { - fprintf(stderr, "Image version mismatch: %d\n", - file_header.ver_major); - return -1; - } - - if ((file_header.flags & BIMG_FLAGS) != BIMG_FLAGS) { - fprintf(stderr, "Unexpected file header flags: %#x\n", - file_header.flags); - return -1; - } - - if (file_header.ver_minor != crc_type.ver_minor) { - fprintf(stderr, - "Minor version mismatch: %d, will try anyways\n", - file_header.ver_minor); - } - - data_size = file_header.data_size; - file_pointer = malloc(data_size); - if (!file_pointer) { - fprintf(stderr, "Failed to allocate %d bytes\n", - file_header.data_size); - return -1; - } - - if (fread(file_pointer, 1, data_size, f) != data_size) { - fprintf(stderr, "Failed to read %d bytes\n", data_size); - free(file_pointer); - return -1; - } - - file_data = file_pointer; - while (data_size > 0) { - memcpy(&data_header, file_data, sizeof(data_header)); - - /* Check the data block header integrity. */ - crc_result = crc_type.crc_f(crc_type.crc_init, &data_header, - sizeof(data_header) - - sizeof(data_header.crc)); - if (data_header.crc != crc_result) { - fprintf(stderr, "Data header CRC mismatch at %d\n", - file_header.data_size - data_size); - free(file_pointer); - return -1; - } - - /* - * Add the block data to the CRC stream, the last block size - * will be zero. - */ - file_data += sizeof(data_header); - data_crc = crc_type.crc_f(data_crc, - file_data, data_header.size); - - data_size -= data_header.size + sizeof(data_header); - file_data += data_header.size; - } - - if (data_size) { - fprintf(stderr, "File size mismatch\n"); - free(file_pointer); - return -1; - } - - if (data_crc != file_header.data_crc) { - fprintf(stderr, "File data CRC mismatch\n"); - free(file_pointer); - return -1; - } - - free(file_pointer); - return 0; -} - -int main(int argc, char *argv[]) -{ - const char *in_filename, *out_filename; - FILE *in_file, *out_file; - int err; - struct bimg_header hdr = { - .magic = BIMG_MAGIC, - .ver_major = crc_type.ver_major, - .ver_minor = crc_type.ver_minor, - .flags = BIMG_FLAGS, - .data_crc = crc_type.crc_init, - }; - - if ((argc != 4) && (argc != 2)) { - usage(stderr); - goto out_err; - } - - in_filename = argv[1]; - - in_file = fopen(in_filename, "r"); - if (!in_file) { - error("Failed to open input file '%s'\n", in_filename); - goto out_err; - } - - if (argc == 2) - return verify_file(in_file); - - out_filename = argv[2]; - hdr.entry_addr = strtoul(argv[3], NULL, 16); - - out_file = fopen(out_filename, "w"); - if (!out_file) { - error("Failed to open output file '%s'\n", out_filename); - goto out_err_close_in; - } - - if (fseek(out_file, sizeof(hdr), SEEK_SET)) { - error("Failed to seek past header: %d\n", errno); - goto out_err_close_out; - } - - err = write_binary(out_file, in_file, &hdr); - if (err) { - error("Failed to write binary: %d\n", err); - goto out_err_close_out; - } - - err = write_final(out_file, &hdr); - if (err) { - error("Failed to write final record: %d\n", err); - goto out_err_close_out; - } - - hdr.crc = crc_type.crc_f(crc_type.crc_init, &hdr, - sizeof(hdr) - sizeof(hdr.crc)); - - if (fseek(out_file, 0, SEEK_SET)) { - error("Failed to seek to header: %d\n", errno); - goto out_err_close_out; - } - - if (fwrite(&hdr, sizeof(hdr), 1, out_file) != 1) { - error("Failed to write header: %d\n", errno); - goto out_err_close_out; - } - - fclose(in_file); - fclose(out_file); - return EXIT_SUCCESS; - -out_err_close_out: - fclose(out_file); -out_err_close_in: - fclose(in_file); -out_err: - return EXIT_FAILURE; -} diff --git a/util/bimgtool/description.md b/util/bimgtool/description.md deleted file mode 100644 index aa1059a..0000000 --- a/util/bimgtool/description.md +++ /dev/null @@ -1,3 +0,0 @@ -A simple tool which generates and verifies boot images in the BIMG -format, used in systems designed by Imagination Technologies, for -example the Pistachio SoC. `C` diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index b082d8c..5fe0304 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -65,7 +65,7 @@ #define CBFS_ARCHITECTURE_X86 0x00000001 #define CBFS_ARCHITECTURE_ARM 0x00000010 #define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 -#define CBFS_ARCHITECTURE_MIPS 0x00000100 +#define CBFS_ARCHITECTURE_MIPS 0x00000100 /* deprecated */ #define CBFS_ARCHITECTURE_RISCV 0xc001d0de #define CBFS_ARCHITECTURE_PPC64 0x407570ff diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index c4f4262..db8b769 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -8,12 +8,12 @@ # Example: BUILDGCC_OPTIONS=-c to remove temporary files before build all all_with_gdb: - $(MAKE) build-i386 build-x64 build-arm build-mips \ + $(MAKE) build-i386 build-x64 build-arm \ build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make build_nasm all_without_gdb: - $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ + $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm \ build-riscv build-aarch64 build-ppc64 build-nds32le \ build_clang build_iasl build_make build_nasm @@ -59,9 +59,6 @@ build-aarch64: @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf -build-mips: - @$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf - build-riscv: # GDB is currently not supported on RISC-V @$(MAKE) build_gcc BUILD_PLATFORM=riscv-elf @@ -88,7 +85,6 @@ .PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ all_without_gdb build_tools build-i386 build-x64 build-arm \ - build-aarch64 build-mips build-riscv build-ppc64 build-nds32le \ - build-nasm \ + build-aarch64 build-riscv build-ppc64 build-nds32le build-nasm \ clean distclean clean_tempfiles .NOTPARALLEL: diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 0ef6b9c..108612f 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -TOOLCHAIN_ARCHES := i386 x64 arm aarch64 mips riscv ppc64 nds32le +TOOLCHAIN_ARCHES := i386 x64 arm aarch64 riscv ppc64 nds32le help_toolchain help:: @echo '*** Toolchain targets ***' @@ -39,9 +39,9 @@ $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ clang crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 \ + crosstools-aarch64 crosstools-riscv crosstools-power8 \ jenkins-build-toolchain gnumake nasm $(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update diff --git a/util/crossgcc/README b/util/crossgcc/README index 5ce9304..c40454f 100644 --- a/util/crossgcc/README +++ b/util/crossgcc/README @@ -7,7 +7,6 @@ i386-elf x86_64-elf powerpc-elf - mipsel-elf arm-elf armv7a-eabi aarch64-elf diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..6b306a6 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -604,7 +604,7 @@ printf " (defaults to $TARGETARCH)\n" printf " [-S|--scripting] build scripting support for GDB\n\n" printf "Platforms for GCC & GDB:\n" - printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" + printf " x86_64 i386-elf i386-mingw32 riscv-elf arm aarch64\n" printf " powerpc64le-linux-gnu nds32le-elf\n\n" } @@ -1016,7 +1016,6 @@ x86_64*) TARGETARCH=x86_64-elf;; i386-elf) ;; i386-mingw32) ;; - mipsel-elf) ;; riscv-elf) TARGETARCH=riscv64-elf;; powerpc64*-linux*) ;; i386*) TARGETARCH=i386-elf;; diff --git a/util/docker/coreboot.org-status/board-status.html/tohtml.sh b/util/docker/coreboot.org-status/board-status.html/tohtml.sh index 41de9ff..8522fd5 100755 --- a/util/docker/coreboot.org-status/board-status.html/tohtml.sh +++ b/util/docker/coreboot.org-status/board-status.html/tohtml.sh @@ -334,9 +334,6 @@ TI_AM335X) cpu_nice="TI AM335X"; socket_nice="?";; - IMGTEC_PISTACHIO) - cpu_nice="Imagination Technologies Pistachio"; - socket_nice="—";; INTEL_APOLLOLAKE) cpu_nice="Intel® Apollo Lake"; socket_nice="—";; diff --git a/util/release/genrelnotes b/util/release/genrelnotes index 2867cbf..25c2993 100755 --- a/util/release/genrelnotes +++ b/util/release/genrelnotes @@ -353,11 +353,6 @@ get_log_dedupe "RISC-V" \ "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \ "riscv\|risc-v\|sifive" - -get_log_dedupe "MIPS" \ - "$(for codedir in $(grep -rl "_MIPS" --include=Kconfig | \ - grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ - do dirname "$codedir"; done | grep -v '^src$')" } get_log_dedupe "X86 intel" \ diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index f431625..b8e4e40 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -195,14 +195,6 @@ "$LDFLAGS --fix-cortex-a53-843419" && \ LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419" ;; - mipsel) - testcc "$GCC" "$CFLAGS_GCC -mno-abicalls -fno-pic" && \ - CFLAGS_GCC+=" -mno-abicalls -fno-pic" - - # Enforce little endian mode. - testcc "$GCC" "$CFLAGS_GCC -EL" && \ - CFLAGS_GCC+=" -EL" - ;; esac } @@ -314,7 +306,7 @@ } # Architecture definitions -SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 ppc64" +SUPPORTED_ARCHITECTURES="arm arm64 riscv x64 x86 ppc64" # TARCH: local name for the architecture # (used as CC_${TARCH} in the build system) @@ -367,16 +359,6 @@ CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3" } -arch_config_mipsel() { - TARCH="mips" - TBFDARCHS="tradlittlemips littlemips" - TCLIST="mipsel" - TWIDTH="32" - TSUPP="mips mipsel" - TABI="elf" - TENDIAN="EL" -} - arch_config_ppc64() { TARCH="ppc64" TBFDARCHS="powerpc" -- To view, visit https://review.coreboot.org/c/coreboot/+/34919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Gerrit-Change-Number: 34919 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: Remove imgtec/pistachio SoC
by Julius Werner (Code Review) 20 Nov '19

20 Nov '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36491 ) Change subject: Remove imgtec/pistachio SoC ...................................................................... Remove imgtec/pistachio SoC After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M .gitignore M Documentation/util.md M Makefile.inc M payloads/libpayload/drivers/Makefile.inc M payloads/libpayload/drivers/timer/Kconfig D src/soc/imgtec/Kconfig D src/soc/imgtec/pistachio/Kconfig D src/soc/imgtec/pistachio/Makefile.inc D src/soc/imgtec/pistachio/bootblock.c D src/soc/imgtec/pistachio/cbmem.c D src/soc/imgtec/pistachio/clocks.c D src/soc/imgtec/pistachio/ddr2_init.c D src/soc/imgtec/pistachio/ddr3_init.c D src/soc/imgtec/pistachio/include/soc/clocks.h D src/soc/imgtec/pistachio/include/soc/cpu.h D src/soc/imgtec/pistachio/include/soc/ddr_init.h D src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h D src/soc/imgtec/pistachio/include/soc/gpio.h D src/soc/imgtec/pistachio/include/soc/memlayout.ld D src/soc/imgtec/pistachio/include/soc/spi.h D src/soc/imgtec/pistachio/monotonic_timer.c D src/soc/imgtec/pistachio/reset.c D src/soc/imgtec/pistachio/romstage.c D src/soc/imgtec/pistachio/soc.c D src/soc/imgtec/pistachio/spi.c D src/soc/imgtec/pistachio/uart.c D util/bimgtool/Makefile D util/bimgtool/bimgtool.c D util/bimgtool/description.md 29 files changed, 1 insertion(+), 3,705 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36491/1 diff --git a/.gitignore b/.gitignore index b90a93f..84b3af1 100644 --- a/.gitignore +++ b/.gitignore @@ -85,7 +85,6 @@ util/*/.test util/amdfwtool/amdfwtool util/archive/archive -util/bimgtool/bimgtool util/bincfg/bincfg util/board_status/board-status util/bucts/bucts diff --git a/Documentation/util.md b/Documentation/util.md index 021af79..1a8f36d 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -14,9 +14,6 @@ platform. `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` -* __bimgtool__ - A simple tool which generates and verifies boot images -in the BIMG format, used in systems designed by Imagination -Technologies, for example the Pistachio SoC. `C` * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex` `Yacc` * __board_status__ - Tools to collect logs and upload them to the board diff --git a/Makefile.inc b/Makefile.inc index f7f3708..fbcc6e8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -479,7 +479,7 @@ additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/options $(objutil)/amdfwtool \ - $(objutil)/cbootimage $(objutil)/bimgtool + $(objutil)/cbootimage export $(COREBOOT_EXPORTS) @@ -572,11 +572,6 @@ subdirs-y += util/nvidia -BIMGTOOL:=$(objutil)/bimgtool/bimgtool -$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< - $(obj)/config.h: $(objutil)/kconfig/conf ####################################################################### diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index b4e7594..a391670 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -54,7 +54,6 @@ libc-y += timer/generic.c endif libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c -libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c # Video console drivers diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 5a61dfa..e3bd0e9 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -50,9 +50,6 @@ config TIMER_RK3399 bool "Timer for Rockchip RK3399" -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - config TIMER_MTK bool "Timer for MediaTek" diff --git a/src/soc/imgtec/Kconfig b/src/soc/imgtec/Kconfig deleted file mode 100644 index 18c6ba1..0000000 --- a/src/soc/imgtec/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -# Load all chipsets -source "src/soc/imgtec/*/Kconfig" diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig deleted file mode 100644 index 30d7bee..0000000 --- a/src/soc/imgtec/pistachio/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config CPU_IMGTEC_PISTACHIO - select ARCH_MIPS - select ARCH_BOOTBLOCK_MIPS - select ARCH_VERSTAGE_MIPS - select ARCH_ROMSTAGE_MIPS - select ARCH_RAMSTAGE_MIPS - select HAVE_UART_SPECIAL - select GENERIC_GPIO_LIB - select UART_OVERRIDE_REFCLK - bool - -if CPU_IMGTEC_PISTACHIO - -config BOOTBLOCK_CPU_INIT - string - default "soc/imgtec/pistachio/bootblock.c" - -endif diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc deleted file mode 100644 index 6e8d539..0000000 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_CPU_IMGTEC_PISTACHIO),y) - -# We enable CBFS_SPI_WRAPPER for Pistachio targets. -bootblock-y += clocks.c -bootblock-y += spi.c -romstage-y += spi.c -ramstage-y += spi.c - -bootblock-y += uart.c -romstage-y += uart.c -ramstage-y += uart.c - -bootblock-y += monotonic_timer.c - -ramstage-y += cbmem.c -ramstage-y += monotonic_timer.c -ramstage-y += soc.c -ramstage-y += reset.c - -romstage-y += cbmem.c -romstage-y += ddr2_init.c -romstage-y += ddr3_init.c -romstage-y += romstage.c -romstage-y += monotonic_timer.c - -CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/ - -# Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BIMGTOOL) - @printf " BIMGTOOL $(subst $(obj)/,,$(@))\n" - $(BIMGTOOL) $< $@ $(call loadaddr,bootblock) - -endif diff --git a/src/soc/imgtec/pistachio/bootblock.c b/src/soc/imgtec/pistachio/bootblock.c deleted file mode 100644 index ac4a740..0000000 --- a/src/soc/imgtec/pistachio/bootblock.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <arch/mmu.h> -#include <assert.h> -#include <stdint.h> -#include <symbols.h> - -static void bootblock_cpu_init(void) -{ - uint32_t cause; - - /* - * Make sure the count register is counting by clearing the "Disable - * Counter" bit, in case it is set. - */ - cause = read_c0_cause(); - if (cause & C0_CAUSE_DC) - write_c0_cause(cause & ~(C0_CAUSE_DC)); - - /* And make sure that it starts from zero. */ - write_c0_count(0); -} - -static void bootblock_mmu_init(void) -{ - uint32_t null_guard_size = 1 * MiB; - uint32_t dram_base, dram_size; - - write_c0_wired(0); - - dram_base = (uint32_t)_dram; - dram_size = CONFIG_DRAM_SIZE_MB * MiB; - - /* - * To be able to catch NULL pointer dereference attempts, lets not map - * memory close to zero. - */ - if (dram_base < null_guard_size) { - dram_base += null_guard_size; - dram_size -= null_guard_size; - } - assert(!identity_map((uint32_t)_sram, REGION_SIZE(sram), - C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map(dram_base, dram_size, C0_ENTRYLO_COHERENCY_WB)); - assert(!identity_map((uint32_t)_soc_registers, - REGION_SIZE(soc_registers), C0_ENTRYLO_COHERENCY_UC)); -} diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c deleted file mode 100644 index 112df7c..0000000 --- a/src/soc/imgtec/pistachio/cbmem.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stdlib.h> -#include <symbols.h> - -void *cbmem_top(void) -{ - return _dram + (CONFIG_DRAM_SIZE_MB << 20); -} diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c deleted file mode 100644 index aa54ebc..0000000 --- a/src/soc/imgtec/pistachio/clocks.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <assert.h> -#include <delay.h> -#include <soc/clocks.h> -#include <timer.h> - -/* Definitions for PLL enable */ -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 - -#define SYS_EXTERN_PLL_BYPASS_MASK 0x00002000 -#define SYS_PLL_CTRL4_ADDR 0xB8144048 -#define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 -#define SYS_PLL_DACPD_ADDR 0xB8144044 -#define SYS_PLL_DACPD_MASK 0x00000002 -#define SYS_PLL_DSMPD_ADDR 0xB8144044 -#define SYS_PLL_DSMPD_MASK 0x00000004 - -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 -#define MIPS_PLL_CTRL2_ADDR 0xB8144008 -#define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 -#define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 -#define MIPS_PLL_DSMPD_ADDR 0xB8144004 -#define MIPS_PLL_DSMPD_MASK 0x02000000 - -/* Definitions for PLL dividers */ -#define SYS_PLL_POSTDIV_ADDR 0xB8144040 -#define SYS_PLL_POSTDIV1_MASK 0x07000000 -#define SYS_PLL_POSTDIV1_SHIFT 24 -#define SYS_PLL_POSTDIV2_MASK 0x38000000 -#define SYS_PLL_POSTDIV2_SHIFT 27 -#define SYS_PLL_STATUS_ADDR 0xB8144038 -#define SYS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define SYS_PLL_REFDIV_ADDR 0xB814403C -#define SYS_PLL_REFDIV_MASK 0x0000003F -#define SYS_PLL_REFDIV_SHIFT 0 -#define SYS_PLL_FEEDBACK_ADDR 0xB814403C -#define SYS_PLL_FEEDBACK_MASK 0x0003FFC0 -#define SYS_PLL_FEEDBACK_SHIFT 6 - -#define MIPS_PLL_POSTDIV_ADDR 0xB8144004 -#define MIPS_PLL_POSTDIV1_MASK 0x001C0000 -#define MIPS_PLL_POSTDIV1_SHIFT 18 -#define MIPS_PLL_POSTDIV2_MASK 0x00E00000 -#define MIPS_PLL_POSTDIV2_SHIFT 21 -#define MIPS_PLL_STATUS_ADDR 0xB8144000 -#define MIPS_PLL_STATUS_LOCK_MASK 0x00000001 - -#define MIPS_REFDIV_ADDR 0xB8144004 -#define MIPS_REFDIV_MASK 0x0000003F -#define MIPS_REFDIV_SHIFT 0 -#define MIPS_FEEDBACK_ADDR 0xB8144004 -#define MIPS_FEEDBACK_MASK 0x0003FFC0 -#define MIPS_FEEDBACK_SHIFT 6 - -/* Definitions for system clock setup */ -#define SYSCLKINTERNAL_CTRL_ADDR 0xB8144244 -#define SYSCLKINTERNAL_MASK 0X00000007 - -/* Definitions for MIPS clock setup */ -#define MIPSCLKINTERNAL_CTRL_ADDR 0xB8144204 -#define MIPSCLKINTERNAL_MASK 0x00000003 -#define MIPSCLKOUT_CTRL_ADDR 0xB8144208 -#define MIPSCLKOUT_MASK 0x000000FF - -/* Peripheral Clock gate reg */ -#define MIPS_CLOCK_GATE_ADDR 0xB8144900 -#define RPU_CLOCK_GATE_ADDR 0xB8144904 -#define MIPS_CLOCK_GATE_ALL_ON 0x3fff -#define RPU_CLOCK_GATE_ALL_OFF 0x0 - -/* Definitions for USB clock setup */ -#define USBPHYCLKOUT_CTRL_ADDR 0xB814422C -#define USBPHYCLKOUT_MASK 0X0000003F -#define USBPHYCONTROL1_ADDR 0xB8149004 -#define USBPHYCONTROL1_FSEL_SHIFT 2 -#define USBPHYCONTROL1_FSEL_MASK 0x1C -#define USBPHYSTRAPCTRL_ADDR 0xB8149010 -#define USBPHYSTRAPCTRL_REFCLKSEL_SHIFT 4 -#define USBPHYSTRAPCTRL_REFCLKSEL_MASK 0x30 -#define USBPHYSTATUS_ADDR 0xB8149014 -#define USBPHYSTATUS_RX_PHY_CLK_MASK 0x200 -#define USBPHYSTATUS_RX_UTMI_CLK_MASK 0x100 -#define USBPHYSTATUS_VBUS_FAULT_MASK 0x80 - -/* Definitions for UART0/1 setup */ -#define UART0CLKINTERNAL_CTRL_ADDR 0xB8144234 -#define UART0CLKINTERNAL_MASK 0x00000007 -#define UART0CLKOUT_CTRL_ADDR 0xB8144238 -#define UART0CLKOUT_MASK 0x000003FF -#define UART1CLKINTERNAL_CTRL_ADDR 0xB814423C -#define UART1CLKINTERNAL_MASK 0x00000007 -#define UART1CLKOUT_CTRL_ADDR 0xB8144240 -#define UART1CLKOUT_MASK 0x000003FF - -/* Definitions for I2C setup */ -#define I2CCLKDIV1_CTRL_ADDR(i) (0xB8144800 + 0x013C + (2*(i)*4)) -#define I2CCLKDIV1_MASK 0x0000007F -#define I2CCLKOUT_CTRL_ADDR(i) (0xB8144800 + 0x0140 + (2*(i)*4)) -#define I2CCLKOUT_MASK 0x0000007F - -/* Definitions for ROM clock setup */ -#define ROMCLKOUT_CTRL_ADDR 0xB814490C -#define ROMCLKOUT_MASK 0x0000007F - -/* Definitions for ETH clock setup */ -#define ENETCLKMUX_MASK 0x00004000 -#define ENETCLKDIV_CTRL_ADDR 0xB8144230 -#define ENETCLKDIV_MASK 0x0000003F - -/* Definitions for timeout values */ -#define PLL_TIMEOUT_VALUE_US 20000 -#define USB_TIMEOUT_VALUE_US 200000 -#define SYS_CLK_LOCK_DELAY 3 - -struct pll_parameters { - u32 external_bypass_mask; - u32 ctrl_addr; - u32 internal_bypass_mask; - u32 power_down_ctrl_addr; - u32 power_down_ctrl_mask; - u32 dacpd_addr; - u32 dacpd_mask; - u32 dsmpd_addr; - u32 dsmpd_mask; - u32 postdiv_addr; - u32 postdiv1_shift; - u32 postdiv1_mask; - u32 postdiv2_shift; - u32 postdiv2_mask; - u32 status_addr; - u32 status_lock_mask; - u32 refdivider; - u32 refdiv_addr; - u32 refdiv_shift; - u32 refdiv_mask; - u32 feedback; - u32 feedback_addr; - u32 feedback_shift; - u32 feedback_mask; -}; - -enum plls { - SYS_PLL = 0, - MIPS_PLL = 1 -}; - -static struct pll_parameters pll_params[] = { - [SYS_PLL] = { - .external_bypass_mask = SYS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = SYS_PLL_CTRL4_ADDR, - .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, - /* Noise cancellation */ - .dacpd_addr = SYS_PLL_DACPD_ADDR, - .dacpd_mask = SYS_PLL_DACPD_MASK, - .dsmpd_addr = SYS_PLL_DSMPD_ADDR, - /* 0 - Integer mode - * SYS_PLL_DSMPD_MASK - Fractional mode - */ - .dsmpd_mask = 0, - .postdiv_addr = SYS_PLL_POSTDIV_ADDR, - .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, - .postdiv2_shift = SYS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = SYS_PLL_POSTDIV2_MASK, - .status_addr = SYS_PLL_STATUS_ADDR, - .status_lock_mask = SYS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = SYS_PLL_REFDIV_ADDR, - .refdiv_shift = SYS_PLL_REFDIV_SHIFT, - .refdiv_mask = SYS_PLL_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = SYS_PLL_FEEDBACK_ADDR, - .feedback_shift = SYS_PLL_FEEDBACK_SHIFT, - .feedback_mask = SYS_PLL_FEEDBACK_MASK - }, - - [MIPS_PLL] = { - .external_bypass_mask = MIPS_EXTERN_PLL_BYPASS_MASK, - .ctrl_addr = MIPS_PLL_CTRL2_ADDR, - .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, - .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, - .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, - .dacpd_addr = 0, - .dacpd_mask = 0, - .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, - .dsmpd_mask = MIPS_PLL_DSMPD_MASK, - .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, - .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, - .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, - .postdiv2_shift = MIPS_PLL_POSTDIV2_SHIFT, - .postdiv2_mask = MIPS_PLL_POSTDIV2_MASK, - .status_addr = MIPS_PLL_STATUS_ADDR, - .status_lock_mask = MIPS_PLL_STATUS_LOCK_MASK, - .refdivider = 0, /* Not defined yet */ - .refdiv_addr = MIPS_REFDIV_ADDR, - .refdiv_shift = MIPS_REFDIV_SHIFT, - .refdiv_mask = MIPS_REFDIV_MASK, - .feedback = 0, /* Not defined yet */ - .feedback_addr = MIPS_FEEDBACK_ADDR, - .feedback_shift = MIPS_FEEDBACK_SHIFT, - .feedback_mask = MIPS_FEEDBACK_MASK - } -}; - -static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!((divider1 << param->postdiv1_shift) & - ~(param->postdiv1_mask))); - assert(!((divider2 << param->postdiv2_shift) & - ~(param->postdiv2_mask))); - - /* Temporary bypass PLL (select XTAL as clock input) */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg &= ~(param->external_bypass_mask); - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - /* Un-bypass PLL's internal bypass */ - reg = read32_x(param->ctrl_addr); - reg &= ~(param->internal_bypass_mask); - write32_x(param->ctrl_addr, reg); - - /* Disable power down */ - reg = read32_x(param->power_down_ctrl_addr); - reg &= ~(param->power_down_ctrl_mask); - write32_x(param->power_down_ctrl_addr, reg); - - /* Noise cancellation */ - if (param->dacpd_addr) { - reg = read32_x(param->dacpd_addr); - reg &= ~(param->dacpd_mask); - write32_x(param->dacpd_addr, reg); - } - - /* Functional mode */ - if (param->dsmpd_addr) { - reg = read32_x(param->dsmpd_addr); - reg &= ~(param->dsmpd_mask); - write32_x(param->dsmpd_addr, reg); - } - - if (param->feedback_addr) { - assert(!((param->feedback << param->feedback_shift) & - ~(param->feedback_mask))); - reg = read32_x(param->feedback_addr); - reg &= ~(param->feedback_mask); - reg |= (param->feedback << param->feedback_shift) & - param->feedback_mask; - write32_x(param->feedback_addr, reg); - } - - if (param->refdiv_addr) { - assert(!((param->refdivider << param->refdiv_shift) & - ~(param->refdiv_mask))); - reg = read32_x(param->refdiv_addr); - reg &= ~(param->refdiv_mask); - reg |= (param->refdivider << param->refdiv_shift) & - param->refdiv_mask; - write32_x(param->refdiv_addr, reg); - } - - /* Read postdivider register value */ - reg = read32_x(param->postdiv_addr); - /* Set divider 1 */ - reg &= ~(param->postdiv1_mask); - reg |= (divider1 << param->postdiv1_shift) & - param->postdiv1_mask; - /* Set divider 2 */ - reg &= ~(param->postdiv2_mask); - reg |= (divider2 << param->postdiv2_shift) & - param->postdiv2_mask; - /* Write back to register */ - write32_x(param->postdiv_addr, reg); - - /* Waiting for PLL to lock*/ - stopwatch_init_usecs_expire(&sw, PLL_TIMEOUT_VALUE_US); - while (!(read32_x(param->status_addr) & param->status_lock_mask)) { - if (stopwatch_expired(&sw)) - return PLL_TIMEOUT; - } - - /* Start using PLL */ - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= param->external_bypass_mask; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - - return CLOCKS_OK; -} - -int sys_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[SYS_PLL].refdivider = refdivider; - pll_params[SYS_PLL].feedback = feedback; - return pll_setup(&(pll_params[SYS_PLL]), divider1, divider2); -} - -int mips_pll_setup(u8 divider1, u8 divider2, u8 refdivider, u32 feedback) -{ - pll_params[MIPS_PLL].refdivider = refdivider; - pll_params[MIPS_PLL].feedback = feedback; - return pll_setup(&(pll_params[MIPS_PLL]), divider1, divider2); -} - -/* - * uart1_clk_setup: sets up clocks for UART1 - * divider1: 3-bit divider value - * divider2: 10-bit divider value - */ -void uart1_clk_setup(u8 divider1, u16 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(UART1CLKINTERNAL_MASK))); - assert(!(divider2 & ~(UART1CLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(UART1CLKINTERNAL_CTRL_ADDR); - reg &= ~UART1CLKINTERNAL_MASK; - reg |= divider1 & UART1CLKINTERNAL_MASK; - write32_x(UART1CLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(UART1CLKOUT_CTRL_ADDR); - reg &= ~UART1CLKOUT_MASK; - reg |= divider2 & UART1CLKOUT_MASK; - write32_x(UART1CLKOUT_CTRL_ADDR, reg); -} - -/* - * i2c_clk_setup: sets up clocks for I2C - * divider1: 7-bit divider value - * divider2: 7-bit divider value - */ -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(I2CCLKDIV1_MASK))); - assert(!(divider2 & ~(I2CCLKOUT_MASK))); - assert(interface < 4); - /* Set divider 1 */ - reg = read32_x(I2CCLKDIV1_CTRL_ADDR(interface)); - reg &= ~I2CCLKDIV1_MASK; - reg |= divider1 & I2CCLKDIV1_MASK; - write32_x(I2CCLKDIV1_CTRL_ADDR(interface), reg); - - /* Set divider 2 */ - reg = read32_x(I2CCLKOUT_CTRL_ADDR(interface)); - reg &= ~I2CCLKOUT_MASK; - reg |= divider2 & I2CCLKOUT_MASK; - write32_x(I2CCLKOUT_CTRL_ADDR(interface), reg); -} - -/* system_clk_setup: sets up the system (peripheral) clock */ -void system_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(SYSCLKINTERNAL_MASK))); - - /* Set system clock divider */ - reg = read32_x(SYSCLKINTERNAL_CTRL_ADDR); - reg &= ~SYSCLKINTERNAL_MASK; - reg |= divider & SYSCLKINTERNAL_MASK; - write32_x(SYSCLKINTERNAL_CTRL_ADDR, reg); - - /* Small delay to cover a maximum lock time of 1500 cycles */ - udelay(SYS_CLK_LOCK_DELAY); -} - -void mips_clk_setup(u8 divider1, u8 divider2) -{ - u32 reg; - - /* Check input parameters */ - assert(!(divider1 & ~(MIPSCLKINTERNAL_MASK))); - assert(!(divider2 & ~(MIPSCLKOUT_MASK))); - - /* Set divider 1 */ - reg = read32_x(MIPSCLKINTERNAL_CTRL_ADDR); - reg &= ~MIPSCLKINTERNAL_MASK; - reg |= divider1 & MIPSCLKINTERNAL_MASK; - write32_x(MIPSCLKINTERNAL_CTRL_ADDR, reg); - - /* Set divider 2 */ - reg = read32_x(MIPSCLKOUT_CTRL_ADDR); - reg &= ~MIPSCLKOUT_MASK; - reg |= divider2 & MIPSCLKOUT_MASK; - write32_x(MIPSCLKOUT_CTRL_ADDR, reg); -} - -/* usb_clk_setup: sets up USB clock */ -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel) -{ - u32 reg; - struct stopwatch sw; - - /* Check input parameters */ - assert(!(divider & ~(USBPHYCLKOUT_MASK))); - assert(!((refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - ~(USBPHYSTRAPCTRL_REFCLKSEL_MASK))); - assert(!((fsel << USBPHYCONTROL1_FSEL_SHIFT) & - ~(USBPHYCONTROL1_FSEL_MASK))); - - /* Set USB divider */ - reg = read32_x(USBPHYCLKOUT_CTRL_ADDR); - reg &= ~USBPHYCLKOUT_MASK; - reg |= divider & USBPHYCLKOUT_MASK; - write32_x(USBPHYCLKOUT_CTRL_ADDR, reg); - - /* Set REFCLKSEL */ - reg = read32_x(USBPHYSTRAPCTRL_ADDR); - reg &= ~USBPHYSTRAPCTRL_REFCLKSEL_MASK; - reg |= (refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) & - USBPHYSTRAPCTRL_REFCLKSEL_MASK; - write32_x(USBPHYSTRAPCTRL_ADDR, reg); - - /* Set FSEL */ - reg = read32_x(USBPHYCONTROL1_ADDR); - reg &= ~USBPHYCONTROL1_FSEL_MASK; - reg |= (fsel << USBPHYCONTROL1_FSEL_SHIFT) & - USBPHYCONTROL1_FSEL_MASK; - write32_x(USBPHYCONTROL1_ADDR, reg); - - /* Waiting for USB clock status */ - stopwatch_init_usecs_expire(&sw, USB_TIMEOUT_VALUE_US); - while (1) { - reg = read32_x(USBPHYSTATUS_ADDR); - if (reg & USBPHYSTATUS_VBUS_FAULT_MASK) - return USB_VBUS_FAULT; - if (stopwatch_expired(&sw)) - return USB_TIMEOUT; - /* Check if USB is set up properly */ - if ((reg & USBPHYSTATUS_RX_PHY_CLK_MASK) && - (reg & USBPHYSTATUS_RX_UTMI_CLK_MASK)) - break; - } - - return CLOCKS_OK; -} - -void rom_clk_setup(u8 divider) -{ - u32 reg; - - /* Check input parameter */ - assert(!(divider & ~(ROMCLKOUT_MASK))); - - /* Set ROM divider */ - reg = read32_x(ROMCLKOUT_CTRL_ADDR); - reg &= ~ROMCLKOUT_MASK; - reg |= divider & ROMCLKOUT_MASK; - write32_x(ROMCLKOUT_CTRL_ADDR, reg); -} - -void eth_clk_setup(u8 mux, u8 divider) -{ - - u32 reg; - - /* Check input parameters */ - assert(!(divider & ~(ENETCLKDIV_MASK))); - /* This can be either 0 or 1, selecting between - * ENET and system clock as clocksource */ - assert(!(mux & ~(0x1))); - - /* Set ETH divider */ - reg = read32_x(ENETCLKDIV_CTRL_ADDR); - reg &= ~ENETCLKDIV_MASK; - reg |= divider & ENETCLKDIV_MASK; - write32_x(ENETCLKDIV_CTRL_ADDR, reg); - - /* Select source */ - if (mux) { - reg = read32_x(PISTACHIO_CLOCK_SWITCH); - reg |= ENETCLKMUX_MASK; - write32_x(PISTACHIO_CLOCK_SWITCH, reg); - } -} - -void setup_clk_gate_defaults(void) -{ - write32_x(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON); - write32_x(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF); -} diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c deleted file mode 100644 index 39b553d..0000000 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ /dev/null @@ -1,443 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <soc/ddr_init.h> -#include <soc/ddr_private_reg.h> -#include <stdint.h> - -#define BL8 0 - -/* - * Configuration for the Winbond W972GG6JB-25 part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr2(void) -{ - - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - note must be done together, - * not sequentially - */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000); - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* - * Dummy read to fence the access between the reset above - * and thw DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 0 = 4 1 = 8 - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 0 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, - 0x00060000 | (BL8 ? 0x1 : 0x0)); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR2 2 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A); - /* Generate to use with PHY and PCTL - * MR0 : MR Register, bits 12:0 imported dfrom MR - * 2:0 BL 8 011 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (101) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0)); - /* MR1 : EMR Register - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 1 DIC Output Driver Imp Ctl 0 Full, 1 Half - * 6,2 ODT 0 Disable, 1 75R, 2 150R, 3 50R; LSB: 2, MSB: 6 - * 5:3 AL = 0 - * 9:7 OCD = 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 RDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044); - /* MR2 : EMR2 Register - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 DDC NA 0 - * 6:4 RSVD - * 7 SFR 0 - * 15:8 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 0 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 2 - * 4:2 tRTP 3 - * 7:5 tWTR 3 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 18 - * 24:21 tRRD 4 - * 30:25 tRC 24 (23) - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 4 Bank Act 45ns = 18 18 - * 10:9 tMOD DDR3 Only 0 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 195ns 78 def 131 78d - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 200, 200d - * 14:10 tXP PD Exit Del 8 3 - * 18:15 tCKE CKE Min pulse 3 - * 28:19 tDLLK DLL Lock time 200d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880 - * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : use PHY for DRAM Init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra tRPall 8 bank 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* - * TRAS : Activate to Precharge cmd time - * Range 8 to 24: 45ns / 2.5ns = 18d - */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012); - /* - * TRC : Min. ROW cycle time - * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018); - /* - * TRCD : Row to Column Delay - * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* - * TWTR : Write to read turn around time - * Range 2 to 4: 7.3ns / 2.5ns = 3 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8); - /* - * TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* - * TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* - * TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* - * TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001)) - return DDR_TIMEOUT; - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 0 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 4 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004); - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - if (BL8) - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - else - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0); - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c deleted file mode 100644 index 7392525..0000000 --- a/src/soc/imgtec/pistachio/ddr3_init.c +++ /dev/null @@ -1,514 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/mmio.h> -#include <soc/ddr_init.h> -#include <soc/ddr_private_reg.h> - -/* - * Configuration for the Winbond W631GG6KB part using - * Synopsys DDR uMCTL and DDR Phy - */ -int init_ddr3(void) -{ - uint32_t temp_rw_val; - - temp_rw_val = read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* Set CLK_EN = 1 */ - temp_rw_val |= 0x2; - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - /* - * Reset the AXI bridge and DDR Controller in case any spurious - * writes have already happened to DDR - */ - /* Drive the 3 resets low */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* And release */ - write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F); - /* Dummy read to fence the access between the reset above and - * the DDR controller writes below - */ - read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET); - - /* Timings for 400MHz - * therefore 200MHz (5ns) uMCTL (Internal) Rate - */ - /* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8); - /* TINIT: t_init Timing Register: at least 200us 200h C8h */ - write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8); - /* TRSTH: Reset High Time Register DDR3 ONLY */ - write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4); - /* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/ - write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014); - /* DTUAWDT DTU Address Width Register - * 1:0 column_addr_width Def 10 - 7 3 10 bits - * 4:3 bank_addr_width Def 3 - 2 1 3 bits (8 bank) - * 7:6 row_addr_width Def 14 - 13 1 3 bits - * 10:9 number_ranks Def 1 - 1 0 0 1 Rank - */ - write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B); - /* MCFG - * 0 BL 1 -> 8 fixed - * 1 RDRIMM 0 - * 2 BL8 Burst Terminate 0 - * 3 2T = 0 - * 4 Multi Rank 0 - * 5 DDR3 En 1 - * 6 LPDDR S4 En - * 7 BST En 0, 1 for LPDDR2/3 - * 15:8 Power down Idle, passed by argument - * 16 Power Down Type, passed by argument - * 17 Power Down Exit 0 = slow, 1 = fast, pba - * 19:18 tFAW 45ns = 9 clk 5*2 -1 1h - * 21:20 mDDR/LPDDR2 BL 0 - * 23:22 mDDR/LPDDR2 Enable 0 - * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021); - /* MCFG1: Memory Configuration-1 Register - * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB - * 10:8 Fine tune MCFG.19:18 -1 - * 15:11 Reserved - * 23:16 Hardware Idle Period NA 0 - * 30:24 Reserved - * 31 c_active_in_pin exit auto clk stop NA 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100); - /* DCR DRAM Config - * 2:0 SDRAM => DDR3 3 - * 3 DDR 8 Bank 1 - * 6:4 Primary DQ DDR3 Only 0 - * 7 Multi-Purpose Register DDR3 Only 0 - * 9:8 DDRTYPE LPDDR2 00 - * 26:10 Reserved - * 27 NOSRA No Simultaneous Rank Access 0 - * 28 DDR 2T 0 - * 29 UDIMM NA 0 - * 30 RDIMM NA 0 - * 31 TPD LPDDR2 0 - */ - write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B); - /* Generate to use with PHY and PCTL - * MR0 : DDR3 mode register 0 - * 1:0 BL 8 fixed 00 - * 3 BT Sequential 0 Interleaved 1 = 0 - * 6:4,2 CL 6 - * 7 TM Normal 0 - * 8 DLL Reset 1 (self Clearing) - * 11:9 WR 15 ns 6 (010) - * 12 PD Slow 1 Fast 0 0 - * 15:13 RSVD RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520); - /* MR1 : DDR3 mode register 1 - * Generate to use with PHY and PCTL - * 0 DE DLL Enable 0 Disable 1 - * 5,1 DIC Output Driver RZQ/6 - * 9,6,2 ODT RZQ/4 - * 4:3 AL = 0 - * 7 write leveling enabled 0 - * 10 DQS 0 diff, 1 single = 0 - * 11 TDQS NA 0 - * 12 QOFF Normal mode 0 - * 15:13 RSVD - * 31:16 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004); - /* MR2 : DDR3 mode register 2 - * Generate to use with PHY and PCTL - * 2:0 PASR, NA 000 - * 3 CWL 000 (5) tck = 22.5ns - * 6 auto self-refresh 1 - * 7 SRT normal 0 - * 8 RSVD - * 10:9 dynamic ODT 10 RZQ/2 - * 31:11 Reserved - */ - write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440); - /* MR3: DDR3 mode register 3 - * 1:0 MPRLOC 00 - * 2 MPR 0 - */ - write32_x(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000); - /* DTAR : Data Training Register - * 11:0 Data Training Column Address - * 27:12 Data Training Row Address - * 30:28 Data Training Bank Address - * 31 Data Training Use MPR (DDR3 Only) - */ - write32_x(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000); - /* DSGCR - * 0 PUREN Def 1 - * 1 BDISEN Def 1 - * 2 ZUEN Def 1 - * 3 LPIOPD DEf 1 0 - * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys - * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys - * 11 NOBUB No Bubbles, adds latency 1 - * 12 FXDLAT Fixed Read Latency 0 - * 15:13 Reserved - * 19:16 CKEPDD CKE Power Down 0000 - * 23:20 ODTPDD ODT Power Down 0000 - * 24 NL2PD Power Down Non LPDDR2 pins 0 - * 25 NL2OE Output Enable Non LPDDR2 pins 1 - * 26 TPDPD LPDDR Only 0 - * 27 TPDOE LPDDR Only 1 - * 28 CKOE Output Enable Clk's 1 - * 29 ODTOE Output Enable ODT 1 - * 30 RSTOE RST# Output Enable 1 - * 31 CKEOE CKE Output Enable 1 - */ - write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927); - /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ - write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); - /* DTPR0 : DRAM Timing Params 0 - * 1:0 tMRD 0 - * 4:2 tRTP 2 - * 7:5 tWTR 4 - * 11:8 tRP 6 - * 15:12 tRCD 6 - * 20:16 tRAS 15 - * 24:21 tRRD 4 for x16 - * 30:25 tRC 21 - * 31 tCCD 0 BL/2 Cas to Cas - */ - write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688); - /* DTPR1 : DRAM Timing Params 1 - * 1:0 ODT On/Off Del Std 0 - * 2 tRTW Rd2Wr Del 0 std 1 +1 0 - * 8:3 tFAW 20 Clk - * 10:9 tMOD DDR3 Only 15 - * 11 tRTODT DDR3 Only 0 - * 15:12 Reserved - * 23:16 tRFC 160ns 64 ref 131 - * 26:24 tDQSCK LPDDR2 only 1 - * 29:27 tDQSCKmax 1 - * 31:30 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0); - /* DTPR2 : DRAM Timing Params 2 - * 9:0 tXS exit SR def 512d - * 14:10 tXP PD Exit Del 8 5 - * 18:15 tCKE CKE Min pulse 5 - * 28:19 tDLLK DLL Lock time 512d - * 32:29 Reserved - */ - write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600); - /* PTR0 : PHY Timing Params 0 - * 5:0 tDLLRST Def 27 - * 17:6 tDLLLOCK Def 2750 - * 21:18 tITMSRST Def 8 - * 31:22 Reserved 0 - */ - write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B); - /* PTR1 : PHY Timing Params 1 - * 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40 - * 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68 - */ - write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40); - /* DQS gating configuration: passive windowing mode */ - /* - * PGCR: PHY General cofiguration register - * 0 ITM DDR mode: 0 - * 1 DQS gading configuration: passive windowing 1 - * 2 DQS drift compensation: not supported in passive windowing 0 - * 4:3 DQS drift limit 0 - * 8:5 Digital test output select 0 - * 11:9 CK Enable: one bit for each 3 CK pair: 0x7 - * 13:12 CK Disable values: 0x2 - * 14 CK Invert 0 - * 15 IO loopback 0 - * 17:16 I/O DDR mode 0 - * 21:18 Ranks enable by training: 0xF - * 23:22 Impedance clock divider select 0x2 - * 24 Power down disable 1 - * 28:25 Refresh during training 0 - * 29 loopback DQS shift 0 - * 30 loopback DQS gating 0 - * 31 loopback mode 0 - */ - write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02); - - /* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : PHY controlled init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007)) - return DDR_TIMEOUT; - /* PIR : controller DRAM initialization */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001); - /* PGSR : Wait for DRAM Init Done */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F)) - return DDR_TIMEOUT; - /********************************************************************/ - /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* POWCTL : Start the memory Power Up seq*/ - write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001); - /* POWSTAT : wait for POWER_UP_DONE */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* - * TREFI : t_refi Timing Register 1X - * 12:0 t_refi 7.8us in 100ns 0x4E - * 15:13 Reserved 0 - * 18:16 num_add_ref 0 - * 30:19 Reserved 0 - * 31 Update 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E); - /* TMRD : t_mrd Timing Register -- Range 2 to 4*/ - write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004); - /* - * TRFC : t_rfc Timing Register -- Range 15 to 131 - * 195ns / 2.5ns 78 x4E - */ - write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E); - /* TRP : t_rp Timing Register -- Range 3 to 7 - * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6 - * 17:16 rpea_extra DDR3 - value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006); - /* TAL : Additive Latency Register -- AL in MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000); - /* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */ - write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006); - /* TCWL : CAS Write Latency Register --CASL-1 */ - write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005); - /* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */ - write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F); - /* TRC : Min. ROW cycle time 21 - * 57.5ns / 2.5ns = 23d Playing safe 24 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015); - /* TRCD : Row to Column Delay # Range 3 to 7 (TCL = TRCD) - * 12.5ns / 2.5ns = 5 but running 6-6-6 6 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006); - /* TRRD : Row to Row delay -- Range 2 to 6 - * 2K Page 10ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004); - /* TRTP : Read to Precharge time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004); - /* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6 */ - write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006); - /* TWTR : Write to read turn around time -- Range 2 to 4 - * Largest 4 or 7.5ns / 2.5ns = 4 - */ - write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004); - /* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */ - write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200); - /* TXP : Exit Power Down to first valid cmd - * tXP 2, Settingto 3 to match PHY - */ - write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003); - /* TDQS : t_dqs Timing Register - * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /* TRTW : Read to Write turn around time Def 3 - * Actual gap t_bl + t_rtw - */ - write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); - /* TCKE : CKE min pulse width DEf 3 */ - write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); - /* TXPDLL : Slow Exit Power Down to first valid cmd delay - * tXARDS 10+AL = 10 - */ - write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A); - /* TCKESR : Min CKE Low width for Self refresh entry to exit - * t_ckesr = 0 DDR2 - */ - write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004); - /* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */ - write32_x(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F); - /* TZQCS : SDRAM ZQ Calibration Short Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040); - /* TZQCL : SDRAM ZQ Calibration Long Period */ - write32_x(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200); - /* SCFG : State Configuration Register (Enabling Self Refresh) - * 0 LP_en Leave Off for Bring Up 0 - * 5:1 Reserved - * 6 Synopsys Internal Only 0 - * 7 Enale PHY indication of LP Opportunity 1 - * 11:8 bbflags_timing max UPCTL_TCU_SED_P - tRP (16 - 6) Use 4 - * 16:12 Additional delay on accertion of ac_pdd 4 - * 31:17 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480); - /* TREFI_MEM_DDR3 */ - write32_x(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30); - - /* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002); - /* DFITRDDATAEN : Read cmd to dfi_rddata_en */ - write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002); - /* - * DFITPHYWRDATA : dfi_wrdata_en to drive wr data - * DFI Clks wrdata_en to wrdata Def 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000); - /* - * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid - * DFI clks max rddata_en to rddata_valid Def 15 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008); - /* DFISTCFG0 : Drive various DFI signals appropriately - * 0 dfi_init_start 1 - * 1 dfi_freq_ratio_en 1 - * 2 dfi_data_byte_disable_en 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007); - /* DFISTCFG1 : Enable various DFI support - * 0 dfi_dram_clk_disable_en 1 - * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001); - /* DFISTCFG2 : Enable Parity and asoc interrupt - * 0 dfi_parity_in Enable 1 - * 1 Interrupt on dfi_parity_error 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003); - /* DFILPCFG0 : DFI Low Power Interface Configuration - * 0 Enable DFI LP IF during PD 1 - * 3:1 Reserved - * 7:4 DFI tlp_wakeup time 0 - * 8 Enable DFI LP IF during SR 1 - * 11:9 Reserved - * 15:12 dfi_lp_wakeup in SR 0 - * 19:16 tlp_resp DFI 2.1 recomend 7 - * 23:20 Reserved - * 24 Enable DFI LP in Deep Power Down 0 - * 27:25 Reserved - * 31:28 DFI LP Deep Power Down Value 0 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101); - /* DFIODTCFG : DFI ODT Configuration - * Only Enabled on Rank0 Writes - * 0 rank0_odt_read_nsel 0 - * 1 rank0_odt_read_sel 0 - * 2 rank0_odt_write_nsel 0 - * 3 rank0_odt_write_sel 1 - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008); - /* DFIODTCFG1 : DFI ODT Configuration - * 4:0 odt_lat_w 0 - * 12:8 odt_lat_r 0 Def - * 4:0 odt_len_bl8_w 6 Def - * 12:8 odt_len_bl8_r 6 Def - */ - write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000); - - /* Memory initialization */ - /* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0 - * 3:0 cmd_opcode PREA 00001 - * 16:4 cmd_addr 0 - * 19:17 bank_addr 0 - * 23:20 rank_sel 0 0001 - * 27:24 cmddelay 0 - * 30:24 Reserved - */ - /* MCMD: MR2 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403)) - return DDR_TIMEOUT; - /* MCMD: MR3 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003)) - return DDR_TIMEOUT; - /* MCMD: MR1 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043)) - return DDR_TIMEOUT; - /* MCMD: MR0 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203)) - return DDR_TIMEOUT; - /* MCMD: ZQS cmd, long 5 short 4 */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000)) - return DDR_TIMEOUT; - /* MCMD: deselect command */ - write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A); - /* MRS cmd wait for completion */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A)) - return DDR_TIMEOUT; - - /* DCFG : DRAM Density 256 Mb 16 Bit IO Width - * 1:0 Devicw Width 1 x8, 2 x16, 3 x32 2 - * 5:2 Density 2Gb = 5 - * 6 Dram Type (MDDR/LPDDR2) Only 0 - * 7 Reserved 0 - * 10:8 Address Map R/B/C = 1 - * 31:11 Reserved - */ - write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116); - /* PCFG_0 : Port 0 AXI config */ - write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0); - /* SCTL : UPCTL switch INIT CONFIG State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001)) - return DDR_TIMEOUT; - /* STAT : Wait for Switch INIT to Config State */ - write32_x(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET, - 0x00000001)) - return DDR_TIMEOUT; - /* Use PHY for DRAM init */ - write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181); - /* STAT : Wait for Switch INIT to Config State */ - if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F)) - return DDR_TIMEOUT; - /* Disable Impedance Calibration */ - write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); - write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); - - /* SCTL : UPCTL switch Config to ACCESS State */ - write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002); - /* STAT : Wait for switch CFG -> GO State */ - if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3)) - return DDR_TIMEOUT; - - return 0; -} diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h deleted file mode 100644 index 27ba6d6..0000000 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ -#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__ - -#include <stdint.h> - -/* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); -int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); - -/* Peripheral divider setting */ -void system_clk_setup(u8 divider); -void mips_clk_setup(u8 divider1, u8 divider2); -void uart1_clk_setup(u8 divider1, u16 divider2); -void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface); -int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); -void rom_clk_setup(u8 divider); -void eth_clk_setup(u8 mux, u8 divider); -void setup_clk_gate_defaults(void); -enum { - CLOCKS_OK = 0, - PLL_TIMEOUT = -1, - USB_TIMEOUT = -2, - USB_VBUS_FAULT = -3 -}; - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h deleted file mode 100644 index c22dceb..0000000 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_DANUBE_CPU_H__ -#define __SOC_IMGTEC_DANUBE_CPU_H__ - -#include <device/mmio.h> - -#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 -#define IMG_SPIM1_BASE_ADDRESS 0xB8101000 - -/* - * This register holds the FPGA image version - * If we're not working on the FPGA this will be 0 - */ -#define PRIMARY_FPGA_VERSION 0xB8149060 -#define IMG_PLATFORM_ID() read32_x(PRIMARY_FPGA_VERSION) -#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */ -#define IMG_PLATFORM_ID_SILICON 0 - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_init.h b/src/soc/imgtec/pistachio/include/soc/ddr_init.h deleted file mode 100644 index d8b5b19..0000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_init.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__ - -#define DDR_TIMEOUT -1 - -int init_ddr2(void); -int init_ddr3(void); - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h deleted file mode 100644 index eab5b3a..0000000 --- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ -#define __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__ - -#include <device/mmio.h> -#include <timer.h> - -#define MAX_WAIT_MICROS 100000 - -#define TOPLEVEL_REGS 0xB8149000 - -#define DDR_CTRL_OFFSET (0x0020) -#define DDR_CLK_EN_MASK (0x00000002) -#define DDR_CLK_EN_SHIFT (1) -#define DDR_CLK_EN_LENGTH (1) - -#define DDR_PCTL 0xB8180000 -#define DDR_PCTL_SCFG_OFFSET (0x0000) -#define DDR_PCTL_SCTL_OFFSET (0x0004) -#define DDR_PCTL_STAT_OFFSET (0x0008) -#define DDR_PCTL_MCMD_OFFSET (0x0040) -#define DDR_PCTL_POWCTL_OFFSET (0x0044) -#define DDR_PCTL_POWSTAT_OFFSET (0x0048) -#define DDR_PCTL_CMDTSTAT_OFFSET (0x004C) -#define DDR_PCTL_CMDTSTATEN_OFFSET (0x0050) -#define DDR_PCTL_MCFG1_OFFSET (0x007C) -#define DDR_PCTL_MCFG_OFFSET (0x0080) -#define DDR_PCTL_MSTAT_OFFSET (0x0088) -#define DDR_PCTL_DTUAWDT_OFFSET (0x00B0) -#define DDR_PCTL_TOGCNT1U_OFFSET (0x00C0) -#define DDR_PCTL_TINIT_OFFSET (0x00C4) -#define DDR_PCTL_TRSTH_OFFSET (0x00C8) -#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET (0x00CC) -#define DDR_PCTL_TREFI_OFFSET (0x00D0) -#define DDR_PCTL_TMRD_OFFSET (0x00D4) -#define DDR_PCTL_TRFC_OFFSET (0x00D8) -#define DDR_PCTL_TRP_OFFSET (0x00DC) -#define DDR_PCTL_TRTW_OFFSET (0x00E0) -#define DDR_PCTL_TAL_OFFSET (0x00E4) -#define DDR_PCTL_TCL_OFFSET (0x00E8) -#define DDR_PCTL_TCWL_OFFSET (0x00EC) -#define DDR_PCTL_TRAS_OFFSET (0x00F0) -#define DDR_PCTL_TRC_OFFSET (0x00F4) -#define DDR_PCTL_TRCD_OFFSET (0x00F8) -#define DDR_PCTL_TRRD_OFFSET (0x00FC) -#define DDR_PCTL_TRTP_OFFSET (0x0100) -#define DDR_PCTL_TWR_OFFSET (0x0104) -#define DDR_PCTL_TWTR_OFFSET (0x0108) -#define DDR_PCTL_TEXSR_OFFSET (0x010C) -#define DDR_PCTL_TXP_OFFSET (0x0110) -#define DDR_PCTL_TXPDLL_OFFSET (0x0114) -#define DDR_PCTL_TZQCS_OFFSET (0x0118) -#define DDR_PCTL_TDQS_OFFSET (0x0120) -#define DDR_PCTL_TCKE_OFFSET (0x012C) -#define DDR_PCTL_TMOD_OFFSET (0x0130) -#define DDR_PCTL_TZQCL_OFFSET (0x0138) -#define DDR_PCTL_TCKESR_OFFSET (0x0140) -#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET (0x0148) -#define DDR_PCTL_DTUWACTL_OFFSET (0x0200) -#define DDR_PCTL_DTURACTL_OFFSET (0x0204) -#define DDR_PCTL_DTUCFG_OFFSET (0x0208) -#define DDR_PCTL_DTUECTL_OFFSET (0x020C) -#define DDR_PCTL_DTUWD0_OFFSET (0x0210) -#define DDR_PCTL_DTUWD1_OFFSET (0x0214) -#define DDR_PCTL_DTUWD2_OFFSET (0x0218) -#define DDR_PCTL_DTUWD3_OFFSET (0x021C) -#define DDR_PCTL_DFIODTCFG_OFFSET (0x0244) -#define DDR_PCTL_DFIODTCFG1_OFFSET (0x0248) -#define DDR_PCTL_DFITPHYWRDATA_OFFSET (0x0250) -#define DDR_PCTL_DFIWRLAT_OFFSET (0x0254) -#define DDR_PCTL_DFITRDDATAEN_OFFSET (0x0260) -#define DDR_PCTL_DFITPHYRDLAT_OFFSET (0x0264) -#define DDR_PCTL_DFIUPDCFG_OFFSET (0x0290) -#define DDR_PCTL_DFISTAT0_OFFSET (0x02C0) -#define DDR_PCTL_DFISTCFG0_OFFSET (0x02C4) -#define DDR_PCTL_DFISTCFG1_OFFSET (0x02C8) -#define DDR_PCTL_DFISTCFG2_OFFSET (0x02D8) -#define DDR_PCTL_DFILPCFG0_OFFSET (0x02F0) -#define DDR_PCTL_PCFG0_OFFSET (0x0400) -#define DDR_PCTL_CCFG_OFFSET (0x0480) -#define DDR_PCTL_DCFG_OFFSET (0x0484) -#define DDR_PCTL_CCFG1_OFFSET (0x048C) - -#define DDR_PHY 0xB8180800 -#define DDRPHY_PIR_OFFSET (0x0004) -#define DDRPHY_PGCR_OFFSET (0x0008) -#define DDRPHY_PGSR_OFFSET (0x000C) -#define DDRPHY_DLLGCR_OFFSET (0x0010) -#define DDRPHY_PTR0_OFFSET (0x0018) -#define DDRPHY_PTR1_OFFSET (0x001C) -#define DDRPHY_DXCCR_OFFSET (0x0028) -#define DDRPHY_DSGCR_OFFSET (0x002C) -#define DDRPHY_DCR_OFFSET (0x0030) -#define DDRPHY_DTPR0_OFFSET (0x0034) -#define DDRPHY_DTPR1_OFFSET (0x0038) -#define DDRPHY_DTPR2_OFFSET (0x003C) -#define DDRPHY_MR_OFFSET (0x0040) -#define DDRPHY_EMR_OFFSET (0x0044) -#define DDRPHY_EMR2_OFFSET (0x0048) -#define DDRPHY_EMR3_OFFSET (0x004C) -#define DDRPHY_DTAR_OFFSET (0x0054) -#define DDRPHY_BISTRR_OFFSET (0x0100) -#define DDRPHY_BISTWCR_OFFSET (0x010C) -#define DDRPHY_BISTAR0_OFFSET (0x0114) -#define DDRPHY_BISTAR1_OFFSET (0x0118) -#define DDRPHY_BISTAR2_OFFSET (0x011C) -#define DDRPHY_BISTUDPR_OFFSET (0x0120) -#define DDRPHY_BISTGSR_OFFSET (0x0124) -#define DDRPHY_ZQ0CR0_OFFSET (0x0180) -#define DDRPHY_ZQ1CR0_OFFSET (0x0190) - -#define DDR_TIMEOUT_VALUE_US 100000 - -static int wait_for_completion(u32 reg, u32 exp_val) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US); - while (read32_x(reg) != exp_val) { - if (stopwatch_expired(&sw)) - return DDR_TIMEOUT; - } - return 0; -} - -#endif diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h deleted file mode 100644 index f2427f24..0000000 --- a/src/soc/imgtec/pistachio/include/soc/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__ -#define __SOC_IMGTECH_PISTACHIO_GPIO_H__ - -typedef unsigned gpio_t; - -#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__ diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld deleted file mode 100644 index cd81093..0000000 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* SRAM memory is mapped in two different locations. Define regions in both for - * full overlap checking and use this to guarantee they're kept in sync. */ -#define ASSERT_MIRRORED(r1, r2) \ - _ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \ - (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \ - STR(r1 and r2 do not match!)); - -SECTIONS -{ - /* - * All of DRAM (other than the DMA coherent area) is accessed through - * the identity mapping. - */ - DRAM_START(0x00000000) - /* DMA coherent area: accessed via KSEG1. */ - DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 512K) - RAMSTAGE(0x00280000, 128K) - - /* 0x18100000 -> 0x18540000 */ - SOC_REGISTERS(0x18100000, 0x440000) - /* - * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock - * and then through the identity mapping in ROM stage. - */ - SRAM_START(0x1a000000) - REGION(gram_bootblock, 0x1a000000, 28K, 1) - ROMSTAGE(0x1a007000, 60K) - VBOOT2_WORK(0x1a016000, 12K) - VBOOT2_TPM_LOG(0x1a019000, 2K) - PRERAM_CBFS_CACHE(0x1a019800, 46K) - SRAM_END(0x1a066000) - - /* Bootblock executes out of KSEG0 and sets up the identity mapping. - * This is identical to SRAM above, and thus also limited 64K and - * needs to avoid conflicts with items set up above. - */ - BOOTBLOCK(0x9a000000, 28K) - REGION(kseg0_romstage, 0x9a007000, 60K, 1) - - /* - * Let's use SRAM for stack and CBMEM console. Always accessed - * through KSEG0. - */ - STACK(0x9b000000, 8K) - PRERAM_CBMEM_CONSOLE(0x9b002000, 8K) - -} - -ASSERT_MIRRORED(bootblock, gram_bootblock) -ASSERT_MIRRORED(romstage, kseg0_romstage) diff --git a/src/soc/imgtec/pistachio/include/soc/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h deleted file mode 100644 index f23cca5..0000000 --- a/src/soc/imgtec/pistachio/include/soc/spi.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef __SOC_IMGTEC_DANUBE_SPI_H__ -#define __SOC_IMGTEC_DANUBE_SPI_H__ - -#include <arch/types.h> - -#define spi_read_reg_field(regval, field) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (regval) : \ - (((regval) & (field##_MASK)) >> (field##_SHIFT))\ -) - -#define spi_write_reg_field(regval, field, val) \ -( \ - ((field##_MASK) == 0xFFFFFFFF) ? \ - (val) : \ - (((regval) & ~(field##_MASK)) | \ - (((val) << (field##_SHIFT)) & (field##_MASK))) \ -) - -/* - * Parameter register - * Each of these corresponds to a single port (ie CS line) in the interface - * Fields Name Description - * ====== ==== =========== - * b31:24 CLK_RATE Bit Clock rate = (24.576 * value / 512) MHz - * b23:16 CS_SETUP Chip Select setup = (40 * value) ns - * b15:8 CS_HOLD Chip Select hold = (40 * value) ns - * b7:0 CS_DELAY Chip Select delay = (40 * value) ns - */ - -#define SPIM_CLK_DIVIDE_MASK (0xFF000000) -#define SPIM_CS_SETUP_MASK (0x00FF0000) -#define SPIM_CS_HOLD_MASK (0x0000FF00) -#define SPIM_CS_DELAY_MASK (0x000000FF) -#define SPIM_CS_PARAM_MASK (SPIM_CS_SETUP_MASK \ - | SPIM_CS_HOLD_MASK \ - | SPIM_CS_DELAY_MASK) - -#define SPIM_CLK_DIVIDE_SHIFT (24) -#define SPIM_CS_SETUP_SHIFT (16) -#define SPIM_CS_HOLD_SHIFT (8) -#define SPIM_CS_DELAY_SHIFT (0) -#define SPIM_CS_PARAM_SHIFT (0) - -/* Control register */ - -#define SPFI_DRIBBLE_COUNT_MASK (0x000e0000) -#define SPFI_MEMORY_IF_MASK (0x00008000) -#define SPIM_BYTE_DELAY_MASK (0x00004000) -#define SPIM_CS_DEASSERT_MASK (0x00002000) -#define SPIM_CONTINUE_MASK (0x00001000) -#define SPIM_SOFT_RESET_MASK (0x00000800) -#define SPIM_SEND_DMA_MASK (0x00000400) -#define SPIM_GET_DMA_MASK (0x00000200) -#define SPIM_EDGE_TX_RX_MASK (0x00000100) -#define SPFI_TRNSFR_MODE_MASK (0x000000e0) -#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c) -#define SPFI_TX_RX_MASK (0x00000002) -#define SPFI_EN_MASK (0x00000001) - -#define SPFI_DRIBBLE_COUNT_SHIFT (17) -#define SPFI_MEMORY_IF_SHIFT (15) -#define SPIM_BYTE_DELAY_SHIFT (14) -#define SPIM_CS_DEASSERT_SHIFT (13) -#define SPIM_CONTINUE_SHIFT (12) -#define SPIM_SOFT_RESET_SHIFT (11) -#define SPIM_SEND_DMA_SHIFT (10) -#define SPIM_GET_DMA_SHIFT (9) -#define SPIM_EDGE_TX_RX_SHIFT (8) -#define SPFI_TRNSFR_MODE_SHIFT (5) -#define SPFI_TRNSFR_MODE_DQ_SHIFT (2) -#define SPFI_TX_RX_SHIFT (1) -#define SPFI_EN_SHIFT (0) - -/* Transaction register */ - -#define SPFI_TSIZE_MASK (0xffff0000) -#define SPFI_CMD_LENGTH_MASK (0x0000e000) -#define SPFI_ADDR_LENGTH_MASK (0x00001c00) -#define SPFI_DUMMY_LENGTH_MASK (0x000003e0) -#define SPFI_PI_LENGTH_MASK (0x0000001c) - -#define SPFI_TSIZE_SHIFT (16) -#define SPFI_CMD_LENGTH_SHIFT (13) -#define SPFI_ADDR_LENGTH_SHIFT (10) -#define SPFI_DUMMY_LENGTH_SHIFT (5) -#define SPFI_PI_LENGTH_SHIFT (2) - -/* Port state register */ - -#define SPFI_PORT_SELECT_MASK (0x00700000) -/* WARNING the following bits are reversed */ -#define SPFI_CLOCK0_IDLE_MASK (0x000f8000) -#define SPFI_CLOCK0_PHASE_MASK (0x00007c00) -#define SPFI_CS0_IDLE_MASK (0x000003e0) -#define SPFI_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_CLOCK0_IDLE_MASK (0x000f8000) -#define SPIM_CLOCK0_PHASE_MASK (0x00007c00) -#define SPIM_CS0_IDLE_MASK (0x000003e0) -#define SPIM_DATA0_IDLE_MASK (0x0000001f) - -#define SPIM_PORT0_MASK (0x00084210) - -#define SPFI_PORT_SELECT_SHIFT (20) -/* WARNING the following bits are reversed, bit 0 is highest */ -#define SPFI_CLOCK0_IDLE_SHIFT (19) -#define SPFI_CLOCK0_PHASE_SHIFT (14) -#define SPFI_CS0_IDLE_SHIFT (9) -#define SPFI_DATA0_IDLE_SHIFT (4) - -#define SPIM_CLOCK0_IDLE_SHIFT (19) -#define SPIM_CLOCK0_PHASE_SHIFT (14) -#define SPIM_CS0_IDLE_SHIFT (9) -#define SPIM_DATA0_IDLE_SHIFT (4) - - -/* - * Interrupt registers - * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls - * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls - */ -#define SPFI_IACCESS_MASK (0x00001000) -#define SPFI_GDEX8BIT_MASK (0x00000800) -#define SPFI_ALLDONE_MASK (0x00000200) -#define SPFI_GDFUL_MASK (0x00000100) -#define SPFI_GDHF_MASK (0x00000080) -#define SPFI_GDEX32BIT_MASK (0x00000040) -#define SPFI_GDTRIG_MASK (0x00000020) -#define SPFI_SDFUL_MASK (0x00000008) -#define SPFI_SDHF_MASK (0x00000004) -#define SPFI_SDE_MASK (0x00000002) -#define SPFI_SDTRIG_MASK (0x00000001) - -#define SPFI_IACCESS_SHIFT (12) -#define SPFI_GDEX8BIT_SHIFT (11) -#define SPFI_ALLDONE_SHIFT (9) -#define SPFI_GDFUL_SHIFT (8) -#define SPFI_GDHF_SHIFT (7) -#define SPFI_GDEX32BIT_SHIFT (6) -#define SPFI_GDTRIG_SHIFT (5) -#define SPFI_SDFUL_SHIFT (3) -#define SPFI_SDHF_SHIFT (2) -#define SPFI_SDE_SHIFT (1) -#define SPFI_SDTRIG_SHIFT (0) - - -/* SPFI register block */ - -#define SPFI_PORT_0_PARAM_REG_OFFSET (0x00) -#define SPFI_PORT_1_PARAM_REG_OFFSET (0x04) -#define SPFI_PORT_2_PARAM_REG_OFFSET (0x08) -#define SPFI_PORT_3_PARAM_REG_OFFSET (0x0C) -#define SPFI_PORT_4_PARAM_REG_OFFSET (0x10) -#define SPFI_CONTROL_REG_OFFSET (0x14) -#define SPFI_TRANSACTION_REG_OFFSET (0x18) -#define SPFI_PORT_STATE_REG_OFFSET (0x1C) - -#define SPFI_SEND_LONG_REG_OFFSET (0x20) -#define SPFI_SEND_BYTE_REG_OFFSET (0x24) -#define SPFI_GET_LONG_REG_OFFSET (0x28) -#define SPFI_GET_BYTE_REG_OFFSET (0x2C) - -#define SPFI_INT_STATUS_REG_OFFSET (0x30) -#define SPFI_INT_ENABLE_REG_OFFSET (0x34) -#define SPFI_INT_CLEAR_REG_OFFSET (0x38) - -#define SPFI_IMMEDIATE_STATUS_REG_OFFSET (0x3c) - -#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET (0x48) -#define SPFI_FLASH_STATUS_REG_OFFSET (0x4C) - -#define IMG_FALSE 0 -#define IMG_TRUE 1 - -/* Number of SPIM interfaces*/ -#define SPIM_NUM_BLOCKS 2 -/* Number of chip select lines supported by the SPI master port. */ -#define SPIM_NUM_PORTS_PER_BLOCK (SPIM_DUMMY_CS) -/* Maximum transfer size (in bytes) for the SPI master port. */ -#define SPIM_MAX_TRANSFER_BYTES (0xFFFF) -/* Maximum size of a flash command: command bytes+address_bytes. */ -#define SPIM_MAX_FLASH_COMMAND_BYTES (0x8) -/* Write operation to fifo done in blocks of 16 words (64 bytes) */ -#define SPIM_MAX_BLOCK_BYTES (0x40) -/* Number of tries until timeout error is returned*/ -#define SPI_TIMEOUT_VALUE_US 500000 - -/* SPIM initialisation function return value.*/ -enum spim_return { - /* Initialisation parameters are valid. */ - SPIM_OK = 0, - /* Mode parameter is invalid. */ - SPIM_INVALID_SPI_MODE, - /* Chip select idle level is invalid. */ - SPIM_INVALID_CS_IDLE_LEVEL, - /* Data idle level is invalid. */ - SPIM_INVALID_DATA_IDLE_LEVEL, - /* Chip select line parameter is invalid. */ - SPIM_INVALID_CS_LINE, - /* Transfer size parameter is invalid. */ - SPIM_INVALID_SIZE, - /* Read/write parameter is invalid. */ - SPIM_INVALID_READ_WRITE, - /* Continue parameter is invalid. */ - SPIM_INVALID_CONTINUE, - /* Invalid block index */ - SPIM_INVALID_BLOCK_INDEX, - /* Extended error values */ - /* Invalid bit rate */ - SPIM_INVALID_BIT_RATE, - /* Invalid CS hold value */ - SPIM_INVALID_CS_HOLD_VALUE, - /* API function called before API is initialised */ - SPIM_API_NOT_INITIALISED, - /* SPI driver initialisation failed */ - SPIM_DRIVER_INIT_ERROR, - /* Invalid transfer description */ - SPIM_INVALID_TRANSFER_DESC, - /* Timeout */ - SPIM_TIMEOUT - -}; - -/* This type defines the SPI Mode.*/ -enum spim_mode { - /* Mode 0 (clock idle low, data valid on first clock transition). */ - SPIM_MODE_0 = 0, - /* Mode 1 (clock idle low, data valid on second clock transition). */ - SPIM_MODE_1, - /* Mode 2 (clock idle high, data valid on first clock transition). */ - SPIM_MODE_2, - /* Mode 3 (clock idle high, data valid on second clock transition). */ - SPIM_MODE_3 - -}; - -/* This type defines the SPIM device numbers (chip select lines). */ -enum spim_device { - /* Device 0 (CS0). */ - SPIM_DEVICE0 = 0, - /* Device 1 (CS1). */ - SPIM_DEVICE1, - /* Device 2 (CS2). */ - SPIM_DEVICE2, - /* Device 3 (CS3). */ - SPIM_DEVICE3, - /* Device 4 (CS4). */ - SPIM_DEVICE4, - /* Dummy chip select. */ - SPIM_DUMMY_CS - -}; - -/* This structure defines communication parameters for a slave device */ -struct spim_device_parameters { - /* Bit rate value.*/ - unsigned char bitrate; - /* - * Chip select set up time. - * Time taken between chip select going active and activity occurring - * on the clock, calculated by dividing the desired set up time in ns - * by the Input clock period. (setup time / Input clock freq) - */ - unsigned char cs_setup; - /* - * Chip select hold time. - * Time after the last clock pulse before chip select goes inactive, - * calculated by dividing the desired hold time in ns by the - * Input clock period (hold time / Input clock freq). - */ - unsigned char cs_hold; - /* - * Chip select delay time (CS minimum inactive time). - * Minimum time after chip select goes inactive before chip select - * can go active again, calculated by dividing the desired delay time - * in ns by the Input clock period (delay time / Input clock freq). - */ - unsigned char cs_delay; - /* SPI Mode. */ - enum spim_mode spi_mode; - /* Chip select idle level (0=low, 1=high, Others=invalid). */ - unsigned int cs_idle_level; - /* Data idle level (0=low, 1=high, Others=invalid). */ - unsigned int data_idle_level; - -}; - -/* Command transfer mode */ -enum command_mode { - /* Command, address, dummy and PI cycles are transferred on sio0 */ - SPIM_CMD_MODE_0 = 0, - /* - * Command and Address are transferred on sio0 port only but dummy - * cycles and PI is transferred on all the interface ports. - */ - SPIM_CMD_MODE_1, - /* - * Command is transferred on sio0 port only but address, dummy - * and PI is transferred on all the interface portS - */ - SPIM_CMD_MODE_2, - /* - * Command, address, dummy and PI bytes are transferred on all - * the interfaces - */ - SPIM_CMD_MODE_3 -}; - -/* Data transfer mode */ -enum transfer_mode { - /* Transfer data in single mode */ - SPIM_DMODE_SINGLE = 0, - /* Transfer data in dual mode */ - SPIM_DMODE_DUAL, - /* Transfer data in quad mode */ - SPIM_DMODE_QUAD -}; - -/* This structure contains parameters that describe an SPIM operation. */ -struct spim_buffer { - /* The buffer to read from or write to. */ - unsigned char *buffer; - - /* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */ - unsigned int size; - - /* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/ - int isread; - - /* - * ByteDelay select. - * Selects whether or not a delay is inserted between bytes. - * 0 - Minimum inter-byte delay - * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk. - */ - int inter_byte_delay; -}; - -#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */ diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c deleted file mode 100644 index bbcd8a1..0000000 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cpu.h> -#include <device/mmio.h> -#include <soc/cpu.h> -#include <stdint.h> -#include <timer.h> - -#define PISTACHIO_CLOCK_SWITCH 0xB8144200 -#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 - -static int get_count_mhz_freq(void) -{ - static unsigned count_mhz_freq; - - if (!count_mhz_freq) { - if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON) - count_mhz_freq = 25; /* FPGA board */ - else { - /* If MIPS PLL external bypass bit is set, it means - * that the MIPS PLL is already set up to work at a - * frequency of 550 MHz; otherwise, the crystal is - * used with a frequency of 52 MHz - */ - if (read32_x(PISTACHIO_CLOCK_SWITCH) & - MIPS_EXTERN_PLL_BYPASS_MASK) - /* Half MIPS PLL freq. */ - count_mhz_freq = 275; - else - /* Half Xtal freq. */ - count_mhz_freq = 26; - } - } - return count_mhz_freq; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq()); -} diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c deleted file mode 100644 index cc56337..0000000 --- a/src/soc/imgtec/pistachio/reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <reset.h> - -#define PISTACHIO_WD_ADDR 0xB8102100 -#define PISTACHIO_WD_SW_RST_OFFSET 0x0000 - -void do_board_reset(void) -{ - /* Generate system reset */ - write32_x(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); -} diff --git a/src/soc/imgtec/pistachio/romstage.c b/src/soc/imgtec/pistachio/romstage.c deleted file mode 100644 index 8e44ea8..0000000 --- a/src/soc/imgtec/pistachio/romstage.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <console/console.h> -#include <halt.h> -#include <program_loading.h> -#include <soc/ddr_init.h> - -void main(void) -{ - int error; - console_init(); - error = init_ddr2(); - - if (!error) { - /* - * When romstage is running it's always on the reboot path and - * never a resume path where cbmem recovery is required. - * Therefore, always initialize the cbmem area to be empty. - */ - cbmem_initialize_empty(); - run_ramstage(); - } - halt(); -} diff --git a/src/soc/imgtec/pistachio/soc.c b/src/soc/imgtec/pistachio/soc.c deleted file mode 100644 index 156d1de..0000000 --- a/src/soc/imgtec/pistachio/soc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 The Chromium OS Authors. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <symbols.h> - -static void soc_read_resources(struct device *dev) -{ - ram_resource(dev, 0, (uintptr_t)_dram / KiB, - (CONFIG_DRAM_SIZE_MB * MiB) / KiB); -} - -static void soc_init(struct device *dev) -{ - printk(BIOS_INFO, "CPU: Imgtec Pistachio\n"); -} - -static struct device_operations soc_ops = { - .read_resources = soc_read_resources, - .init = soc_init, -}; - -static void enable_soc_dev(struct device *dev) -{ - dev->ops = &soc_ops; -} - -struct chip_operations soc_imgtec_pistachio_ops = { - CHIP_NAME("SOC: Imgtec Pistachio") - .enable_dev = enable_soc_dev, -}; diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c deleted file mode 100644 index acbbd90..0000000 --- a/src/soc/imgtec/pistachio/spi.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/mmio.h> -#include <soc/cpu.h> -#include <soc/spi.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <stdlib.h> -#include <string.h> -#include <timer.h> - -/* Imgtec controller uses 16 bit packet length. */ -#define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) - -struct img_spi_slave { - /* SPIM instance device parameters */ - struct spim_device_parameters device_parameters; - /* SPIM instance base address */ - u32 base; - /* Boolean property that is TRUE if API has been initialised */ - int initialised; -}; - -/* Allocate memory for the maximum number of devices */ -static struct -img_spi_slave img_spi_slaves[SPIM_NUM_BLOCKS*SPIM_NUM_PORTS_PER_BLOCK]; - -/* - * Wait for the bit at the shift position to be set in reg - * If the bit is not set in SPI_TIMEOUT_VALUE_US return with error - */ -static int wait_status(u32 reg, u32 shift) -{ - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_VALUE_US); - while (!(read32_x(reg) & (1 << shift))) { - if (stopwatch_expired(&sw)) - return -SPIM_TIMEOUT; - } - return SPIM_OK; -} - -static struct img_spi_slave *get_img_slave(const struct spi_slave *slave) -{ - return img_spi_slaves + slave->bus * SPIM_NUM_PORTS_PER_BLOCK + - slave->cs; -} - -/* Transmitter function. Fills TX FIFO with data before enabling SPIM */ -static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 blocksize, base, write_data; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - while (size) { - /* Wait until FIFO empty */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK); - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_SDE_SHIFT); - if (ret) - return ret; - - /* - * Write to FIFO in blocks of 16 words (64 bytes) - * Do 32bit writes first. - */ - blocksize = SPIM_MAX_BLOCK_BYTES; - while ((size >= sizeof(u32)) && blocksize) { - memcpy(&write_data, buffer, sizeof(u32)); - write32_x(base + SPFI_SEND_LONG_REG_OFFSET, write_data); - buffer += sizeof(u32); - size -= sizeof(u32); - blocksize -= sizeof(u32); - } - while (size && blocksize) { - write32_x(base + SPFI_SEND_BYTE_REG_OFFSET, *buffer); - buffer++; - size--; - blocksize--; - } - } - return SPIM_OK; -} - -/* Receiver function */ -static int receivedata(const struct spi_slave *slave, u8 *buffer, u32 size) -{ - u32 read_data, base; - int ret; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - /* - * Do 32bit reads first. Clear status GDEX32BIT here so that the first - * status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - while (size >= sizeof(u32)) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX32BIT_SHIFT); - if (ret) - return ret; - read_data = read32_x(base + SPFI_GET_LONG_REG_OFFSET); - memcpy(buffer, &read_data, sizeof(u32)); - buffer += sizeof(u32); - size -= sizeof(u32); - /* Clear interrupt status on GDEX32BITL */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK); - } - - /* - * Do the remaining 8bit reads. Clear status GDEX8BIT here so that - * the first status reg. read gets the actual bit state - */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - while (size) { - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_GDEX8BIT_SHIFT); - if (ret) - return ret; - *buffer = read32_x(base + SPFI_GET_BYTE_REG_OFFSET); - buffer++; - size--; - /* Clear interrupt status on SPFI_GDEX8BIT */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK); - } - return SPIM_OK; -} - -/* Sets port parameters in port state register. */ -static void setparams(const struct spi_slave *slave, u32 port, - struct spim_device_parameters *params) -{ - u32 spim_parameters, port_state, base; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - spim_parameters = 0; - port_state = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - port_state &= ~((SPIM_PORT0_MASK>>port)|SPFI_PORT_SELECT_MASK); - port_state |= params->cs_idle_level<<(SPIM_CS0_IDLE_SHIFT-port); - port_state |= - params->data_idle_level<<(SPIM_DATA0_IDLE_SHIFT-port); - - /* Clock idle level and phase */ - switch (params->spi_mode) { - case SPIM_MODE_0: - break; - case SPIM_MODE_1: - port_state |= (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - case SPIM_MODE_2: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)); - break; - case SPIM_MODE_3: - port_state |= (1 << (SPIM_CLOCK0_IDLE_SHIFT - port)) | - (1 << (SPIM_CLOCK0_PHASE_SHIFT - port)); - break; - } - /* Set port state register */ - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, port_state); - - /* Set up values to be written to device parameter register */ - spim_parameters |= params->bitrate << SPIM_CLK_DIVIDE_SHIFT; - spim_parameters |= params->cs_setup << SPIM_CS_SETUP_SHIFT; - spim_parameters |= params->cs_hold << SPIM_CS_HOLD_SHIFT; - spim_parameters |= params->cs_delay << SPIM_CS_DELAY_SHIFT; - - write32_x(base + SPFI_PORT_0_PARAM_REG_OFFSET + 4 * port, - spim_parameters); -} - -/* Sets up transaction register */ -static u32 transaction_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg = 0; - - /* 2nd transfer exists? */ - if (second) { - /* - * If second transfer exists, it's a "command followed by data" - * type of transfer and first transfer is defined by - * CMD_LENGTH, ADDR_LENGTH, DUMMY_LENGTH... fields of - * transaction register - */ - reg = spi_write_reg_field(reg, SPFI_CMD_LENGTH, 1); - reg = spi_write_reg_field(reg, SPFI_ADDR_LENGTH, - first->size - 1); - reg = spi_write_reg_field(reg, SPFI_DUMMY_LENGTH, 0); - /* Set data size (size of the second transfer) */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, second->size); - } else { - /* Set data size, in this case size of the 1st transfer */ - reg = spi_write_reg_field(reg, SPFI_TSIZE, first->size); - } - return reg; -} - -/* Sets up control register */ -static u32 control_reg_setup(struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg; - - /* Enable SPFI */ - reg = SPFI_EN_MASK; - reg |= first->inter_byte_delay ? SPIM_BYTE_DELAY_MASK : 0; - - /* Set up the transfer mode */ - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE_DQ, SPIM_CMD_MODE_0); - reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE, SPIM_DMODE_SINGLE); - reg = spi_write_reg_field(reg, SPIM_EDGE_TX_RX, 1); - - if (second) { - /* Set TX bit if the 2nd transaction is 'send' */ - reg = spi_write_reg_field(reg, SPFI_TX_RX, - second->isread ? 0 : 1); - /* - * Set send/get DMA for both transactions - * (first is always 'send') - */ - reg = spi_write_reg_field(reg, SPIM_SEND_DMA, 1); - if (second->isread) - reg = spi_write_reg_field(reg, SPIM_GET_DMA, 1); - - } else { - /* Set TX bit if the 1st transaction is 'send' */ - reg |= first->isread ? 0 : SPFI_TX_RX_MASK; - /* Set send/get DMA */ - reg |= first->isread ? SPIM_GET_DMA_MASK : SPIM_SEND_DMA_MASK; - } - return reg; -} - -/* Checks the given buffer information */ -static int check_buffers(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second){ - - struct img_spi_slave *img_slave = get_img_slave(slave); - - if (!(img_slave->initialised)) - return -SPIM_API_NOT_INITIALISED; - /* - * First operation must always be defined - * It can be either a read or a write and its size cannot be bigge - * than SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (!first) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (first->isread > 1) - return -SPIM_INVALID_READ_WRITE; - /* Check operation parameters for 'second' */ - if (second) { - /* - * If the second operation is defined it must be a read - * operation and its size must not be bigger than - * SPIM_MAX_TANSFER_BYTES = 64KB - 1 (0xFFFF) - */ - if (second->size > SPIM_MAX_TRANSFER_BYTES) - return -SPIM_INVALID_SIZE; - if (!second->isread) - return -SPIM_INVALID_READ_WRITE; - /* - * If the second operations is defined, the first operation - * must be a write and its size cannot be bigger than - * SPIM_MAX_FLASH_COMMAND_BYTES(8): command size (1) + - * address size (7). - */ - if (first->isread) - return -SPIM_INVALID_READ_WRITE; - if (first->size > SPIM_MAX_FLASH_COMMAND_BYTES) - return -SPIM_INVALID_SIZE; - - } - return SPIM_OK; -} - -/* Checks the set bitrate */ -static int check_bitrate(u32 rate) -{ - /* Bitrate must be 1, 2, 4, 8, 16, 32, 64, or 128 */ - switch (rate) { - case 1: - case 2: - case 4: - case 8: - case 16: - case 32: - case 64: - case 128: - return SPIM_OK; - default: - return -SPIM_INVALID_BIT_RATE; - } - return -SPIM_INVALID_BIT_RATE; -} - -/* Checks device parameters for errors */ -static int check_device_params(struct spim_device_parameters *pdev_param) -{ - if (pdev_param->spi_mode < SPIM_MODE_0 || - pdev_param->spi_mode > SPIM_MODE_3) - return -SPIM_INVALID_SPI_MODE; - if (check_bitrate(pdev_param->bitrate) != SPIM_OK) - return -SPIM_INVALID_BIT_RATE; - if (pdev_param->cs_idle_level > 1) - return -SPIM_INVALID_CS_IDLE_LEVEL; - if (pdev_param->data_idle_level > 1) - return -SPIM_INVALID_DATA_IDLE_LEVEL; - return SPIM_OK; -} - -/* Function that carries out read/write operations */ -static int spim_io(const struct spi_slave *slave, struct spim_buffer *first, - struct spim_buffer *second) -{ - u32 reg, base; - int i, trans_count, ret; - struct spim_buffer *transaction[2]; - struct img_spi_slave *img_slave = get_img_slave(slave); - - base = img_slave->base; - - ret = check_buffers(slave, first, second); - if (ret) - return ret; - - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - /* Port state register */ - reg = read32_x(base + SPFI_PORT_STATE_REG_OFFSET); - reg = spi_write_reg_field(reg, SPFI_PORT_SELECT, slave->cs); - write32_x(base + SPFI_PORT_STATE_REG_OFFSET, reg); - /* Set transaction register */ - reg = transaction_reg_setup(first, second); - write32_x(base + SPFI_TRANSACTION_REG_OFFSET, reg); - /* Clear status */ - write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, 0xffffffff); - /* Set control register */ - reg = control_reg_setup(first, second); - write32_x(base + SPFI_CONTROL_REG_OFFSET, reg); - /* First transaction always exists */ - transaction[0] = first; - trans_count = 1; - /* Is there a second transaction? */ - if (second) { - transaction[1] = second; - trans_count++; - } - /* Now write/read FIFO's */ - for (i = 0; i < trans_count; i++) - /* Which transaction to execute, "Send" or "Get"? */ - if (transaction[i]->isread) { - /* Get */ - ret = receivedata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: receive data failed.\n", - __func__); - return ret; - } - } else { - /* Send */ - ret = transmitdata(slave, transaction[i]->buffer, - transaction[i]->size); - if (ret) { - printk(BIOS_ERR, - "%s: Error: transmit data failed.\n", - __func__); - return ret; - } - } - - /* Wait for end of the transaction */ - ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET, - SPFI_ALLDONE_SHIFT); - if (ret) - return ret; - /* - * Soft reset peripheral internals, this will terminate any - * pending transactions - */ - write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK); - write32_x(base + SPFI_CONTROL_REG_OFFSET, 0); - - return SPIM_OK; -} - -/* Claim the bus and prepare it for communication */ -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - int ret; - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - img_slave = get_img_slave(slave); - if (img_slave->initialised) - return SPIM_OK; - /* Check device parameters */ - ret = check_device_params(&(img_slave->device_parameters)); - if (ret) { - printk(BIOS_ERR, "%s: Error: incorrect device parameters.\n", - __func__); - return ret; - } - /* Set device parameters */ - setparams(slave, slave->cs, &(img_slave->device_parameters)); - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); - img_slave->initialised = IMG_TRUE; - return SPIM_OK; -} - -/* Release the SPI bus */ -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return; - } - img_slave = get_img_slave(slave); - img_slave->initialised = IMG_FALSE; - /* Soft reset peripheral internals */ - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, - SPIM_SOFT_RESET_MASK); - write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0); -} - -/* SPI transfer */ -static int do_spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - struct spim_buffer buff_0; - struct spim_buffer buff_1; - - /* If we only have a read or a write operation - * the parameters for it will be put in the first buffer - */ - buff_0.buffer = (dout) ? (void *)dout : (void *)din; - buff_0.size = (dout) ? bytesout : bytesin; - buff_0.isread = (dout) ? IMG_FALSE : IMG_TRUE; - buff_0.inter_byte_delay = 0; - - if (dout && din) { - /* Set up the read buffer to receive our data */ - buff_1.buffer = din; - buff_1.size = bytesin; - buff_1.isread = IMG_TRUE; - buff_1.inter_byte_delay = 0; - } - return spim_io(slave, &buff_0, (dout && din) ? &buff_1 : NULL); -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - unsigned int in_sz, out_sz; - int ret; - - if (!slave) { - printk(BIOS_ERR, "%s: Error: slave was not set up.\n", - __func__); - return -SPIM_API_NOT_INITIALISED; - } - if (!dout && !din) { - printk(BIOS_ERR, "%s: Error: both buffers are NULL.\n", - __func__); - return -SPIM_INVALID_TRANSFER_DESC; - } - - while (bytesin || bytesout) { - in_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesin); - out_sz = min(IMGTEC_SPI_MAX_TRANSFER_SIZE, bytesout); - - ret = do_spi_xfer(slave, dout, out_sz, din, in_sz); - if (ret) - return ret; - - bytesin -= in_sz; - bytesout -= out_sz; - - if (bytesin) - din += in_sz; - else - din = NULL; - - if (bytesout) - dout += out_sz; - else - dout = NULL; - } - - return SPIM_OK; -} - -static int spi_ctrlr_setup(const struct spi_slave *slave) -{ - struct img_spi_slave *img_slave = NULL; - struct spim_device_parameters *device_parameters; - u32 base; - - switch (slave->bus) { - case 0: - base = IMG_SPIM0_BASE_ADDRESS; - break; - case 1: - base = IMG_SPIM1_BASE_ADDRESS; - break; - default: - printk(BIOS_ERR, "%s: Error: unsupported bus.\n", - __func__); - return -1; - } - if (slave->cs > SPIM_DEVICE4) { - printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", - __func__); - return -1; - } - - img_slave = get_img_slave(slave); - device_parameters = &(img_slave->device_parameters); - - img_slave->base = base; - - device_parameters->bitrate = 64; - device_parameters->cs_setup = 0; - device_parameters->cs_hold = 0; - device_parameters->cs_delay = 0; - device_parameters->spi_mode = SPIM_MODE_0; - device_parameters->cs_idle_level = 1; - device_parameters->data_idle_level = 0; - img_slave->initialised = IMG_FALSE; - - return 0; -} - -static const struct spi_ctrlr spi_ctrlr = { - .setup = spi_ctrlr_setup, - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .max_xfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 1, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c deleted file mode 100644 index 1eb232a..0000000 --- a/src/soc/imgtec/pistachio/uart.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <boot/coreboot_tables.h> -#include <console/uart.h> -#include <device/device.h> -#include <delay.h> -#include <drivers/uart/uart8250reg.h> - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -#define UART_SHIFT 2 - -#define GEN_ACCESSOR(name, idx) \ -static inline uint8_t read_##name(unsigned base_port) \ -{ \ - return read8((void *)(base_port + (idx << UART_SHIFT))); \ -} \ - \ -static inline void write_##name(unsigned base_port, uint8_t val) \ -{ \ - write8((void *)(base_port + (idx << UART_SHIFT)), val); \ -} - -GEN_ACCESSOR(rbr, UART8250_RBR) -GEN_ACCESSOR(tbr, UART8250_TBR) -GEN_ACCESSOR(ier, UART8250_IER) -GEN_ACCESSOR(fcr, UART8250_FCR) -GEN_ACCESSOR(lcr, UART8250_LCR) -GEN_ACCESSOR(mcr, UART8250_MCR) -GEN_ACCESSOR(lsr, UART8250_LSR) -GEN_ACCESSOR(dll, UART8250_DLL) -GEN_ACCESSOR(dlm, UART8250_DLM) - -static int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read_lsr(base_port) & UART8250_LSR_THRE; -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); - write_tbr(base_port, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(read_lsr(base_port) & UART8250_LSR_TEMT)) - udelay(1); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read_lsr(base_port) & UART8250_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read_rbr(base_port); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write_ier(base_port, 0x0); - /* Enable FIFOs */ - write_fcr(base_port, UART8250_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write_mcr(base_port, UART8250_MCR_DTR | UART8250_MCR_RTS); - - /* DLAB on */ - write_lcr(base_port, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS); - - write_dll(base_port, divisor & 0xFF); - write_dlm(base_port, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write_lcr(base_port, CONFIG_TTYS0_LCS); -} - -unsigned int uart_platform_refclk(void) -{ - /* 1.8433179 MHz */ - return 1843318; -} - -void uart_init(int idx) -{ - u32 base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - if (!base) - return; - - unsigned int div; - div = uart_baudrate_divisor(get_uart_baudrate(), - uart_platform_refclk(), 16); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - uart8250_mem_tx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS, data); -} - -unsigned char uart_rx_byte(int idx) -{ - return uart8250_mem_rx_byte(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -void uart_tx_flush(int idx) -{ - uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); -} - -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - serial.baud = get_uart_baudrate(); - serial.regwidth = 1 << UART_SHIFT; - serial.input_hertz = uart_platform_refclk(); - serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} diff --git a/util/bimgtool/Makefile b/util/bimgtool/Makefile deleted file mode 100644 index 05ddf7d..0000000 --- a/util/bimgtool/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -obj ?= $(CURDIR) - -HOSTCC ?= gcc -CFLAGS ?= -g -CFLAGS += -D_7ZIP_ST -CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow -Werror - -all: $(obj)/bimgtool - -clean: - rm -f $(obj)/bimgtool - -$(obj)/bimgtool: bimgtool.c - $(HOSTCC) $(CFLAGS) -o $@ $^ diff --git a/util/bimgtool/bimgtool.c b/util/bimgtool/bimgtool.c deleted file mode 100644 index 518674c..0000000 --- a/util/bimgtool/bimgtool.c +++ /dev/null @@ -1,430 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Imagination Technologies Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <errno.h> -#include <stdint.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <sys/stat.h> -#include <sys/types.h> - -struct bimg_header { - uint32_t magic; - uint16_t ver_major; - uint16_t ver_minor; - uint32_t data_size; - uint32_t entry_addr; - uint32_t flags; - uint32_t data_crc; - uint32_t crc; -} __attribute__((packed)); - -struct bimg_data_header { - uint32_t size; - uint32_t dest_addr; - uint16_t dummy; - uint16_t crc; -} __attribute__((packed)); - -struct crc_t { - uint16_t (*crc_f)(uint16_t crc, void *void_buf, size_t size); - uint32_t crc_init; - uint16_t ver_major; - uint16_t ver_minor; -}; - - -#define BIMG_MAGIC /* y */ 0xabbadaba /* doo! */ - -#define BIMG_OP_MASK (0xf << 0) -#define BIMG_OP_EXEC_RETURN (0x1 << 0) -#define BIMG_OP_EXEC_NO_RETURN (0x2 << 0) -#define BIMG_DATA_CHECKSUM (0x1 << 4) - -/* Typical use case for this utility. */ -#define BIMG_FLAGS (BIMG_OP_EXEC_NO_RETURN | BIMG_DATA_CHECKSUM) - -#define MAX_RECORD_BYTES 0x8000 - -#define CRC_16 - -#define error(msg...) fprintf(stderr, "ERROR: " msg) - -#define error_ret(ret, msg...) { \ - error(msg); \ - return ret; \ -} - -#if defined(CRC_X25) -static uint16_t crc_x25(uint16_t crc, void *void_buf, size_t size) -{ - static const uint16_t crc_table[16] = { - 0x0000, 0x1021, 0x2042, 0x3063, - 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, - 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 4)) & 0xf]; - crc = (crc << 4) ^ crc_table[((crc >> 12) ^ (data >> 0)) & 0xf]; - } - - return crc; -} -#endif - -#if defined(CRC_16) -static uint16_t crc_16(uint16_t crc, void *void_buf, size_t size) -{ - /* - * CRC table for the CRC-16. - * The poly is 0x8005 (x^16 + x^15 + x^2 + 1) - */ - static const uint16_t crc16_table[256] = { - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 - }; - uint8_t *buf, data; - - for (buf = void_buf; size; size--) { - data = *buf++; - crc = (crc >> 8) ^ crc16_table[(crc ^ data) & 0xff]; - } - - return crc; -} -#endif - -static const struct crc_t crc_type = { -#if defined(CRC_16) - .crc_f = crc_16, - .crc_init = 0, - .ver_major = 2, - .ver_minor = 0 -#elif defined(CRC_X25) - .crc_f = crc_x25, - .crc_init = 0xffff, - .ver_major = 1, - .ver_minor = 0 -#endif -}; - -static int write_binary(FILE *out, FILE *in, struct bimg_header *hdr) -{ - static uint8_t file_buf[MAX_RECORD_BYTES]; - struct bimg_data_header data_hdr = { 0 }; - size_t n_written; - - data_hdr.dest_addr = hdr->entry_addr; - - /* - * The read binary data has to be split in chunks of max 64KiB - 1 byte - * (SPI controller limitation). Each chunk will have its own header in - * order to respect the BIMG format. - */ - while ((data_hdr.size = fread(file_buf, 1, sizeof(file_buf), in))) { - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", - errno); - - n_written = fwrite(file_buf, 1, data_hdr.size, out); - if (n_written != data_hdr.size) - error_ret(-EIO, "Failed to write to output file: %d\n", - errno); - - data_hdr.dest_addr += n_written; - hdr->data_size += sizeof(data_hdr) + n_written; - hdr->data_crc = crc_type.crc_f(hdr->data_crc, - file_buf, n_written); - } - - if (ferror(in)) - error_ret(-EIO, "Failed to read input file\n"); - - return 0; -} - -static int write_final(FILE *out, struct bimg_header *hdr) -{ - struct bimg_data_header data_hdr = { - .size = 0, - .dest_addr = ~0, - }; - - data_hdr.crc = crc_type.crc_f(crc_type.crc_init, &data_hdr, - sizeof(data_hdr) - sizeof(data_hdr.crc)); - - if (fwrite(&data_hdr, sizeof(data_hdr), 1, out) != 1) - error_ret(-EIO, "Failed to write data header: %d\n", errno); - - hdr->data_size += sizeof(data_hdr); - - return 0; -} - -static const char *help_message = - "Usage: bimgtool <input> [<output> <base-address>]\n" - "\n" - "This is a simple tool which generates and verifies boot images in\n" - "the BIMG format, used in systems designed by Imagination\n" - "Technologies, for example the Pistachio SoC. This version of the\n" - "tool works with BIMG images version %d.\n" - "\n" - " input: The binary file to be converted to a BIMG\n" - " or verified\n" - " output: The name of the output BIMG file\n" - " base-address: The address in memory at which you wish the " - " input binary to be loaded.\n"; - -static void usage(FILE *f) -{ - fprintf(f, help_message, crc_type.ver_major); -} - -static int verify_file(FILE *f) -{ - struct bimg_header file_header; - struct bimg_data_header data_header; - char *file_pointer; - char *file_data; - struct stat buf; - int data_size; - int fd = fileno(f); - uint32_t data_crc = crc_type.crc_init; - uint32_t crc_result; - - if (fread(&file_header, 1, sizeof(struct bimg_header), f) != - sizeof(struct bimg_header)) { - perror("Problems trying to read input file header\n"); - return -1; - } - - if (fstat(fd, &buf)) { - perror("Problems trying to stat input file\n"); - return -1; - } - - if (file_header.magic != BIMG_MAGIC) { - fprintf(stderr, "Wrong magic value %#x\n", file_header.magic); - return -1; - } - - crc_result = crc_type.crc_f(crc_type.crc_init, &file_header, - sizeof(file_header) - - sizeof(file_header.crc)); - if (file_header.crc != crc_result) { - fprintf(stderr, "File header CRC mismatch\n"); - return -1; - } - - if ((file_header.data_size + sizeof(struct bimg_header)) > - buf.st_size) { - fprintf(stderr, "Data size too big: %d > %zd\n", - file_header.data_size, buf.st_size); - return -1; - } - - if (file_header.ver_major != crc_type.ver_major) { - fprintf(stderr, "Image version mismatch: %d\n", - file_header.ver_major); - return -1; - } - - if ((file_header.flags & BIMG_FLAGS) != BIMG_FLAGS) { - fprintf(stderr, "Unexpected file header flags: %#x\n", - file_header.flags); - return -1; - } - - if (file_header.ver_minor != crc_type.ver_minor) { - fprintf(stderr, - "Minor version mismatch: %d, will try anyways\n", - file_header.ver_minor); - } - - data_size = file_header.data_size; - file_pointer = malloc(data_size); - if (!file_pointer) { - fprintf(stderr, "Failed to allocate %d bytes\n", - file_header.data_size); - return -1; - } - - if (fread(file_pointer, 1, data_size, f) != data_size) { - fprintf(stderr, "Failed to read %d bytes\n", data_size); - free(file_pointer); - return -1; - } - - file_data = file_pointer; - while (data_size > 0) { - memcpy(&data_header, file_data, sizeof(data_header)); - - /* Check the data block header integrity. */ - crc_result = crc_type.crc_f(crc_type.crc_init, &data_header, - sizeof(data_header) - - sizeof(data_header.crc)); - if (data_header.crc != crc_result) { - fprintf(stderr, "Data header CRC mismatch at %d\n", - file_header.data_size - data_size); - free(file_pointer); - return -1; - } - - /* - * Add the block data to the CRC stream, the last block size - * will be zero. - */ - file_data += sizeof(data_header); - data_crc = crc_type.crc_f(data_crc, - file_data, data_header.size); - - data_size -= data_header.size + sizeof(data_header); - file_data += data_header.size; - } - - if (data_size) { - fprintf(stderr, "File size mismatch\n"); - free(file_pointer); - return -1; - } - - if (data_crc != file_header.data_crc) { - fprintf(stderr, "File data CRC mismatch\n"); - free(file_pointer); - return -1; - } - - free(file_pointer); - return 0; -} - -int main(int argc, char *argv[]) -{ - const char *in_filename, *out_filename; - FILE *in_file, *out_file; - int err; - struct bimg_header hdr = { - .magic = BIMG_MAGIC, - .ver_major = crc_type.ver_major, - .ver_minor = crc_type.ver_minor, - .flags = BIMG_FLAGS, - .data_crc = crc_type.crc_init, - }; - - if ((argc != 4) && (argc != 2)) { - usage(stderr); - goto out_err; - } - - in_filename = argv[1]; - - in_file = fopen(in_filename, "r"); - if (!in_file) { - error("Failed to open input file '%s'\n", in_filename); - goto out_err; - } - - if (argc == 2) - return verify_file(in_file); - - out_filename = argv[2]; - hdr.entry_addr = strtoul(argv[3], NULL, 16); - - out_file = fopen(out_filename, "w"); - if (!out_file) { - error("Failed to open output file '%s'\n", out_filename); - goto out_err_close_in; - } - - if (fseek(out_file, sizeof(hdr), SEEK_SET)) { - error("Failed to seek past header: %d\n", errno); - goto out_err_close_out; - } - - err = write_binary(out_file, in_file, &hdr); - if (err) { - error("Failed to write binary: %d\n", err); - goto out_err_close_out; - } - - err = write_final(out_file, &hdr); - if (err) { - error("Failed to write final record: %d\n", err); - goto out_err_close_out; - } - - hdr.crc = crc_type.crc_f(crc_type.crc_init, &hdr, - sizeof(hdr) - sizeof(hdr.crc)); - - if (fseek(out_file, 0, SEEK_SET)) { - error("Failed to seek to header: %d\n", errno); - goto out_err_close_out; - } - - if (fwrite(&hdr, sizeof(hdr), 1, out_file) != 1) { - error("Failed to write header: %d\n", errno); - goto out_err_close_out; - } - - fclose(in_file); - fclose(out_file); - return EXIT_SUCCESS; - -out_err_close_out: - fclose(out_file); -out_err_close_in: - fclose(in_file); -out_err: - return EXIT_FAILURE; -} diff --git a/util/bimgtool/description.md b/util/bimgtool/description.md deleted file mode 100644 index aa1059a..0000000 --- a/util/bimgtool/description.md +++ /dev/null @@ -1,3 +0,0 @@ -A simple tool which generates and verifies boot images in the BIMG -format, used in systems designed by Imagination Technologies, for -example the Pistachio SoC. `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/36491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Gerrit-Change-Number: 36491 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: Remove google/urara mainboard
by Julius Werner (Code Review) 19 Nov '19

19 Nov '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36490 ) Change subject: Remove google/urara mainboard ...................................................................... Remove google/urara mainboard This board never really existed and nobody has any hardware left over for it. Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- D src/mainboard/google/urara/Kconfig D src/mainboard/google/urara/Kconfig.name D src/mainboard/google/urara/Makefile.inc D src/mainboard/google/urara/board_info.txt D src/mainboard/google/urara/boardid.c D src/mainboard/google/urara/bootblock.c D src/mainboard/google/urara/chromeos.c D src/mainboard/google/urara/chromeos.fmd D src/mainboard/google/urara/devicetree.cb D src/mainboard/google/urara/mainboard.c D src/mainboard/google/urara/memlayout.ld D src/mainboard/google/urara/urara_boardid.h 12 files changed, 0 insertions(+), 632 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36490/1 diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig deleted file mode 100644 index 3cbe7ed..0000000 --- a/src/mainboard/google/urara/Kconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -if BOARD_GOOGLE_URARA - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_512 - select SPI_FLASH_WINBOND - select CPU_IMGTEC_PISTACHIO - select COMMON_CBFS_SPI_WRAPPER - select SPI_FLASH - -config MAINBOARD_DIR - string - default "google/urara" - -config MAINBOARD_PART_NUMBER - string - default "ImgTec Pistachio Virtual Platform" - -config BOOTBLOCK_MAINBOARD_INIT - string - default "mainboard/google/urara/bootblock.c" - -config DRAM_SIZE_MB - int - default 256 - -config TTYS0_LCS - int - default 3 - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on DRIVERS_UART - default 0xB8101500 - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 1 -endif diff --git a/src/mainboard/google/urara/Kconfig.name b/src/mainboard/google/urara/Kconfig.name deleted file mode 100644 index edc935a..0000000 --- a/src/mainboard/google/urara/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_URARA - bool "Urara" diff --git a/src/mainboard/google/urara/Makefile.inc b/src/mainboard/google/urara/Makefile.inc deleted file mode 100644 index 7ad779d..0000000 --- a/src/mainboard/google/urara/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright 2014 Imagination Technologies Ltd. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -bootblock-y += boardid.c -ramstage-y += boardid.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-y += mainboard.c - -bootblock-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt deleted file mode 100644 index 0458abd..0000000 --- a/src/mainboard/google/urara/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Vendor name: Google -Board name: Urara Imgtec Pistachio reference board -Category: eval -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c deleted file mode 100644 index 9a6b64e..0000000 --- a/src/mainboard/google/urara/boardid.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <string.h> - -#include <boardid.h> -#include <cbfs.h> -#include <console/console.h> - -#include "mainboard/google/urara/urara_boardid.h" - -/* Name of the CBFS file were the board ID string is read from. */ -#define CBFS_BOARD_ID_FILE_NAME "board_id" - -const struct bid_map { - const char *board_name; - uint8_t board_id; - struct board_hw hardware; -} board_id_map[] = { - {"urara", URARA_BOARD_ID_BUB, {0} }, - {"buranku", URARA_BOARD_ID_BURANKU, {3} }, - {"derwent", URARA_BOARD_ID_DERWENT, {3} }, - {"jaguar", URARA_BOARD_ID_JAGUAR, {3} }, - {"kennet", URARA_BOARD_ID_KENNET, {3} }, - {"space", URARA_BOARD_ID_SPACE, {3} }, -}; - -static int cached_board_id = -1; - -static uint8_t retrieve_board_id(void) -{ - const char *board_id_file_name = CBFS_BOARD_ID_FILE_NAME; - char *file_contents; - int i; - size_t length; - - file_contents = cbfs_boot_map_with_leak(board_id_file_name, - CBFS_TYPE_RAW, &length); - - if (!file_contents) { - printk(BIOS_WARNING, - "board_id: failed to locate file '%s'\n", - board_id_file_name); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - const struct bid_map *entry = board_id_map + i; - - if ((strlen(entry->board_name) == length) && - !strncmp(entry->board_name, file_contents, length)) { - printk(BIOS_INFO, "board_id: name '%s', ID %d\n", - entry->board_name, entry->board_id); - return entry->board_id; - } - } - - printk(BIOS_WARNING, "board_id: no match for board name '%.*s'\n", - length, file_contents); - printk(BIOS_WARNING, "board_id: will use default board ID 0\n"); - - return 0; -} - -const struct board_hw *board_get_hw(void) -{ - int i; - uint8_t bid = board_id(); - - for (i = 0; i < ARRAY_SIZE(board_id_map); i++) { - if (bid == board_id_map[i].board_id) - return &(board_id_map[i].hardware); - } - - return 0; -} - -uint32_t board_id(void) -{ - if (cached_board_id == -1) - cached_board_id = retrieve_board_id(); - - return cached_board_id; -} diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c deleted file mode 100644 index 16e7580..0000000 --- a/src/mainboard/google/urara/bootblock.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/mmio.h> -#include <stdint.h> -#include <soc/clocks.h> -#include <assert.h> -#include <boardid.h> - -#include "urara_boardid.h" - -#define PADS_FUNCTION_SELECT0_ADDR (0xB8101C00 + 0xC0) - -#define GPIO_BIT_EN_ADDR(bank) (0xB8101C00 + 0x200 + (0x24 * (bank))) -#define PAD_DRIVE_STRENGTH_ADDR(bank) (0xB8101C00 + 0x120 + (0x4 * (bank))) -#define MAX_NO_MFIOS 89 -#define PAD_DRIVE_STRENGTH_LENGTH 2 -#define PAD_DRIVE_STRENGTH_MASK 0x3 - -typedef enum { - DRIVE_STRENGTH_2mA = 0, - DRIVE_STRENGTH_4mA = 1, - DRIVE_STRENGTH_8mA = 2, - DRIVE_STRENGTH_12mA = 3 -} drive_strength; - -/* MFIO definitions for UART1 */ -#define UART1_RXD_MFIO 59 -#define UART1_TXD_MFIO 60 - -/* MFIO definitions for SPIM */ -#define SPIM1_D0_TXD_MFIO 5 -#define SPIM1_D1_RXD_MFIO 4 -#define SPIM1_MCLK_MFIO 3 -#define SPIM1_D2_MFIO 6 -#define SPIM1_D3_MFIO 7 -#define SPIM1_CS0_MFIO 0 - -/* MFIO definitions for I2C */ -#define I2C_DATA_MFIO(i) (28 + (2*(i))) -#define I2C_CLK_MFIO(i) (29 + (2*(i))) -#define I2C_DATA_FUNCTION_OFFSET(i) (20 + (2*(i))) -#define I2C_CLK_FUNCTION_OFFSET(i) (21 + (2*(i))) -#define I2C_DATA_FUNCTION_MASK 0x1 -#define I2C_CLK_FUNCTION_MASK 0x1 - -static void pad_drive_strength(u32 pad, drive_strength strength) -{ - u32 reg, drive_strength_shift; - - assert(pad <= MAX_NO_MFIOS); - assert(!(strength & ~(PAD_DRIVE_STRENGTH_MASK))); - - /* Set drive strength value */ - drive_strength_shift = (pad % 16) * PAD_DRIVE_STRENGTH_LENGTH; - reg = read32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16)); - reg &= ~(PAD_DRIVE_STRENGTH_MASK << drive_strength_shift); - reg |= strength << drive_strength_shift; - write32_x(PAD_DRIVE_STRENGTH_ADDR(pad / 16), reg); -} - -static void uart1_mfio_setup(void) -{ - u32 reg, mfio_mask; - - /* - * Disable GPIO for UART1 MFIOs - * All UART MFIOs have MFIO/16 = 3, therefore we use GPIO pad 3 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(3)); - mfio_mask = 1 << (UART1_RXD_MFIO % 16); - mfio_mask |= 1 << (UART1_TXD_MFIO % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(3), reg); -} - -static void spim1_mfio_setup(void) -{ - u32 reg, mfio_mask; - /* - * Disable GPIO for SPIM1 MFIOs - * All SPFI1 MFIOs have MFIO/16 = 0, therefore we use GPIO pad 0 - * This is the only function (0) of these MFIOs and therfore there - * is no need to set up a function number in the corresponding - * function select register. - */ - reg = read32_x(GPIO_BIT_EN_ADDR(0)); - - /* Disable GPIO for SPIM1 MFIOs */ - mfio_mask = 1 << (SPIM1_D0_TXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D1_RXD_MFIO % 16); - mfio_mask |= 1 << (SPIM1_MCLK_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D2_MFIO % 16); - mfio_mask |= 1 << (SPIM1_D3_MFIO % 16); - mfio_mask |= 1 << (SPIM1_CS0_MFIO % 16); - - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(0), reg); - - /* Set drive strength to maximum for these MFIOs */ - pad_drive_strength(SPIM1_CS0_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D1_RXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D0_TXD_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D2_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_D3_MFIO, DRIVE_STRENGTH_12mA); - pad_drive_strength(SPIM1_MCLK_MFIO, DRIVE_STRENGTH_12mA); -} - -static void i2c_mfio_setup(int interface) -{ - u32 reg, mfio_mask; - - assert(interface < 4); - /* - * Disable GPIO for I2C MFIOs - */ - reg = read32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16)); - mfio_mask = 1 << (I2C_DATA_MFIO(interface) % 16); - mfio_mask |= 1 << (I2C_CLK_MFIO(interface) % 16); - /* Clear relevant bits */ - reg &= ~mfio_mask; - /* - * Set corresponding bits in the upper half word - * in order to be able to modify the chosen pins - */ - reg |= mfio_mask << 16; - write32_x(GPIO_BIT_EN_ADDR(I2C_DATA_MFIO(interface) / 16), reg); - - /* for I2C0 and I2C1: - * Set bits to 0 (clear) which is the primary function - * for these MFIOs; those bits will all be set to 1 by - * default. - * There is no need to do that for I2C2 and I2C3 - */ - if (interface > 1) - return; - reg = read32_x(PADS_FUNCTION_SELECT0_ADDR); - reg &= ~(I2C_DATA_FUNCTION_MASK << - I2C_DATA_FUNCTION_OFFSET(interface)); - reg &= ~(I2C_CLK_FUNCTION_MASK << - I2C_CLK_FUNCTION_OFFSET(interface)); - write32_x(PADS_FUNCTION_SELECT0_ADDR, reg); -} - -static void bootblock_mainboard_init(void) -{ - int ret; - - /* System PLL divided by 2 -> 350 MHz */ - /* The same frequency will be the input frequency for the SPFI block */ - system_clk_setup(1); - - /* MIPS CPU dividers: division by 1 -> 546 MHz - * This is set up as we cannot make any assumption about - * the values set or not by the boot ROM code */ - mips_clk_setup(0, 0); - - /* Setup system PLL at 700 MHz */ - ret = sys_pll_setup(2, 1, 13, 350); - if (ret != CLOCKS_OK) - return; - /* Setup MIPS PLL at 546 MHz */ - ret = mips_pll_setup(2, 1, 1, 21); - if (ret != CLOCKS_OK) - return; - - /* - * Move peripheral clock control from RPU to MIPS. - * The RPU gate register is not managed in Linux so disable its default - * values and assign MIPS gate register the default values. - * *Note*: All unused clocks will be gated by Linux - */ - setup_clk_gate_defaults(); - - /* Setup SPIM1 MFIOs */ - spim1_mfio_setup(); - /* Setup UART1 clock and MFIOs - * System PLL divided by 5 divided by 76 -> 1.8421 Mhz - */ - uart1_clk_setup(4, 75); - uart1_mfio_setup(); -} - - -static int init_extra_hardware(void) -{ - const struct board_hw *hardware; - - /* Obtain information about current board */ - hardware = board_get_hw(); - if (!hardware) { - printk(BIOS_ERR, "%s: Invalid hardware information.\n", - __func__); - return -1; - } - - /* Setup USB clock - * System clock divided by 7 -> 50 MHz - */ - if (usb_clk_setup(6, 2, 7) != CLOCKS_OK) { - printk(BIOS_ERR, "%s: Failed to set up USB clock.\n", - __func__); - return -1; - } - - /* Setup I2C clocks and MFIOs - * System clock divided by 4 divided by 3 -> 29.1(6) MHz - */ - i2c_clk_setup(3, 2, hardware->i2c_interface); - i2c_mfio_setup(hardware->i2c_interface); - - /* Ethernet clocks setup: ENET as clock source */ - eth_clk_setup(0, 6); - /* ROM clock setup: system clock divided by 2 -> 175 MHz */ - /* Hash accelerator is driven from the ROM clock */ - rom_clk_setup(1); - - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c deleted file mode 100644 index 3f7ec32..0000000 --- a/src/mainboard/google/urara/chromeos.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <bootmode.h> -#include <console/console.h> -#include <gpio.h> - -int get_write_protect_state(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); -} - -int get_recovery_mode_switch(void) -{ - printk(BIOS_ERR, "%s unsupported, but called\n", __func__); - return 0; -} diff --git a/src/mainboard/google/urara/chromeos.fmd b/src/mainboard/google/urara/chromeos.fmd deleted file mode 100644 index 4bc0db4..0000000 --- a/src/mainboard/google/urara/chromeos.fmd +++ /dev/null @@ -1,32 +0,0 @@ -FLASH@0x0 0x200000 { - WP_RO@0x0 0x100000 { - RO_SECTION@0x0 0xf0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x60000 - FMAP@0xe0000 0x1000 - GBB@0xe1000 0xef00 - RO_FRID@0xeff00 0x100 - } - RO_VPD(PRESERVE)@0xf0000 0x10000 - } - RW_SECTION_A@0x100000 0x70000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x6df00 - RW_FWID_A@0x6ff00 0x100 - } - RW_SHARED@0x170000 0x2000 { - SHARED_DATA@0x0 0x2000 - } - RW_GPT@0x172000 0x2000 { - RW_GPT_PRIMARY@0x0 0x1000 - RW_GPT_SECONDARY@0x1000 0x1000 - } - RW_ELOG(PRESERVE)@0x174000 0x4000 - RW_VPD(PRESERVE)@0x178000 0x8000 - RW_SECTION_B@0x180000 0x70000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x6df00 - RW_FWID_B@0x6ff00 0x100 - } - RW_NVRAM(PRESERVE)@0x1f0000 0x10000 -} diff --git a/src/mainboard/google/urara/devicetree.cb b/src/mainboard/google/urara/devicetree.cb deleted file mode 100644 index d865add..0000000 --- a/src/mainboard/google/urara/devicetree.cb +++ /dev/null @@ -1,22 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Imagination Technologies -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -chip soc/imgtec/pistachio - device cpu_cluster 0 on end - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # Fake component for testing - end -end diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c deleted file mode 100644 index 7bf8b90..0000000 --- a/src/mainboard/google/urara/mainboard.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <symbols.h> -#include <console/console.h> -#include <device/device.h> -#include <boot/coreboot_tables.h> - -#include <vendorcode/google/chromeos/chromeos.h> - -static void mainboard_init(struct device *dev) -{ -#if CONFIG(CHROMEOS) - /* Copy WIFI calibration data into CBMEM. */ - cbmem_add_vpd_calibration_data(); -#endif -} - -static void mainboard_enable(struct device *dev) -{ - printk(BIOS_INFO, "Enable Pistachio device...\n"); - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAG_DMA; - dma->size = sizeof(*dma); - dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = REGION_SIZE(dma_coherent); - -#if CONFIG(CHROMEOS) - /* Retrieve the switch interface MAC addresses. */ - lb_table_add_macs_from_vpd(header); -#endif -} diff --git a/src/mainboard/google/urara/memlayout.ld b/src/mainboard/google/urara/memlayout.ld deleted file mode 100644 index 14703291..0000000 --- a/src/mainboard/google/urara/memlayout.ld +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h deleted file mode 100644 index fbd9179..0000000 --- a/src/mainboard/google/urara/urara_boardid.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ -#define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ - -#include <stdint.h> - -/* - * List of URARA derivatives board ID definitions. They are stored in uint8_t - * across the code, using #defines here not to imply any specific size. - */ -#define URARA_BOARD_ID_BUB 0 -#define URARA_BOARD_ID_BURANKU 1 -#define URARA_BOARD_ID_DERWENT 2 -#define URARA_BOARD_ID_JAGUAR 3 -#define URARA_BOARD_ID_KENNET 4 -#define URARA_BOARD_ID_SPACE 5 - -struct board_hw { - uint8_t i2c_interface; -}; - -const struct board_hw *board_get_hw(void); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdba4f5209725995e4a55dcdbc299a9e91a5869a Gerrit-Change-Number: 36490 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Documentation: Remove duplicated entry
by Patrick Rudolph (Code Review) 19 Nov '19

19 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36077 ) Change subject: Documentation: Remove duplicated entry ...................................................................... Documentation: Remove duplicated entry The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36077/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c9204f6..56daebe 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -86,10 +86,6 @@ - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) -## Portwell - -- [PQ7-M107](portwell/pq7-m107.md) - ## MSI - [MS-7707](msi/ms7707/ms7707.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Gerrit-Change-Number: 36077 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: util/chromeos: Indent code blocks instead of using ```
by Paul Menzel (Code Review) 19 Nov '19

19 Nov '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35729 ) Change subject: util/chromeos: Indent code blocks instead of using ``` ...................................................................... util/chromeos: Indent code blocks instead of using ``` This uses less lines, is the original Markdown syntax, and for short blocks bette readable. Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M util/chromeos/README.md 1 file changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35729/1 diff --git a/util/chromeos/README.md b/util/chromeos/README.md index 0b9a7d7..964c6c5 100644 --- a/util/chromeos/README.md +++ b/util/chromeos/README.md @@ -11,14 +11,13 @@ extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run -``` -$ ./crosfirmware.sh -``` + + $ ./crosfirmware.sh + To download, e.g. the Panther firmware image, run -``` -$ ./crosfirmware.sh panther -``` + + $ ./crosfirmware.sh panther ## extract_blobs.sh @@ -33,12 +32,10 @@ compatible format. Usage: -``` -$ ./gen_test_hwid.sh BOARD_NAME -``` + + $ ./gen_test_hwid.sh BOARD_NAME Example: -``` -$ ./gen_test_hwid.sh Kukui -KUKUI TEST 9847 -``` + + $ ./gen_test_hwid.sh Kukui + KUKUI TEST 9847 -- To view, visit https://review.coreboot.org/c/coreboot/+/35729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9 Gerrit-Change-Number: 35729 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: util/docker/Makefile: Add documentation docker image targets
by Arthur Heymans (Code Review) 19 Nov '19

19 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36104 ) Change subject: util/docker/Makefile: Add documentation docker image targets ...................................................................... util/docker/Makefile: Add documentation docker image targets Run - make -C util/docker doc.coreboot.org to build the docker image - make -C util/docker docker-build-docs to build the documentation - make -C docker-livehtml-docs to serve autoupdated documentation over http://0.0.0.0:8000 Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/docker/Makefile 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/36104/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index 6925b57..fbe3785 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -71,6 +71,10 @@ upload-coreboot-jenkins-node: test-docker-login $(DOCKER) push coreboot/coreboot-jenkins-node:$(COREBOOT_IMAGE_TAG) +doc.coreboot.org: test-docker + $(DOCKER) build --force-rm -t doc.coreboot.org \ + $(top)/util/docker/doc.coreboot.org/ + docker-killall: test-docker @if [ -n "$$($(DOCKER) ps | grep 'coreboot')" ]; then \ $(DOCKER) kill $$($(DOCKER) ps | grep 'coreboot' | cut -f1 -d ' '); \ @@ -166,6 +170,20 @@ -it "$$(docker ps | grep coreboot-jenkins-node | cut -f1 -d' ')" \ /bin/bash -l +docker-build-docs: test-docker +docker-build-docs: + $(DOCKER) run -it --rm \ + --user "$(id -u):$(id -g)" \ + -v "$(top)/:/data-in/:ro" \ + -v "$(top)Documentation/_build/:/data-out/" \ + doc.coreboot.org + +docker-livehtml-docs: test-docker +docker-livehtml-docs: + $(DOCKER) run -it --rm \ + --net=host -v "$(top)/:/data-in/:ro" \ + doc.coreboot.org livehtml + help: @echo "Commands for working with docker images:" @echo " coreboot-sdk - Build coreboot-sdk container" @@ -199,5 +217,5 @@ .PHONY: coreboot-sdk upload-coreboot-sdk .PHONY: clean-coreboot-containers clean-coreboot-images .PHONY: docker-abuild -.PHONY: docker-what-jenkins-does docker-shell docker-jenkins-server docker-jenkins-attach +.PHONY: docker-what-jenkins-does docker-shell docker-jenkins-server docker-jenkins-attach docker-build-docs .PHONY: help -- To view, visit https://review.coreboot.org/c/coreboot/+/36104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3 Gerrit-Change-Number: 36104 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: Documentation: Reword Supermicro X10SLM+-F sentence
by Paul Menzel (Code Review) 19 Nov '19

19 Nov '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35486 ) Change subject: Documentation: Reword Supermicro X10SLM+-F sentence ...................................................................... Documentation: Reword Supermicro X10SLM+-F sentence Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/mainboard/supermicro/x10slm-f.md 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35486/1 diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 8a91c89..7abbbfd 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -87,8 +87,7 @@ This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400]. -This chip is an MX25L25635F, whose datasheet can be found -[here][MX25L25635F]. +This chip is an MX25L25635F ([datasheet](MX25L25635F). ### Removing the BMC functionality -- To view, visit https://review.coreboot.org/c/coreboot/+/35486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Gerrit-Change-Number: 35486 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: build system: Add various compiler flags that enable warnings on UB
by Patrick Georgi (Code Review) 18 Nov '19

18 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32814 Change subject: build system: Add various compiler flags that enable warnings on UB ...................................................................... build system: Add various compiler flags that enable warnings on UB Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32814/1 diff --git a/Makefile.inc b/Makefile.inc index 9860da1..f2e010c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,6 +410,8 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack +CFLAGS_common += -pedantic-errors -Wnull-dereference +CFLAGS_common += -Wno-aggressive-loop-optimizations -Wreturn-type # cf. commit f69a99db (coreboot: x86: enable gc-sections) CFLAGS_common += -Wno-unused-but-set-variable endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Gerrit-Change-Number: 32814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 17 Nov '19

17 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32970 Change subject: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK ...................................................................... [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK untested. Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc A src/soc/intel/baytrail/bootblock/Makefile.inc M src/soc/intel/baytrail/bootblock/bootblock.c R src/soc/intel/baytrail/bootblock/uart.c A src/soc/intel/baytrail/include/soc/bootblock.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c 11 files changed, 118 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32970/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 03ad31d..f71fc02 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -41,14 +41,12 @@ select POSTCAR_CONSOLE select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BASE_ADDRESS hex @@ -94,6 +92,13 @@ bool "Enable MRC RMT training + debug prints" default n +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE @@ -132,6 +137,13 @@ help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6e6eb9c..e6a5704 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage +subdirs-y += bootblock subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -12,13 +13,16 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +verstage-y += tsc_freq.c romstage-y += spi.c postcar-y += spi.c ramstage-y += spi.c +verstage-y += spi.c smm-y += spi.c ramstage-y += chip.c ramstage-y += gfx.c @@ -30,6 +34,8 @@ ramstage-y += ramstage.c ramstage-y += gpio.c ramstage-y += cpu.c +bootblock-y += pmutil.c +verstage-y += pmutil.c romstage-y += pmutil.c ramstage-y += pmutil.c smm-y += pmutil.c diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc new file mode 100644 index 0000000..d093550 --- /dev/null +++ b/src/soc/intel/baytrail/bootblock/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += ../../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../../cpu/x86/early_reset.S +bootblock-y += bootblock.c +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..d371a98 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -18,32 +18,56 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/spi.h> +#include <soc/pmc.h> +#include <soc/bootblock.h> +#include <cpu/intel/car/bootblock.h> -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void program_base_addresses(void) { - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); } -static void enable_rom_caching(void) +static void spi_init(void) { - msr_t msr; + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); } static void setup_mmconfig(void) @@ -64,12 +88,22 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +void bootblock_early_cpu_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + tco_disable(); + byt_config_com1_and_enable(); + spi_init(); } diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/bootblock/uart.c similarity index 96% rename from src/soc/intel/baytrail/romstage/uart.c rename to src/soc/intel/baytrail/bootblock/uart.c index f9f2fe4..e5788cb 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/bootblock/uart.c @@ -18,7 +18,7 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/bootblock.h> void byt_config_com1_and_enable(void) { diff --git a/src/soc/intel/baytrail/include/soc/bootblock.h b/src/soc/intel/baytrail/include/soc/bootblock.h new file mode 100644 index 0000000..65ba6bb --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/bootblock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BAYTRAIL_BOOTBLOCK_H_ +#define _BAYTRAIL_BOOTBLOCK_H_ + +#if CONFIG(ENABLE_BUILTIN_COM1) +void byt_config_com1_and_enable(void); +#else +static inline void byt_config_com1_and_enable(void) { } +#endif + + +#endif /* _BAYTRAIL_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 7730893..248112f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -27,15 +27,8 @@ void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if CONFIG(ENABLE_BUILTIN_COM1) -void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif - #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03..1fa22f6 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -369,7 +369,12 @@ { uint32_t gen_pmcon1; int rtc_fail; + +#if !(ENV_BOOTBLOCK || ENV_VERSTAGE) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); +#else + struct chipset_power_state *ps = NULL; +#endif if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 8f009bd..afab9c0 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,7 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 596ed11..9fc3538 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -27,15 +27,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2a530b4..a9b6566 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -50,51 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -171,16 +126,8 @@ struct chipset_power_state *ps; int prev_sleep_state; - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - console_init(); - spi_init(); - set_max_freq(); punit_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Gerrit-Change-Number: 32970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019