coreboot-gerrit October 2019

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Change in ...coreboot[master]: mb/lenovo/t430: Add support for MRC raminit
by Petr K (Code Review) 22 Nov '19

22 Nov '19

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33539 Change subject: mb/lenovo/t430: Add support for MRC raminit ...................................................................... mb/lenovo/t430: Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on 32500 Signed-off-by: Petr K <piotrkloc94(a)hotmail.com> Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/romstage.c 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33539/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69..a992377 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,32 @@ end end + # PEI data + + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index db50bb3..fa46dc3 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -96,3 +97,19 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + + +void mainboard_fill_pei_data(struct pei_data *pei_data) + +{ + +} + + +int mainboard_should_reset_usb(int s3resume) + +{ + + return !s3resume; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 Gerrit-Change-Number: 33539 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: intel/smm: Provide common smm_relocation_params
by Kyösti Mälkki (Code Review) 22 Nov '19

22 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34840 ) Change subject: intel/smm: Provide common smm_relocation_params ...................................................................... intel/smm: Provide common smm_relocation_params Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c A src/include/cpu/intel/smm_reloc.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/broadwell/include/soc/smm.h M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/common/Makefile.inc M src/soc/intel/fsp_broadwell_de/include/soc/smm.h M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/smmrelocate.c 16 files changed, 91 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5cda618..5a26aff 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -46,49 +47,10 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index d200805..bb19c8c 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,6 +28,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <smp/node.h> #include "smi.h" @@ -47,15 +48,9 @@ } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; -}; /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; /* On model_6fx, model_1067x and model_106cx SMRR functions slightly differently. The MSR are at different location from the rest @@ -95,15 +90,6 @@ wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - static void fill_in_relocation_params(struct smm_relocation_params *params) { uintptr_t tseg_base; diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h new file mode 100644 index 0000000..cbcdb56 --- /dev/null +++ b/src/include/cpu/intel/smm_reloc.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INTEL_SMM_RELOC_H__ +#define __INTEL_SMM_RELOC_H__ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +struct smm_relocation_params { + uintptr_t ied_base; + size_t ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t prmrr_base; + msr_t prmrr_mask; + msr_t uncore_prmrr_base; + msr_t uncore_prmrr_mask; + /* + * The smm_save_state_in_msrs field indicates if SMM save state + * locations live in MSRs. This indicates to the CPUs how to adjust + * the SMMBASE and IEDBASE + */ + int smm_save_state_in_msrs; +}; + +extern struct smm_relocation_params smm_reloc_params; + +void fill_in_smrr(struct smm_relocation_params *params); + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); +} + +static inline void write_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); + wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); + wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); +} + +static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_prmrr_base.lo, + relo_params->uncore_prmrr_mask.lo); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); +} + +#endif diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 9fbcc07..e834142 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d25a740..05d7a82 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <reg_script.h> #include <soc/iosf.h> diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h index 9ad3128..08c1ad8 100644 --- a/src/soc/intel/broadwell/include/soc/smm.h +++ b/src/soc/intel/broadwell/include/soc/smm.h @@ -25,20 +25,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - msr_t uncore_prmrr_base; - msr_t uncore_prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 2cf97e3..5cac560 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -33,33 +34,8 @@ #include <soc/systemagent.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} - -static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, - "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_prmrr_base.lo, - relo_params->uncore_prmrr_mask.lo); - wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base); - wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index ed8cbef..3c1f35c 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -28,19 +28,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; - /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 3da1a56..a552b58 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -27,6 +27,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -37,15 +38,8 @@ #include "chip.h" /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350c..b5d45bb 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -4,6 +4,8 @@ subdirs-y += block/ subdirs-y += pch/ +subdirs-y += ../../../cpu/intel/smm + verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h index 3307cb0..3040688 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h @@ -26,18 +26,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - msr_t prmrr_base; - msr_t prmrr_mask; - /* The smm_save_state_in_msrs field indicates if SMM save state - locations live in MSRs. This indicates to the CPUs how to adjust - the SMMBASE and IEDBASE. */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index 283f5c1..d797438 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -24,6 +24,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <device/pci_ops.h> #include <soc/lpc.h> @@ -33,23 +34,8 @@ #include <soc/broadwell_de.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} - -static inline void write_prmrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo); - wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base); - wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index 5d64d3b..b427085 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -27,18 +27,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 3e949b2..21b9a13 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include <soc/systemagent.h> /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 6eb6b1e..8fa415c 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -29,18 +29,6 @@ u8 reserved[34]; } __packed; -struct smm_relocation_params { - uintptr_t ied_base; - size_t ied_size; - msr_t smrr_base; - msr_t smrr_mask; - /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE - */ - int smm_save_state_in_msrs; -}; void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index ebb853a..b80aa14 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -26,6 +26,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <intelblocks/smm.h> #include <soc/cpu.h> @@ -36,15 +37,8 @@ #include "chip.h" /* This gets filled in and used during relocation. */ -static struct smm_relocation_params smm_reloc_params; +struct smm_relocation_params smm_reloc_params; -static inline void write_smrr(struct smm_relocation_params *relo_params) -{ - printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); -} static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, -- To view, visit https://review.coreboot.org/c/coreboot/+/34840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Gerrit-Change-Number: 34840 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: intel/microcode: Remove uses of __PRE_RAM__
by Kyösti Mälkki (Code Review) 22 Nov '19

22 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34929 ) Change subject: intel/microcode: Remove uses of __PRE_RAM__ ...................................................................... intel/microcode: Remove uses of __PRE_RAM__ Include file <smp/spinlock.h> has the required logic to define empty stubs for spinlocks. Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34929/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 44f7f1f..7bd072f 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -27,11 +27,9 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> - -#if !defined(__PRE_RAM__) #include <smp/spinlock.h> + DECLARE_SPIN_LOCK(microcode_lock) -#endif struct microcode { u32 hdrver; /* Header Version */ @@ -152,7 +150,7 @@ unsigned int x86_model, x86_family; msr_t msr; -#ifdef __ROMCC__ +#if defined(__ROMCC__) struct cbfs_file *microcode_file; microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); @@ -228,15 +226,11 @@ { const void *patch = intel_microcode_find(); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_lock(&microcode_lock); -#endif intel_microcode_load_unlocked(patch); -#if !defined(__ROMCC__) && !defined(__PRE_RAM__) spin_unlock(&microcode_lock); -#endif } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/34929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0 Gerrit-Change-Number: 34929 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: device/pci: Reduce scope of dev_find_slot()
by Kyösti Mälkki (Code Review) 21 Nov '19

21 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34084 ) Change subject: device/pci: Reduce scope of dev_find_slot() ...................................................................... device/pci: Reduce scope of dev_find_slot() We only keep it around because amdfam10 does not yet work correctly without it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34084/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index c1b0b06..691cd80 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -35,6 +35,8 @@ * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. */ + +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn) { @@ -51,6 +53,7 @@ } return result; } +#endif /** * Given a Device Path Type, find the device structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/34084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Gerrit-Change-Number: 34084 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: [POC,RFC] Pass cbmem_top from romstage to relocatable stages param
by Arthur Heymans (Code Review) 21 Nov '19

21 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36140 ) Change subject: [POC,RFC] Pass cbmem_top from romstage to relocatable stages param ...................................................................... [POC,RFC] Pass cbmem_top from romstage to relocatable stages param Currently all stages that need cbmem need an implementation of a cbmem_top function. On FSP and AGESA platforms this proves to be painful and using the top of lower memory if often passed via lower memory or via a PCI scratchpad register. The problem with writing to lower memory is that also need to be written on S3 as one cannot assume it to be still there. Writing things on S3 is always a fragile thing to do. A better and more generic solution is to pass along cbmem_top via relocatable module parameters. TODO: other platforms, nb/intel/i945 only at the moment. Tested on Thinkpad X60. Change-Id: I3195560f110720959fd7389b366d001bfde4da05 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S A src/arch/x86/cbmem_top.c M src/arch/x86/exit_car.S M src/arch/x86/postcar_loader.c M src/lib/prog_loaders.c M src/lib/program.ld M src/northbridge/intel/i945/memmap.c 8 files changed, 64 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36140/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 612424d..8d90fc5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -277,6 +277,7 @@ postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +postcar-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_top.c LDFLAGS_postcar += -Map $(objcbfs)/postcar.map @@ -330,6 +331,7 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S +ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_top.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memcpy.c diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 32b848d..8112b31 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -13,6 +13,15 @@ #include <cpu/x86/post_code.h> + .section ".module_parameters", "aw", @progbits +.global cbmem_top_ptr +cbmem_top_ptr: +#if defined(__X86_64__) + .quad 0 +#else + .long 0 +#endif + /* Place the stack in the bss section. It's not necessary to define it in the * the linker script. */ .section .bss, "aw", @nobits diff --git a/src/arch/x86/cbmem_top.c b/src/arch/x86/cbmem_top.c new file mode 100644 index 0000000..0c42035 --- /dev/null +++ b/src/arch/x86/cbmem_top.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +extern uintptr_t cbmem_top_ptr; + +void *cbmem_top(void) +{ + return (void *)cbmem_top_ptr; +} diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 679e335e..0440a0b 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -18,9 +18,18 @@ .section ".module_parameters", "aw", @progbits /* stack_top indicates the stack to pull MTRR information from. */ .global post_car_stack_top +.global cbmem_top_ptr +#if defined(__X86_64__) +post_car_stack_top: +.quad 0 +cbmem_top_ptr: +.quad 0 +#else post_car_stack_top: .long 0 +cbmem_top_ptr: .long 0 +#endif .text .global _start diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index c6149ab..87e55a5 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -153,15 +153,20 @@ stack_push(pcf, pcf->max_var_mtrrs); } -static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) +struct postcar_param { + uintptr_t stack_top_ptr; + uintptr_t cbmem_top_ptr; +}; + +static void finalize_load(struct postcar_param *param, uintptr_t stack_top) { - *stack_top_ptr = stack_top; + param->stack_top_ptr = stack_top; + param->cbmem_top_ptr = (uintptr_t)cbmem_top(); /* * Signal to rest of system that another update was made to the * postcar program prior to running it. */ - prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), - SEG_FINAL); + prog_segment_loaded((uintptr_t)param, sizeof(uintptr_t), SEG_FINAL); } static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 2ef6bdf..ccf9f4a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -99,12 +99,22 @@ static int load_relocatable_ramstage(struct prog *ramstage) { + int ret; struct rmod_stage_load rmod_ram = { .cbmem_id = CBMEM_ID_RAMSTAGE, .prog = ramstage, }; - return rmodule_stage_load(&rmod_ram); + ret = rmodule_stage_load(&rmod_ram); + + if (rmod_ram.params == NULL) + die_with_post_code(POST_INVALID_ROM, + "No parameters found in ramstagege program.\n"); + *(uintptr_t *)rmod_ram.params = (uintptr_t)cbmem_top(); + + prog_segment_loaded((uintptr_t)rmod_ram.params, sizeof(uintptr_t), SEG_FINAL); + + return ret; } void run_ramstage(void) diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..317e720 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -97,7 +97,7 @@ * traditional stages in the coreboot infrastructure. Therefore it's easier * to specialize this case. */ -#if ENV_RMODULE || ENV_POSTCAR +#if ENV_RMODULE || ENV_POSTCAR || ENV_RAMSTAGE _rmodule_params = .; KEEP(*(.module_parameters)); _ermodule_params = .; diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 8207d06..b1326a3 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -71,11 +71,13 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ +#if ENV_ROMSTAGE void *cbmem_top(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; } +#endif /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) -- To view, visit https://review.coreboot.org/c/coreboot/+/36140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3195560f110720959fd7389b366d001bfde4da05 Gerrit-Change-Number: 36140 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: sb/intel/i82801gx: Don't program CIR3
by Arthur Heymans (Code Review) 21 Nov '19

21 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36218 ) Change subject: sb/intel/i82801gx: Don't program CIR3 ...................................................................... sb/intel/i82801gx: Don't program CIR3 X4x likely does not properly init the DMI Virtual Channels, causing problems to this reg. Change-Id: Ic2deeabc96c2097f3ded80d262af21d2009ce063 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/early_cir.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36218/1 diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c index 29791bb..8efbbd1 100644 --- a/src/southbridge/intel/i82801gx/early_cir.c +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -30,7 +30,10 @@ RCBA32(CG) = 1; RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; + /* CIR3, Private virtual channel routing, skip on x4x because of + issues. (likely needs to properly set up DMI virtual channel. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + RCBA16(0x01fc) = 0x060f; RCBA32(0x01f4) = 0x86000040; /* Although bit 6 is set, it is not read back */ RCBA32(0x0214) = 0x10030549; -- To view, visit https://review.coreboot.org/c/coreboot/+/36218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2deeabc96c2097f3ded80d262af21d2009ce063 Gerrit-Change-Number: 36218 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [TEST]mb/asrock/g41c-gs: Move CIR init after dmi init
by Arthur Heymans (Code Review) 21 Nov '19

21 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36202 ) Change subject: [TEST]mb/asrock/g41c-gs: Move CIR init after dmi init ...................................................................... [TEST]mb/asrock/g41c-gs: Move CIR init after dmi init Change-Id: I8a700b58c48d1f35364a2352b75d2f0cbde226cd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36202/1 diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index bb7a342..090bb79 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -63,8 +63,6 @@ /* Enable IOAPIC */ RCBA8(OIC) = 0x03; RCBA8(OIC); - - ich7_setup_cir(); } static void ich7_enable_lpc(void) @@ -103,6 +101,8 @@ x4x_late_init(s3_resume); + ich7_setup_cir(); + printk(BIOS_DEBUG, "x4x late init complete\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a700b58c48d1f35364a2352b75d2f0cbde226cd Gerrit-Change-Number: 36202 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
by HAOUAS Elyes (Code Review) 21 Nov '19

21 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32915 Change subject: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) ...................................................................... {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001' Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..9ab4af1 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -140,9 +140,6 @@ static void rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 0c7c0cf..8c0b3e4 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 502eac3..2404fb7 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; -- To view, visit https://review.coreboot.org/c/coreboot/+/32915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Gerrit-Change-Number: 32915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: [WIP] amdfam10: Remove generic device for SPD eeproms
by Kyösti Mälkki (Code Review) 21 Nov '19

21 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35101 ) Change subject: [WIP] amdfam10: Remove generic device for SPD eeproms ...................................................................... [WIP] amdfam10: Remove generic device for SPD eeproms Change-Id: Id675d3e53c80f84e233b61a3e5e5d127ced2eb40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/advansus/a785e-i/devicetree.cb M src/mainboard/amd/bimini_fam10/devicetree.cb M src/mainboard/amd/mahogany_fam10/devicetree.cb M src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb M src/mainboard/amd/tilapia_fam10/devicetree.cb M src/mainboard/asus/kcma-d8/devicetree.cb M src/mainboard/asus/kfsn4-dre/devicetree.cb M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/m4a78-em/devicetree.cb M src/mainboard/asus/m4a785-m/devicetree.cb M src/mainboard/asus/m4a785t-m/devicetree.cb M src/mainboard/asus/m5a88-v/devicetree.cb M src/mainboard/biostar/a68n_5200/devicetree.cb M src/mainboard/gigabyte/ma785gm/devicetree.cb M src/mainboard/gigabyte/ma785gmt/devicetree.cb M src/mainboard/gigabyte/ma78gm/devicetree.cb M src/mainboard/iei/kino-780am2-fam10/devicetree.cb M src/mainboard/jetway/pa78vm5/devicetree.cb M src/mainboard/msi/ms9652_fam10/devicetree.cb M src/mainboard/supermicro/h8dmr_fam10/devicetree.cb M src/mainboard/tyan/s2912_fam10/devicetree.cb M src/mainboard/via/epia-m850/devicetree.cb 22 files changed, 0 insertions(+), 381 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35101/1 diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index c78c508..fb87f81 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index ba6a0faf..0d40b20 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -39,18 +39,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index dba1470..81c7e73 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 54c34f8..c827678 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -73,32 +73,8 @@ chip drivers/i2c/i2cmux2 # pca9556 smbus mux chip drivers/i2c/i2cmux2 # pca9556 smbus mux device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end end end end diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 06e33f7..9bf9d08 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index f8a2d83..7320716 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -50,30 +50,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83795 register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 50e2862..8807a47 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -52,30 +52,6 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83793 register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..4b5488e 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -57,30 +57,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end chip drivers/i2c/w83795 register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb index f336c2b..4ed962b 100644 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ b/src/mainboard/asus/m4a78-em/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb index 9dc937c..f426ab5 100644 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ b/src/mainboard/asus/m4a785-m/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index 6fce0f3..4a584f3 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -43,18 +43,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb index d0efbdf..7d7f8f5 100644 --- a/src/mainboard/asus/m5a88-v/devicetree.cb +++ b/src/mainboard/asus/m5a88-v/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index fd9b6ed..667e333 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -43,12 +43,6 @@ device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb index 65c76fb..cfc71a7 100644 --- a/src/mainboard/gigabyte/ma785gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb index a38ebd8..3a99f5c 100644 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb @@ -42,18 +42,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 3e69cb3..cedf2f8 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -41,18 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index 6517c97..de7dcce 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -40,12 +40,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 79915ac..de91304 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -41,12 +41,6 @@ device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index c6dae6d..3efe8ec 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -86,56 +86,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index ee88c31..5c8d40c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -55,53 +55,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end chip drivers/generic/generic # MAC EEPROM device i2c 51 on end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index e49e16b..dfc3139 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -55,53 +55,11 @@ end end device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 1.1 on # SM 1 # PCI device SMBus address will # depend on addon PCI device, do # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end chip drivers/generic/generic # MAC EEPROM device i2c 51 on end end diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb index 4dc7c27..e33b173 100644 --- a/src/mainboard/via/epia-m850/devicetree.cb +++ b/src/mainboard/via/epia-m850/devicetree.cb @@ -71,12 +71,6 @@ register "base" = "(void *)0xfec00000" device ioapic 1 on end end - #chip drivers/generic/generic # DIMM 0 channel 1 - # device i2c 50 on end - #end - #chip drivers/generic/generic # DIMM 1 channel 1 - # device i2c 51 on end - #end chip superio/fintek/f81865f # Super duper IO device pnp 4e.0 off end # Floppy device pnp 4e.3 off end # Parallel Port -- To view, visit https://review.coreboot.org/c/coreboot/+/35101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id675d3e53c80f84e233b61a3e5e5d127ced2eb40 Gerrit-Change-Number: 35101 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/spi: Use 64 bits in multiplication
by Jacob Garber (Code Review) 20 Nov '19

20 Nov '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34373 ) Change subject: drivers/spi: Use 64 bits in multiplication ...................................................................... drivers/spi: Use 64 bits in multiplication speed is a 64 bit variable, so use 64 bits in the intermediate calculations to avoid possible overflow. Change-Id: Id36eda6d64057cde4750184d03c9701011edb890 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1402094 --- M src/drivers/spi/cbfs_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34373/1 diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index ad282c6..9437c2e 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -55,7 +55,7 @@ u64 speed; /* KiB/s */ int bps; /* Bits per second */ - speed = size * 1000 / usecs; + speed = size * 1000ULL / usecs; bps = speed * 8; printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/34373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36eda6d64057cde4750184d03c9701011edb890 Gerrit-Change-Number: 34373 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019