coreboot-gerrit May 2018

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Change in coreboot[master]: arch/x86/acpi_device: Add macros to define gpio with wake flag
by build bot (Jenkins) (Code Review) 03 May '18

03 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25838 ) Change subject: arch/x86/acpi_device: Add macros to define gpio with wake flag ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/71248/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/25420/ : SUCCESS -- To view, visit https://review.coreboot.org/25838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0 Gerrit-Change-Number: 25838 Gerrit-PatchSet: 4 Gerrit-Owner: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 02 May 2018 22:01:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Remove USB30PortInit setting
by build bot (Jenkins) (Code Review) 02 May '18

02 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26015 ) Change subject: soc/amd/stoneyridge: Remove USB30PortInit setting ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71247/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25419/ : SUCCESS -- To view, visit https://review.coreboot.org/26015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Gerrit-Change-Number: 26015 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 May 2018 21:41:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Remove USB30PortInit setting
by Martin Roth (Code Review) 02 May '18

02 May '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26015 Change subject: soc/amd/stoneyridge: Remove USB30PortInit setting ...................................................................... soc/amd/stoneyridge: Remove USB30PortInit setting This bitmask sets the USB PORTSC.DR bit for each XHCI port. This is mainboard specific, and only for non-removable devices attached to the XHCI port. BUG=b:72859972 TEST=Boot grunt Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/soc/amd/stoneyridge/BiosCallOuts.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26015/1 diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c6eef1a..d2f7a32 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -68,9 +68,6 @@ FchParams_env->Usb.Xhci0Enable = FALSE; FchParams_env->Usb.Xhci1Enable = FALSE; - /* 8: If USB3 port is unremoveable. */ - FchParams_env->Usb.USB30PortInit = 8; - /* SATA configuration */ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { -- To view, visit https://review.coreboot.org/26015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Gerrit-Change-Number: 26015 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: google/kahlee: Set SPI 100 MHz and SPI Dual Read IO mode
by Martin Roth (Code Review) 02 May '18

02 May '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/25970 ) Change subject: google/kahlee: Set SPI 100 MHz and SPI Dual Read IO mode ...................................................................... google/kahlee: Set SPI 100 MHz and SPI Dual Read IO mode Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/bootblock/bootblock.c 1 file changed, 10 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 577c105..aac1d95 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -34,9 +34,17 @@ void bootblock_mainboard_init(void) { + /* + * W25Q128FW Setup + * Normal Read 40MHz + * Fast Read 104MHz + * Dual Read IO (1-2-2) + */ + sb_read_mode(SPI_READ_MODE_DUAL122); + /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_22M, /* Normal */ - SPI_SPEED_66M, /* Fast */ + sb_set_spi100(SPI_SPEED_33M, /* Normal */ + SPI_SPEED_100M, /* Fast */ SPI_SPEED_66M, /* AltIO */ SPI_SPEED_66M); /* TPM */ -- To view, visit https://review.coreboot.org/25970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Gerrit-Change-Number: 25970 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: remove sb_set_readspeed function
by Martin Roth (Code Review) 02 May '18

02 May '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/25969 ) Change subject: soc/amd/stoneyridge: remove sb_set_readspeed function ...................................................................... soc/amd/stoneyridge: remove sb_set_readspeed function The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 0 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 96826e3..0a23fca 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -379,7 +379,6 @@ void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void sb_set_readspeed(u16 norm, u16 fast); void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a767e0c..eb8820f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -442,15 +442,6 @@ & ~SPI_RD4DW_EN_HOST); } -void sb_set_readspeed(u16 norm, u16 fast) -{ - uintptr_t base = sb_spibase(); - write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) - & ~SPI_CNTRL1_SPEED_MASK) - | (norm << SPI_NORM_SPEED_SH) - | (fast << SPI_FAST_SPEED_SH)); -} - void sb_read_mode(u32 mode) { uintptr_t base = sb_spibase(); -- To view, visit https://review.coreboot.org/25969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Gerrit-Change-Number: 25969 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee: Revert "Resume on AC insertion"
by build bot (Jenkins) (Code Review) 02 May '18

02 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26014 ) Change subject: google/kahlee: Revert "Resume on AC insertion" ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71246/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25418/ : SUCCESS -- To view, visit https://review.coreboot.org/26014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Gerrit-Change-Number: 26014 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 May 2018 20:32:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Revert "Resume on AC insertion"
by Martin Roth (Code Review) 02 May '18

02 May '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26014 Change subject: google/kahlee: Revert "Resume on AC insertion" ...................................................................... google/kahlee: Revert "Resume on AC insertion" This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/26014/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h index 7eef99d..976b621 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h @@ -44,11 +44,10 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) -/* EC can wake from S3 with lid, power button, key press, or AC connect */ +/* EC can wake from S3 with lid or power button or key press */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ -- To view, visit https://review.coreboot.org/26014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Gerrit-Change-Number: 26014 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: drivers/ricoh/rce822: Get rid of device_t
by build bot (Jenkins) (Code Review) 02 May '18

02 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26013 ) Change subject: drivers/ricoh/rce822: Get rid of device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71245/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25417/ : SUCCESS -- To view, visit https://review.coreboot.org/26013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d Gerrit-Change-Number: 26013 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 May 2018 20:14:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/uart/oxpcie.c: Get rid of device_t
by build bot (Jenkins) (Code Review) 02 May '18

02 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26012 ) Change subject: drivers/uart/oxpcie.c: Get rid of device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71244/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25416/ : SUCCESS -- To view, visit https://review.coreboot.org/26012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743 Gerrit-Change-Number: 26012 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 May 2018 20:07:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/drivers/lenovo/wacom.c: Get rid of device_t
by build bot (Jenkins) (Code Review) 02 May '18

02 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26011 ) Change subject: src/drivers/lenovo/wacom.c: Get rid of device_t ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/71243/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/25415/ : SUCCESS -- To view, visit https://review.coreboot.org/26011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785 Gerrit-Change-Number: 26011 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 02 May 2018 20:07:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit May 2018