coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/hatch: Add memory init setup for hatch
by Subrata Banik (Code Review) 22 Dec '18

22 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30248 ) Change subject: mb/google/hatch: Add memory init setup for hatch ...................................................................... Patch Set 13: please rebase this patch to get it merged ? -- To view, visit https://review.coreboot.org/c/coreboot/+/30248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Gerrit-Change-Number: 30248 Gerrit-PatchSet: 13 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 06:38:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Add memory init setup for hatch
by Shelley Chen (Code Review) 22 Dec '18

22 Dec '18

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30248 ) Change subject: mb/google/hatch: Add memory init setup for hatch ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Gerrit-Change-Number: 30248 Gerrit-PatchSet: 13 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 06:33:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Enable IGD (Integrated GFX Device)
by Subrata Banik (Code Review) 22 Dec '18

22 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30364 ) Change subject: mb/google/hatch: Enable IGD (Integrated GFX Device) ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30364/1/src/mainboard/google/hatch/variants… File src/mainboard/google/hatch/variants/baseboard/devicetree.cb: https://review.coreboot.org/#/c/30364/1/src/mainboard/google/hatch/variants… PS1, Line 31: SkipExtGfxScan just to confirm we don't want FSP to scan for external display ? Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices -- To view, visit https://review.coreboot.org/c/coreboot/+/30364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d Gerrit-Change-Number: 30364 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 04:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Add HPD GPIO support for displays
by Subrata Banik (Code Review) 22 Dec '18

22 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30365 ) Change subject: mb/google/hatch: Add HPD GPIO support for displays ...................................................................... Patch Set 1: -Code-Review (1 comment) https://review.coreboot.org/#/c/30365/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30365/1//COMMIT_MSG@9 PS1, Line 9: type Type-C -- To view, visit https://review.coreboot.org/c/coreboot/+/30365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650 Gerrit-Change-Number: 30365 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 04:25:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Add HPD GPIO support for displays
by Subrata Banik (Code Review) 22 Dec '18

22 Dec '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30365 ) Change subject: mb/google/hatch: Add HPD GPIO support for displays ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9d52dc0f9916f761c8fdd88c76968aaf663e650 Gerrit-Change-Number: 30365 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 04:25:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Adjust GPD3 pin termination
by Lijian Zhao (Code Review) 22 Dec '18

22 Dec '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30374 Change subject: mb/google/sarien: Adjust GPD3 pin termination ...................................................................... mb/google/sarien: Adjust GPD3 pin termination Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30374/1 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 38d21c8..3f43e73 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -213,7 +213,6 @@ /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -237,6 +236,7 @@ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/30374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Gerrit-Change-Number: 30374 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Disable pcie interface for wwan
by Duncan Laurie (Code Review) 21 Dec '18

21 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30350 ) Change subject: mb/google/sarien: Disable pcie interface for wwan ...................................................................... mb/google/sarien: Disable pcie interface for wwan WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12. BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved EricR Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a8bb342..52840de 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -86,11 +86,6 @@ register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" - # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[3]" = "11" - register "PcieClkSrcClkReq[3]" = "3" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" @@ -240,7 +235,7 @@ device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c24cd02..47abadc 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -95,11 +95,6 @@ register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" - # PCIe port 12 for M.2 3042 - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[0]" = "11" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" @@ -259,7 +254,7 @@ device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Gerrit-Change-Number: 30350 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/intel/coffeelake_rvp: Update default configuration
by Patrick Georgi (Code Review) 21 Dec '18

21 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30318 ) Change subject: mb/intel/coffeelake_rvp: Update default configuration ...................................................................... mb/intel/coffeelake_rvp: Update default configuration Report correct board information for Whiskeylake RVP to OS. Use short board name like other RVP as it's used for firmware version check in auto test. Change-Id: I3f7c95f136e39b978a335cc7855cac819043db7c Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Reviewed-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved Boon Tiong Teo: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 85c8d2f..7597629 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -30,7 +30,8 @@ config MAINBOARD_PART_NUMBER string - default "Coffeelake RVP" + default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "cflrvp" config MAINBOARD_VENDOR string @@ -38,7 +39,8 @@ config MAINBOARD_FAMILY string - default "Intel_coffeelake_rvp" + default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "Intel_cflrvp" config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/30318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7c95f136e39b978a335cc7855cac819043db7c Gerrit-Change-Number: 30318 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: car/non-evict/cache_as_ram.S: Use tabs instead of spaces
by Patrick Georgi (Code Review) 21 Dec '18

21 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30336 ) Change subject: car/non-evict/cache_as_ram.S: Use tabs instead of spaces ...................................................................... car/non-evict/cache_as_ram.S: Use tabs instead of spaces Change-Id: Icc5fc9ca4aadf02bd9e63b4abc02131b6c2a79da Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30336 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 8f4cfe7..163f4b4 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -128,10 +128,10 @@ movl %eax, %cr0 /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr /* Clear the cache memory region. This will also fill up the cache. */ @@ -142,9 +142,9 @@ rep stosl /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr post_code(0x26) -- To view, visit https://review.coreboot.org/c/coreboot/+/30336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc5fc9ca4aadf02bd9e63b4abc02131b6c2a79da Gerrit-Change-Number: 30336 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPD
by Patrick Georgi (Code Review) 21 Dec '18

21 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30327 ) Change subject: mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPD ...................................................................... mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPD Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 2 files changed, 33 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex b/src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex new file mode 100644 index 0000000..4c44041 --- /dev/null +++ b/src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 D0 19 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 33 47 32 4A 31 20 20 20 31 80 2C +4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 53c7cd1..7f86bb7 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -13,7 +13,7 @@ SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 SPD_SOURCES += hynix_dimm_H5AN4G6NAFR-UHC # 0b1010 SPD_SOURCES += micron_dimm_MT40A256M16LY-075F # 0b1011 -SPD_SOURCES += empty_ddr4 # 0b1100 +SPD_SOURCES += micron_dimm_MT40A512M16TB-062EJ # 0b1100 SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b1110 SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b1111 -- To view, visit https://review.coreboot.org/c/coreboot/+/30327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Gerrit-Change-Number: 30327 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit December 2018