coreboot-gerrit January 2018

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Change in coreboot[master]: cpu/intel/socket_mPGA478mn, socket_BGA956: Use common CAR code
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23454 ) Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21239/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66629/ : SUCCESS -- To view, visit https://review.coreboot.org/23454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e Gerrit-Change-Number: 23454 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 13:43:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/gm45: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23455 ) Change subject: nb/intel/gm45: Use postcar stage to tear down CAR ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21240/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66630/ : SUCCESS -- To view, visit https://review.coreboot.org/23455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e848dcadeffb092b98bc5868e370dffce44a0c0 Gerrit-Change-Number: 23455 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 13:28:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/haswell: Use postcar stage and common CAR code
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23465 ) Change subject: cpu/intel/haswell: Use postcar stage and common CAR code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21241/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66631/ : SUCCESS -- To view, visit https://review.coreboot.org/23465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibf58ae38d28d220c5c356d2e2bd14b0c9f828262 Gerrit-Change-Number: 23465 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 13:26:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/sandybridge: Tear down CAR in a separate postcar stage
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23450 ) Change subject: intel/sandybridge: Tear down CAR in a separate postcar stage ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21238/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66628/ : SUCCESS -- To view, visit https://review.coreboot.org/23450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieefe0564af3470cba484eea131802f1529dbe22c Gerrit-Change-Number: 23450 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 13:25:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/haswell: Use postcar stage and common CAR code
by Arthur Heymans (Code Review) 27 Jan '18

27 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23465 Change subject: cpu/intel/haswell: Use postcar stage and common CAR code ...................................................................... cpu/intel/haswell: Use postcar stage and common CAR code Uses postcar_frame_and_mtrr functions to set up the postcar stack frame. Tested on ACER C720 (peppy): still boots. Change-Id: Ibf58ae38d28d220c5c356d2e2bd14b0c9f828262 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc D src/cpu/intel/haswell/cache_as_ram.inc M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/Makefile.inc 5 files changed, 27 insertions(+), 355 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/23465/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index d6df9c0..46bf41b 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -27,6 +27,11 @@ select PARALLEL_CPU_INIT select PARALLEL_MP select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_CAR + select CPU_HAS_NO_EVICT_MODE + select CPU_HAS_20_VARIABLE_MTRR + select POSTCAR_STAGE + select POSTCAR_CONSOLE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bb0f376..fabd246 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -10,11 +10,13 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-y += monotonic_timer.c -cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc +subdirs-y += ../car subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc deleted file mode 100644 index 388c2ea..0000000 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ /dev/null @@ -1,297 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define NoEvictMod_MSR 0x2e0 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - post_code(0x22) - /* Configure the default memory type to uncacheable. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - andl $~2, %eax - wrmsr - - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $3, %eax - wrmsr - - post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRPROT, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x27) - /* Enable caching for RAM init code to run faster */ - movl $MTRR_PHYS_BASE(2), %ecx - movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x28) - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %esp - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x32) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - invd - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F - .word 0x210, 0x211, 0x212, 0x213 -mtrr_table_end: diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 6d9fbc4..de4453b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -68,82 +68,41 @@ /* setup_romstage_stack_after_car() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_romstage_stack_after_car(void) +static void setup_romstage_stack_after_car(void) { - int num_mtrrs; - u32 *slot; - u32 mtrr_mask_upper; + struct postcar_frame pcf; u32 top_of_ram; - /* Top of stack needs to be aligned to a 4-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; - - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of RAM. On haswell systems the top of - * RAM under 4GiB is the start of the TSEG region. It is required to + top_of_ram = (uintptr_t)cbmem_top(); + /* Cache 8MiB below the top of ram. On sandybridge systems the top of + * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems + /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM * handler as well as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; + run_postcar_phase(&pcf); } asmlinkage void *romstage_main(unsigned long bist) { int i; - void *romstage_stack_after_car; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + @@ -164,9 +123,10 @@ } /* Get the stack to use after cache-as-ram is torn down. */ - romstage_stack_after_car = setup_romstage_stack_after_car(); + setup_romstage_stack_after_car(); - return romstage_stack_after_car; + /* We don't return here */ + return NULL; } void romstage_common(const struct romstage_params *params) diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f198b7c..4bcc9f3 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -28,6 +28,8 @@ romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S +postcar-y += ram_calc.c + smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail -- To view, visit https://review.coreboot.org/23465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf58ae38d28d220c5c356d2e2bd14b0c9f828262 Gerrit-Change-Number: 23465 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/haswell: Use the common MRC cache driver
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23464 ) Change subject: nb/intel/haswell: Use the common MRC cache driver ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21237/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66627/ : SUCCESS -- To view, visit https://review.coreboot.org/23464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Gerrit-Change-Number: 23464 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 12:46:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/haswell: Use the common MRC cache driver
by Arthur Heymans (Code Review) 27 Jan '18

27 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23464 Change subject: nb/intel/haswell: Use the common MRC cache driver ...................................................................... nb/intel/haswell: Use the common MRC cache driver This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/raminit.c 3 files changed, 13 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/23464/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index d5dec53..5c8caea 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -16,7 +16,7 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE @@ -39,11 +39,6 @@ int default 512 -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x10000 - config DCACHE_RAM_BASE hex default 0xff7c0000 diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f198b7c..c6d6b2e 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -36,16 +36,4 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -ifneq ($(CONFIG_CHROMEOS),y) -$(obj)/mrc.cache: $(obj)/config.h - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif - endif diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index f17a374..e5e2b93 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -22,42 +22,44 @@ #include <halt.h> #include <ip_checksum.h> #include <memory_info.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include <device/dram/ddr3.h> #include <smbios.h> #include <spd.h> #include <security/vboot/vboot_common.h> +#include <commonlib/region.h> #include "raminit.h" #include "pei_data.h" #include "haswell.h" +#define MRC_CACHE_VERSION 1 + void save_mrc_data(struct pei_data *pei_data) { /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + pei_data->mrc_output, pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) { - struct mrc_data_container *mrc_cache; + struct region_device rdev; // preset just in case there is an error pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; - if ((mrc_cache = find_current_mrc_cache()) == NULL) { + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) /* error message printed in find_current_mrc_cache */ return; - } - pei_data->mrc_input = mrc_cache->mrc_data; - pei_data->mrc_input_len = mrc_cache->mrc_data_size; + pei_data->mrc_input = rdev_mmap_full(&rdev); + pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", - __func__, pei_data->mrc_input, - pei_data->mrc_input_len, mrc_cache->mrc_checksum); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", + __func__, pei_data->mrc_input, pei_data->mrc_input_len); } static const char* ecc_decoder[] = { -- To view, visit https://review.coreboot.org/23464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Gerrit-Change-Number: 23464 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/intel/glkrvp: Set S0ix lazy wake mask
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23453 ) Change subject: mb/intel/glkrvp: Set S0ix lazy wake mask ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21236/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66626/ : SUCCESS -- To view, visit https://review.coreboot.org/23453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7 Gerrit-Change-Number: 23453 Gerrit-PatchSet: 2 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 06:36:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v82_51
by Hannah Williams (Code Review) 27 Jan '18

27 Jan '18

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/23460 ) Change subject: vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v82_51 ...................................................................... Patch Set 1: You can abandon this patch because looks like there is no change to FSP header - no new UPDs -- To view, visit https://review.coreboot.org/23460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd13e917b91dd4356d381edecffea670cad930eb Gerrit-Change-Number: 23460 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 06:10:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add IPU enable option
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23447 ) Change subject: soc/intel/cannonlake: Add IPU enable option ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21235/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66625/ : SUCCESS -- To view, visit https://review.coreboot.org/23447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2aa7d22795c96d4c907b8f8a5d6bb22f75de71a Gerrit-Change-Number: 23447 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 03:46:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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