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Change subject: cpu/intel/haswell: Use postcar stage and common CAR code
......................................................................
Patch Set 6: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/21271/ : SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/66662/ : SUCCESS
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Change subject: nb/intel/gm45: Use postcar stage to tear down CAR
......................................................................
Patch Set 9: Verified+1
Build Successful
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Change subject: intel/sandybridge: Tear down CAR in a separate postcar stage
......................................................................
Patch Set 15:
Build Successful
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Change subject: cpu/intel/car: Compute more things during runtime
......................................................................
Patch Set 5: Verified+1
Build Successful
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Change subject: cpu/intel/haswell: Use postcar stage and common CAR code
......................................................................
Patch Set 5: Verified-1
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Change subject: nb/intel/gm45: Use postcar stage to tear down CAR
......................................................................
Patch Set 8: Verified-1
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Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code
......................................................................
Patch Set 8: Verified-1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/23467
to look at the new patch set (#5).
Change subject: cpu/intel/car: Compute more things during runtime
......................................................................
cpu/intel/car: Compute more things during runtime
This does a few more things during runtime:
* Compute the amount of variable MTRR's during runtime from
MTRR_CAP_MSR;
* Compute the PHYSMASK_HI during runtime from cpuid;
* Rely less on the assembler to get values derived from
CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE;
* Detect based on CPUID if the CPU requires L2 cache to be separatly
enabled.
Tested on X220: still boots
Change-Id: I67d03ad5d612bd5e022e6eb619d988e8ccbf087a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/Kconfig
M src/cpu/intel/car/cache_as_ram.S
2 files changed, 100 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23467/5
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23419 )
Change subject: nb/intel/gm45: Use common code for SMM in TSEG
......................................................................
Patch Set 16: Verified+1
Build Successful
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