coreboot-gerrit January 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/gm45: Use postcar stage to tear down CAR
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23455 ) Change subject: nb/intel/gm45: Use postcar stage to tear down CAR ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21279/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66670/ : SUCCESS -- To view, visit https://review.coreboot.org/23455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e848dcadeffb092b98bc5868e370dffce44a0c0 Gerrit-Change-Number: 23455 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 23:53:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/socket_mPGA478mn, socket_BGA956: Use common CAR code
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23454 ) Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21278/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66669/ : SUCCESS -- To view, visit https://review.coreboot.org/23454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e Gerrit-Change-Number: 23454 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 23:52:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel: Move the Sandy Bridge CAR to a common place
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23449 ) Change subject: cpu/intel: Move the Sandy Bridge CAR to a common place ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21276/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66667/ : SUCCESS -- To view, visit https://review.coreboot.org/23449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I68ae66f2620ed061a54d07025295a0eb8f64fa62 Gerrit-Change-Number: 23449 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 23:47:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/sandybridge: Tear down CAR in a separate postcar stage
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23450 ) Change subject: intel/sandybridge: Tear down CAR in a separate postcar stage ...................................................................... Patch Set 16: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21277/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66668/ : SUCCESS -- To view, visit https://review.coreboot.org/23450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieefe0564af3470cba484eea131802f1529dbe22c Gerrit-Change-Number: 23450 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 23:43:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Makefile: Add filelist to help
by Martin Roth (Code Review) 28 Jan '18

28 Jan '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23472 Change subject: Makefile: Add filelist to help ...................................................................... Makefile: Add filelist to help The filelist target has been around for a while, but was never added to the help. Add it now. Change-Id: Idc24ecc8028fc61c6b798c0c81431b05dfa25b0e Signed-off-by: Martin Roth <martinroth(a)google.com> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/23472/1 diff --git a/Makefile b/Makefile index 33b12f8..4aa179d 100644 --- a/Makefile +++ b/Makefile @@ -98,6 +98,7 @@ @echo ' distclean - Remove build artifacts and config files' @echo ' doxygen - Build doxygen documentation for coreboot' @echo ' doxyplatform - Build doxygen documentation for the current platform' + @echo ' filelist - Show files used in current build' @echo ' printall - print makefile info for debugging' @echo ' gitconfig - set up git to submit patches to coreboot' @echo ' ctags / ctags-project - make ctags file for all of coreboot or current board' -- To view, visit https://review.coreboot.org/23472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idc24ecc8028fc61c6b798c0c81431b05dfa25b0e Gerrit-Change-Number: 23472 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: cpu/intel/car: Compute more things during runtime
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23467 ) Change subject: cpu/intel/car: Compute more things during runtime ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21275/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66666/ : SUCCESS -- To view, visit https://review.coreboot.org/23467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67d03ad5d612bd5e022e6eb619d988e8ccbf087a Gerrit-Change-Number: 23467 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 23:42:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/i945: Use postcar stage to tear down CAR
by Arthur Heymans (Code Review) 28 Jan '18

28 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23471 Change subject: nb/intel/i945: Use postcar stage to tear down CAR ...................................................................... nb/intel/i945: Use postcar stage to tear down CAR Tested on Intel d945gclf: still boots. Change-Id: Ibfa54d48377a9bac62bfa5de667f089ed3ae52ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/ram_calc.c 3 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/23471/1 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 482f98a..e04d0c3 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,6 +28,8 @@ select RELOCATABLE_RAMSTAGE select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select POSTCAR_STAGE + select POSTCAR_CONSOLE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 0e4fcfc..ffeabdc 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -29,4 +29,6 @@ smm-y += udelay.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 990df97..fccd388 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -78,8 +78,6 @@ return ggc2uma[gms] << 10; } -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) @@ -87,7 +85,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ @@ -106,8 +104,7 @@ postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + /* Needs to return something but we never go back to the caller */ + return NULL; } -- To view, visit https://review.coreboot.org/23471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibfa54d48377a9bac62bfa5de667f089ed3ae52ed Gerrit-Change-Number: 23471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/socket_441, mFCPGA478: Use common CAR
by Arthur Heymans (Code Review) 28 Jan '18

28 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23469 Change subject: cpu/intel/socket_441,mFCPGA478: Use common CAR ...................................................................... cpu/intel/socket_441,mFCPGA478: Use common CAR Tested on Intel d945gclf, still boots fine. This removes the model_6ex cache as ram since it is no longer needed. Change-Id: I0b5def66e903b448f7f1a77210404657afbedadf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/cpu/intel/model_6ex/cache_as_ram.inc M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_mFCPGA478/Kconfig M src/cpu/intel/socket_mFCPGA478/Makefile.inc 5 files changed, 4 insertions(+), 269 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23469/1 diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc deleted file mode 100644 index 4b85c07..0000000 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) >> 1), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - post_code(0x22) - /* Configure the default memory type to uncacheable. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRR_PHYS_MASK(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory region. This will also fill up the cache. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - post_code(0x26) - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRPROT, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - post_code(0x28) - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %esp - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - andl $(~MTRR_DEF_TYPE_EN), %eax - wrmsr - - post_code(0x32) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Clear all of the variable MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx - clr %eax - clr %edx - -1: - testl %ebx, %ebx - jz 1f - wrmsr /* Write MTRR base. */ - inc %ecx - wrmsr /* Write MTRR mask. */ - inc %ecx - dec %ebx - jmp 1b - -1: - /* Get number of MTRRs. */ - popl %ebx - movl $MTRR_PHYS_BASE(0), %ecx -2: - testl %ebx, %ebx - jz 2f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 2b -2: - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - orl $MTRR_DEF_TYPE_EN, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index ac249c5..b157f62 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -8,6 +8,7 @@ select CPU_INTEL_MODEL_106CX select MMX select SSE + select CPU_INTEL_COMMON_CAR config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index dbf300b..87e1939 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -8,5 +8,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +subdirs-y += ../car romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 075abad..4a20af5 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -9,6 +9,7 @@ select CPU_INTEL_MODEL_6FX select MMX select SSE + select CPU_INTEL_COMMON_CAR config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index 6056d3c..8486bc4 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -11,5 +11,5 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +subdirs-y += ../car romstage-y += ../car/romstage.c -- To view, visit https://review.coreboot.org/23469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b5def66e903b448f7f1a77210404657afbedadf Gerrit-Change-Number: 23469 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/socket_LGA775: Use common CAR
by Arthur Heymans (Code Review) 28 Jan '18

28 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23470 Change subject: cpu/intel/socket_LGA775: Use common CAR ...................................................................... cpu/intel/socket_LGA775: Use common CAR This code will most likely not work on Intel Netburst CPUs but there are reports that these don't work anyway and on some boards Netburst CPUs don't even get to output a post_code (even if placed very early on, after entering 32bit protected mode). Change-Id: I6bf2fe603b4458f14fb7cfaa55d68ebf6d75b347 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/23470/1 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..a965d13 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -6,14 +6,15 @@ config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_MODEL_6FX - select CPU_INTEL_MODEL_F3X - select CPU_INTEL_MODEL_F4X + select CPU_INTEL_MODEL_F3X # Probably not working + select CPU_INTEL_MODEL_F4X # Probably not working # select CPU_INTEL_MODEL_F6X # select CPU_INTEL_MODEL_1066X select CPU_INTEL_MODEL_1067X select MMX select SSE select SIPI_VECTOR_IN_ROM + select CPU_INTEL_COMMON_CAR config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ffcd1cb..b53d9af 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,6 +13,6 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc +subdirs-y += ../car romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c -- To view, visit https://review.coreboot.org/23470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6bf2fe603b4458f14fb7cfaa55d68ebf6d75b347 Gerrit-Change-Number: 23470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/socket_mPGA478mn, socket_BGA956: Use common CAR code
by build bot (Jenkins) (Code Review) 27 Jan '18

27 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23454 ) Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21270/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66661/ : SUCCESS -- To view, visit https://review.coreboot.org/23454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e Gerrit-Change-Number: 23454 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 27 Jan 2018 21:22:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit January 2018