build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23454 )
Change subject: cpu/intel/socket_mPGA478mn,socket_BGA956: Use common CAR code
......................................................................
Patch Set 11:
Build Successful
https://qa.coreboot.org/job/coreboot-checkpatch/21293/ : SUCCESS
https://qa.coreboot.org/job/coreboot-gerrit/66685/ : SUCCESS
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Icc768a88820ea70db15597e4f42b9d29abba796e
Gerrit-Change-Number: 23454
Gerrit-PatchSet: 11
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sun, 28 Jan 2018 19:34:48 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: No
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23479
Change subject: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
......................................................................
inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
Tested to display the register content correctly on a Lenovo Thinkpad
X220.
Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/inteltool/spi.c
1 file changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/23479/1
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index bd84995..ad8f592 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -130,6 +130,36 @@
case PCI_DEVICE_ID_INTEL_PM55:
case PCI_DEVICE_ID_INTEL_QM57:
case PCI_DEVICE_ID_INTEL_QS57:
+ case PCI_DEVICE_ID_INTEL_Z68:
+ case PCI_DEVICE_ID_INTEL_P67:
+ case PCI_DEVICE_ID_INTEL_UM67:
+ case PCI_DEVICE_ID_INTEL_HM65:
+ case PCI_DEVICE_ID_INTEL_H67:
+ case PCI_DEVICE_ID_INTEL_HM67:
+ case PCI_DEVICE_ID_INTEL_Q65:
+ case PCI_DEVICE_ID_INTEL_QS67:
+ case PCI_DEVICE_ID_INTEL_Q67:
+ case PCI_DEVICE_ID_INTEL_QM67:
+ case PCI_DEVICE_ID_INTEL_B65:
+ case PCI_DEVICE_ID_INTEL_C202:
+ case PCI_DEVICE_ID_INTEL_C204:
+ case PCI_DEVICE_ID_INTEL_C206:
+ case PCI_DEVICE_ID_INTEL_H61:
+ case PCI_DEVICE_ID_INTEL_Z77:
+ case PCI_DEVICE_ID_INTEL_Z75:
+ case PCI_DEVICE_ID_INTEL_Q77:
+ case PCI_DEVICE_ID_INTEL_Q75:
+ case PCI_DEVICE_ID_INTEL_B75:
+ case PCI_DEVICE_ID_INTEL_H77:
+ case PCI_DEVICE_ID_INTEL_C216:
+ case PCI_DEVICE_ID_INTEL_QM77:
+ case PCI_DEVICE_ID_INTEL_QS77:
+ case PCI_DEVICE_ID_INTEL_HM77:
+ case PCI_DEVICE_ID_INTEL_UM77:
+ case PCI_DEVICE_ID_INTEL_HM76:
+ case PCI_DEVICE_ID_INTEL_HM75:
+ case PCI_DEVICE_ID_INTEL_HM70:
+ case PCI_DEVICE_ID_INTEL_NM70:
bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = pch_bios_cntl_registers;
size = ARRAY_SIZE(pch_bios_cntl_registers);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Gerrit-Change-Number: 23479
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23477
Change subject: nb/intel/pineview: Use postcar stage to tear down CAR
......................................................................
nb/intel/pineview: Use postcar stage to tear down CAR
This allows to cleanly migrate car globals
Tested on Intel D510MO, still boots fine.
Change-Id: I67887b87d8ca2439259c6e1b7349e4d93514194b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/Makefile.inc
M src/northbridge/intel/pineview/ram_calc.c
3 files changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/23477/1
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index e8ef9d9..80f566a 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -29,6 +29,8 @@
select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
select RELOCATABLE_RAMSTAGE
select INTEL_GMA_ACPI
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index a4c08c8..d7936c1 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -25,4 +25,6 @@
romstage-y += raminit.c
romstage-y += early_init.c
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 63f3942..82073c0 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -105,8 +105,6 @@
return (void *) top_of_ram;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
@@ -114,7 +112,7 @@
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
@@ -133,8 +131,7 @@
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
+ /* We don't return here */
+ return NULL;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I67887b87d8ca2439259c6e1b7349e4d93514194b
Gerrit-Change-Number: 23477
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>