coreboot-gerrit January 2018

coreboot-gerrit@coreboot.org

1 participants
2315 discussions

Change in coreboot[master]: inteltool: Fix displaying 64bit spi registers
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23478 ) Change subject: inteltool: Fix displaying 64bit spi registers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21306/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66698/ : SUCCESS -- To view, visit https://review.coreboot.org/23478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Gerrit-Change-Number: 23478 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 21:41:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd/agesa/family14, 15 & 16: Remove unnecessary whitespace
by Elyes HAOUAS (Code Review) 28 Jan '18

28 Jan '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23481 Change subject: amd/agesa/family14,15 & 16: Remove unnecessary whitespace ...................................................................... amd/agesa/family14,15 & 16: Remove unnecessary whitespace Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/23481/1 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index a03516d..2f7abd8 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -42,7 +42,7 @@ #endif printk(BIOS_DEBUG, "Model 14 Init.\n"); - disable_cache (); + disable_cache(); /* * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index e0bff4f..5f2c603 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -46,7 +46,7 @@ //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index d49216a..aa56881 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -44,7 +44,7 @@ //x86_enable_cache(); //amd_setup_mtrrs(); //x86_mtrr_check(); - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; -- To view, visit https://review.coreboot.org/23481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933 Gerrit-Change-Number: 23481 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: inteltool: Fix displaying 64bit spi registers
by Nico Huber (Code Review) 28 Jan '18

28 Jan '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23478 ) Change subject: inteltool: Fix displaying 64bit spi registers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/23478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Gerrit-Change-Number: 23478 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 21:30:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: inteltool: Fix displaying 64bit spi registers
by Arthur Heymans (Code Review) 28 Jan '18

28 Jan '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/23478 to look at the new patch set (#2). Change subject: inteltool: Fix displaying 64bit spi registers ...................................................................... inteltool: Fix displaying 64bit spi registers The registers were taken from the wrong addess since the spibar offset was not added to it. This also fixes the endianness. Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/inteltool/spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23478/2 -- To view, visit https://review.coreboot.org/23478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Gerrit-Change-Number: 23478 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
by Nico Huber (Code Review) 28 Jan '18

28 Jan '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23479 ) Change subject: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/23479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67 Gerrit-Change-Number: 23479 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 21:00:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: inteltool: Fix displaying 64bit spi registers
by Nico Huber (Code Review) 28 Jan '18

28 Jan '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23478 ) Change subject: inteltool: Fix displaying 64bit spi registers ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/23478/1/util/inteltool/spi.c File util/inteltool/spi.c: https://review.coreboot.org/#/c/23478/1/util/inteltool/spi.c@283 PS1, Line 283: *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr + 4), spi_register[i].name); Mind fixing endianess too? -- To view, visit https://review.coreboot.org/23478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Gerrit-Change-Number: 23478 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 20:59:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: inteltool: Fix displaying 64bit spi registers
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23478 ) Change subject: inteltool: Fix displaying 64bit spi registers ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21303/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66695/ : SUCCESS -- To view, visit https://review.coreboot.org/23478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Gerrit-Change-Number: 23478 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 20:20:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Update chromeec submodule to upstream master
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23480 ) Change subject: Update chromeec submodule to upstream master ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/66697/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21305/ : SUCCESS -- To view, visit https://review.coreboot.org/23480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b Gerrit-Change-Number: 23480 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 20:18:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23479 ) Change subject: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21304/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66696/ : SUCCESS -- To view, visit https://review.coreboot.org/23479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67 Gerrit-Change-Number: 23479 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 20:08:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: Update chromeec submodule to upstream master
by Martin Roth (Code Review) 28 Jan '18

28 Jan '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23480 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700 - (Poppy: Configure camera PMIC to low power mode.) to commit id 4e3940460: 2018-01-26 16:12:08 -0800 - (ectool: increase image capture delay to 200ms) This brings in 1101 new commits. Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23480/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 9fb1038..4e39404 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 9fb10386a720d270e37ce61da3ff3a6d5a69951e +Subproject commit 4e39404604cbe0336eff7e1d087aebdec58a2021 -- To view, visit https://review.coreboot.org/23480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b Gerrit-Change-Number: 23480 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2018