coreboot-gerrit January 2018

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Change in coreboot[master]: nb/common/intel: Remove the mrc cache code
by build bot (Jenkins) (Code Review) 29 Jan '18

29 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23485 ) Change subject: nb/common/intel: Remove the mrc cache code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21311/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66703/ : SUCCESS -- To view, visit https://review.coreboot.org/23485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Gerrit-Change-Number: 23485 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Jan 2018 09:52:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/nehalem: Use the common mrc cache driver
by build bot (Jenkins) (Code Review) 29 Jan '18

29 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23484 ) Change subject: nb/intel/nehalem: Use the common mrc cache driver ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21310/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66702/ : SUCCESS -- To view, visit https://review.coreboot.org/23484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Gerrit-Change-Number: 23484 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Jan 2018 09:26:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/common/intel: Remove the mrc cache code
by Arthur Heymans (Code Review) 29 Jan '18

29 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23485 Change subject: nb/common/intel: Remove the mrc cache code ...................................................................... nb/common/intel: Remove the mrc cache code This is now unused, since all intel northbridges now use the equivalent in drivers/mrc_cache. Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/northbridge/intel/common/Kconfig D src/northbridge/intel/common/Makefile.inc D src/northbridge/intel/common/mrc_cache.c D src/northbridge/intel/common/mrc_cache.h 4 files changed, 0 insertions(+), 329 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/23485/1 diff --git a/src/northbridge/intel/common/Kconfig b/src/northbridge/intel/common/Kconfig deleted file mode 100644 index 80593d6..0000000 --- a/src/northbridge/intel/common/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config NORTHBRIDGE_INTEL_COMMON_MRC_CACHE - def_bool n diff --git a/src/northbridge/intel/common/Makefile.inc b/src/northbridge/intel/common/Makefile.inc deleted file mode 100644 index 73427cb..0000000 --- a/src/northbridge/intel/common/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Alexander Couzens <lynxis(a)fe80.eu> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c -ramstage-$(CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE) += mrc_cache.c diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c deleted file mode 100644 index f692282..0000000 --- a/src/northbridge/intel/common/mrc_cache.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> -#include <cbfs.h> -#include <fmap.h> -#include <arch/acpi.h> -#include <ip_checksum.h> -#include <device/device.h> -#include <cbmem.h> -#include <spi-generic.h> -#include <spi_flash.h> -#include "mrc_cache.h" - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - -static struct mrc_data_container *next_mrc_block( - struct mrc_data_container *mrc_cache) -{ - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - u8 *region_ptr = (u8*)mrc_cache; - region_ptr += mrc_size; - return (struct mrc_data_container *)region_ptr; -} - -static int is_mrc_cache(struct mrc_data_container *mrc_cache) -{ - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); -} - -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ -static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) -{ - size_t region_size = 0; - *mrc_region_ptr = NULL; - - if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } - } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - } - return region_size; -} - -/* - * Find the largest index block in the MRC cache. Return NULL if non is - * found. - */ -static struct mrc_data_container *find_current_mrc_cache_local - (struct mrc_data_container *mrc_cache, u32 region_size) -{ - u32 region_end; - u32 entry_id = 0; - struct mrc_data_container *mrc_next = mrc_cache; - - region_end = (u32) mrc_cache + region_size; - - /* Search for the last filled entry in the region */ - while (is_mrc_cache(mrc_next)) { - entry_id++; - mrc_cache = mrc_next; - mrc_next = next_mrc_block(mrc_next); - if ((u32)mrc_next >= region_end) { - /* Stay in the MRC data region */ - break; - } - } - - if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__); - return NULL; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); - return NULL; - } - - printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); - - return mrc_cache; -} - -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ - -/* find the first empty block in the MRC cache area. - * If there's none, return NULL. - * - * @mrc_cache_base - base address of the MRC cache area - * @mrc_cache - current entry (for which we need to find next) - * @region_size - total size of the MRC cache area - */ -static struct mrc_data_container *find_next_mrc_cache - (struct mrc_data_container *mrc_cache_base, - struct mrc_data_container *mrc_cache, - u32 region_size) -{ - u32 region_end = (u32) mrc_cache_base + region_size; - - mrc_cache = next_mrc_block(mrc_cache); - if ((u32)mrc_cache >= region_end) { - /* Crossed the boundary */ - mrc_cache = NULL; - printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); - } else { - printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); - } - - return mrc_cache; -} - -static void update_mrc_cache(void *unused) -{ - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); - struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); - struct mrc_data_container *cache, *cache_base; - u32 cache_size; - int ret; - struct spi_flash flash; - - if (acpi_is_wakeup_s3()) - return; - - if (!current) { - printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); - return; - } - if (current->mrc_data_size == -1) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; - } - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - cache = find_current_mrc_cache_local(cache_base, cache_size); - - if (cache && (cache->mrc_data_size == current->mrc_data_size) && - (memcmp(cache, current, cache->mrc_data_size) == 0)) { - printk(BIOS_DEBUG, - "MRC data in flash is up to date. No update.\n"); - return; - } - - // 1. use spi_flash_probe() to find the flash, then - spi_init(); - if (spi_flash_probe(0, 0, &flash)) { - printk(BIOS_DEBUG, "Could not find SPI device\n"); - return; - } - - // 2. look up the first unused block - if (cache) - cache = find_next_mrc_cache(cache_base, cache, cache_size); - - /* - * 3. if no such place exists, erase entire mrc-cache range & use - * block 0. First time around the erase is not needed, but this is a - * small overhead for simpler code. - */ - if (!cache) { - printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); - - spi_flash_erase(&flash, to_flash_offset(&flash, cache_base), - cache_size); - - /* we will start at the beginning again */ - cache = cache_base; - } - // 4. write mrc data with flash->write() - printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); - ret = spi_flash_write(&flash, to_flash_offset(&flash, cache), - current->mrc_data_size + sizeof(*current), current); - - if (ret) - printk(BIOS_WARNING, "Writing the MRC cache failed with ret %d\n", - ret); - else - printk(BIOS_DEBUG, "Successfully wrote MRC cache\n"); -} - -/* Do it before chipset is locked during BS_POST_DEVICE. */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, update_mrc_cache, NULL); - -struct mrc_data_container *find_current_mrc_cache(void) -{ - struct mrc_data_container *cache_base; - u32 cache_size; - - cache_size = get_mrc_cache_region(&cache_base); - if (cache_base == NULL) { - printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); - return NULL; - } - - /* - * we need to: - */ - // 0. compare MRC data to last mrc-cache block (exit if same) - return find_current_mrc_cache_local(cache_base, cache_size); -} - -struct mrc_data_container * -store_current_mrc_cache(void *data, unsigned length) -{ - struct mrc_data_container *mrcdata; - int output_len = ALIGN(length, 16); - - /* Save the MRC S3 restore data to cbmem */ - mrcdata = cbmem_add - (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - if (!mrcdata) - return NULL; - - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - data, mrcdata, output_len); - - mrcdata->mrc_signature = MRC_DATA_SIGNATURE; - mrcdata->mrc_data_size = output_len; - mrcdata->reserved = 0; - memcpy(mrcdata->mrc_data, data, length); - - /* Zero the unused space in aligned buffer. */ - if (output_len > length) - memset(mrcdata->mrc_data+length, 0, output_len - length); - - mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); - - return mrcdata; -} diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h deleted file mode 100644 index 6f0dd6e..0000000 --- a/src/northbridge/intel/common/mrc_cache.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H -#define NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H - -#include <compiler.h> - -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __packed; - -struct mrc_data_container *find_current_mrc_cache(void); -struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length); - -#endif /* NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H */ -- To view, visit https://review.coreboot.org/23485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Gerrit-Change-Number: 23485 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/nehalem: Use the common mrc cache driver
by Arthur Heymans (Code Review) 29 Jan '18

29 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23484 Change subject: nb/intel/nehalem: Use the common mrc cache driver ...................................................................... nb/intel/nehalem: Use the common mrc cache driver The common mrc cache driver allows to save the raminit training results to a separate fmap region which is more manageable than a cbfsfile. Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/nehalem/raminit.c 3 files changed, 10 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/23484/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 4fdd2bd..5fac263 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -20,7 +20,7 @@ select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select ACPI_HUGE_LOWMEM_BACKUP select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index b5c19ff..acb828c 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -29,14 +29,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -$(obj)/mrc.cache: - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache - endif diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b7b445e..6eb36ef 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -43,7 +43,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #endif #if !REAL @@ -90,6 +90,8 @@ u8 largest; } timing_bounds_t[2][2][2][9]; +#define MRC_CACHE_VERSION 1 + struct ram_training { /* [TM][CHANNEL][SLOT][RANK][LANE] */ u16 lane_timings[4][2][2][2][9]; @@ -1740,17 +1742,18 @@ printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(&train, sizeof(train)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &train, sizeof(train)); } #if REAL static const struct ram_training *get_cached_training(void) { - struct mrc_data_container *cont; - cont = find_current_mrc_cache(); - if (!cont) + struct region_device rdev; + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &rdev)) return 0; - return (void *)cont->mrc_data; + return (void *)rdev_mmap_full(&rdev); } #endif -- To view, visit https://review.coreboot.org/23484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Gerrit-Change-Number: 23484 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: payload/tianocore: Fix patch to preserve coreboot table
by Arthur Heymans (Code Review) 29 Jan '18

29 Jan '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23483 ) Change subject: payload/tianocore: Fix patch to preserve coreboot table ...................................................................... Patch Set 1: Any idea why this works? -- To view, visit https://review.coreboot.org/23483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 Gerrit-Change-Number: 23483 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Jan 2018 08:16:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: payload/tianocore: Fix patch to preserve coreboot table
by build bot (Jenkins) (Code Review) 29 Jan '18

29 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23483 ) Change subject: payload/tianocore: Fix patch to preserve coreboot table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21309/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66701/ : SUCCESS -- To view, visit https://review.coreboot.org/23483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 Gerrit-Change-Number: 23483 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Jan 2018 06:32:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payload/tianocore: Fix patch to preserve coreboot table
by Matt DeVillier (Code Review) 29 Jan '18

29 Jan '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23483 Change subject: payload/tianocore: Fix patch to preserve coreboot table ...................................................................... payload/tianocore: Fix patch to preserve coreboot table Part of the original patch, commit 85a90e1, reverted edk2 commit: 1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED] which had the unintended effect of causing memory above 2GiB from being unavailable (marked reserved) when booting without a connected display (aka headles mode). This commit strips the patch to only the component needed to fix reading of the coreboot table low memory pointer. TEST: boot 4GB google/panther without connected display, verify memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m' Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch 1 file changed, 15 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/23483/1 diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch index 649c6ee..e75052b 100644 --- a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch +++ b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch @@ -1,4 +1,4 @@ -From 07742664925f8d055505220258f2589a9c73a80b Mon Sep 17 00:00:00 2001 +From ef89b11ce6f93c96fbd1753a8006dd9c3da212e0 Mon Sep 17 00:00:00 2001 From: ReddestDream <reddestdream(a)gmail.com> Date: Wed, 3 May 2017 00:13:28 -0400 Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being @@ -7,46 +7,20 @@ Exclude the bottom 4kb from being included in System Memory HoB diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -index 262e6b9d7d..da8f060783 100755 +index 262e6b9..d3c5723 100755 --- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c +++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c -@@ -246,23 +246,20 @@ CbPeiEntryPoint ( - UINTN PmGpeEnBase; - CB_MEM_INFO CbMemInfo; - -- // -- // Report lower 640KB of RAM. Attribute EFI_RESOURCE_ATTRIBUTE_TESTED -- // is intentionally omitted to prevent erasing of the coreboot header -- // record before it is processed by CbParseMemoryInfo. -- // - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | -+ EFI_RESOURCE_ATTRIBUTE_TESTED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ), -- (EFI_PHYSICAL_ADDRESS)(0), -- (UINT64)(0xA0000) -+ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides -+ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000), -+ (UINT64)(0xA0000 - 0x1000) - ); - - -@@ -309,7 +306,7 @@ CbPeiEntryPoint ( - // Set cache on the physical memory - // - MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack); -- MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack); -+ MtrrSetMemoryAttribute ((0 + 0x1000), (0xA0000 - 0x1000), CacheWriteBack); - - // - // Create Memory Type Information HOB --- -2.14.0 +@@ -261,8 +261,9 @@ CbPeiEntryPoint ( + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), +- (EFI_PHYSICAL_ADDRESS)(0), +- (UINT64)(0xA0000) ++ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides ++ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000), ++ (UINT64)(0xA0000 - 0x1000) + ); + +-- +2.14.0 -- To view, visit https://review.coreboot.org/23483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 Gerrit-Change-Number: 23483 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: util/docker/coreboot-sdk: Add libftdi1-dev
by build bot (Jenkins) (Code Review) 29 Jan '18

29 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23482 ) Change subject: util/docker/coreboot-sdk: Add libftdi1-dev ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21308/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66700/ : SUCCESS -- To view, visit https://review.coreboot.org/23482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698 Gerrit-Change-Number: 23482 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 23:21:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/docker/coreboot-sdk: Add libftdi1-dev
by Martin Roth (Code Review) 29 Jan '18

29 Jan '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/23482 Change subject: util/docker/coreboot-sdk: Add libftdi1-dev ...................................................................... util/docker/coreboot-sdk: Add libftdi1-dev chromeec uses libftdi1-dev, so add it to the image. Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/23482/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index a954444..9ea8a66 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -37,6 +37,7 @@ libelf-dev \ libfreetype6-dev \ libftdi-dev \ + libftdi1-dev \ libglib2.0-dev \ libgmp-dev \ libgmp-dev \ -- To view, visit https://review.coreboot.org/23482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698 Gerrit-Change-Number: 23482 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: amd/agesa/family14, 15 & 16: Remove unnecessary whitespace
by build bot (Jenkins) (Code Review) 28 Jan '18

28 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23481 ) Change subject: amd/agesa/family14,15 & 16: Remove unnecessary whitespace ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21307/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66699/ : SUCCESS -- To view, visit https://review.coreboot.org/23481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933 Gerrit-Change-Number: 23481 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 28 Jan 2018 21:47:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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