coreboot-gerrit January 2018

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Change in coreboot[master]: sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMU
by Arthur Heymans (Code Review) 04 Jan '18

04 Jan '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23090 Change subject: sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMU ...................................................................... sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMU The Qemu q35 target doesn't support or needs Intel Firmware blobs so it doesn't make sense to select that option on this hardware. The result of this change will be that when changing the ROM chip size, CBFS_SIZE will automatically fill the whole flash which is desirable in this case. Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801ix/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/23090/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 6879bce..fcf2eb5 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -25,7 +25,7 @@ select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_GPIO - select HAVE_INTEL_FIRMWARE + select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35 if SOUTHBRIDGE_INTEL_I82801IX -- To view, visit https://review.coreboot.org/23090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa Gerrit-Change-Number: 23090 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mainboard/hp: Add Elitebook Revolve 810 G1
by build bot (Jenkins) (Code Review) 04 Jan '18

04 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Elitebook Revolve 810 G1 ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19995/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65262/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 12 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 13:37:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout
by build bot (Jenkins) (Code Review) 04 Jan '18

04 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22997 ) Change subject: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19994/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65261/ : SUCCESS -- To view, visit https://review.coreboot.org/22997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Gerrit-Change-Number: 22997 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 13:03:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Reduce storage size
by Arthur Heymans (Code Review) 04 Jan '18

04 Jan '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23088 ) Change subject: nb/intel/sandybridge: Reduce storage size ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/23088/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/23088/1/src/northbridge/intel/sandybridge/r… PS1, Line 2106: MIN(MAX(timC, 0), MAX_TIMC); I haven't check what exactly this function is supposed to do but wouldn't you want a warning on overflows? -- To view, visit https://review.coreboot.org/23088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f Gerrit-Change-Number: 23088 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 11:50:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add workaround for timC
by Arthur Heymans (Code Review) 04 Jan '18

04 Jan '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23087 ) Change subject: nb/intel/sandybridge/raminit: Add workaround for timC ...................................................................... Patch Set 1: Is this something that ought to be constant for one board? -- To view, visit https://review.coreboot.org/23087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I535ea4e320c4572bfae55ce1d0f2c1723e9c54d6 Gerrit-Change-Number: 23087 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 11:46:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/sandybridge: Reduce storage size
by build bot (Jenkins) (Code Review) 04 Jan '18

04 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23088 ) Change subject: nb/intel/sandybridge: Reduce storage size ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19993/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65260/ : SUCCESS -- To view, visit https://review.coreboot.org/23088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f Gerrit-Change-Number: 23088 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 11:36:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Reduce storage size
by Patrick Rudolph (Code Review) 04 Jan '18

04 Jan '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23088 Change subject: nb/intel/sandybridge: Reduce storage size ...................................................................... nb/intel/sandybridge: Reduce storage size * Reduce storage size of raminit structure (and mrc cache). * Get rid of function dram_dimm_mapping as everything can be calculated from existing information. * Add checks to make sure the unsigned raminit timings doesn't overflow. Tested on Lenovo T430. Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c 5 files changed, 21 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/23088/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 12384b4..9f84010 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -68,7 +68,6 @@ memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); ctrl->channel_size_mb[channel] = 0; ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } @@ -271,7 +270,7 @@ } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { - const int ref_card_offset_table[6][6] = { + const u8 ref_card_offset_table[6][6] = { { 0, 0, 0, 0, 2, 2, }, { 0, 0, 0, 0, 2, 2, }, { 0, 0, 0, 0, 2, 2, }, diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..7f53c41 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -293,13 +293,13 @@ } } -void dram_dimm_mapping(ramctr_timing *ctrl) +void dram_dimm_set_mapping(const ramctr_timing *ctrl) { int channel; - dimm_info *info = &ctrl->info; + const dimm_info *info = &ctrl->info; FOR_ALL_CHANNELS { - dimm_attr *dimmA, *dimmB; + const dimm_attr *dimmA, *dimmB; u32 reg = 0; if (info->dimm[channel][0].size_mb >= @@ -330,21 +330,13 @@ if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { - ctrl->mad_dimm[channel] = reg; + MCHBAR32(0x5004 + channel * 4) = reg; } else { - ctrl->mad_dimm[channel] = 0; + MCHBAR32(0x5004 + channel * 4) = 0; } } } -void dram_dimm_set_mapping(ramctr_timing * ctrl) -{ - int channel; - FOR_ALL_CHANNELS { - MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel]; - } -} - void dram_zones(ramctr_timing * ctrl, int training) { u32 reg, ch0size, ch1size; @@ -2109,8 +2101,9 @@ for (timC_delta = -5; timC_delta <= 5; timC_delta++) { FOR_ALL_LANES { + const int timC = saved_rt.lanes[lane].timC + timC_delta; ctrl->timings[channel][slotrank].lanes[lane].timC = - saved_rt.lanes[lane].timC + timC_delta; + MIN(MAX(timC, 0), MAX_TIMC); } program_timings(ctrl, channel); FOR_ALL_LANES { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ab6e592..ede0414 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -57,7 +57,7 @@ /* Register 4028. One nibble per slotrank. */ u8 val_4028; - int val_320c; + int16_t val_320c; struct ram_lane_timings { /* lane register offset 0x10. */ @@ -66,7 +66,7 @@ u8 falling; /* bits 20 - 26. */ /* lane register offset 0x20. */ - int timC; /* bit 0 - 5, 19. */ + u16 timC; /* bit 0 - 5, 19. */ u16 timB; /* bits 8 - 13, 15 - 17. */ } lanes[NUM_LANES]; }; @@ -111,21 +111,20 @@ u16 reg_5064b0; /* bits 0-11. */ u8 rankmap[NUM_CHANNELS]; - int ref_card_offset[NUM_CHANNELS]; - u32 mad_dimm[NUM_CHANNELS]; - int channel_size_mb[NUM_CHANNELS]; - u32 cmd_stretch[NUM_CHANNELS]; + u8 ref_card_offset[NUM_CHANNELS]; + u16 channel_size_mb[NUM_CHANNELS]; + u8 cmd_stretch[NUM_CHANNELS]; - int reg_c14_offset; - int reg_320c_range_threshold; + int16_t reg_c14_offset; + u8 reg_320c_range_threshold; - int edge_offset[3]; - int timC_offset[3]; + u8 edge_offset[3]; + u8 timC_offset[3]; - int extended_temperature_range; - int auto_self_refresh; + u8 extended_temperature_range; + u8 auto_self_refresh; - int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; + u8 rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; @@ -157,8 +156,7 @@ void dram_find_common_params(ramctr_timing *ctrl); void dram_xover(ramctr_timing * ctrl); void dram_timing_regs(ramctr_timing * ctrl); -void dram_dimm_mapping(ramctr_timing *ctrl); -void dram_dimm_set_mapping(ramctr_timing * ctrl); +void dram_dimm_set_mapping(const ramctr_timing *ctrl); void dram_zones(ramctr_timing * ctrl, int training); unsigned int get_mem_min_tck(void); void dram_memorymap(ramctr_timing * ctrl, int me_uma_size); diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 675ac71..a94a825 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -642,8 +642,6 @@ if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); - - dram_dimm_mapping(ctrl); } /* Set MCU frequency */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 3acc563..289fb76 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -412,8 +412,6 @@ if (!fast_boot) { /* Find fastest common supported parameters */ dram_find_common_params(ctrl); - - dram_dimm_mapping(ctrl); } /* Set MCU frequency */ -- To view, visit https://review.coreboot.org/23088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3bb026fb1bd81b66f8a5be333760990d924071f Gerrit-Change-Number: 23088 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add workaround for timC
by build bot (Jenkins) (Code Review) 04 Jan '18

04 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23087 ) Change subject: nb/intel/sandybridge/raminit: Add workaround for timC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19992/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65259/ : SUCCESS -- To view, visit https://review.coreboot.org/23087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I535ea4e320c4572bfae55ce1d0f2c1723e9c54d6 Gerrit-Change-Number: 23087 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 11:23:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drvs/lenovo/h8: Morse death message
by build bot (Jenkins) (Code Review) 04 Jan '18

04 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23072 ) Change subject: drvs/lenovo/h8: Morse death message ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19991/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65258/ : SUCCESS -- To view, visit https://review.coreboot.org/23072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iccf6a43a28d0eb515051b5be0a0f23d40e82c2d2 Gerrit-Change-Number: 23072 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Jan 2018 11:18:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add workaround for timC
by Patrick Rudolph (Code Review) 04 Jan '18

04 Jan '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23087 Change subject: nb/intel/sandybridge/raminit: Add workaround for timC ...................................................................... nb/intel/sandybridge/raminit: Add workaround for timC The initial phase between CMD and CLK can be calculated if the board does follow the design guidelines. Some do not and may have a different phase. As we don't know we have to test. Add a loop that changes the initial phase in quarter steps to fix the issue "timC discovery failed". The additional loop is only taken on failed timC discovery and should have no influence on working boards. Tested on Lenovo T430. Needs test on affected hardware. Change-Id: I535ea4e320c4572bfae55ce1d0f2c1723e9c54d6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23087/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..0d84cd6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2076,11 +2076,32 @@ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timC(ctrl, channel, slotrank); - if (err) - return err; - } + do { + FOR_ALL_CHANNELS { + FOR_ALL_POPULATED_RANKS { + err = discover_timC(ctrl, channel, slotrank); + if (err) + break; + } + if (err) + break; + } + + if (err) { + /* + * This path is rarely taken and a result of ignorance. + * In case the board doesn't follow design guidelines, + * the calculated value of reg_c14_offset doesn't work. + * As it only affects a very small amount of boards and + * the real value is discovered in a later step, just + * try to find a "good" one for now. + * Increment CLK/CMD phase offset by one quarter. + */ + ctrl->reg_c14_offset += 128 / 4; + } + } while (err && ctrl->reg_c14_offset < 128); + if (err) + return err; FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); -- To view, visit https://review.coreboot.org/23087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I535ea4e320c4572bfae55ce1d0f2c1723e9c54d6 Gerrit-Change-Number: 23087 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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coreboot-gerrit January 2018