coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode
by build bot (Jenkins) (Code Review) 16 Sep '17

16 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21466 ) Change subject: sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15762/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60555/ : SUCCESS -- To view, visit https://review.coreboot.org/21466 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Gerrit-Change-Number: 21466 Gerrit-PatchSet: 12 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Sep 2017 01:19:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add northbridge definitions
by Marshall Dawson (Code Review) 16 Sep '17

16 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21562 Change subject: amd/stoneyridge: Add northbridge definitions ...................................................................... amd/stoneyridge: Add northbridge definitions Begin adding D18F1 definitions to northbridge.h. Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/21562/1 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 13d7d36..5984637 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -20,6 +20,11 @@ #include <arch/io.h> #include <device/device.h> +/* D18F1 - Address Map Registers */ +#define D18F1_DRAM_HOLE 0xf0 +# define DRAM_HOIST_VALID (1 << 1) +# define DRAM_HOLE_VALID (1 << 0) + void cpu_bus_scan(device_t dev); void domain_enable_resources(device_t dev); void domain_read_resources(device_t dev); -- To view, visit https://review.coreboot.org/21562 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958 Gerrit-Change-Number: 21562 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block: Add pci device id for CNL-Y
by build bot (Jenkins) (Code Review) 16 Sep '17

16 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21561 ) Change subject: soc/intel/common/block: Add pci device id for CNL-Y ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15761/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60554/ : SUCCESS -- To view, visit https://review.coreboot.org/21561 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Gerrit-Change-Number: 21561 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Sep 2017 00:37:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add pci device id for CNL-Y
by Bora Guvendik (Code Review) 16 Sep '17

16 Sep '17

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/21561 Change subject: soc/intel/common/block: Add pci device id for CNL-Y ...................................................................... soc/intel/common/block: Add pci device id for CNL-Y Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/lpc/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/21561/1 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 1c4e2ce..2bd9d07 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -113,6 +113,7 @@ PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_APL_LPC, PCI_DEVICE_ID_INTEL_GLK_LPC, + PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, 0 }; -- To view, visit https://review.coreboot.org/21561 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Gerrit-Change-Number: 21561 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: mb/google/{poppy, soraka}: Enable LTR for Root port
by build bot (Jenkins) (Code Review) 15 Sep '17

15 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21548 ) Change subject: mb/google/{poppy,soraka}: Enable LTR for Root port ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60537/ : SUCCESS -- To view, visit https://review.coreboot.org/21548 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Gerrit-Change-Number: 21548 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Sep 2017 23:21:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/{poppy, soraka}: Enable LTR for Root port
by build bot (Jenkins) (Code Review) 15 Sep '17

15 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21548 ) Change subject: mb/google/{poppy,soraka}: Enable LTR for Root port ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/15742/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/60536/ : ABORTED -- To view, visit https://review.coreboot.org/21548 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Gerrit-Change-Number: 21548 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Sep 2017 23:13:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add config for enabling LTR for PCIe Root port
by build bot (Jenkins) (Code Review) 15 Sep '17

15 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21547 ) Change subject: soc/intel/skylake: Add config for enabling LTR for PCIe Root port ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15716/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60512/ : SUCCESS -- To view, visit https://review.coreboot.org/21547 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a Gerrit-Change-Number: 21547 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Sep 2017 21:30:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/gogle/poppy/*: Enable LTR for Root port 0
by build bot (Jenkins) (Code Review) 15 Sep '17

15 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21548 ) Change subject: mb/gogle/poppy/*: Enable LTR for Root port 0 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60513/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15717/ : SUCCESS -- To view, visit https://review.coreboot.org/21548 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Gerrit-Change-Number: 21548 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 15 Sep 2017 21:25:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/gogle/poppy/*: Enable LTR for Root port 0
by Rizwan Qureshi (Code Review) 15 Sep '17

15 Sep '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21548 Change subject: mb/gogle/poppy/*: Enable LTR for Root port 0 ...................................................................... mb/gogle/poppy/*: Enable LTR for Root port 0 Enable LTR for Root port 0, where wifi card is connected. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21548/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0bd2efc..d4d7c2e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -154,6 +154,8 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register PcieRpAdvancedErrorReporting[0] = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register PcieRpLtrEnable[0] = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ee9c5b7..cac618c 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -154,6 +154,8 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register PcieRpAdvancedErrorReporting[0] = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register PcieRpLtrEnable[0] = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port -- To view, visit https://review.coreboot.org/21548 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Gerrit-Change-Number: 21548 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add config for enabling LTR for PCIe Root port
by Rizwan Qureshi (Code Review) 15 Sep '17

15 Sep '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21547 Change subject: soc/intel/skylake: Add config for enabling LTR for PCIe Root port ...................................................................... soc/intel/skylake: Add config for enabling LTR for PCIe Root port There are a lot errors reported by AER driver for root port 0. The erors are being caused by an unsupported request from the device to the upstream port. Enabling LTR on the root port stops these errors, it is because LTR is enabled on the device side but not on the root port and hence root port was logging the LTR messages from the device as unsupported. The PCIe base spec (v3.1a) section 6.18 also states that: LTR support is discovered and enabled through reporting and control registers described in Chapter 7. Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR. Note that it is not required that all Endpoints support LTR to permit enabling LTR in those Endpoints that do support it. When enabling the LTR mechanism in a hierarchy, devices closest to the Root Port must be enabled first. If an LTR Message is received at a Downstream Port that does not support LTR or if LTR is not enabled, the Message must be treated as an Unsupported Request. FSP has a UPD for enabling/disabling LTR on root port, use the same for configuring LTR on PCIe root ports. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21547/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 45f3f99..606078b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -169,12 +169,45 @@ /* DCI Enable/Disable */ u8 PchDciEn; - /* Pcie Root Ports */ + /* + * Pcie Root Port configuration: + * each element of array corresponds to + * respective PCIe root port. + */ + + /* + * Enable/Disable Root Port + * 0: Disable Root Port + * 1: Enable Root Port + */ u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + + /* + * Enable/Disable Clk-req support for Root Port + * 0: Disable Clk-Req + * 1: Enable Clk-req + */ u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; + + /* + * Clk-req source for Root Port + */ u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + + /* + * Enable/Disable AER (Advanced Error Reporting) for Root Port + * 0: Disable AER + * 1: Enable AER + */ u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + /* + * Enable/Disable Latency Tolerance Reporting for Root Port + * 0: Disable LTR + * 1: Enable LTR + */ + u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index adf8772..b1697ae 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -169,6 +169,8 @@ memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, + sizeof(params->PcieRpLtrEnable)); /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- To view, visit https://review.coreboot.org/21547 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a Gerrit-Change-Number: 21547 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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coreboot-gerrit September 2017