coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/common: Add function to get soc reserved memory size
by build bot (Jenkins) (Code Review) 14 Sep '17

14 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21539 ) Change subject: soc/intel/common: Add function to get soc reserved memory size ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/15657/ : ABORTED -- To view, visit https://review.coreboot.org/21539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242 Gerrit-Change-Number: 21539 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Sep 2017 12:38:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Use EBDA area to store cbmem_top address
by build bot (Jenkins) (Code Review) 14 Sep '17

14 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21424 ) Change subject: soc/intel/skylake: Use EBDA area to store cbmem_top address ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60442/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15654/ : SUCCESS -- To view, visit https://review.coreboot.org/21424 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398 Gerrit-Change-Number: 21424 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 14 Sep 2017 12:33:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Calculate soc reserved memory size
by Subrata Banik (Code Review) 14 Sep '17

14 Sep '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21540 Change subject: soc/intel/skylake: Calculate soc reserved memory size ...................................................................... soc/intel/skylake: Calculate soc reserved memory size Read EBDA area to get intel various reserved memory (PRMRR, TraceHub, PTT etc) size which generates during romstage memory calculation. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of intel soc reserved ranges. Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/systemagent.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/21540/1 diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 6149fa2..f2948ab 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> +#include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -62,3 +63,20 @@ mdelay(1); set_power_limits(28); } + +/* + * SoC implementation + * + * SoC call to summarize all Intel Reserve MMIO size and report to SA + */ +size_t soc_reversed_mmio_size(void) +{ + ebda_config *cfg = NULL; + + if (!is_ebda_initialized(cfg)) + return 0; + + cfg = (ebda_config *)read_ebda_data(sizeof(ebda_config)); + + return cfg->prmrr_size + cfg->tracehub_size + cfg->ptt_size; +} -- To view, visit https://review.coreboot.org/21540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec Gerrit-Change-Number: 21540 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add function to get soc reserved memory size
by Subrata Banik (Code Review) 14 Sep '17

14 Sep '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21539 Change subject: soc/intel/common: Add function to get soc reserved memory size ...................................................................... soc/intel/common: Add function to get soc reserved memory size This patch ensures to consider soc reserved memory size while allocating DRAM based resources. Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21539/1 diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 4ca19e6..f6b9a0b 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -99,5 +99,7 @@ * struct sa_mmio_descriptor along with resource count. */ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); +/* SoC call to summarize all Intel Reserve MMIO size and report to SA */ +size_t soc_reversed_mmio_size(void); #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index cb7af41..23e7984 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -36,6 +36,11 @@ /* no-op */ } +__attribute__((weak)) size_t soc_reversed_mmio_size(void) +{ + return 0; +} + /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. @@ -134,12 +139,16 @@ { uintptr_t base_k, touud_k; size_t dpr_size = 0, size_k; + size_t reserved_mmio_size; uint64_t sa_map_values[MAX_MAP_ENTRIES]; uintptr_t top_of_ram; int index = *resource_count; if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) dpr_size = sa_get_dpr_size(); + + /* Get SoC reserve memory size as per user selection */ + reserved_mmio_size = soc_reversed_mmio_size(); top_of_ram = (uintptr_t)cbmem_top(); @@ -155,13 +164,14 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> TSEG - DPR */ + /* top_of_ram -> TSEG - DPR - Intel Reserve Memory SIze*/ base_k = top_of_ram; - size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k; + size_k = sa_map_values[SA_TSEG_REG] - dpr_size - base_k + - reserved_mmio_size; mmio_resource(dev, index++, base_k / KiB, size_k / KiB); - /* TSEG - DPR -> BGSM */ - base_k = sa_map_values[SA_TSEG_REG] - dpr_size; + /* TSEG - DPR - Intel Reserve Memory SIze -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG] - dpr_size - reserved_mmio_size; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/21539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242 Gerrit-Change-Number: 21539 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add intel common EBDA support
by Subrata Banik (Code Review) 14 Sep '17

14 Sep '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21538 Change subject: soc/intel/common: Add intel common EBDA support ...................................................................... soc/intel/common: Add intel common EBDA support This patch provides EBDA library for soc usage. Change-Id: I8355a1dd528b111f1391e6d28a9b174edddc9ca0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/ebda/Kconfig A src/soc/intel/common/block/ebda/Makefile.inc A src/soc/intel/common/block/ebda/ebda.c A src/soc/intel/common/block/include/intelblocks/ebda.h 4 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/21538/1 diff --git a/src/soc/intel/common/block/ebda/Kconfig b/src/soc/intel/common/block/ebda/Kconfig new file mode 100644 index 0000000..67c7b48 --- /dev/null +++ b/src/soc/intel/common/block/ebda/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_EBDA + bool + select EARLY_EBDA_INIT + help + Intel Processor common EBDA library support diff --git a/src/soc/intel/common/block/ebda/Makefile.inc b/src/soc/intel/common/block/ebda/Makefile.inc new file mode 100644 index 0000000..beeba51 --- /dev/null +++ b/src/soc/intel/common/block/ebda/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA) += ebda.c diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c new file mode 100644 index 0000000..f8058b8 --- /dev/null +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/ebda.h> + +/* + * Mainboard Override function + * + * Mainboard directory may implement below functionality for romstage. + */ + +/* Fill up EBDA structure inside Mainboard directory */ +__attribute__((weak)) void create_mainboard_ebda(ebda_config *cfg) +{ + /* no-op */ +} + +/* + * SoC overrides + * + * All new SoC must implement below functionality for romstage. + */ +__attribute__((weak)) void fill_soc_memmap_ebda(ebda_config *cfg) +{ + /* no-op */ +} + +bool is_ebda_initialized(ebda_config *cfg) +{ + cfg = (ebda_config *)read_ebda_data(sizeof(ebda_config)); + + if (cfg->signature == EBDA_SIGNATURE) + return true; + + return false; +} + +static void create_soc_ebda(ebda_config *cfg) +{ + /* Create EBDA header */ + cfg->signature = EBDA_SIGNATURE; + /* Fill up memory layout information */ + fill_soc_memmap_ebda(cfg); +} + +void fill_ebda_area(void) +{ + ebda_config *cfg = NULL; + + /* If EBDA area is already initialized then return */ + if (is_ebda_initialized(cfg)) + return; + + /* Initialize EBDA area early during romstage. */ + setup_default_ebda(); + create_soc_ebda(cfg); + create_mainboard_ebda(cfg); + write_ebda_data(cfg, sizeof(ebda_config)); +} diff --git a/src/soc/intel/common/block/include/intelblocks/ebda.h b/src/soc/intel/common/block/include/intelblocks/ebda.h new file mode 100644 index 0000000..ccb968a --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/ebda.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_EBDA_H +#define SOC_INTEL_COMMON_BLOCK_EBDA_H + +#include <arch/ebda.h> +#include <compiler.h> +#include <soc/ebda.h> + +#define EBDA_SIGNATURE 0xebda + +/* API to check if EBDA area already initialized */ +bool is_ebda_initialized(ebda_config *cfg); + +/* + * Mainboard Override function + * + * Mainboard directory may implement below functionality for romstage. + */ + +/* Fill up EBDA structure inside Mainboard directory */ +void create_mainboard_ebda(ebda_config *cfg); + +/* + * SoC overrides + * + * All new SoC must implement below functionality for romstage. + */ +void fill_soc_memmap_ebda(ebda_config *cfg); + +/* + * API to perform below operation + * 1. Initialize EBDA area + * 2. Fill up EBDA structure inside SOC directory + * 3. Fill up EBDA structure inside Mainboard directory + * 4. Store EBDA structure into EBDA area + */ +void fill_ebda_area(void); + +/* + * EBDA structure + * + * SOC should implement EBDA structure as per need + * as below. + * + * Note: First 4 bytes should be reserved for signature as + * 0xEBDA + * + * typedef struct { + * uint32_t signature; + * <Required variables..> + * }__packed ebda_config; + * + */ + +#endif -- To view, visit https://review.coreboot.org/21538 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8355a1dd528b111f1391e6d28a9b174edddc9ca0 Gerrit-Change-Number: 21538 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Store Memory Layout information into CAR
by Subrata Banik (Code Review) 14 Sep '17

14 Sep '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21537 Change subject: soc/intel/skylake: Store Memory Layout information into CAR ...................................................................... soc/intel/skylake: Store Memory Layout information into CAR This patch stores non-generic memory layout information (i.e. PRMRR, TraceHub, PTT etc) into CAR for EBDA common code usage. Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/memmap.c 1 file changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/21537/1 diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 6c64073..628421a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <arch/io.h> #include <cbmem.h> #include <chip.h> @@ -26,6 +27,31 @@ #include <soc/smm.h> #include <soc/systemagent.h> #include <stdlib.h> + +struct soc_memory_info { + uint32_t cbmem_top; + uint32_t prmrr_size; + uint32_t tracehub_size; + uint32_t ptt_size; +} __packed; + +static struct soc_memory_info memory_info CAR_GLOBAL; + +static struct soc_memory_info *get_memory_ptr(void) +{ + return car_get_var_ptr(&memory_info); +} + +static void set_memory_info(uint32_t cbtop, uint32_t prmrr_size, + uint32_t tracehub_size, uint32_t ptt_size) +{ + struct soc_memory_info *mi = get_memory_ptr(); + + mi->cbmem_top = cbtop; + mi->prmrr_size = prmrr_size; + mi->tracehub_size = tracehub_size; + mi->ptt_size = ptt_size; +} size_t mmap_region_granularity(void) { @@ -139,7 +165,9 @@ const struct device *dev; uint32_t dram_base; uint32_t prmrr_base; + uint32_t tracehub_base; size_t prmrr_size; + size_t tracehub_size = 0; dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) @@ -177,13 +205,18 @@ die("PRMRR Sizes that are > 1MB and < 32MB are not" "supported!\n"); - prmrr_base = dram_base - prmrr_size; + prmrr_base = dram_base; + dram_base -= prmrr_size; if (prmrr_size >= 32*MiB) - prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); - dram_base = prmrr_base; + dram_base = ALIGN_DOWN(dram_base, 128*MiB); + + /* PRMRR Area Size */ + prmrr_size = prmrr_base - dram_base; } if (config->ProbelessTrace) { + tracehub_base = dram_base; + /* GDXC MOT */ dram_base -= GDXC_MOT_MEMORY_SIZE; /* Round down to natual boundary accroding to PSMI size */ @@ -192,11 +225,17 @@ dram_base -= GDXC_IOT_MEMORY_SIZE; /* PSMI buffer area */ dram_base -= PSMI_BUFFER_AREA_SIZE; + + /* TraceHub Area Size */ + tracehub_size = tracehub_base - dram_base; } if (is_ptt_enable()) dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */ + set_memory_info(dram_base, prmrr_size, tracehub_size, + is_ptt_enable() ? 4*KiB : 0); + return dram_base; } -- To view, visit https://review.coreboot.org/21537 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f Gerrit-Change-Number: 21537 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: arch/x86: Add ebda read/write functions into EBDA library
by Subrata Banik (Code Review) 14 Sep '17

14 Sep '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21536 Change subject: arch/x86: Add ebda read/write functions into EBDA library ...................................................................... arch/x86: Add ebda read/write functions into EBDA library This patch provides new APIs to write into EBDA area and read from EBDA area based on user input structure. Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/ebda.c M src/arch/x86/include/arch/ebda.h 2 files changed, 67 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21536/1 diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index c828aa4..61db30e 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -20,6 +20,58 @@ #include <arch/ebda.h> #include <arch/acpi.h> #include <commonlib/endian.h> +#include <console/console.h> + +static void *get_ebda_start(void) +{ + return (void *)((uintptr_t)DEFAULT_EBDA_SEGMENT << 4); +} + +/* + * EBDA area is representing a 1KB memory area just below + * the top of conventional memory (below 1MB) + */ + +/* + * write_ebda_data is a wrapper function to write into EBDA area + * in DWORD mode. + * + * data = data to be written into EBDA area + * length = input data size in bytes + */ +void write_ebda_data(void *data, size_t length) +{ + void *ebda; + int count = 0; + + if (length > DEFAULT_EBDA_SIZE) + die("Input data width is more than EBDA size!"); + + ebda = get_ebda_start(); + + while (count < length) { + write_le32(ebda, *((uint32_t *)(data + count))); + count += sizeof(uint32_t); + ebda += sizeof(uint32_t); + } +} + +/* + * read_ebda_data is a wrapper function to read from EBDA area + * + * return data read from EBDA area + */ +void *read_ebda_data(size_t length) +{ + void *ebda; + static void *data; + + ebda = get_ebda_start(); + + memcpy(data, ebda, length); + + return data; +} void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size) { @@ -36,7 +88,7 @@ low_memory_kb = low_memory_size >> 10; ebda_kb = ebda_size >> 10; - ebda = (void *)((uintptr_t)ebda_segment << 4); + ebda = get_ebda_start(); /* clear BIOS DATA AREA */ zero_n(X86_BDA_BASE, X86_BDA_SIZE); diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h index 428bc92..7e2e4fa 100644 --- a/src/arch/x86/include/arch/ebda.h +++ b/src/arch/x86/include/arch/ebda.h @@ -31,5 +31,19 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size); void setup_default_ebda(void); +/* + * write_ebda_data is a wrapper function to write into EBDA area + * in DWORD mode. + * + * data = data to be written into EBDA area + * length = input data size in bytes + */ +void write_ebda_data(void *data, size_t length); +/* + * read_ebda_data is a wrapper function to read from EBDA area + * + * return data read from EBDA area + */ +void *read_ebda_data(size_t length); #endif -- To view, visit https://review.coreboot.org/21536 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4 Gerrit-Change-Number: 21536 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/google/poppy: Modify the HID for VCM device
by build bot (Jenkins) (Code Review) 14 Sep '17

14 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21535 ) Change subject: mb/google/poppy: Modify the HID for VCM device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15651/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60440/ : SUCCESS -- To view, visit https://review.coreboot.org/21535 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9802e54838b74ba3c580fb68ad6843db974b348c Gerrit-Change-Number: 21535 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Sep 2017 10:53:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Add device tree support for VCM device
by build bot (Jenkins) (Code Review) 14 Sep '17

14 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21508 ) Change subject: mb/google/poppy: Add device tree support for VCM device ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15650/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60439/ : SUCCESS -- To view, visit https://review.coreboot.org/21508 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6 Gerrit-Change-Number: 21508 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Sep 2017 10:45:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Modify the HID for VCM device
by V Sowmya (Code Review) 14 Sep '17

14 Sep '17

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/21535 Change subject: mb/google/poppy: Modify the HID for VCM device ...................................................................... mb/google/poppy: Modify the HID for VCM device Modify the HID to align with ACPI specification. BUG=b:65423422 BRANCH=none CQ-DEPEND=CL:654383 TEST=Build and boot soraka. Verified that the VCM device probe is successful. Change-Id: I9802e54838b74ba3c580fb68ad6843db974b348c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/poppy/acpi/mipi_camera.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21535/1 diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl index 135b4e6..f6a9ea3 100644 --- a/src/mainboard/google/poppy/acpi/mipi_camera.asl +++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl @@ -703,7 +703,7 @@ Device (VCM0) { - Name (_HID, "DWDWD000") /* _HID: Hardware ID */ + Name (_HID, "PRP0001") /* _HID: Hardware ID */ Name (_UID, Zero) /* _UID: Unique ID */ Name (_DDN, "Dongwoon AF DAC") /* _DDN: DOS Device Name */ Name (CAMD, 0x03) -- To view, visit https://review.coreboot.org/21535 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9802e54838b74ba3c580fb68ad6843db974b348c Gerrit-Change-Number: 21535 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>

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coreboot-gerrit September 2017