coreboot-gerrit May 2017

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Change in coreboot[master]: soc/marvell/armada38x: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19774 ) Change subject: soc/marvell/armada38x: Move spi driver to use spi_bus_map ...................................................................... soc/marvell/armada38x: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I795ecd825d03a3a915222da5e920bfd581567d5f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/marvell/armada38x/spi.c 1 file changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/19774/1 diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c index 47631f4..f7d1714 100644 --- a/src/soc/marvell/armada38x/spi.c +++ b/src/soc/marvell/armada38x/spi.c @@ -471,18 +471,26 @@ return ret; } +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED); + return 0; +} + static const spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = &spi_ctrlr; - mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED); - return 0; -} +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 1, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19774 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I795ecd825d03a3a915222da5e920bfd581567d5f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/broadcom/cygnus: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19773 ) Change subject: soc/broadcom/cygnus: Move spi driver to use spi_bus_map ...................................................................... soc/broadcom/cygnus: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I48b242dd6226e392ed0f403051843b3ae02cd9a4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/broadcom/cygnus/spi.c 1 file changed, 20 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/19773/1 diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index fde21ba..37d7c2a 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -275,22 +275,10 @@ return 0; } -static const struct spi_ctrlr spi_ctrlr = { - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, - .max_xfer_size = 65535, -}; - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +static int spi_ctrlr_setup(const struct spi_slave *slave) { struct qspi_priv *priv = &qspi_slave; unsigned int spbr; - - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = &spi_ctrlr; priv->max_hz = QSPI_MAX_HZ; priv->spi_mode = QSPI_MODE; @@ -319,3 +307,22 @@ return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19773 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I48b242dd6226e392ed0f403051843b3ae02cd9a4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/imgtec/pistachio: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19772 ) Change subject: soc/imgtec/pistachio: Move spi driver to use spi_bus_map ...................................................................... soc/imgtec/pistachio: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: Ie4ec74fccaf25900537ccd5c146bb0a333a2754c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/imgtec/pistachio/spi.c 1 file changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/19772/1 diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 30e14fa..bfd982c 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -533,22 +533,13 @@ return SPIM_OK; } -static const struct spi_ctrlr spi_ctrlr = { - .claim_bus = spi_ctrlr_claim_bus, - .release_bus = spi_ctrlr_release_bus, - .xfer = spi_ctrlr_xfer, - .xfer_vector = spi_xfer_two_vectors, - .max_xfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE, -}; - -/* Set up communications parameters for a SPI slave. */ -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +static int spi_ctrlr_setup(const struct spi_slave *slave) { struct img_spi_slave *img_slave = NULL; struct spim_device_parameters *device_parameters; u32 base; - switch (bus) { + switch (slave->bus) { case 0: base = IMG_SPIM0_BASE_ADDRESS; break; @@ -560,15 +551,11 @@ __func__); return -1; } - if (cs > SPIM_DEVICE4) { + if (slave->cs > SPIM_DEVICE4) { printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", __func__); return -1; } - - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = &spi_ctrlr; img_slave = get_img_slave(slave); device_parameters = &(img_slave->device_parameters); @@ -586,3 +573,22 @@ return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, + .max_xfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = 1, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19772 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4ec74fccaf25900537ccd5c146bb0a333a2754c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/rockchip: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19771 ) Change subject: soc/rockchip: Move spi driver to use spi_bus_map ...................................................................... soc/rockchip: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/rockchip/common/spi.c 1 file changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/19771/1 diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0e73769..4f8f41b 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -323,20 +323,26 @@ return ret < 0 ? ret : 0; } +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + assert(slave->bus < ARRAY_SIZE(rockchip_spi_slaves)); + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, .max_xfer_size = 65535, }; -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = ARRAY_SIZE(rockchip_spi_slaves) - 1, + }, +}; - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = &spi_ctrlr; - - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19771 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/nvidia/tegra*: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19769 ) Change subject: soc/nvidia/tegra*: Move spi driver to use spi_bus_map ...................................................................... soc/nvidia/tegra*: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I873b96d286655a814554bfd89f899ee87302b06d Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra210/spi.c 2 files changed, 36 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19769/1 diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 4ecd67a..3e281c3 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -793,22 +793,29 @@ return ret; } +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct tegra_spi_channel *channel = to_tegra_spi(slave->bus); + if (!channel) + return -1; + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct tegra_spi_channel *channel = to_tegra_spi(bus); - if (!channel) - return -1; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 1, + .bus_end = ARRAY_SIZE(tegra_spi_channels) + }, +}; - slave->bus = channel->slave.bus; - slave->cs = channel->slave.cs; - slave->ctrlr = &spi_ctrlr; - - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 0987ddb..e3246ec 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -829,22 +829,29 @@ return ret; } +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct tegra_spi_channel *channel = to_tegra_spi(slave->bus); + if (!channel) + return -1; + + return 0; +} + static const struct spi_ctrlr spi_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct tegra_spi_channel *channel = to_tegra_spi(bus); - if (!channel) - return -1; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 1, + .bus_end = ARRAY_SIZE(tegra_spi_channels) + }, +}; - slave->cs = channel->slave.cs; - slave->bus = channel->slave.bus; - slave->ctrlr = &spi_ctrlr; - - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19769 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I873b96d286655a814554bfd89f899ee87302b06d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/mediatek/mt8173: Move spi driver to use spi_bus_map
by Furquan Shaikh (Code Review) 18 May '17

18 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19770 ) Change subject: soc/mediatek/mt8173: Move spi driver to use spi_bus_map ...................................................................... soc/mediatek/mt8173: Move spi driver to use spi_bus_map This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: Ib0d6e4e8185ce1285b671af5ebcead1d42e049bc Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/mediatek/mt8173/spi.c 1 file changed, 41 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/19770/1 diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index b8ee423..fbbdf14 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -289,7 +289,26 @@ mtk_slave->state = MTK_SPI_IDLE; } -static const struct spi_ctrlr spi_ctrlr = { +static int spi_ctrlr_setup(const struct spi_slave *slave) +{ + struct mtk_spi_bus *eslave; + + switch (slave->bus) { + case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: + eslave = to_mtk_spi(slave); + assert(read32(&eslave->regs->spi_cfg0_reg) != 0); + spi_sw_reset(eslave->regs); + return 0; + case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: + return 0; + default: + die ("wrong bus number.\n"); + }; + return -1; +} + +static const struct spi_ctrlr spi_flash_ctrlr = { + .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, @@ -298,26 +317,26 @@ .flash_probe = mtk_spi_flash_probe, }; -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct mtk_spi_bus *eslave; +static const struct spi_ctrlr spi_ec_ctrlr = { + .setup = spi_ctrlr_setup, + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, + .max_xfer_size = 65535, +}; - slave->ctrlr = &spi_ctrlr; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ec_ctrlr, + .bus_start = CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, + .bus_end = CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, + }, + { + .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; - switch (bus) { - case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: - slave->bus = bus; - slave->cs = cs; - eslave = to_mtk_spi(slave); - assert(read32(&eslave->regs->spi_cfg0_reg) != 0); - spi_sw_reset(eslave->regs); - return 0; - case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: - slave->bus = bus; - slave->cs = cs; - return 0; - default: - die ("wrong bus number.\n"); - }; - return -1; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/19770 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib0d6e4e8185ce1285b671af5ebcead1d42e049bc Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: nb/intel/x4x/raminit: Rework receive enable calibration
by Arthur Heymans (Code Review) 18 May '17

18 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18692 ) Change subject: nb/intel/x4x/raminit: Rework receive enable calibration ...................................................................... Patch Set 16: Strobe is unreliable :( found DQS high on coarse=5, medium=2. Then when decreasing medium and looking for DQS high while increasing TAP it find it at coarse=5, medium=1, tap=0... after that it decreases tap so coarse=5, medium=0, tap=14. DQS high is not found later when increasing medium. Difference with previous code is that tap did not get decreased this way if it was 0. now it hits the "Not at DQS HIGH d'oh" a few things could be done: * check for strobe consistency by running it multiple times * add a check if (tap == 0) to bring back old behavior * when finding preamble increase medium until DQS high instead of one medium -- To view, visit https://review.coreboot.org/18692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Gerrit-PatchSet: 16 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 for GLK
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19746 ) Change subject: soc/intel/apollolake: configure RAPL PL1 for GLK ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53958/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9695/ : SUCCESS -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 for GLK
by Cole Nelson (Code Review) 18 May '17

18 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19746 to look at the new patch set (#2). Change subject: soc/intel/apollolake: configure RAPL PL1 for GLK ...................................................................... soc/intel/apollolake: configure RAPL PL1 for GLK Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime. Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Signed-off-by: Cole Nelson <colex.nelson(a)intel.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/19746/2 -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/intel/glkrvp: Add support for GLKRVP
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19604 ) Change subject: mainboard/intel/glkrvp: Add support for GLKRVP ...................................................................... Patch Set 28: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53957/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9694/ : SUCCESS -- To view, visit https://review.coreboot.org/19604 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Gerrit-PatchSet: 28 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017