coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/glk: Use intel/common/xhci driver
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18450 -gerrit commit efb6196a62ebacb5d94441b63feb2024bd7fb9ec Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:39:23 2017 +0530 soc/intel/glk: Use intel/common/xhci driver Change-Id: I08fbe7c7ac83d12af1cc77450001103a7069d7d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 9e843d8..c09aa3e 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_XHCI select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/xhci driver
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18223 -gerrit commit 1ffe8b43c949f3d4a9f8de66c94db5d6820888ce Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:16:37 2017 +0530 soc/intel/skylake: Use intel/common/xhci driver Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/xhci.c | 43 -------------------------------------- 3 files changed, 1 insertion(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8cc83a6..400fd0e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_XHCI select SMM_TSEG select SMP select SSE2 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..2a6b152 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -90,7 +90,6 @@ ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c -ramstage-y += xhci.c smm-y += cpu_info.c smm-y += gpio.c diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c deleted file mode 100644 index 0912f10..0000000 --- a/src/soc/intel/skylake/xhci.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <soc/ramstage.h> -#include <soc/cpu.h> - -static struct device_operations usb_xhci_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d2f, /* SunRisePoint LP */ - 0xa12f, /* KBL-H*/ - 0 -}; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -};

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Patch set updated for coreboot: soc/intel/common/block: Add Intel XHCI driver support
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221 -gerrit commit a69b6d1d1dc73dd3455cae205258170c9e461736 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:08:49 2017 +0530 soc/intel/common/block: Add Intel XHCI driver support Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- .../intel/common/block/include/intelblocks/xhci.h | 22 +++++++++++ src/soc/intel/common/block/xhci/Kconfig | 4 ++ src/soc/intel/common/block/xhci/Makefile.inc | 1 + src/soc/intel/common/block/xhci/xhci.c | 44 ++++++++++++++++++++++ 4 files changed, 71 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h new file mode 100644 index 0000000..2e893ca --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_XHCI_H +#define SOC_INTEL_COMMON_XHCI_H + +void soc_xhci_init(struct device *dev); + +#endif /* SOC_INTEL_COMMON_XHCI_H */ + diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig new file mode 100644 index 0000000..23313d7 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_XHCI + bool + help + Intel Processor common XHCI support diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..a501581 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_XHCI) += xhci.c diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c new file mode 100644 index 0000000..32fad93 --- /dev/null +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <intelblocks/xhci.h> + +__attribute__((weak)) void soc_xhci_init(struct device *dev) { /* no-op */ } + +static struct device_operations usb_xhci_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = soc_xhci_init, +}; + +static const unsigned short pci_device_ids[] = { + 0x5aa8, /* ApolloLake */ + 0x31a8, /* GLK */ + 0x9d2f, /* SunRisePoint LP */ + 0xa12f, /* KBL-H*/ + 0 +}; + +static const struct pci_driver pch_usb_xhci __pci_driver = { + .ops = &usb_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: soc/intel/skylake: Clean up XHCI code
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18508 -gerrit commit fcf50daa3f912755eb400009f6b6f1908161d145 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 12:21:49 2017 +0530 soc/intel/skylake: Clean up XHCI code Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/include/soc/xhci.h | 60 -------------------------------- src/soc/intel/skylake/xhci.c | 1 - 2 files changed, 61 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h deleted file mode 100644 index c520223..0000000 --- a/src/soc/intel/skylake/include/soc/xhci.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_XHCI_H_ -#define _SOC_XHCI_H_ - -#include <rules.h> - -/* XHCI PCI Registers */ -#define XHCI_PWR_CTL_STS 0x74 -#define XHCI_PWR_CTL_SET_MASK 0x3 -#define XHCI_PWR_CTL_SET_D0 0x0 -#define XHCI_PWR_CTL_SET_D3 0x3 -#define XHCI_PWR_CTL_ENABLE_PME (1 << 8) -#define XHCI_PWR_CTL_STATUS_PME (1 << 15) -#define XHCI_USB2PR 0xd0 -#define XHCI_USB2PRM 0xd4 -#define XHCI_USB2PR_HCSEL 0x7fff -#define XHCI_USB3PR 0xd8 -#define XHCI_USB3PR_SSEN 0x3f -#define XHCI_USB3PRM 0xdc -#define XHCI_USB3FUS 0xe0 -#define XHCI_USB3FUS_SS_MASK 3 -#define XHCI_USB3FUS_SS_SHIFT 3 -#define XHCI_USB3PDO 0xe8 - -/* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10)) -#define XHCI_USB3_PORTSC_CHST (0x7f << 17) -#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ - -#if ENV_SMM -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); -#endif - -#endif diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c index 5ee34df..0912f10 100644 --- a/src/soc/intel/skylake/xhci.c +++ b/src/soc/intel/skylake/xhci.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <soc/ramstage.h> -#include <soc/xhci.h> #include <soc/cpu.h> static struct device_operations usb_xhci_ops = {

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Patch set updated for coreboot: soc/intel/apollolake: Move XDCI in its own file
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18226 -gerrit commit 83058842e468ee2d486546d21efbd44d99efddee Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jan 24 21:56:36 2017 -0800 soc/intel/apollolake: Move XDCI in its own file Split out dual-port switching functionality into dedicated xdci.c. Change-Id: Ia58fc3fb6d017dd0c19cc450d1caba307fc89a7b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/xdci.c | 105 +++++++++++++++++++++++++ src/soc/intel/apollolake/xhci.c | 72 ----------------- 4 files changed, 107 insertions(+), 72 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index df93f0b..5e1cf73 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -83,6 +83,7 @@ ramstage-y += reset.c ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c +ramstage-y += xdci.c ramstage-y += xhci.c postcar-y += flash_ctrlr.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 130263b..4c2956f 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_XDCI 0x5aaa /* 00:15.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */ diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c new file mode 100644 index 0000000..2812957 --- /dev/null +++ b/src/soc/intel/apollolake/xdci.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <timer.h> + +#define DUAL_ROLE_CFG0 0x80d8 +# define DRD_CONFIG_MASK (0x3 << 0) +# define DRD_CONFIG_DYNAMIC (0x0 << 0) +# define DRD_CONFIG_HOST (0x1 << 0) +# define DRD_CONFIG_DEVICE (0x2 << 0) +# define SW_VBUS_VALID_MASK (1 << 24) +# define SW_VBUS_DEASSERT_VALID (0 << 24) +# define SW_VBUS_ASSERT_VALID (1 << 24) +# define SW_IDPIN_EN_MASK (1 << 21) +# define SW_IDPIN_DIS (0 << 21) +# define SW_IDPIN_EN (1 << 21) +# define SW_IDPIN_MASK (1 << 20) +# define SW_IDPIN_HOST (0 << 20) +# define SW_IDPIN_DEVICE (1 << 20) +#define DUAL_ROLE_CFG1 0x80dc +# define DRD_MODE_MASK (1 << 29) +# define DRD_MODE_DEVICE (0 << 29) +# define DRD_MODE_HOST (1 << 29) + +static void configure_host_mode_port0(struct device *dev) +{ + uint32_t *cfg0; + uint32_t *cfg1; + const struct resource *res; + uint32_t reg; + struct stopwatch sw; + struct device *xhci_dev = XHCI_DEV; + + /* + * Only default to host mode if the xdci device is present and + * enabled. If it's disabled assume the switch was already done + * in FSP. + */ + if (!dev->enabled || !xhci_dev->enabled) + return; + + printk(BIOS_INFO, "Putting port 0 into host mode.\n"); + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + + cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); + cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); + + reg = read32(cfg0); + reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); + reg &= ~(SW_VBUS_VALID_MASK); + reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; + reg |= SW_VBUS_DEASSERT_VALID; + write32(cfg0, reg); + + stopwatch_init_msecs_expire(&sw, 10); + + /* Wait for the host mode status bit. */ + while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Timed out waiting for host mode.\n"); + break; + } + } + + printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +static void xdci_init(struct device *dev) +{ + configure_host_mode_port0(dev); +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xdci_init, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_XDCI, +}; diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 7b3cb46..3dd4f7d 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -14,88 +14,16 @@ */ #include <arch/io.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <soc/pci_ids.h> -#include <timer.h> - -#define DUAL_ROLE_CFG0 0x80d8 -# define DRD_CONFIG_MASK (0x3 << 0) -# define DRD_CONFIG_DYNAMIC (0x0 << 0) -# define DRD_CONFIG_HOST (0x1 << 0) -# define DRD_CONFIG_DEVICE (0x2 << 0) -# define SW_VBUS_VALID_MASK (1 << 24) -# define SW_VBUS_DEASSERT_VALID (0 << 24) -# define SW_VBUS_ASSERT_VALID (1 << 24) -# define SW_IDPIN_EN_MASK (1 << 21) -# define SW_IDPIN_DIS (0 << 21) -# define SW_IDPIN_EN (1 << 21) -# define SW_IDPIN_MASK (1 << 20) -# define SW_IDPIN_HOST (0 << 20) -# define SW_IDPIN_DEVICE (1 << 20) -#define DUAL_ROLE_CFG1 0x80dc -# define DRD_MODE_MASK (1 << 29) -# define DRD_MODE_DEVICE (0 << 29) -# define DRD_MODE_HOST (1 << 29) - -static void configure_host_mode_port0(struct device *dev) -{ - uint32_t *cfg0; - uint32_t *cfg1; - const struct resource *res; - uint32_t reg; - struct device *xdci_dev = XDCI_DEV; - struct stopwatch sw; - - /* - * Only default to host mode if the xdci device is present and - * enabled. If it's disabled assume the switch was already done - * in FSP. - */ - if (xdci_dev == NULL || !xdci_dev->enabled) - return; - - printk(BIOS_INFO, "Putting port 0 into host mode.\n"); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); - cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); - - reg = read32(cfg0); - reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); - reg &= ~(SW_VBUS_VALID_MASK); - reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; - reg |= SW_VBUS_DEASSERT_VALID; - write32(cfg0, reg); - - stopwatch_init_msecs_expire(&sw, 10); - - /* Wait for the host mode status bit. */ - while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { - if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "Timed out waiting for host mode.\n"); - break; - } - } - - printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -static void xhci_init(struct device *dev) -{ - configure_host_mode_port0(dev); -} static const struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = xhci_init, }; static const struct pci_driver pmc __pci_driver = {

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Patch set updated for coreboot: soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP]
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18449 -gerrit commit 32549bfb1c4e453a06dd89b4d32c291e6f7331de Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:01:26 2017 +0530 soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP] Copied from APL latest git. Change-Id: Icf1bb95cd2503e12f8ce26d77d2cd940a2ea1b69 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 233 +++++++++++++++++++++++++++++++++++++++++ src/soc/intel/glk/Makefile.inc | 40 +++++++ 2 files changed, 273 insertions(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig new file mode 100644 index 0000000..9e843d8 --- /dev/null +++ b/src/soc/intel/glk/Kconfig @@ -0,0 +1,233 @@ +config SOC_INTEL_GLK + bool + help + Intel GLK support + +if SOC_INTEL_GLK + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + # CPU specific options + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select IOAPIC + select SMP + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT + select SOC_INTEL_COMMON_NHLT + # Misc options + select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select COLLECT_TIMESTAMPS + select COMMON_FADT + select GENERIC_GPIO_LIB + select HAVE_INTEL_FIRMWARE + select HAVE_SMI_HANDLER + select MRC_SETTINGS_PROTECT + select NO_FIXED_XIP_ROM_SIZE + select NO_XIP_EARLY_STAGES + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select POSTCAR_CONSOLE + select POSTCAR_STAGE + select REG_SCRIPT + select RELOCATABLE_RAMSTAGE # Build fails if this is not selected + select RTC + select SMM_TSEG + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select HAVE_MONOTONIC_TIMER + select PLATFORM_USES_FSP2_0 + select HAVE_HARD_RESET + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_GFX_OPREGION + select ADD_VBT_DATA_FILE + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC + select SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VIRTUAL_DEV_SWITCH + +config TPM_ON_FAST_SPI + bool + default n + select LPC_TPM + help + TPM part is conntected on Fast SPI interface, but the LPC MMIO + TPM transactions are decoded and serialized over the SPI interface. + +config SOC_INTEL_COMMON_RESET + bool + default y + +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0xc0000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config CPU_ADDR_BITS + int + default 36 + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + depends on SOC_INTEL_COMMON_LPSS_I2C + int + default 133 + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex "MMIO base address for UART" + default 0xde000000 + +config SOC_UART_DEBUG + bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." + default n + select CONSOLE_SERIAL + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + +# This SoC does not map SPI flash like many previous SoC. Therefore we provide +# a custom media driver that facilitates mapping +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n + +config ROMSTAGE_ADDR + hex + default 0xfef20000 + help + The base address (in CAR) where romstage should be linked + +config VERSTAGE_ADDR + hex + default 0xfef40000 + help + The base address (in CAR) where verstage should be linked + +config CACHE_MRC_SETTINGS + bool + default y + +config MRC_SETTINGS_VARIABLE_DATA + bool + default y + +config FSP_M_ADDR + hex + default 0xfef40000 + help + The address FSP-M will be relocated to during build time + +config NEED_LBP2 + bool "Write contents for logical boot partition 2." + default n + help + Write the contents from a file into the logical boot partition 2 + region defined by LBP2_FMAP_NAME. + +config LBP2_FMAP_NAME + string "Name of FMAP region to put logical boot partition 2" + depends on NEED_LBP2 + default "SIGN_CSE" + help + Name of FMAP region to write logical boot partition 2 data. + +config LBP2_FILE_NAME + string "Path of file to write to logical boot partition 2 region" + depends on NEED_LBP2 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" + help + Name of file to store in the logical boot partition 2 region. + +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + +config HEAP_SIZE + hex + default 0x8000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config IFD_CHIPSET + string + default "aplk" + +endif diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc new file mode 100644 index 0000000..92c3bc2 --- /dev/null +++ b/src/soc/intel/glk/Makefile.inc @@ -0,0 +1,40 @@ +ifeq ($(CONFIG_SOC_INTEL_GLK),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache + +CPPFLAGS_common += -I$(src)/soc/intel/glk/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk + +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) + +ifeq ($(CONFIG_NEED_LBP2),y) +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward +endif + +# Bootblock on GLK platform lies in the IFWI region. In order to place +# the bootblock at the right location in IFWI image - +# a. Using ifwitool: +# 1. Create IFWI image (ifwi.bin.tmp) from input image +# (CONFIG_IFWI_FILE_NAME). +# 2. Delete OBBP sub-partition, if present. +# 3. Replace IBBL directory entry in IBBP sub-partition with currently +# generated bootblock.bin. +# b. Using cbfstool: +# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME. +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: $(IFWITOOL) + $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward +endif + +endif

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Patch set updated for coreboot: soc/intel/common: Make infrastructure ready for Intel common code
by Subrata Banik 03 Mar '17

03 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18377 -gerrit commit 4b3faaf0096cfa1eb0686a7c38037d9ba7aa0ed1 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 14:22:44 2017 +0530 soc/intel/common: Make infrastructure ready for Intel common code Select all Kconfig belongs into Intel SoC Family block/ips common code model and include required header.h file. Change-Id: Idbce59a57533dbeb9ccfadca966c3d7560537fa0 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/Makefile.inc | 3 +++ src/soc/intel/common/block/Kconfig | 11 +++++++++++ src/soc/intel/common/block/Makefile.inc | 7 +++++++ 4 files changed, 25 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 68bb38a..3d2ced9 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -5,6 +5,10 @@ config SOC_INTEL_COMMON if SOC_INTEL_COMMON +comment "Intel SoC Common Code" +source "src/soc/intel/common/basecode/Kconfig" +source "src/soc/intel/common/block/Kconfig" + config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d6e1e75..77639ce 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +subdirs-y += basecode/ +subdirs-y += block/ + bootblock-y += util.c verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c diff --git a/src/soc/intel/common/block/Kconfig b/src/soc/intel/common/block/Kconfig new file mode 100644 index 0000000..e5375d2 --- /dev/null +++ b/src/soc/intel/common/block/Kconfig @@ -0,0 +1,11 @@ +config SOC_INTEL_COMMON_BLOCK + bool + help + SoC driver for intel common IP code + +if SOC_INTEL_COMMON_BLOCK + +comment "Intel SoC Common IP Code" +source "src/soc/intel/common/block/*/Kconfig" + +endif diff --git a/src/soc/intel/common/block/Makefile.inc b/src/soc/intel/common/block/Makefile.inc new file mode 100644 index 0000000..d6f53c8 --- /dev/null +++ b/src/soc/intel/common/block/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK),y) + +subdirs-y += ./* + +CPPFLAGS_common += -I$(src)/soc/intel/common/block/include/ + +endif

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Patch set updated for coreboot: nb/intel/i945: Fix PEG port on 945gc
by Arthur Heymans 03 Mar '17

03 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18549 -gerrit commit 64eadd843a62faa434c06d7657a2038eda4ee278 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Mar 2 23:51:09 2017 +0100 nb/intel/i945: Fix PEG port on 945gc Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203). Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port. According to lspci the link width is at the desired x16. Unknown if devices requesting a lower width work automatically or needs more configuration. Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/early_init.c | 3 ++- src/northbridge/intel/i945/raminit.c | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 81a6c83..e7b460b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -935,7 +935,8 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - i945_setup_pci_express_x16(); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe5f24..52bb355 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2524,17 +2524,19 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (i945_silicon_revision()>1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (i945_silicon_revision()>1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; + } } reg16 = MCHBAR16(UPMC2);

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Patch merged into coreboot/master: mb/getac/p470: Do not select EARLY_CBMEM_INIT
by gerrit＠coreboot.org 03 Mar '17

03 Mar '17

the following patch was just integrated into master: commit d55ea7b69e2aaa77ff15da0e26a4dbdcce8ac81d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Mar 2 14:57:05 2017 +0100 mb/getac/p470: Do not select EARLY_CBMEM_INIT This is selected by default and not overwritten anywhere else for this board. Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18541 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18541 for details. -gerrit

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Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 03 Mar '17

03 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit d5e2d4a3064141cf3d9a1afc83b863d7b8f04112 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 6ca90d5..720132e 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -200,8 +200,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -210,10 +214,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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coreboot-gerrit March 2017