coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intelblocks/pci_dev: Create header for pci devices
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18576 -gerrit commit fea78355f85f06716325affc5df4271ecbd4d4f4 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sun Mar 5 12:37:00 2017 +0530 intelblocks/pci_dev: Create header for pci devices Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- .../common/block/include/intelblocks/pci_devs.h | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/pci_devs.h b/src/soc/intel/common/block/include/intelblocks/pci_devs.h new file mode 100644 index 0000000..9862cc4 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pci_devs.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_PCI_DEVS_H +#define SOC_INTEL_COMMON_PCI_DEVS_H + +#include <device/pci_def.h> +#include <rules.h> + +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) + +#if ENV_RAMSTAGE +#include <device/device.h> +#include <device/pci_def.h> +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#else +#include <arch/io.h> +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#endif + +#endif +

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Patch set updated for coreboot: soc/intel/glk: Use intel/common/block/systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18455 -gerrit commit 067b3be9f6c35f80e177594bea13ed5707e6418f Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:39:08 2017 +0530 soc/intel/glk: Use intel/common/block/systemagent code Change-Id: Ibde64058e9f23f25daabab82956cc360e693e422 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 5566366..7205b4a 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/block/systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18456 -gerrit commit 42236f561aedc67f8ef16c80e741c89dc6c15b0a Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:43:43 2017 +0530 soc/intel/skylake: Use intel/common/block/systemagent code Change-Id: Ib471ef3d3ae96b69e2bdfaf81554325d0393900d Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/systemagent.c | 43 --------------------------- 3 files changed, 1 insertion(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 01ffa9b..c656bed 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 181e17b..dfda301 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/smbus.c -bootblock-y += bootblock/systemagent.c bootblock-y += flash_controller.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c deleted file mode 100644 index e76d4d2..0000000 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/bootblock.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> - -void bootblock_systemagent_early_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. - */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); -}

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Patch set updated for coreboot: soc/intel/apollolake: Clean up Systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18567 -gerrit commit 161d732077f8b12ca371a62d16c4c53daff30af1 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Mar 4 23:39:47 2017 +0530 soc/intel/apollolake: Clean up Systemagent code Use common systemagent header. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 --- src/soc/intel/apollolake/bootblock/bootblock.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/include/soc/iomap.h | 2 ++ src/soc/intel/apollolake/include/soc/northbridge.h | 40 ---------------------- src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/northbridge.c | 2 +- src/soc/intel/apollolake/romstage.c | 2 +- 8 files changed, 7 insertions(+), 49 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4ff64d2..0322318 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -88,10 +88,6 @@ config SOC_INTEL_COMMON_RESET bool default y -config MMCONF_BASE_ADDRESS - hex "PCI MMIO Base Address" - default 0xe0000000 - config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" default 0xd0000000 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 1f5055d..4f4e25f 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <intelblocks/systemagent.h> #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -25,7 +26,6 @@ #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> -#include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/uart.h> diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1de41cf..5383082 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -26,6 +26,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/systemagent.h> #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -37,7 +38,6 @@ #include <spi-generic.h> #include <soc/pm.h> #include <soc/p2sb.h> -#include <soc/northbridge.h> #include "chip.h" diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 3c94d1b..5e65592 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,8 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define PCIEX_SIZE (256 * MiB) + #define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 #define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 #define PUNIT_THERMAL_DEVICE_IRQ 0x700C diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h deleted file mode 100644 index 04e369e..0000000 --- a/src/soc/intel/apollolake/include/soc/northbridge.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ -#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ - -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define PCIEX_SIZE (256 * MiB) - -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ - -/* IMR registers are found under MCHBAR. */ -#define MCHBAR_IMR0BASE 0x6870 -#define MCHBAR_IMR0MASK 0x6874 -#define MCH_IMR_PITCH 0x20 -#define MCH_NUM_IMRS 20 - -/* RAPL Package Power Limit register under MCHBAR. */ -#define MCHBAR_RAPL_PPL 0x70A8 - -#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index cccbffd..4a43136 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -27,7 +27,7 @@ #include <assert.h> #include <cbmem.h> #include <device/pci.h> -#include <soc/northbridge.h> +#include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/smm.h> diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index cc097ba..855df09 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/northbridge.h> +#include <intelblocks/systemagent.h> #include <soc/pci_ids.h> static uint32_t get_bar(device_t dev, unsigned int index) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 97be0f6..5195909 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -31,11 +31,11 @@ #include <fsp/api.h> #include <fsp/memmap.h> #include <fsp/util.h> +#include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> -#include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h>

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Patch set updated for coreboot: soc/intel/skylake: Clean up Systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18566 -gerrit commit 5ccbb6fb9d47806aab2db471f54589c8525a2d46 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Mar 4 23:37:28 2017 +0530 soc/intel/skylake: Clean up Systemagent code Use common systemagent header. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 4 -- src/soc/intel/skylake/include/soc/bootblock.h | 3 +- src/soc/intel/skylake/include/soc/iomap.h | 3 + src/soc/intel/skylake/include/soc/systemagent.h | 78 +------------------------ 4 files changed, 6 insertions(+), 82 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7618fd3..01ffa9b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -148,10 +148,6 @@ config IED_REGION_SIZE hex default 0x400000 -config MMCONF_BASE_ADDRESS - hex "MMIO Base Address" - default 0xe0000000 - config MONOTONIC_TIMER_MSR def_bool y select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index df81d3f..f290d0f 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -16,6 +16,8 @@ #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ #define _SOC_SKYLAKE_BOOTBLOCK_H_ +#include <intelblocks/systemagent.h> + #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/bootblock.h> #else @@ -25,7 +27,6 @@ static inline void bootblock_fsp_temp_ram_init(void) {} /* Bootblock pre console init programing */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); -void bootblock_systemagent_early_init(void); void pch_uart_init(void); /* Bootblock post console init programing */ diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index e736d3b..9f50c48 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -58,6 +58,9 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 +/* CPU Trace reserved memory size */ +#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index c82f691..81c6dd7 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -18,6 +18,7 @@ #ifndef _SOC_SYSTEMAGENT_H_ #define _SOC_SYSTEMAGENT_H_ +#include <intelblocks/systemagent.h> #include <soc/iomap.h> #define SA_IGD_OPROM_VENDEV 0x80860406 @@ -41,89 +42,12 @@ #define MCH_KABYLAKE_ID_Y 0x590c #define MCH_KABYLAKE_ID_H 0x5910 -/* Device 0:0.0 PCI configuration space */ - -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define GGC 0x50 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) -#define DPR 0x5c -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define SKPAD 0xdc /* Scratchpad Data */ - /* MCHBAR */ #define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 -#define EDRAMBAR 0x5408 -#define MCH_PAIR 0x5418 -#define GDXCBAR 0x5420 - -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - -/* CPU Trace reserved memory size */ -#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ - /* System Agent identification */ u8 systemagent_revision(void);

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Patch set updated for coreboot: soc/intel/common/block: [WIP]Add Intel common systemagent support
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18454 -gerrit commit 0a6800a04f60e46a48a9a741c6a2ce95bcbef5bc Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sun Mar 5 13:19:42 2017 +0530 soc/intel/common/block: [WIP]Add Intel common systemagent support Create common Intel systemagent code. This code currently contains the SA initialization required in Bootblock phase, which has the following programming- * Set PCIEXBAR * Clear TSEG register More code will get added up in the subsequent phases. Change-Id: Ib8a77aec8b20bafd4175048d442701250f1aa9c8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/block/systemagent/Kconfig | 27 +++++++++++++++ .../intel/common/block/systemagent/Makefile.inc | 1 + .../intel/common/block/systemagent/systemagent.c | 39 ++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig new file mode 100644 index 0000000..75ec6aa --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -0,0 +1,27 @@ +config SOC_INTEL_COMMON_BLOCK_SA + bool + help + Intel Processor common System Agent support + +config PCIEX_BASE_ADDRESS + hex + default 0xe0000000 + +config SA_PCIEX_LENGTH + hex + default PCIEX_LENGTH_256MB if (SOC_INTEL_CAR_SMALL_CORE) + default PCIEX_LENGTH_64MB if (SOC_INTEL_CAR_BIG_CORE) + help + This option allows you to select length of PCIEX region. + +config PCIEX_LENGTH_256MB + hex + default 0x0 + +config PCIEX_LENGTH_128MB + hex + default 0x2 + +config PCIEX_LENGTH_64MB + hex + default 0x4 diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc new file mode 100644 index 0000000..75d5626 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -0,0 +1 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c new file mode 100644 index 0000000..7c356f9 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <intelblocks/systemagent.h> + +void bootblock_systemagent_early_init(void) +{ + uint32_t reg; + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + reg = CONFIG_PCIEX_BASE_ADDRESS | CONFIG_SA_PCIEX_LENGTH | 1; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + + /* + * Clear TSEG register - TSEG register comes out of reset with a + * non-zero default value. Clear this register to ensure that there are + * no surprises in CBMEM handling. + */ + pci_io_write_config32(SA_DEV_ROOT, TSEG, 0); +} +

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Patch set updated for coreboot: intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18565 -gerrit commit 21487e54b99ebf73d88313332630462e0de48259 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Mar 4 23:32:41 2017 +0530 intelblocks/systemagent: Create header for host bridge B0:D0:F0 registers Move all common registers and specific to SOC registers into a common location to avoid duplication. Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- .../common/block/include/intelblocks/systemagent.h | 129 +++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h new file mode 100644 index 0000000..ab09fb2 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_SA_H +#define SOC_INTEL_COMMON_SA_H + +#include <intelblocks/pci_devs.h> + +/* System Agent Devices */ +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) +#define SA_DEV_ROOT _SA_DEV(ROOT) + +/* Device 0:0.0 PCI configuration space */ + +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define GGC 0x50 + +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#if IS_ENABLED(CONFIG_SOC_INTEL_CAR_SMALL_CORE) + +/* Device 0:0.0 PCI configuration space */ +#define DEVEN 0x54 +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D0F1EN (1 << 1) +#define DEVEN_D0EN (1 << 0) + +/* MCHBAR */ + +/* IMR registers are found under MCHBAR. */ +#define MCHBAR_IMR0BASE 0x6870 +#define MCHBAR_IMR0MASK 0x6874 +#define MCH_IMR_PITCH 0x20 +#define MCH_NUM_IMRS 20 +/* RAPL Package Power Limit register under MCHBAR. */ +#define MCHBAR_RAPL_PPL 0x70A8 + +#elif IS_ENABLED(CONFIG_SOC_INTEL_CAR_BIG_CORE) + +/* Device 0:0.0 PCI configuration space */ +#define EPBAR 0x40 +#define DMIBAR 0x68 +#define DEVEN 0x54 +#define DEVEN_D7EN (1 << 14) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D1F0EN (1 << 3) +#define DEVEN_D1F1EN (1 << 2) +#define DEVEN_D1F2EN (1 << 1) +#define DEVEN_D0EN (1 << 0) +#define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define MESEG_BASE 0x70 /* Management Engine Base. */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ +#define REMAPBASE 0x90 /* Remap base. */ +#define REMAPLIMIT 0x98 /* Remap limit. */ +#define TOM 0xa0 /* Top of DRAM in memory controller space. */ + +/* MCHBAR */ + +#define MCHBAR_PEI_VERSION 0x5034 +#define BIOS_RESET_CPL 0x5da8 +#define EDRAMBAR 0x5408 +#define MCH_PAIR 0x5418 +#define GDXCBAR 0x5420 + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +/* PCODE MMIO communications live in the MCHBAR. */ +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +/* Errors are returned back in bits 7:0. */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 +/* Data is passed through bits 31:0 of the data register. */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#endif + +void bootblock_systemagent_early_init(void); + +#endif /* SOC_INTEL_COMMON_SA_H */

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Patch set updated for coreboot: board_status/towiki.sh: Fix Socket for Sandy and Ivy Bridge
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18478 -gerrit commit eedbfe10fc6923d48efba11e9364313737bcc667 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Feb 23 23:40:56 2017 +0100 board_status/towiki.sh: Fix Socket for Sandy and Ivy Bridge Change-Id: I4c94209c424f56516033c07c4365401a6b217a37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- util/board_status/to-wiki/towiki.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 8b2d1af..769ae5f 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -326,7 +326,7 @@ EOF socket_nice="?" ;; INTEL_SOCKET_RPGA989|INTEL_SOCKET_LGA1155|INTEL_SOCKET_RPGA988B) - socket_nice="`echo $socket | sed 's,INTEL_SOCKET_,Socket ,g'`" + socket_nice="`echo $cpu | sed 's,INTEL_SOCKET_,Socket ,g'`" case $northbridge in INTEL_HASWELL) cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";;

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Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit 68d1e7bbc9fc09569a5d2b456d5c61e525212cac Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1d6c8ff..9e9f44e 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit 9e5f88079605c8d510396e8886a97ee131513417 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Mar 5 10:57:02 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit46 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index b455324..9007bf2 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -55,17 +55,22 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); + } else { /* Does not feature internal graphics */ + pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); - /* * Disabling IGD later is possible but somehow reclaiming its UMA * resources fails so enable/disable IGD before raminit if external

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coreboot-gerrit March 2017