coreboot-gerrit March 2017

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Patch set updated for coreboot: nb/x4x: Disable IGD when external GPU is found
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit 387b34a51e5adfba8ba4e5e610ff8f7f325aca92 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x: Disable IGD when external GPU is found This disables IGD before raminit if an external GPU is found unless CONFIG_ONBOARD_VGA_IS_PRIMARY is set. This adds a disable function for IGD to allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. TESTED on ga-g41m-es2l Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++++++++++++ src/northbridge/intel/x4x/gma.c | 17 +++++++++++++++++ src/northbridge/intel/x4x/x4x.h | 1 + 3 files changed, 43 insertions(+) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc9..dfa90cc 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -24,10 +24,12 @@ #include <console/console.h> #include <halt.h> #include <romstage_handoff.h> +#include <device/pci_def.h> void x4x_early_init(void) { const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); + u32 reg32; /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); @@ -64,6 +66,29 @@ void x4x_early_init(void) gfxsize = 6; } pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); + + /* + * Disabling IGD later is possible but somehow reclaiming its UMA + * resources fails so enable/disable IGD before raminit if external + * GPU is found. + * NOTE: PCI specifies that one needs to wait at least 100msec after + * reset. In practise GPUs seem to get detected fine without this. + */ + if (pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS) & (1 << 6) && + !IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY)) { + pci_write_config8(PCI_DEV(0, 0x01, 0), PCI_SECONDARY_BUS, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), + PCI_SUBORDINATE_BUS, 0x0a); + reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); + if (reg32 == 0x030000) { + printk(BIOS_DEBUG,"External GPU is found." + " xDisabling IGD before raminit\n"); + reg32 = pci_read_config32(d0f0, D0F0_DEVEN); + pci_write_config32(d0f0, D0F0_DEVEN, + reg32 & ~(IGD0EN | IGD1EN)); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); + } + } } static void init_egress(void) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..4bf8125 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,22 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 ggc; + + ggc = pci_read_config16(dev_host, D0F0_GGC); + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, ggc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +436,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index faae775..834128b 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -60,6 +60,7 @@ */ #define PEG_CAP 0xa2 #define SLOTCAP 0xb4 +#define SLOTSTS 0xba #define PEGLC 0xec #define D1F0_VCCAP 0x104 #define D1F0_VC0RCTL 0x114

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Patch set updated for coreboot: [RFC] mainboard/sapphire/pureplatinumh61: Add new board
by Nicola Corna 05 Mar '17

05 Mar '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18564 -gerrit commit a8d1448c9cf81725938a4f6fe8d7ae58667939fa Author: Nicola Corna <nicola(a)corna.info> Date: Fri Mar 3 18:04:48 2017 +0100 [RFC] mainboard/sapphire/pureplatinumh61: Add new board Add support for Sapphire Pure Platinum H61 This board has a socketed SOIC-8 4 MB flash chip. All the flash regions are unlocked by default but unfortunately flashrom doesn't work on this platform; the stock UEFI flash tool refuses to flash the coreboot image (different image ID), but maybe it can be spoofed. For now, the external programmer seems to be the only option. Everything works well, with the following exceptions: * The USB 3.0 doesn't work in coreboot (as it is controlled by a separate PCI controller). * S3 resume doesn't work (FIXME) * The raminit is somewhat unstable, as the RAM training sometimes fails and sometimes succeeds, with the same couple of DIMMs. (FIXME) Untested: * Integrated GPU * Backside Mini PCI-E port * Ethernet in coreboot * Microsoft Windows Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/mainboard/sapphire/Kconfig | 16 + src/mainboard/sapphire/Kconfig.name | 2 + src/mainboard/sapphire/pureplatinumh61/Kconfig | 63 +++ .../sapphire/pureplatinumh61/Kconfig.name | 2 + .../sapphire/pureplatinumh61/Makefile.inc | 3 + src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl | 0 .../sapphire/pureplatinumh61/acpi/platform.asl | 30 ++ .../sapphire/pureplatinumh61/acpi/superio.asl | 0 .../sapphire/pureplatinumh61/acpi_tables.c | 1 + .../sapphire/pureplatinumh61/board_info.txt | 6 + .../sapphire/pureplatinumh61/devicetree.cb | 146 +++++++ src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 46 +++ .../sapphire/pureplatinumh61/early_southbridge.c | 82 ++++ src/mainboard/sapphire/pureplatinumh61/gnvs.c | 34 ++ src/mainboard/sapphire/pureplatinumh61/gpio.c | 185 +++++++++ src/mainboard/sapphire/pureplatinumh61/gpio_old.c | 433 +++++++++++++++++++++ src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 87 +++++ src/mainboard/sapphire/pureplatinumh61/mainboard.c | 38 ++ src/mainboard/sapphire/pureplatinumh61/romstage.c | 1 + 19 files changed, 1175 insertions(+) diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig new file mode 100644 index 0000000..130c1f4 --- /dev/null +++ b/src/mainboard/sapphire/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SAPPHIRE + +choice + prompt "Mainboard model" + +source "src/mainboard/sapphire/*/Kconfig.name" + +endchoice + +source "src/mainboard/sapphire/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Sapphire" + +endif # VENDOR_SAPPHIRE diff --git a/src/mainboard/sapphire/Kconfig.name b/src/mainboard/sapphire/Kconfig.name new file mode 100644 index 0000000..8ea84ad --- /dev/null +++ b/src/mainboard/sapphire/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SAPPHIRE + bool "Sapphire" diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig new file mode 100644 index 0000000..77ee428 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -0,0 +1,63 @@ +if BOARD_SAPPHIRE_PUREPLATINUMH61 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_LGA1155 + select SUPERIO_FINTEK_F71808A + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default sapphire/pureplatinumh61 + +config MAINBOARD_PART_NUMBER + string + default "PURE Platinum H61" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1007 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x174b + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 4 +endif diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig.name b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name new file mode 100644 index 0000000..7b642bd --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SAPPHIRE_PUREPLATINUMH61 + bool "Pure Platinum H61" diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc new file mode 100644 index 0000000..6064cea --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl new file mode 100644 index 0000000..ef07275 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/sapphire/pureplatinumh61/board_info.txt b/src/mainboard/sapphire/pureplatinumh61/board_info.txt new file mode 100644 index 0000000..c6360e2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb new file mode 100644 index 0000000..a5d62e5 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -0,0 +1,146 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0a01" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x174b 0x1007 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x174b 0x1007 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x174b 0x1007 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x174b 0x1007 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x174b 0x1007 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x174b 0x1007 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x174b 0x1007 + chip superio/fintek/f71808a + register "multi_function_register_1" = "0x00" + register "multi_function_register_2" = "0xc4" + register "multi_function_register_3" = "0x21" + register "multi_function_register_4" = "0x2f" + register "multi_function_register_5" = "0x5c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86% + register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74% + register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62% + register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50% + register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2 + device pnp 4e.1 off end # Serial Port 1 + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off end # Keyboard + device pnp 4e.6 on # GPIO + io 0xc5 = 0x1f + end + device pnp 4e.7 on # WDT + io 0x60 = 0xa00 + end + device pnp 4e.8 off end # CIR + device pnp 4e.a off end # PME, ACPI, EUP + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x174b 0x1007 + end + device pci 1f.3 on # SMBus + subsystemid 0x174b 0x1007 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x174b 0x1007 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x174b 0x1007 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl new file mode 100644 index 0000000..eb98bb2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c new file mode 100644 index 0000000..d9c5ee9 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; + RCBA32(0x3418) = 0x1fce1fe3; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gnvs.c b/src/mainboard/sapphire/pureplatinumh61/gnvs.c new file mode 100644 index 0000000..a790b0b --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gnvs.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c new file mode 100644 index 0000000..5d66f47 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio6 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio6 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_PWROK, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio35 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio35 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio_old.c b/src/mainboard/sapphire/pureplatinumh61/gpio_old.c new file mode 100644 index 0000000..2a1281b --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gpio_old.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_PWROK, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c new file mode 100644 index 0000000..cf723d0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0000, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x10ec0000), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c new file mode 100644 index 0000000..83cfd76 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002009; + RCBA32(0x38c4) = 0x00802009; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -0,0 +1 @@ +/* dummy file */

1 0

Patch set updated for coreboot: [RFC] mainboard/sapphire/pureplatinumh61: Add new board
by Nicola Corna 05 Mar '17

05 Mar '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18564 -gerrit commit d62f9387a4b6abde84b0ef69abf53cb1d76bf540 Author: Nicola Corna <nicola(a)corna.info> Date: Fri Mar 3 18:04:48 2017 +0100 [RFC] mainboard/sapphire/pureplatinumh61: Add new board Add support for Sapphire Pure Platinum H61 This board has a socketed SOIC-8 4 MB flash chip. All the flash regions are unlocked by default but unfortunately flashrom doesn't work on this platform; the stock UEFI flash tool refuses to flash the coreboot image (different image ID), but maybe it can be spoofed. For now, the external programmer seems to be the only option. Everything works well, with the following exceptions: * The USB 3.0 doesn't work in coreboot (as it is controlled by a separate PCI controller). * S3 resume doesn't work (FIXME) * The raminit is somewhat unstable, as the RAM training sometimes fails and sometimes succeeds, with the same couple of DIMMs. (FIXME) Untested: * Integrated GPU * Backside Mini PCI-E port * Ethernet in coreboot * Microsoft Windows Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/mainboard/sapphire/Kconfig | 16 + src/mainboard/sapphire/Kconfig.name | 2 + src/mainboard/sapphire/pureplatinumh61/Kconfig | 63 +++ .../sapphire/pureplatinumh61/Kconfig.name | 2 + .../sapphire/pureplatinumh61/Makefile.inc | 3 + src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl | 0 .../sapphire/pureplatinumh61/acpi/platform.asl | 30 ++ .../sapphire/pureplatinumh61/acpi/superio.asl | 0 .../sapphire/pureplatinumh61/acpi_tables.c | 1 + .../sapphire/pureplatinumh61/board_info.txt | 6 + .../sapphire/pureplatinumh61/devicetree.cb | 146 +++++++ src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 46 +++ .../sapphire/pureplatinumh61/early_southbridge.c | 82 ++++ src/mainboard/sapphire/pureplatinumh61/gnvs.c | 34 ++ src/mainboard/sapphire/pureplatinumh61/gpio.c | 185 +++++++++ src/mainboard/sapphire/pureplatinumh61/gpio_old.c | 433 +++++++++++++++++++++ src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 87 +++++ src/mainboard/sapphire/pureplatinumh61/mainboard.c | 38 ++ src/mainboard/sapphire/pureplatinumh61/romstage.c | 1 + 19 files changed, 1175 insertions(+) diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig new file mode 100644 index 0000000..130c1f4 --- /dev/null +++ b/src/mainboard/sapphire/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SAPPHIRE + +choice + prompt "Mainboard model" + +source "src/mainboard/sapphire/*/Kconfig.name" + +endchoice + +source "src/mainboard/sapphire/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Sapphire" + +endif # VENDOR_SAPPHIRE diff --git a/src/mainboard/sapphire/Kconfig.name b/src/mainboard/sapphire/Kconfig.name new file mode 100644 index 0000000..8ea84ad --- /dev/null +++ b/src/mainboard/sapphire/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SAPPHIRE + bool "Sapphire" diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig new file mode 100644 index 0000000..77ee428 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -0,0 +1,63 @@ +if BOARD_SAPPHIRE_PUREPLATINUMH61 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_LGA1155 + select SUPERIO_FINTEK_F71808A + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default sapphire/pureplatinumh61 + +config MAINBOARD_PART_NUMBER + string + default "PURE Platinum H61" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1007 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x174b + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 4 +endif diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig.name b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name new file mode 100644 index 0000000..7b642bd --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SAPPHIRE_PUREPLATINUMH61 + bool "Pure Platinum H61" diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc new file mode 100644 index 0000000..6064cea --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl new file mode 100644 index 0000000..ef07275 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/sapphire/pureplatinumh61/board_info.txt b/src/mainboard/sapphire/pureplatinumh61/board_info.txt new file mode 100644 index 0000000..c6360e2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb new file mode 100644 index 0000000..4e499d4 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -0,0 +1,146 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0a01" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x174b 0x1007 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x174b 0x1007 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x174b 0x1007 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x174b 0x1007 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x174b 0x1007 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x174b 0x1007 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x174b 0x1007 + chip superio/fintek/f71808a + register "multi_function_register_1" = "0x00" + register "multi_function_register_2" = "0xc4" + register "multi_function_register_3" = "0x21" + register "multi_function_register_4" = "0x2f" + register "multi_function_register_5" = "0x5c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86% + register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74% + register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62% + register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50% + register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2 + device pnp 4e.1 off # Serial Port 1 + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off end # Keyboard + device pnp 4e.6 on # GPIO + io 0xc5 = 0x1f + end + device pnp 4e.7 on # WDT + io 0x60 = 0xa00 + end + device pnp 4e.8 off end # CIR + device pnp 4e.a off end # PME, ACPI, EUP + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x174b 0x1007 + end + device pci 1f.3 on # SMBus + subsystemid 0x174b 0x1007 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x174b 0x1007 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x174b 0x1007 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl new file mode 100644 index 0000000..eb98bb2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c new file mode 100644 index 0000000..d9c5ee9 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; + RCBA32(0x3418) = 0x1fce1fe3; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gnvs.c b/src/mainboard/sapphire/pureplatinumh61/gnvs.c new file mode 100644 index 0000000..a790b0b --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gnvs.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c new file mode 100644 index 0000000..5d66f47 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio6 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio6 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_PWROK, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio35 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio35 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio_old.c b/src/mainboard/sapphire/pureplatinumh61/gpio_old.c new file mode 100644 index 0000000..2a1281b --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gpio_old.c @@ -0,0 +1,433 @@ +#include <southbridge/intel/common/gpio.h> +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_PWROK, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c new file mode 100644 index 0000000..cf723d0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0000, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x10ec0000), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c new file mode 100644 index 0000000..83cfd76 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002009; + RCBA32(0x38c4) = 0x00802009; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -0,0 +1 @@ +/* dummy file */

1 0

Patch set updated for coreboot: superio/fintek: Add support for Fintek F71808A
by Nicola Corna 05 Mar '17

05 Mar '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18563 -gerrit commit 74f05631e0a38752c9a795c3d3a8ccc4890e13ac Author: Nicola Corna <nicola(a)corna.info> Date: Thu Mar 2 08:08:45 2017 +0100 superio/fintek: Add support for Fintek F71808A Change-Id: Iba3f3dadf2b15071981f52d0b08da7847354bd23 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f71808a/Kconfig | 18 ++++++ src/superio/fintek/f71808a/Makefile.inc | 19 +++++++ src/superio/fintek/f71808a/chip.h | 53 ++++++++++++++++++ src/superio/fintek/f71808a/f71808a.h | 29 ++++++++++ src/superio/fintek/f71808a/f71808a_hwm.c | 77 ++++++++++++++++++++++++++ src/superio/fintek/f71808a/f71808a_multifunc.c | 57 +++++++++++++++++++ src/superio/fintek/f71808a/fintek_internal.h | 27 +++++++++ src/superio/fintek/f71808a/superio.c | 67 ++++++++++++++++++++++ 9 files changed, 348 insertions(+) diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66..2222644 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -17,6 +17,7 @@ romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c subdirs-y += f71805f +subdirs-y += f71808a subdirs-y += f71859 subdirs-y += f71863fg subdirs-y += f71869ad diff --git a/src/superio/fintek/f71808a/Kconfig b/src/superio/fintek/f71808a/Kconfig new file mode 100644 index 0000000..756f28d --- /dev/null +++ b/src/superio/fintek/f71808a/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_FINTEK_F71808A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71808a/Makefile.inc b/src/superio/fintek/f71808a/Makefile.inc new file mode 100644 index 0000000..f43e602 --- /dev/null +++ b/src/superio/fintek/f71808a/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += superio.c diff --git a/src/superio/fintek/f71808a/chip.h b/src/superio/fintek/f71808a/chip.h new file mode 100644 index 0000000..fae056d --- /dev/null +++ b/src/superio/fintek/f71808a/chip.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_CHIP_H +#define SUPERIO_FINTEK_F71808A_CHIP_H + +#include <stdint.h> + +struct superio_fintek_f71808a_config { + + /* Multi function registers */ + uint8_t multi_function_register_1; + uint8_t multi_function_register_2; + uint8_t multi_function_register_3; + uint8_t multi_function_register_4; + uint8_t multi_function_register_5; + + /* Intel Ibex Peak/PECI/AMD TSI */ + uint8_t hwm_peci_tsi_ctrl; + uint8_t hwm_tcc_temp; + + /* Fan 1 control */ + uint8_t hwm_fan1_seg1_speed; + uint8_t hwm_fan1_seg2_speed; + uint8_t hwm_fan1_seg3_speed; + uint8_t hwm_fan1_seg4_speed; + uint8_t hwm_fan1_seg5_speed; + uint8_t hwm_fan1_temp_src; + + /* Fan 2 control */ + uint8_t hwm_fan2_seg1_speed; + uint8_t hwm_fan2_seg2_speed; + uint8_t hwm_fan2_seg3_speed; + uint8_t hwm_fan2_seg4_speed; + uint8_t hwm_fan2_seg5_speed; + uint8_t hwm_fan2_temp_src; +}; + +#endif /* SUPERIO_FINTEK_F71808A_CHIP_H */ diff --git a/src/superio/fintek/f71808a/f71808a.h b/src/superio/fintek/f71808a/f71808a.h new file mode 100644 index 0000000..fbce494 --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_H +#define SUPERIO_FINTEK_F71808A_H + +/* Logical Device Numbers (LDN). */ +#define F71808A_SP1 0x01 /* UART1 */ +#define F71808A_HWM 0x04 /* Hardware monitor */ +#define F71808A_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71808A_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71808A_WDT 0x07 /* WDT */ +#define F71808A_CIR 0x08 /* CIR */ +#define F71808A_PME 0x0a /* Power Management Events (PME) and ACPI */ + +#endif /* SUPERIO_FINTEK_F71808A_H */ diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c new file mode 100644 index 0000000..9beb87c --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" + +/* Intel Ibex Peak/PECI/AMD TSI */ +#define HWM_PECI_TSI_CTRL_REG 0x0a +#define HWM_TCC_TEMPERATURE_REG 0x0c + +/* Fan 1 control */ +#define HWM_FAN1_SEG1_SPEED_REG 0xaa +#define HWM_FAN1_SEG2_SPEED_REG 0xab +#define HWM_FAN1_SEG3_SPEED_REG 0xac +#define HWM_FAN1_SEG4_SPEED_REG 0xad +#define HWM_FAN1_SEG5_SPEED_REG 0xae +#define HWM_FAN1_TEMP_SRC_REG 0xaf + +/* Fan 2 control */ +#define HWM_FAN2_SEG1_SPEED_REG 0xba +#define HWM_FAN2_SEG2_SPEED_REG 0xbb +#define HWM_FAN2_SEG3_SPEED_REG 0xbc +#define HWM_FAN2_SEG4_SPEED_REG 0xbd +#define HWM_FAN2_SEG5_SPEED_REG 0xbe +#define HWM_FAN2_TEMP_SRC_REG 0xbf + +void f71808a_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + const struct superio_fintek_f71808a_config *reg = dev->chip_info; + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + pnp_write_index(port, HWM_PECI_TSI_CTRL_REG, reg->hwm_peci_tsi_ctrl); + pnp_write_index(port, HWM_TCC_TEMPERATURE_REG, reg->hwm_tcc_temp); + + pnp_write_index(port, HWM_FAN1_SEG1_SPEED_REG, reg->hwm_fan1_seg1_speed); + pnp_write_index(port, HWM_FAN1_SEG2_SPEED_REG, reg->hwm_fan1_seg2_speed); + pnp_write_index(port, HWM_FAN1_SEG3_SPEED_REG, reg->hwm_fan1_seg3_speed); + pnp_write_index(port, HWM_FAN1_SEG4_SPEED_REG, reg->hwm_fan1_seg4_speed); + pnp_write_index(port, HWM_FAN1_SEG5_SPEED_REG, reg->hwm_fan1_seg5_speed); + pnp_write_index(port, HWM_FAN1_TEMP_SRC_REG, reg->hwm_fan1_temp_src); + + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_REG, reg->hwm_fan2_seg1_speed); + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_REG, reg->hwm_fan2_seg2_speed); + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_REG, reg->hwm_fan2_seg3_speed); + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_REG, reg->hwm_fan2_seg4_speed); + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_REG, reg->hwm_fan2_seg5_speed); + pnp_write_index(port, HWM_FAN2_TEMP_SRC_REG, reg->hwm_fan2_temp_src); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71808a/f71808a_multifunc.c b/src/superio/fintek/f71808a/f71808a_multifunc.c new file mode 100644 index 0000000..fe42c7b --- /dev/null +++ b/src/superio/fintek/f71808a/f71808a_multifunc.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define MULTI_FUNC_SEL_REG1 0x28 +#define MULTI_FUNC_SEL_REG2 0x29 +#define MULTI_FUNC_SEL_REG3 0x2A +#define MULTI_FUNC_SEL_REG4 0x2B +#define MULTI_FUNC_SEL_REG5 0x2C + +void f71808a_multifunc_init(struct device *dev) +{ + const struct superio_fintek_f71808a_config *conf = dev->chip_info; + + pnp_enter_conf_mode(dev); + + /* multi-func select reg1 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + + /* multi-func select reg2 (CLK_TUNE_EN = 0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + + /* multi-func select reg3 (CLK_TUNE_EN = 0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + + /* multi-func select reg4 (CLK_TUNE_EN = 0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + + /* multi-func select reg5 (CLK_TUNE_EN = 0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG5, + conf->multi_function_register_5); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71808a/fintek_internal.h b/src/superio/fintek/f71808a/fintek_internal.h new file mode 100644 index 0000000..715ae5d --- /dev/null +++ b/src/superio/fintek/f71808a/fintek_internal.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71808A_INTERNAL_H +#define SUPERIO_FINTEK_F71808A_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f71808a_multifunc_init(struct device *dev); +void f71808a_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F71808A_INTERNAL_H */ diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c new file mode 100644 index 0000000..53a8e85 --- /dev/null +++ b/src/superio/fintek/f71808a/superio.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include "f71808a.h" +#include "fintek_internal.h" + +static void f71808a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + /* TODO: Might potentially need code for UART, GPIO... */ + if (dev->path.pnp.device == F71808A_HWM) { + f71808a_multifunc_init(dev); + f71808a_hwm_init(dev); + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71808a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71808A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71808A_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71808A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71808A_GPIO, PNP_IRQ0, }, + { &ops, F71808A_WDT, }, + { &ops, F71808A_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71808A_PME, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71808a_ops = { + CHIP_NAME("Fintek F71808A Super I/O") + .enable_dev = enable_dev +};

1 0

Patch set updated for coreboot: util/superiotool: Add support for Fintek F71808A
by Nicola Corna 05 Mar '17

05 Mar '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18562 -gerrit commit 00f2e2a997105d0bf21d9881f9f90748bce5fb15 Author: Nicola Corna <nicola(a)corna.info> Date: Tue Feb 28 23:45:42 2017 +0100 util/superiotool: Add support for Fintek F71808A Default values taken from the datasheet and from the dump of an uninitialized F71808A on a Sapphire Pure Platinum H61. Both the control registers and the HWM configuration registers are added. Change-Id: Ia6e2a7c13a5086d19ebdb426f2f975b43220a273 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- util/superiotool/README | 1 + util/superiotool/fintek.c | 112 +++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 112 insertions(+), 1 deletion(-) diff --git a/util/superiotool/README b/util/superiotool/README index 7ff6138..1f6a20a 100644 --- a/util/superiotool/README +++ b/util/superiotool/README @@ -102,6 +102,7 @@ Josh Profitt <zorn169(a)gmail.com> Luc Verhaegen <libv(a)skynet.be> Michael Gold <mgold(a)ncf.ca> Michał Mirosław <mirq-linux(a)rere.qmqm.pl> +Nicola Corna <nicola(a)corna.info> Nikos Barkas <levelwol(a)gmail.com> Rasmus Wiman <rasmus(a)wiman.org> Robinson P. Tryon <bishop.robinson(a)gmail.com> diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 5a30652..22418cc 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -5,6 +5,7 @@ * Copyright (C) 2007-2008 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * Copyright (C) 2014 Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -74,6 +75,49 @@ static const struct superio_registers reg_table[] = { {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, {EOT}}}, + {0x0110, "F71808A", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,EOT}, + {0x00,0x00,0x10,0x01,0x19,0x34,0x00,0x00,0x11,0x00, + 0xc0,0x21,0x2f,0x5c,0x27,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xfe,0xff,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x01,0x29,EOT}}, + {0x6, "GPIO", + {0x70,0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xcb,0xcc, + 0xcd,0xce,0xcf,0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6, + 0xd7,0xd8,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2,0xf3, + EOT}, + {0x00,0x00,0x3f,NANA,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0xe0,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x1f,0x00,0x00,0x00,0xff,0x00,0x00, + EOT}}, + {0x7, "WDT", + {0x30,0x60,0x61,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + EOT}, + {0x00,0x00,0x00,0x03,NANA,NANA,NANA,0x00,0x0a,0x00, + EOT}}, + {0x8, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf8,0xf9,0xfa,0xfb, + 0xfc,0xfd,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x80,0x3b, + 0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI, and EUP Power Saving", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xec,0xed,0xee,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, + 0xf6,0xf7,0xf8,0xf9,0xfa,0xfd,EOT}, + {0x00,0x10,0xc0,0x00,0x13,0x09,0xc7,0x09,0x63,0x00, + 0x0f,0x00,0x00,0x00,0x00,NANA,0x00,NANA,0x06,0x3c, + 0x1f,0x00,0x00,0x00,0x00,NANA,EOT}}, + {EOT}}}, {0x0710, "F71869A/AD", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL, @@ -426,9 +470,64 @@ static const struct superio_registers reg_table[] = { {EOT} }; +static const struct superio_registers hwm_table[] = { + {0x0110, "F71808A", { + {NOLDN, NULL, + {0x01, 0x02, 0x03, 0x08, 0x0a, 0x0b, 0x0c, 0x0d, + 0x0f, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + /* 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, */ + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x66, 0x6b, 0x6c, + 0x6d, 0x6f, 0x7f, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x98, + 0x9b, 0x9c, 0x9e, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xec, 0xed, 0xee, + 0xef, EOT}, + {0x03, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x55, 0x00, + 0x20, + NANA, NANA, NANA, NANA, RSVD, RSVD, RSVD, NANA, + NANA, RSVD, RSVD, RSVD, RSVD, NANA, NANA, NANA, + /* RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, */ + 0x44, 0x00, NANA, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x40, + 0x04, 0x00, 0x00, + RSVD, RSVD, NANA, RSVD, NANA, RSVD, RSVD, RSVD, + NANA, NANA, NANA, NANA, NANA, RSVD, RSVD, + RSVD, RSVD, NANA, NANA, NANA, NANA, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, + 0x00, NANA, NANA, 0x00, 0x2e, 0xff, 0x05, 0x44, + 0x05, 0x55, 0x66, 0x00, + 0x03, 0xff, 0x00, 0x83, 0x03, 0xff, 0x3c, 0x32, + 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1d, + 0x0c, 0x25, 0x00, 0x80, 0x03, 0xff, 0x3c, 0x32, + 0x28, 0x1e, 0xff, 0xd9, 0xb2, 0x99, 0x80, 0x1e, + 0x0f, 0xff, RSVD, 0x7f, RSVD, RSVD, RSVD, RSVD, + RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, RSVD, 0x00, + NANA, NANA, NANA, NANA, NANA, 0x00, 0x01, 0x01, + 0x00, EOT}}, + {EOT}}}, + {EOT} +}; + void probe_idregs_fintek(uint16_t port) { - uint16_t vid, did; + uint16_t vid, did, hwmport; probing_for("Fintek", "", port); @@ -453,6 +552,17 @@ void probe_idregs_fintek(uint16_t port) dump_superio("Fintek", reg_table, port, did, LDN_SEL); + if (extra_dump) { + regwrite(port, LDN_SEL, 0x04); /* Select LDN 4 (HWM). */ + + /* Get HWM base address (stored in LDN 4, index 0x60/0x61). */ + hwmport = regval(port, 0x60) << 8; + hwmport |= regval(port, 0x61); + + printf("Hardware monitor (0x%04x)\n", hwmport); + dump_superio("Fintek-HWM", hwm_table, hwmport, did, LDN_SEL); + } + exit_conf_mode_winbond_fintek_ite_8787(port); }

1 0

Patch set updated for coreboot: soc/intel/glk: Use intel/common/block/systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18455 -gerrit commit df564dc551a6e8183e77000f81adaf213b4987eb Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:39:08 2017 +0530 soc/intel/glk: Use intel/common/block/systemagent code Change-Id: Ibde64058e9f23f25daabab82956cc360e693e422 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index 5566366..7205b4a 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/block/systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18456 -gerrit commit 7b93d552d3f72d8280647d470f68a03089decc74 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:43:43 2017 +0530 soc/intel/skylake: Use intel/common/block/systemagent code Change-Id: Ib471ef3d3ae96b69e2bdfaf81554325d0393900d Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/systemagent.c | 43 --------------------------- 3 files changed, 1 insertion(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 01ffa9b..c656bed 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 181e17b..dfda301 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/smbus.c -bootblock-y += bootblock/systemagent.c bootblock-y += flash_controller.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c deleted file mode 100644 index e76d4d2..0000000 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/bootblock.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> - -void bootblock_systemagent_early_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. - */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); -}

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Patch set updated for coreboot: soc/intel/apollolake: Clean up Systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18567 -gerrit commit 068c2da1b1ad2bc9b3d6a5ff623b1aa432cb7681 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Mar 4 23:39:47 2017 +0530 soc/intel/apollolake: Clean up Systemagent code Use common systemagent header. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 --- src/soc/intel/apollolake/bootblock/bootblock.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/include/soc/iomap.h | 2 ++ src/soc/intel/apollolake/include/soc/northbridge.h | 40 ---------------------- src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/northbridge.c | 2 +- src/soc/intel/apollolake/romstage.c | 2 +- 8 files changed, 7 insertions(+), 49 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4ff64d2..0322318 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -88,10 +88,6 @@ config SOC_INTEL_COMMON_RESET bool default y -config MMCONF_BASE_ADDRESS - hex "PCI MMIO Base Address" - default 0xe0000000 - config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" default 0xd0000000 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 1f5055d..4f4e25f 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <intelblocks/systemagent.h> #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -25,7 +26,6 @@ #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> -#include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/uart.h> diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1de41cf..5383082 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -26,6 +26,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/systemagent.h> #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -37,7 +38,6 @@ #include <spi-generic.h> #include <soc/pm.h> #include <soc/p2sb.h> -#include <soc/northbridge.h> #include "chip.h" diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 3c94d1b..5e65592 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,8 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define PCIEX_SIZE (256 * MiB) + #define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 #define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 #define PUNIT_THERMAL_DEVICE_IRQ 0x700C diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h deleted file mode 100644 index 04e369e..0000000 --- a/src/soc/intel/apollolake/include/soc/northbridge.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ -#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ - -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define PCIEX_SIZE (256 * MiB) - -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ - -/* IMR registers are found under MCHBAR. */ -#define MCHBAR_IMR0BASE 0x6870 -#define MCHBAR_IMR0MASK 0x6874 -#define MCH_IMR_PITCH 0x20 -#define MCH_NUM_IMRS 20 - -/* RAPL Package Power Limit register under MCHBAR. */ -#define MCHBAR_RAPL_PPL 0x70A8 - -#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index cccbffd..4a43136 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -27,7 +27,7 @@ #include <assert.h> #include <cbmem.h> #include <device/pci.h> -#include <soc/northbridge.h> +#include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/smm.h> diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index cc097ba..855df09 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/northbridge.h> +#include <intelblocks/systemagent.h> #include <soc/pci_ids.h> static uint32_t get_bar(device_t dev, unsigned int index) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 97be0f6..5195909 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -31,11 +31,11 @@ #include <fsp/api.h> #include <fsp/memmap.h> #include <fsp/util.h> +#include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> -#include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h>

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Patch set updated for coreboot: soc/intel/skylake: Clean up Systemagent code
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18566 -gerrit commit f6b1a25ab92284104860e3e7720aa05cfab3aaf0 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Mar 4 23:37:28 2017 +0530 soc/intel/skylake: Clean up Systemagent code Use common systemagent header. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 4 -- src/soc/intel/skylake/include/soc/bootblock.h | 3 +- src/soc/intel/skylake/include/soc/iomap.h | 3 + src/soc/intel/skylake/include/soc/systemagent.h | 78 +------------------------ 4 files changed, 6 insertions(+), 82 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7618fd3..01ffa9b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -148,10 +148,6 @@ config IED_REGION_SIZE hex default 0x400000 -config MMCONF_BASE_ADDRESS - hex "MMIO Base Address" - default 0xe0000000 - config MONOTONIC_TIMER_MSR def_bool y select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index df81d3f..f290d0f 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -16,6 +16,8 @@ #ifndef _SOC_SKYLAKE_BOOTBLOCK_H_ #define _SOC_SKYLAKE_BOOTBLOCK_H_ +#include <intelblocks/systemagent.h> + #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/bootblock.h> #else @@ -25,7 +27,6 @@ static inline void bootblock_fsp_temp_ram_init(void) {} /* Bootblock pre console init programing */ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); -void bootblock_systemagent_early_init(void); void pch_uart_init(void); /* Bootblock post console init programing */ diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index e736d3b..9f50c48 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -58,6 +58,9 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 +/* CPU Trace reserved memory size */ +#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index c82f691..81c6dd7 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -18,6 +18,7 @@ #ifndef _SOC_SYSTEMAGENT_H_ #define _SOC_SYSTEMAGENT_H_ +#include <intelblocks/systemagent.h> #include <soc/iomap.h> #define SA_IGD_OPROM_VENDEV 0x80860406 @@ -41,89 +42,12 @@ #define MCH_KABYLAKE_ID_Y 0x590c #define MCH_KABYLAKE_ID_H 0x5910 -/* Device 0:0.0 PCI configuration space */ - -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define GGC 0x50 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) -#define DPR 0x5c -#define DPR_EPM (1 << 2) -#define DPR_PRS (1 << 1) -#define DPR_SIZE_MASK 0xff0 - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define SKPAD 0xdc /* Scratchpad Data */ - /* MCHBAR */ #define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x)) #define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x)) -#define MCHBAR_PEI_VERSION 0x5034 -#define BIOS_RESET_CPL 0x5da8 -#define EDRAMBAR 0x5408 -#define MCH_PAIR 0x5418 -#define GDXCBAR 0x5420 - -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -/* PCODE MMIO communications live in the MCHBAR. */ -#define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1 << 31) -/* Errors are returned back in bits 7:0. */ -#define MAILBOX_BIOS_ERROR_NONE 0 -#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -#define MAILBOX_BIOS_ERROR_TIMEOUT 2 -#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 -#define MAILBOX_BIOS_ERROR_RESERVED 4 -#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 -#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 -#define MAILBOX_BIOS_ERROR_VR_ERROR 7 -/* Data is passed through bits 31:0 of the data register. */ -#define BIOS_MAILBOX_DATA 0x5da0 - -/* CPU Trace reserved memory size */ -#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ - /* System Agent identification */ u8 systemagent_revision(void);

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Patch set updated for coreboot: soc/intel/common/block: Add Intel common systemagent support[WIP]
by Subrata Banik 05 Mar '17

05 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18454 -gerrit commit 73f5de599b67a7e939f9cb8823dc6a0504a398dd Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sun Mar 5 13:19:42 2017 +0530 soc/intel/common/block: Add Intel common systemagent support[WIP] Create common Intel systemagent code. This code currently contains the SA initialization required in Bootblock phase, which has the following programming- * Set PCIEXBAR * Clear TSEG register More code will get added up in the subsequent phases. Change-Id: Ib8a77aec8b20bafd4175048d442701250f1aa9c8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/block/systemagent/Kconfig | 27 +++++++++++++++ .../intel/common/block/systemagent/Makefile.inc | 1 + .../intel/common/block/systemagent/systemagent.c | 39 ++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig new file mode 100644 index 0000000..da0e980 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -0,0 +1,27 @@ +config SOC_INTEL_COMMON_BLOCK_SA + bool + help + Intel Processor common System Agent support + +config PCIEX_BASE_ADDRESS + hex + default 0xe0000000 + +config SA_PCIEX_LENGTH + hex + default PCIEX_LENGTH_256MB if (SOC_INTEL_CAR_SMALL_CORE) + default PCIEX_LENGTH_64MB if (SOC_INTEL_CAR_BIG_CORE) + help + This option allows you to select length of PCIEX region. + +config PCIEX_LENGTH_256MB + hex + default 0x0 + +config PCIEX_LENGTH_128MB + hex + default 0x2 + +config PCIEX_LENGTH_64MB + hex + default 0x4 diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc new file mode 100644 index 0000000..75d5626 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -0,0 +1 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c new file mode 100644 index 0000000..7c356f9 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <intelblocks/systemagent.h> + +void bootblock_systemagent_early_init(void) +{ + uint32_t reg; + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + reg = CONFIG_PCIEX_BASE_ADDRESS | CONFIG_SA_PCIEX_LENGTH | 1; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + + /* + * Clear TSEG register - TSEG register comes out of reset with a + * non-zero default value. Clear this register to ensure that there are + * no surprises in CBMEM handling. + */ + pci_io_write_config32(SA_DEV_ROOT, TSEG, 0); +} +

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coreboot-gerrit March 2017