coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: util/scripts/get_maintainer.pl: Remove linux tree check
by Martin Roth 05 Mar '17

05 Mar '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18577 -gerrit commit ed4cb16783f4bd2eb0e12fb7e8ccdb2ad2e22bc9 Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 5 10:34:45 2017 -0700 util/scripts/get_maintainer.pl: Remove linux tree check This was removed from the previous version, but we'd like it in a separate patch, so it's obvious and can easily be applied to the next version. Change-Id: I9396009e82e762aa0cc037dbe9e7133962af6354 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/scripts/get_maintainer.pl | 5 ----- 1 file changed, 5 deletions(-) diff --git a/util/scripts/get_maintainer.pl b/util/scripts/get_maintainer.pl index 633f2dd..4f34a4e 100755 --- a/util/scripts/get_maintainer.pl +++ b/util/scripts/get_maintainer.pl @@ -297,11 +297,6 @@ if ($email && die "$P: Please select at least 1 email option\n"; } -if (!top_of_kernel_tree($lk_path)) { - die "$P: The current directory does not appear to be " - . "a linux kernel source tree.\n"; -} - ## Read MAINTAINERS for type/value pairs my @typevalue = ();

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Patch merged into coreboot/master: buildgcc: Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM
by gerrit＠coreboot.org 05 Mar '17

05 Mar '17

the following patch was just integrated into master: commit 03353de80b2c0604e778d81e9010af787a183ab3 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sat Oct 29 23:37:42 2016 +0800 buildgcc: Update GCC, Binutils, GMP, MPFR, GDB, IASL and LLVM - GCC gets updated from 5.2.0 to 6.3.0: gcc-6.3.0_riscv.patch is a diff between 5fcb8c4 and 173684b in riscv-gcc, and it needs gcc-6.3.0_memmodel.patch. - Binutils goes from 2.26.1 to 2.28: There is a build error for MIPS gold so I add patch for it. - GMP gets a bump from 6.1.0 to 6.1.2 - MPFR is updated from 3.1.4 to 3.1.5 - GDB is upgraded from 6.1.1 to 6.1.2 - IASL is changed from 20160831 to 20161222 - LLVM is changed from 3.8.0 to 3.9.1 Change-Id: I20fea838d798c430d8c4d2cc6b07614d967c60c5 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17189 Tested-by: build bot (Jenkins) See https://review.coreboot.org/17189 for details. -gerrit

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Patch set updated for coreboot: util/scripts: Update get_maintainer.pl to latest from linux kernel
by Martin Roth 05 Mar '17

05 Mar '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18571 -gerrit commit dc431eb542a6e16a141ac1335f44cb76f36c2158 Author: Martin Roth <martinroth(a)google.com> Date: Sat Mar 4 19:43:02 2017 -0700 util/scripts: Update get_maintainer.pl to latest from linux kernel This is version 03aed21 from linux/scripts, updated on Dec 12, 2016. The version needs to be updated because Perl version 5.20 deprecated the /C regex expression. Perl version 5.24 removed it completely, so the old version fails to run on the coreboot builders. Change-Id: Ib97997237ca64c65d7f91d568ae4bec000804331 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/scripts/get_maintainer.pl | 155 +++++++++++++++++++++++++++++++---------- 1 file changed, 117 insertions(+), 38 deletions(-) diff --git a/util/scripts/get_maintainer.pl b/util/scripts/get_maintainer.pl index 19a7725..633f2dd 100755 --- a/util/scripts/get_maintainer.pl +++ b/util/scripts/get_maintainer.pl @@ -16,7 +16,9 @@ my $P = $0; my $V = '0.26'; use Getopt::Long qw(:config no_auto_abbrev); +use Cwd; +my $cur_path = fastgetcwd() . '/'; my $lk_path = "./"; my $email = 1; my $email_usename = 1; @@ -42,10 +44,12 @@ my $output_multiline = 1; my $output_separator = ", "; my $output_roles = 0; my $output_rolestats = 1; +my $output_section_maxlen = 50; my $scm = 0; my $web = 0; my $subsystem = 0; my $status = 0; +my $letters = ""; my $keywords = 1; my $sections = 0; my $file_emails = 0; @@ -130,6 +134,7 @@ my %VCS_cmds_git = ( "author_pattern" => "^GitAuthor: (.*)", "subject_pattern" => "^GitSubject: (.*)", "stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$", + "file_exists_cmd" => "git ls-files \$file", ); my %VCS_cmds_hg = ( @@ -158,6 +163,7 @@ my %VCS_cmds_hg = ( "author_pattern" => "^HgAuthor: (.*)", "subject_pattern" => "^HgSubject: (.*)", "stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$", + "file_exists_cmd" => "hg files \$file", ); my $conf = which_conf(".get_maintainer.conf"); @@ -186,6 +192,27 @@ if (-f $conf) { unshift(@ARGV, @conf_args) if @conf_args; } +my @ignore_emails = (); +my $ignore_file = which_conf(".get_maintainer.ignore"); +if (-f $ignore_file) { + open(my $ignore, '<', "$ignore_file") + or warn "$P: Can't find a readable .get_maintainer.ignore file $!\n"; + while (<$ignore>) { + my $line = $_; + + $line =~ s/\s*\n?$//; + $line =~ s/^\s*//; + $line =~ s/\s+$//; + $line =~ s/#.*$//; + + next if ($line =~ m/^\s*$/); + if (rfc822_valid($line)) { + push(@ignore_emails, $line); + } + } + close($ignore); +} + if (!GetOptions( 'email!' => \$email, 'git!' => \$email_git, @@ -215,6 +242,7 @@ if (!GetOptions( 'status!' => \$status, 'scm!' => \$scm, 'web!' => \$web, + 'letters=s' => \$letters, 'pattern-depth=i' => \$pattern_depth, 'k|keywords!' => \$keywords, 'sections!' => \$sections, @@ -245,7 +273,8 @@ $output_multiline = 0 if ($output_separator ne ", "); $output_rolestats = 1 if ($interactive); $output_roles = 1 if ($output_rolestats); -if ($sections) { +if ($sections || $letters ne "") { + $sections = 1; $email = 0; $email_list = 0; $scm = 0; @@ -270,7 +299,7 @@ if ($email && if (!top_of_kernel_tree($lk_path)) { die "$P: The current directory does not appear to be " - . "a coreboot source tree.\n"; + . "a linux kernel source tree.\n"; } ## Read MAINTAINERS for type/value pairs @@ -283,7 +312,7 @@ open (my $maint, '<', "${lk_path}MAINTAINERS") while (<$maint>) { my $line = $_; - if ($line =~ m/^(\C):\s*(.*)/) { + if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; my $value = $2; @@ -406,7 +435,9 @@ foreach my $file (@ARGV) { die "$P: file '${file}' not found\n"; } } - if ($from_filename) { + if ($from_filename || ($file ne "&STDIN" && vcs_file_exists($file))) { + $file =~ s/^\Q${cur_path}\E//; #strip any absolute path + $file =~ s/^\Q${lk_path}\E//; #or the path to the lk tree push(@files, $file); if ($file ne "MAINTAINERS" && -f $file && ($keywords || $file_emails)) { open(my $f, '<', $file) @@ -513,12 +544,22 @@ if ($web) { exit($exit); +sub ignore_email_address { + my ($address) = @_; + + foreach my $ignore (@ignore_emails) { + return 1 if ($ignore eq $address); + } + + return 0; +} + sub range_is_maintained { my ($start, $end) = @_; for (my $i = $start; $i < $end; $i++) { my $line = $typevalue[$i]; - if ($line =~ m/^(\C):\s*(.*)/) { + if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; my $value = $2; if ($type eq 'S') { @@ -536,7 +577,7 @@ sub range_has_maintainer { for (my $i = $start; $i < $end; $i++) { my $line = $typevalue[$i]; - if ($line =~ m/^(\C):\s*(.*)/) { + if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; my $value = $2; if ($type eq 'M') { @@ -585,7 +626,7 @@ sub get_maintainers { for ($i = $start; $i < $end; $i++) { my $line = $typevalue[$i]; - if ($line =~ m/^(\C):\s*(.*)/) { + if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; my $value = $2; if ($type eq 'X') { @@ -600,7 +641,7 @@ sub get_maintainers { if (!$exclude) { for ($i = $start; $i < $end; $i++) { my $line = $typevalue[$i]; - if ($line =~ m/^(\C):\s*(.*)/) { + if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; my $value = $2; if ($type eq 'F') { @@ -644,8 +685,10 @@ sub get_maintainers { $line =~ s/\\\./\./g; ##Convert \. to . $line =~ s/\.\*/\*/g; ##Convert .* to * } - $line =~ s/^([A-Z]):/$1:\t/g; - print("$line\n"); + my $count = $line =~ s/^([A-Z]):/$1:\t/g; + if ($letters eq "" || (!$count || $letters =~ /$1/i)) { + print("$line\n"); + } } print("\n"); } @@ -749,6 +792,7 @@ MAINTAINER field selection options: --git-max-maintainers => maximum maintainers to add (default: $email_git_max_maintainers) --git-min-percent => minimum percentage of commits required (default: $email_git_min_percent) --git-blame => use git blame to find modified commits for patch or file + --git-blame-signatures => when used with --git-blame, also include all commit signers --git-since => git history to use (default: $email_git_since) --hg-since => hg history to use (default: $email_hg_since) --interactive => display a menu (mostly useful if used with the --git option) @@ -775,12 +819,13 @@ Other options: --pattern-depth => Number of pattern directory traversals (default: 0 (all)) --keywords => scan patch for keywords (default: $keywords) --sections => print all of the subsystem sections with pattern matches + --letters => print all matching 'letter' types from all matching sections --mailmap => use .mailmap file (default: $email_use_mailmap) --version => show version --help => show this help information Default options: - [--email --nogit --git-fallback --m --n --l --multiline -pattern-depth=0 + [--email --nogit --git-fallback --m --r --n --l --multiline --pattern-depth=0 --remove-duplicates --rolestats] Notes: @@ -812,6 +857,9 @@ Notes: Entries in this file can be any command line argument. This file is prepended to any additional command line arguments. Multiple lines and # comments are allowed. + Most options have both positive and negative forms. + The negative forms for --<foo> are --no<foo> and --no-<foo>. + EOT } @@ -821,11 +869,22 @@ sub top_of_kernel_tree { if ($lk_path ne "" && substr($lk_path,length($lk_path)-1,1) ne "/") { $lk_path .= "/"; } - if ( (-f "${lk_path}MAINTAINERS") + if ( (-f "${lk_path}COPYING") + && (-f "${lk_path}CREDITS") + && (-f "${lk_path}Kbuild") + && (-f "${lk_path}MAINTAINERS") && (-f "${lk_path}Makefile") + && (-f "${lk_path}README") && (-d "${lk_path}Documentation") - && (-d "${lk_path}src") - && (-d "${lk_path}util")) { + && (-d "${lk_path}arch") + && (-d "${lk_path}include") + && (-d "${lk_path}drivers") + && (-d "${lk_path}fs") + && (-d "${lk_path}init") + && (-d "${lk_path}ipc") + && (-d "${lk_path}kernel") + && (-d "${lk_path}lib") + && (-d "${lk_path}scripts")) { return 1; } return 0; @@ -890,7 +949,7 @@ sub find_first_section { while ($index < @typevalue) { my $tv = $typevalue[$index]; - if (($tv =~ m/^(\C):\s*(.*)/)) { + if (($tv =~ m/^([A-Z]):\s*(.*)/)) { last; } $index++; @@ -904,7 +963,7 @@ sub find_starting_index { while ($index > 0) { my $tv = $typevalue[$index]; - if (!($tv =~ m/^(\C):\s*(.*)/)) { + if (!($tv =~ m/^([A-Z]):\s*(.*)/)) { last; } $index--; @@ -918,7 +977,7 @@ sub find_ending_index { while ($index < @typevalue) { my $tv = $typevalue[$index]; - if (!($tv =~ m/^(\C):\s*(.*)/)) { + if (!($tv =~ m/^([A-Z]):\s*(.*)/)) { last; } $index++; @@ -927,24 +986,33 @@ sub find_ending_index { return $index; } -sub get_maintainer_role { +sub get_subsystem_name { my ($index) = @_; - my $i; my $start = find_starting_index($index); - my $end = find_ending_index($index); - my $role = "unknown"; my $subsystem = $typevalue[$start]; - if (length($subsystem) > 20) { - $subsystem = substr($subsystem, 0, 17); + if ($output_section_maxlen && length($subsystem) > $output_section_maxlen) { + $subsystem = substr($subsystem, 0, $output_section_maxlen - 3); $subsystem =~ s/\s*$//; $subsystem = $subsystem . "..."; } + return $subsystem; +} + +sub get_maintainer_role { + my ($index) = @_; + + my $i; + my $start = find_starting_index($index); + my $end = find_ending_index($index); + + my $role = "unknown"; + my $subsystem = get_subsystem_name($index); for ($i = $start + 1; $i < $end; $i++) { my $tv = $typevalue[$i]; - if ($tv =~ m/^(\C):\s*(.*)/) { + if ($tv =~ m/^([A-Z]):\s*(.*)/) { my $ptype = $1; my $pvalue = $2; if ($ptype eq "S") { @@ -974,16 +1042,7 @@ sub get_maintainer_role { sub get_list_role { my ($index) = @_; - my $i; - my $start = find_starting_index($index); - my $end = find_ending_index($index); - - my $subsystem = $typevalue[$start]; - if (length($subsystem) > 20) { - $subsystem = substr($subsystem, 0, 17); - $subsystem =~ s/\s*$//; - $subsystem = $subsystem . "..."; - } + my $subsystem = get_subsystem_name($index); if ($subsystem eq "THE REST") { $subsystem = ""; @@ -1003,7 +1062,7 @@ sub add_categories { for ($i = $start + 1; $i < $end; $i++) { my $tv = $typevalue[$i]; - if ($tv =~ m/^(\C):\s*(.*)/) { + if ($tv =~ m/^([A-Z]):\s*(.*)/) { my $ptype = $1; my $pvalue = $2; if ($ptype eq "L") { @@ -1045,7 +1104,7 @@ sub add_categories { if ($name eq "") { if ($i > 0) { my $tv = $typevalue[$i - 1]; - if ($tv =~ m/^(\C):\s*(.*)/) { + if ($tv =~ m/^([A-Z]):\s*(.*)/) { if ($1 eq "P") { $name = $2; $pvalue = format_email($name, $address, $email_usename); @@ -1062,7 +1121,7 @@ sub add_categories { if ($name eq "") { if ($i > 0) { my $tv = $typevalue[$i - 1]; - if ($tv =~ m/^(\C):\s*(.*)/) { + if ($tv =~ m/^([A-Z]):\s*(.*)/) { if ($1 eq "P") { $name = $2; $pvalue = format_email($name, $address, $email_usename); @@ -1071,7 +1130,8 @@ sub add_categories { } } if ($email_reviewer) { - push_email_addresses($pvalue, 'reviewer'); + my $subsystem = get_subsystem_name($i); + push_email_addresses($pvalue, "reviewer:$subsystem"); } } elsif ($ptype eq "T") { push(@scm, $pvalue); @@ -1857,6 +1917,7 @@ sub vcs_assign { my $percent = $sign_offs * 100 / $divisor; $percent = 100 if ($percent > 100); + next if (ignore_email_address($line)); $count++; last if ($sign_offs < $email_git_min_signatures || $count > $email_git_max_maintainers || @@ -2071,6 +2132,24 @@ sub vcs_file_blame { } } +sub vcs_file_exists { + my ($file) = @_; + + my $exists; + + my $vcs_used = vcs_exists(); + return 0 if (!$vcs_used); + + my $cmd = $VCS_cmds{"file_exists_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + $cmd .= " 2>&1"; + $exists = &{$VCS_cmds{"execute_cmd"}}($cmd); + + return 0 if ($? != 0); + + return $exists; +} + sub uniq { my (@parms) = @_;

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Patch set updated for coreboot: [RFC] mainboard/sapphire/pureplatinumh61: Add new board
by Nicola Corna 05 Mar '17

05 Mar '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18564 -gerrit commit 7ed3db3e114804183a305eb4996212002c1f6d1c Author: Nicola Corna <nicola(a)corna.info> Date: Fri Mar 3 18:04:48 2017 +0100 [RFC] mainboard/sapphire/pureplatinumh61: Add new board Add support for Sapphire Pure Platinum H61 This board has a socketed SOIC-8 4 MB flash chip. All the flash regions are unlocked by default but unfortunately flashrom doesn't work on this platform; the stock UEFI flash tool refuses to flash the coreboot image (different image ID), but maybe it can be spoofed. For now, the external programmer seems to be the only option. Everything works well, with the following exceptions: * The USB 3.0 doesn't work in coreboot (as it is controlled by a separate PCI controller). * S3 resume doesn't work (FIXME) * The raminit is somewhat unstable, as the RAM training sometimes fails and sometimes succeeds, with the same couple of DIMMs. (FIXME) Untested: * Integrated GPU * Backside Mini PCI-E port * Ethernet in coreboot * Microsoft Windows Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/mainboard/sapphire/Kconfig | 16 ++ src/mainboard/sapphire/Kconfig.name | 2 + src/mainboard/sapphire/pureplatinumh61/Kconfig | 63 +++++++ .../sapphire/pureplatinumh61/Kconfig.name | 2 + .../sapphire/pureplatinumh61/Makefile.inc | 3 + src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl | 0 .../sapphire/pureplatinumh61/acpi/platform.asl | 30 ++++ .../sapphire/pureplatinumh61/acpi/superio.asl | 0 .../sapphire/pureplatinumh61/acpi_tables.c | 1 + .../sapphire/pureplatinumh61/board_info.txt | 6 + .../sapphire/pureplatinumh61/devicetree.cb | 162 ++++++++++++++++++ src/mainboard/sapphire/pureplatinumh61/dsdt.asl | 46 +++++ .../sapphire/pureplatinumh61/early_southbridge.c | 82 +++++++++ src/mainboard/sapphire/pureplatinumh61/gnvs.c | 34 ++++ src/mainboard/sapphire/pureplatinumh61/gpio.c | 185 +++++++++++++++++++++ src/mainboard/sapphire/pureplatinumh61/hda_verb.c | 87 ++++++++++ src/mainboard/sapphire/pureplatinumh61/mainboard.c | 38 +++++ src/mainboard/sapphire/pureplatinumh61/romstage.c | 1 + 18 files changed, 758 insertions(+) diff --git a/src/mainboard/sapphire/Kconfig b/src/mainboard/sapphire/Kconfig new file mode 100644 index 0000000..130c1f4 --- /dev/null +++ b/src/mainboard/sapphire/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SAPPHIRE + +choice + prompt "Mainboard model" + +source "src/mainboard/sapphire/*/Kconfig.name" + +endchoice + +source "src/mainboard/sapphire/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Sapphire" + +endif # VENDOR_SAPPHIRE diff --git a/src/mainboard/sapphire/Kconfig.name b/src/mainboard/sapphire/Kconfig.name new file mode 100644 index 0000000..8ea84ad --- /dev/null +++ b/src/mainboard/sapphire/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SAPPHIRE + bool "Sapphire" diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig b/src/mainboard/sapphire/pureplatinumh61/Kconfig new file mode 100644 index 0000000..77ee428 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig @@ -0,0 +1,63 @@ +if BOARD_SAPPHIRE_PUREPLATINUMH61 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_LGA1155 + select SUPERIO_FINTEK_F71808A + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default sapphire/pureplatinumh61 + +config MAINBOARD_PART_NUMBER + string + default "PURE Platinum H61" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1007 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x174b + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 4 +endif diff --git a/src/mainboard/sapphire/pureplatinumh61/Kconfig.name b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name new file mode 100644 index 0000000..7b642bd --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SAPPHIRE_PUREPLATINUMH61 + bool "Pure Platinum H61" diff --git a/src/mainboard/sapphire/pureplatinumh61/Makefile.inc b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc new file mode 100644 index 0000000..6064cea --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl new file mode 100644 index 0000000..ef07275 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi/platform.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl b/src/mainboard/sapphire/pureplatinumh61/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/sapphire/pureplatinumh61/board_info.txt b/src/mainboard/sapphire/pureplatinumh61/board_info.txt new file mode 100644 index 0000000..c6360e2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb new file mode 100644 index 0000000..1612188 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -0,0 +1,162 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0a01" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x174b 0x1007 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x174b 0x1007 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x174b 0x1007 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x174b 0x1007 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x174b 0x1007 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x174b 0x1007 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x174b 0x1007 + chip superio/fintek/f71808a + register "multi_function_register_1" = "0x00" + register "multi_function_register_2" = "0xc4" + register "multi_function_register_3" = "0x21" + register "multi_function_register_4" = "0x2f" + register "multi_function_register_5" = "0x5c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x66" # TCC temperature = 102 °C + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xdb" # Fan 1 segment 2 = 86% + register "hwm_fan1_seg3_speed" = "0xbc" # Fan 1 segment 3 = 74% + register "hwm_fan1_seg4_speed" = "0x9e" # Fan 1 segment 4 = 62% + register "hwm_fan1_seg5_speed" = "0x7f" # Fan 1 segment 5 = 50% + register "hwm_fan1_temp_src" = "0x18" # Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xdb" # Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xbc" # Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x9e" # Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x7f" # Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # Fan 2 source = temperature 2 + device pnp 4e.1 off end # Serial Port 1 + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off end # Keyboard + device pnp 4e.6 on # GPIO + io 0xc5 = 0x1f + end + device pnp 4e.7 on # WDT + io 0x60 = 0xa00 + end + device pnp 4e.8 off end # CIR + device pnp 4e.a off end # PME, ACPI, EUP + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x174b 0x1007 + end + device pci 1f.3 on # SMBus + subsystemid 0x174b 0x1007 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x174b 0x1007 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x174b 0x1007 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl new file mode 100644 index 0000000..eb98bb2 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c new file mode 100644 index 0000000..d9c5ee9 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/early_southbridge.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; + RCBA32(0x3418) = 0x1fce1fe3; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gnvs.c b/src/mainboard/sapphire/pureplatinumh61/gnvs.c new file mode 100644 index 0000000..a790b0b --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gnvs.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sapphire/pureplatinumh61/gpio.c b/src/mainboard/sapphire/pureplatinumh61/gpio.c new file mode 100644 index 0000000..5d66f47 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/gpio.c @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio6 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio6 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_PWROK, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio35 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio35 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio35 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c new file mode 100644 index 0000000..cf723d0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10ec0000, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x10ec0000), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014c10), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x01011c12), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x01016c11), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x01012c14), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x01813c4f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x0321403f), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x0145e130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sapphire/pureplatinumh61/mainboard.c b/src/mainboard/sapphire/pureplatinumh61/mainboard.c new file mode 100644 index 0000000..83cfd76 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002009; + RCBA32(0x38c4) = 0x00802009; + RCBA32(0x38c0) = 0x00000007; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -0,0 +1 @@ +/* dummy file */

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Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit 0f5fa5bae34064d6e83d2e02e0164bfd86a9514c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1d6c8ff..9e9f44e 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit fbacd523cd2e5c5ccdae0013606cb38d5497e8de Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Mar 5 10:57:02 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit46 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index dfa90cc..56b7da7 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -56,17 +56,22 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); + } else { /* Does not feature internal graphics */ + pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); - /* * Disabling IGD later is possible but somehow reclaiming its UMA * resources fails so enable/disable IGD before raminit if external

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Patch set updated for coreboot: nb/x4x: Disable IGD when external GPU is found
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit 9c09a6fc2c3369755a17b670b98d61ce90d01905 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x: Disable IGD when external GPU is found This disables IGD before raminit if an external GPU is found unless CONFIG_ONBOARD_VGA_IS_PRIMARY is set. TESTED on ga-g41m-es2l Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++++++++++++ src/northbridge/intel/x4x/x4x.h | 1 + 2 files changed, 26 insertions(+) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc9..dfa90cc 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -24,10 +24,12 @@ #include <console/console.h> #include <halt.h> #include <romstage_handoff.h> +#include <device/pci_def.h> void x4x_early_init(void) { const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); + u32 reg32; /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); @@ -64,6 +66,29 @@ void x4x_early_init(void) gfxsize = 6; } pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); + + /* + * Disabling IGD later is possible but somehow reclaiming its UMA + * resources fails so enable/disable IGD before raminit if external + * GPU is found. + * NOTE: PCI specifies that one needs to wait at least 100msec after + * reset. In practise GPUs seem to get detected fine without this. + */ + if (pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS) & (1 << 6) && + !IS_ENABLED(CONFIG_ONBOARD_VGA_IS_PRIMARY)) { + pci_write_config8(PCI_DEV(0, 0x01, 0), PCI_SECONDARY_BUS, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), + PCI_SUBORDINATE_BUS, 0x0a); + reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); + if (reg32 == 0x030000) { + printk(BIOS_DEBUG,"External GPU is found." + " xDisabling IGD before raminit\n"); + reg32 = pci_read_config32(d0f0, D0F0_DEVEN); + pci_write_config32(d0f0, D0F0_DEVEN, + reg32 & ~(IGD0EN | IGD1EN)); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); + } + } } static void init_egress(void) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index faae775..834128b 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -60,6 +60,7 @@ */ #define PEG_CAP 0xa2 #define SLOTCAP 0xb4 +#define SLOTSTS 0xba #define PEGLC 0xec #define D1F0_VCCAP 0x104 #define D1F0_VC0RCTL 0x114

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Patch set updated for coreboot: util/intelmetool: Fix segfault on edge cases
by Huan Truong 05 Mar '17

05 Mar '17

Huan Truong (htruong(a)tnhh.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18573 -gerrit commit 49c21ab9c5947338147de096682489378ea6d5ba Author: Huan Truong <htruong(a)tnhh.net> Date: Sun Mar 5 02:24:51 2017 -0600 util/intelmetool: Fix segfault on edge cases The intel ME checker tool would segfault if it reaches the end of the loop without having the dev pointer set. This happens when it gets to the end of the previous loop without knowing what to do with any of the devices it sees. This patch makes sure the pointer is not NULL before accessing it. Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a Signed-off-by: Huan Truong <htruong(a)tnhh.net> --- util/intelmetool/intelmetool.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/intelmetool/intelmetool.c b/util/intelmetool/intelmetool.c index 70b23fb..45e8c8f 100644 --- a/util/intelmetool/intelmetool.c +++ b/util/intelmetool/intelmetool.c @@ -137,7 +137,8 @@ static int pci_platform_scan() { } } - if (!PCI_DEV_HAS_ME_DISABLE(dev->device_id) && + if (dev != NULL && + !PCI_DEV_HAS_ME_DISABLE(dev->device_id) && !PCI_DEV_HAS_ME_DIFFICULT(dev->device_id) && !PCI_DEV_CAN_DISABLE_ME_IF_PRESENT(dev->device_id) && !PCI_DEV_ME_NOT_SURE(dev->device_id)) {

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Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit 82ed28050126f94be0e395a6bf5696175a9d0077 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1d6c8ff..9e9f44e 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -196,8 +196,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -206,10 +210,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 05 Mar '17

05 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit dd6ac8cc193ae5f97fed9a0b453685e9f2780c59 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Mar 5 10:57:02 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit46 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index dfa90cc..56b7da7 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -56,17 +56,22 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); + } else { /* Does not feature internal graphics */ + pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); - /* * Disabling IGD later is possible but somehow reclaiming its UMA * resources fails so enable/disable IGD before raminit if external

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coreboot-gerrit March 2017