coreboot-gerrit March 2017

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Patch set updated for coreboot: [NOTFORMERGE] agesa-wrapper-killer
by Kyösti Mälkki 06 Mar '17

06 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18477 -gerrit commit 4db5d37ac4b1d3012bf8a9d5b700bba19c23c051 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 20:50:53 2017 +0200 [NOTFORMERGE] agesa-wrapper-killer Change-Id: I5fcfed645ccc6f3c78b5050535d97dc95e82ed94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/agesa/amd_late_init.c | 42 --- src/cpu/amd/agesa/cache_as_ram.inc | 92 ++--- src/cpu/amd/agesa/family12/Makefile.inc | 1 + src/cpu/amd/agesa/family12/fixme.c | 3 +- src/cpu/amd/agesa/family12/romstage.c | 37 ++ src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/cpu/amd/agesa/family14/fixme.c | 4 +- src/cpu/amd/agesa/family14/romstage.c | 33 ++ src/cpu/amd/agesa/family15/Makefile.inc | 1 + src/cpu/amd/agesa/family15/fixme.c | 3 +- src/cpu/amd/agesa/family15/romstage.c | 56 ++++ src/cpu/amd/agesa/family15rl/Makefile.inc | 1 + src/cpu/amd/agesa/family15rl/fixme.c | 3 +- src/cpu/amd/agesa/family15rl/romstage.c | 29 ++ src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/fixme.c | 3 +- src/cpu/amd/agesa/family15tn/romstage.c | 30 ++ src/cpu/amd/agesa/family16kb/Makefile.inc | 1 + src/cpu/amd/agesa/family16kb/fixme.c | 3 +- src/cpu/amd/agesa/family16kb/romstage.c | 29 ++ src/cpu/amd/agesa/heapmanager.c | 2 +- src/cpu/amd/agesa/romstage.c | 101 ++++++ src/cpu/amd/agesa/s3_resume.c | 45 +-- src/cpu/amd/agesa/s3_resume.h | 18 +- src/include/cpu/amd/car.h | 11 +- src/mainboard/amd/dinar/BiosCallOuts.c | 2 +- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/OemCustomize.c | 19 +- src/mainboard/amd/dinar/acpi_tables.c | 1 - src/mainboard/amd/dinar/romstage.c | 78 +---- src/mainboard/amd/inagua/OemCustomize.c | 18 +- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/inagua/acpi_tables.c | 1 - src/mainboard/amd/inagua/romstage.c | 65 +--- src/mainboard/amd/olivehill/Kconfig | 1 + src/mainboard/amd/olivehill/OemCustomize.c | 28 +- src/mainboard/amd/olivehill/acpi_tables.c | 1 - src/mainboard/amd/olivehill/mainboard.c | 6 +- src/mainboard/amd/olivehill/romstage.c | 82 +---- src/mainboard/amd/parmer/Kconfig | 1 + src/mainboard/amd/parmer/OemCustomize.c | 28 +- src/mainboard/amd/parmer/acpi_tables.c | 1 - src/mainboard/amd/parmer/mainboard.c | 5 +- src/mainboard/amd/parmer/romstage.c | 76 +---- src/mainboard/amd/persimmon/OemCustomize.c | 18 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 5 - src/mainboard/amd/persimmon/acpi_tables.c | 1 - src/mainboard/amd/persimmon/mainboard.c | 1 - src/mainboard/amd/persimmon/romstage.c | 82 +---- src/mainboard/amd/south_station/OemCustomize.c | 18 +- .../amd/south_station/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/south_station/acpi_tables.c | 1 - src/mainboard/amd/south_station/romstage.c | 63 +--- src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/thatcher/OemCustomize.c | 28 +- src/mainboard/amd/thatcher/acpi_tables.c | 1 - src/mainboard/amd/thatcher/mainboard.c | 5 +- src/mainboard/amd/thatcher/romstage.c | 81 +---- src/mainboard/amd/torpedo/OemCustomize.c | 19 +- src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/torpedo/acpi_tables.c | 1 - src/mainboard/amd/torpedo/romstage.c | 75 +---- src/mainboard/amd/union_station/OemCustomize.c | 18 +- .../amd/union_station/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/union_station/acpi_tables.c | 1 - src/mainboard/amd/union_station/romstage.c | 64 +--- src/mainboard/asrock/e350m1/OemCustomize.c | 18 +- .../asrock/e350m1/PlatformGnbPcieComplex.h | 4 - src/mainboard/asrock/e350m1/acpi_tables.c | 1 - src/mainboard/asrock/e350m1/romstage.c | 81 +---- src/mainboard/asrock/imb-a180/Kconfig | 1 + src/mainboard/asrock/imb-a180/OemCustomize.c | 29 +- src/mainboard/asrock/imb-a180/acpi_tables.c | 1 - src/mainboard/asrock/imb-a180/mainboard.c | 6 +- src/mainboard/asrock/imb-a180/romstage.c | 91 +---- src/mainboard/asus/f2a85-m/Kconfig | 1 + src/mainboard/asus/f2a85-m/OemCustomize.c | 39 ++- src/mainboard/asus/f2a85-m/acpi_tables.c | 1 - src/mainboard/asus/f2a85-m/mainboard.c | 6 +- src/mainboard/asus/f2a85-m/romstage.c | 151 +++------ src/mainboard/asus/f2a85-m_le/Kconfig | 1 + src/mainboard/asus/f2a85-m_le/OemCustomize.c | 27 -- src/mainboard/bap/ode_e20XX/OemCustomize.c | 28 +- src/mainboard/bap/ode_e20XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e20XX/mainboard.c | 6 +- src/mainboard/bap/ode_e20XX/romstage.c | 80 +---- src/mainboard/biostar/am1ml/Kconfig | 1 + src/mainboard/biostar/am1ml/OemCustomize.c | 28 +- src/mainboard/biostar/am1ml/acpi_tables.c | 1 - src/mainboard/biostar/am1ml/mainboard.c | 6 +- src/mainboard/biostar/am1ml/romstage.c | 111 ++---- src/mainboard/elmex/pcm205400/OemCustomize.c | 18 +- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 5 - src/mainboard/elmex/pcm205400/acpi_tables.c | 1 - src/mainboard/elmex/pcm205400/mainboard.c | 1 - src/mainboard/elmex/pcm205400/romstage.c | 83 +---- src/mainboard/gizmosphere/gizmo/OemCustomize.c | 18 +- .../gizmosphere/gizmo/PlatformGnbPcieComplex.h | 5 - src/mainboard/gizmosphere/gizmo/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo/mainboard.c | 1 - src/mainboard/gizmosphere/gizmo/romstage.c | 80 +---- src/mainboard/gizmosphere/gizmo2/Kconfig | 1 + src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 28 +- src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/mainboard.c | 7 +- src/mainboard/gizmosphere/gizmo2/romstage.c | 91 +---- src/mainboard/hp/abm/OemCustomize.c | 28 +- src/mainboard/hp/abm/acpi_tables.c | 1 - src/mainboard/hp/abm/mainboard.c | 6 +- src/mainboard/hp/abm/romstage.c | 94 ++---- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c | 28 +- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 8 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 70 +--- src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 18 +- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 3 - src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 1 - src/mainboard/jetway/nf81-t56n-lf/romstage.c | 98 +----- src/mainboard/lenovo/g505s/Kconfig | 1 + src/mainboard/lenovo/g505s/OemCustomize.c | 28 +- src/mainboard/lenovo/g505s/acpi_tables.c | 1 - src/mainboard/lenovo/g505s/mainboard.c | 7 +- src/mainboard/lenovo/g505s/romstage.c | 70 +--- .../lippert/frontrunner-af/OemCustomize.c | 18 +- .../frontrunner-af/PlatformGnbPcieComplex.h | 5 - src/mainboard/lippert/frontrunner-af/acpi_tables.c | 1 - src/mainboard/lippert/frontrunner-af/mainboard.c | 1 - src/mainboard/lippert/frontrunner-af/romstage.c | 98 +----- src/mainboard/lippert/toucan-af/OemCustomize.c | 18 +- .../lippert/toucan-af/PlatformGnbPcieComplex.h | 5 - src/mainboard/lippert/toucan-af/acpi_tables.c | 1 - src/mainboard/lippert/toucan-af/mainboard.c | 1 - src/mainboard/lippert/toucan-af/romstage.c | 98 +----- src/mainboard/msi/ms7721/OemCustomize.c | 29 +- src/mainboard/msi/ms7721/acpi_tables.c | 1 - src/mainboard/msi/ms7721/mainboard.c | 6 +- src/mainboard/msi/ms7721/romstage.c | 135 ++------ src/mainboard/pcengines/apu1/OemCustomize.c | 18 +- .../pcengines/apu1/PlatformGnbPcieComplex.h | 5 - src/mainboard/pcengines/apu1/acpi_tables.c | 1 - src/mainboard/pcengines/apu1/mainboard.c | 1 - src/mainboard/pcengines/apu1/romstage.c | 93 +----- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/OemCustomize.c | 18 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 1 - src/mainboard/supermicro/h8qgi/romstage.c | 62 +--- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8scm/OemCustomize.c | 20 +- src/mainboard/supermicro/h8scm/acpi_tables.c | 1 - src/mainboard/supermicro/h8scm/romstage.c | 78 +---- src/mainboard/tyan/s8226/BiosCallOuts.c | 2 +- src/mainboard/tyan/s8226/OemCustomize.c | 18 +- src/mainboard/tyan/s8226/acpi_tables.c | 1 - src/mainboard/tyan/s8226/romstage.c | 62 +--- src/northbridge/amd/agesa/Makefile.inc | 7 +- src/northbridge/amd/agesa/agesa_helper.h | 55 +++ src/northbridge/amd/agesa/agesawrapper.c | 352 ------------------- src/northbridge/amd/agesa/agesawrapper.h | 75 ----- src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/agesa/eventlog.c | 36 +- src/northbridge/amd/agesa/family10/reset_test.h | 1 + src/northbridge/amd/agesa/family12/Makefile.inc | 3 + src/northbridge/amd/agesa/family12/northbridge.c | 23 +- src/northbridge/amd/agesa/family12/state_machine.c | 90 +++++ src/northbridge/amd/agesa/family14/Makefile.inc | 3 + src/northbridge/amd/agesa/family14/northbridge.c | 31 +- src/northbridge/amd/agesa/family14/state_machine.c | 86 +++++ src/northbridge/amd/agesa/family15/Makefile.inc | 3 + src/northbridge/amd/agesa/family15/northbridge.c | 20 +- src/northbridge/amd/agesa/family15/state_machine.c | 78 +++++ src/northbridge/amd/agesa/family15rl/Makefile.inc | 3 + src/northbridge/amd/agesa/family15rl/northbridge.c | 20 +- .../amd/agesa/family15rl/state_machine.c | 84 +++++ src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 + src/northbridge/amd/agesa/family15tn/northbridge.c | 20 +- .../amd/agesa/family15tn/state_machine.c | 84 +++++ src/northbridge/amd/agesa/family16kb/Makefile.inc | 3 + src/northbridge/amd/agesa/family16kb/northbridge.c | 20 +- .../amd/agesa/family16kb/state_machine.c | 84 +++++ src/northbridge/amd/agesa/oem_s3.c | 3 +- src/northbridge/amd/agesa/state_machine.c | 372 +++++++++++++++++++++ src/northbridge/amd/agesa/state_machine.h | 83 +++++ src/southbridge/amd/agesa/hudson/Makefile.inc | 2 - src/southbridge/amd/agesa/hudson/agesawrapper.c | 92 ----- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 3 +- 189 files changed, 2175 insertions(+), 3361 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 60bae12..b9dae57 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,10 +24,10 @@ romstage-y += s3_resume.c ramstage-y += s3_mtrr.c cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +romstage-y += romstage.c romstage-y += heapmanager.c ramstage-y += heapmanager.c -ramstage-y += amd_late_init.c ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c deleted file mode 100644 index a55ebd8..0000000 --- a/src/cpu/amd/agesa/amd_late_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <bootstate.h> - -#include <northbridge/amd/agesa/agesawrapper.h> - -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif - -static void agesawrapper_post_device(void *unused) -{ - if (acpi_is_wakeup_s3()) - return; - - agesawrapper_amdinitlate(); - -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif - if (!acpi_s3_resume_allowed()) - return; - - agesawrapper_amdS3Save(); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 24db600..f43e6a4 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -26,43 +26,24 @@ #include "gcccar.inc" #include <cpu/x86/cache.h> -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup, cache_as_ram_setup_out cache_as_ram_setup: - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ + /* Preserve BIST. */ + movl %eax, %ebp - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 + post_code(0xa0) post_code(0xa1) + /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK + /* Align the stack to 128 bits. No harm on i386, required on x86_64? */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -105,42 +86,36 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the cpu_init_detected */ - cvtsd2si %xmm1, %esi - /* Pass the BIST result */ - cvtsd2si %xmm0, %edi + .code64 + + /* Calling conventions preserve BIST in %ebp. */ - /* align the stack */ - and $0xFFFFFFF0, %esp + call early_all_cores + + movl %ebp, %edi + call romstage_main + movl %eax, %ebx - .code64 - call cache_as_ram_main .code32 #else - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx + /* Calling conventions preserve BIST in %ebp. */ - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx + call early_all_cores + + pushl %ebp + call romstage_main + movl %eax, %ebx - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main #endif - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop +/* Register %ebx is new stacktop for remaining of romstage. + * It is the only register preserved in AMD_DISABLE_STACK. + */ disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -152,13 +127,20 @@ disable_cache_as_ram: movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0 - xorl %eax, %eax - /* Restore the return stack */ wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret + +#ifdef __x86_64__ +.code64 +#endif + + movl %ebx, %esp + call romstage_after_car + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop cache_as_ram_setup_out: #ifdef __x86_64__ diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 578e178..1a7465d 100644 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,6 +28,7 @@ #***************************************************************************** romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index deeb8b9..d946e1b 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c new file mode 100644 index 0000000..e803f60 --- /dev/null +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include "sb_cimx.h" +#include "SbPlatform.h" +#include "platform_cfg.h" + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + gpioEarlyInit(); + + sb_poweron_init(); + + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 9b4e76b..3da8dd5 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 9a171ed..7d59585 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -14,7 +14,9 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c new file mode 100644 index 0000000..67affbf --- /dev/null +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + sb_Poweron_Init(); + + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index 5742e7a..d01cb2a 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c index 7b8598d..03f4dff 100644 --- a/src/cpu/amd/agesa/family15/fixme.c +++ b/src/cpu/amd/agesa/family15/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" UINT64 diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c new file mode 100644 index 0000000..d7f6d38 --- /dev/null +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include "northbridge/amd/agesa/family10/reset_test.h" +#include <nb_cimx.h> +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + nb_Poweron_Init(); + + sb_Poweron_Init(); + + board_BeforeAgesa(cb); +} + +#if 0 + /* after AMD_INIT_EARLY, before AMD_INIT_POST */ + nb_Ht_Init(); + + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + distinguish_cpu_resets(0); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } +#endif diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15rl/Makefile.inc +++ b/src/cpu/amd/agesa/family15rl/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15rl/fixme.c b/src/cpu/amd/agesa/family15rl/fixme.c index b35d115..2eb9689 100644 --- a/src/cpu/amd/agesa/family15rl/fixme.c +++ b/src/cpu/amd/agesa/family15rl/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c new file mode 100644 index 0000000..d7c7c11 --- /dev/null +++ b/src/cpu/amd/agesa/family15rl/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index b35d115..2eb9689 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c new file mode 100644 index 0000000..2cf436d --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 9367b45..5c2ba8f 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index d1bc4bc..4ea52cc 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c new file mode 100644 index 0000000..d7c7c11 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 087959d..9acd0bd 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -17,7 +17,7 @@ #include "heapManager.h" #include <cbmem.h> -#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c new file mode 100644 index 0000000..1c5ef12 --- /dev/null +++ b/src/cpu/amd/agesa/romstage.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/amd/car.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <halt.h> +#include <program_loading.h> +#include <smp/node.h> +#include <string.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/state_machine.h> + +static void fill_sysinfo(struct sysinfo *cb) +{ + memset(cb, 0, sizeof(*cb)); + cb->s3resume = acpi_is_wakeup_s3(); + + agesa_set_interface(cb); +} + +void * asmlinkage romstage_main(unsigned long bist) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); + + fill_sysinfo(cb); + + if ((initial_apic_id == 0) && boot_cpu()) { + + platform_once(cb); + + console_init(); + } + + printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + initial_apic_id, cpuid_eax(1)); + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + if (!cb->s3resume) + agesa_execute_state(cb, AMD_INIT_POST); + else + agesa_execute_state(cb, AMD_INIT_RESUME); + + uintptr_t stack_top = CACHE_TMP_RAMTOP; + if (cb->s3resume) { + if (!cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } + stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += HIGH_ROMSTAGE_STACK_SIZE; + } + + printk(BIOS_DEBUG, "Move CAR stack.\n"); + return (void*)stack_top; +} + +void asmlinkage romstage_after_car(void) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + printk(BIOS_DEBUG, "CAR disabled.\n"); + + fill_sysinfo(cb); + + if (!cb->s3resume) + agesa_execute_state(cb, AMD_INIT_ENV); + else + agesa_execute_state(cb, AMD_S3LATE_RESTORE); + + if (cb->s3resume) + set_resume_cache(); + + run_ramstage(); +} diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 1e4aadb..34717b9 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -25,32 +25,9 @@ #include <string.h> #include <halt.h> #include "s3_resume.h" +#include <northbridge/amd/agesa/agesa_helper.h> -static void move_stack_high_mem(void) -{ - uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - if (!high_stack) - halt(); - - /* TODO: Make the switch with empty stack instead. */ - memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); - - /* TODO: We only switch stack on BSP. */ -#ifdef __x86_64__ - __asm__ - volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#else - __asm__ - volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#endif -} - -static void set_resume_cache(void) +void set_resume_cache(void) { msr_t msr; @@ -74,21 +51,3 @@ static void set_resume_cache(void) enable_cache(); } - -void prepare_for_resume(void) -{ - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - -} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index ff23966..37ce0d5 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -17,25 +17,9 @@ #define S3_RESUME_H void restore_mtrr(void); -void prepare_for_resume(void); +void set_resume_cache(void); void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); -void *GetHeapBase(void); -void EmptyHeap(void); -void ResumeHeap(void **heap, size_t *len); - -#define BSP_STACK_BASE_ADDR 0x30000 - -#if 1 -/* This covers node 0 only. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) -#else -/* This covers total of 8 nodes. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) -#endif - -#define HIGH_MEMORY_SCRATCH 0x30000 - #endif diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 6950a38..f0ba31c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,7 +1,11 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H +#include <arch/cpu.h> + +#if IS_ENABLED(CONFIG_CPU_AMD_GEODE_GX2) void main(unsigned long bist); +#endif void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void done_cache_as_ram_main(void); @@ -10,8 +14,13 @@ void post_cache_as_ram(void); void cache_as_ram_switch_stack(void *stacktop); void cache_as_ram_new_stack(void); -#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI +#if IS_ENABLED(CONFIG_CPU_AMD_PI) void disable_cache_as_ram(void); #endif +void asmlinkage early_all_cores(void); + +void * asmlinkage romstage_main(unsigned long bist); +void asmlinkage romstage_after_car(void); + #endif diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 004fe3e..21e066b 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index b80af9c..32142fe 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES + #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID select GFXUMA diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c index 84866de..dfd5189 100644 --- a/src/mainboard/amd/dinar/OemCustomize.c +++ b/src/mainboard/amd/dinar/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -27,7 +31,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { // Dinar has the following routing: // CS0 M[B,A]_CLK_H/L[0] // CS1 M[B,A]_CLK_H/L[2] @@ -38,15 +42,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; - -static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost) +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; InitPost->MemConfig.UmaMode = UMA_AUTO; InitPost->MemConfig.BottomIo = 0xE0; InitPost->MemConfig.UmaSize = 0xE0-0xC0; - return AGESA_SUCCESS; } -const struct OEM_HOOK OemCustomize = { - .InitPost = OemInitPost, -}; +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index c205d08..5e2b22f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam15.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 0edc346..201bfa1 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -15,44 +15,23 @@ #include <stdint.h> #include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include <cpu/x86/lapic.h> #include "nb_cimx.h" #include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + sch4037_early_init(0x2e); + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { - - post_code(0x30); - - sch4037_early_init(0x2e); - - sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - post_code(0x31); - console_init(); - /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. @@ -60,47 +39,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr56x0_rd890_disable_pcie_bridge(); } - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - if(boot_cpu()) { - post_code(0x34); - sb_Poweron_Init(); - } - - post_code(0x35); - agesawrapper_amdinitreset(); - - post_code(0x36); - agesawrapper_amdinitearly(); - - post_code(0x37); - nb_Poweron_Init(); - post_code(0x38); - nb_Ht_Init(); - - - post_code(0x39); - agesawrapper_amdinitpost(); - - post_code(0x40); - agesawrapper_amdinitenv(); - - - post_code(0x43); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x44); - copy_and_run(); - - post_code(0x45); // Should never see this post code. -} +#endif diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index d1f715c..092acf8 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -38,7 +38,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -126,7 +126,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -140,12 +139,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 60045e1..30f674a 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3d0eecf..e4fcdfe 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -13,71 +13,14 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 37fb43f..2f3b849 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index 70c5035..b55b4d5 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 61272d0..3560c85 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -22,8 +22,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /********************************************** * enable the dedicated function in mainboard. @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index bb1ad30..f52f9d4 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,29 +17,21 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -49,67 +41,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index aecf065..ab92d8c 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index fb6177a..33a49da 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -157,7 +157,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -189,14 +189,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -221,7 +213,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index a902bad..d8003f8 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index c519772..1e471bc 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /************************************************* * enable the dedicated function in parmer board. @@ -31,9 +31,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 1f251ab..1736d48 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -13,83 +13,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - post_code(0x54); /* Should never see this post code. */ + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); } diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364e..abc20ed 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -36,7 +36,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index 4132c7c..0342e8e 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index e0440f2..c2fc613 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index c8a8d74..f7dd9e5 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -13,90 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 74b0aa8..25e129e 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -38,7 +38,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -134,7 +134,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,12 +147,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 95f6dde..f7dd9e5 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -13,71 +13,14 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 73487b0..2ce919a 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_SMSC_LPC47N217 select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 66058f2..81318ce 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -163,7 +163,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -215,14 +215,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -236,7 +228,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -247,7 +239,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index a902bad..d8003f8 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index c89ce5a..2ee8ba5 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /************************************************* * enable the dedicated function in thatcher board. @@ -46,9 +46,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 147f31a..4f7a872 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -22,88 +22,41 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> + #include <superio/smsc/lpc47n217/lpc47n217.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); + byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - *(u8 *)0xfed80101 = 0x98; - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - post_code(0x50); - copy_and_run(); + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - post_code(0x54); /* Should never see this post code. */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; } diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 3c20047..568e683 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -16,9 +16,10 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> +#include "amdlib.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE @@ -105,7 +106,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *LlanoPcieComplexListPtr; @@ -159,7 +160,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -173,12 +173,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index a0b3933..050b311 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam12.h> extern u32 apicid_sb900; diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index d28608e..e4fcdfe 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -13,81 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> -#include "sb_cimx.h" -#include "SbPlatform.h" -#include <arch/cpu.h> -#include "platform_cfg.h" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x35); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - gpioEarlyInit(); - sb_poweron_init(); - - post_code(0x31); - - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - post_code(0x32); - post_code(0x33); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x36); - agesawrapper_amdinitreset(); - - post_code(0x37); - agesawrapper_amdinitearly(); - - post_code(0x38); - agesawrapper_amdinitpost(); - - post_code(0x39); - printk(BIOS_DEBUG, "sb_before_pci_init "); - sb_before_pci_init(); - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x40); - agesawrapper_amdinitenv(); - - post_code(0x43); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run returned!\n"); - - post_code(0x44); // Should never see this post code. + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 6f4dbfc..d97ba65 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -140,7 +140,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -154,12 +153,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7a5d348..f2b00bc 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -13,68 +13,8 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" +#include <northbridge/amd/agesa/state_machine.h> -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index ab563ae..4f4baa9 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -120,7 +120,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -134,12 +133,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 07f985a..83daa6e 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 82fbecf..292ecf2 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -13,87 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ +void board_BeforeAgesa(struct sysinfo *cb) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index e118bfb..e666549 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index aec1343..aa0b1ef 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( @@ -183,7 +175,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} + diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 61272d0..3560c85 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -22,8 +22,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /********************************************** * enable the dedicated function in mainboard. @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 29d831d..ff401c6 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -21,45 +21,26 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val, t32; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7); - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + volatile u32* addr32; + u32 t32; /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); @@ -76,64 +57,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); +#endif - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 04eb936..5d1a00c 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 6348d5a..ccd955a 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -139,7 +139,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -190,14 +190,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -205,14 +197,13 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) *---------------------------------------------------------------------------------------- */ -#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -225,9 +216,25 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ PSO_END }; -#endif /* CONFIG_BOARD_ASUS_F2A85_M */ -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, +static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + PSO_END }; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M; + else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} + diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index 2d4ab69..53ad1bc 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 2566037..114db4d 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> @@ -46,9 +45,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 51cadc7..4217f66 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -14,29 +14,19 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smbus.h> -#include <stdint.h> -#include <string.h> + #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) @@ -58,97 +48,50 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - -#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) - hudson_pci_port80(); -#endif -#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) - hudson_lpc_port80(); -#endif - - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(GPIO_DEV); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - - /* set DDR3 voltage */ - byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - - /* default is byte = 0x0, so no need to set it in this case */ - if (byte) - do_smbus_write_byte(0xb20, 0x15, 0x3, byte); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(GPIO_DEV); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/mainboard/asus/f2a85-m_le/Kconfig b/src/mainboard/asus/f2a85-m_le/Kconfig index a81f700..d771e6c 100644 --- a/src/mainboard/asus/f2a85-m_le/Kconfig +++ b/src/mainboard/asus/f2a85-m_le/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/asus/f2a85-m_le/OemCustomize.c b/src/mainboard/asus/f2a85-m_le/OemCustomize.c index ea1c871..c8a48d9 100644 --- a/src/mainboard/asus/f2a85-m_le/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m_le/OemCustomize.c @@ -1,28 +1 @@ #include "../f2a85-m/OemCustomize.c" -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE) -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), - -/* - TODO: is this OK for DDR3 socket FM2? - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - */ - PSO_END -}; -#endif /* CONFIG_BOARD_ASUS_F2A85M_LE */ diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 752293a..dabd778 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -105,7 +105,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -127,14 +127,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,7 +140,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -174,7 +166,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index baddf0b..7e729f0 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -28,8 +28,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -121,9 +120,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index a43d035..5c3328e 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -15,36 +15,21 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> -#include "cbmem.h" + #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); +#if 0 /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -52,62 +37,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 1b131dd..513975d 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index c44a994..f54fd69 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index 1818e08..430aeb3 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index 7dc9f4d..f4ea2f3 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -25,8 +25,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> #include <southbridge/amd/common/amd_pci_util.h> @@ -112,9 +111,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 1672349..20708cc 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -14,26 +14,13 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -105,17 +92,13 @@ static void ite_gpio_conf(pnp_devfn_t dev) ite_exit_conf (dev); } - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val, t32; u8 byte; pci_devfn_t dev; u32 *addr32; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -146,75 +129,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - post_code(0x30); - post_code(0x31); - - /* run ite */ - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - printk(BIOS_DEBUG, "Console inited!\n"); - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); - post_code(0x50); /* This functions configure SIO as it been done under vendor bios */ printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); ite_evc_conf(ENVC_DEV); @@ -222,7 +147,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_gpio_conf(GPIO_DEV); printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - copy_and_run(); - post_code(0x54); /* Should never see this post code. */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); } diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 825364e..71f4b80 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -36,7 +36,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h index 0f3fdc6..0bea897 100644 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - /* * GNB GPP Port4 * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index e0440f2..c2fc613 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index c8a8d74..1fbdd4b 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -13,90 +13,13 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index 2184fb2..2cd31ed 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -23,7 +23,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*---------------------------------------------------------------------------------------*/ /** @@ -41,7 +41,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -137,7 +137,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -151,7 +150,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), @@ -168,6 +167,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h index 66618ae..acdb655 100644 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h @@ -17,11 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 49f4e1f..5992401 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -21,7 +21,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 00847e0..98cafae 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <delay.h> diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 6d06621..8dec7fe 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -14,84 +14,8 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/state_machine.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index f5509f6..e07e584 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index 933b036..9bcff35 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -114,7 +114,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -136,14 +136,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -157,7 +149,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -183,7 +175,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index baddf0b..ad4f9c9 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -28,8 +28,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -120,10 +119,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index bb1ad30..283bea1 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -13,33 +13,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -48,68 +32,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); +} - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index 730c97e..7b3a7b2 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -21,7 +21,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -116,7 +116,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -138,14 +138,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -159,7 +151,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -178,7 +170,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index 45e2f81..4af8678 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -20,8 +20,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> @@ -114,9 +113,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 02ebbc9..88ba01a 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -14,45 +14,35 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val, t32; u32 *addr32; + u32 t32; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ + /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x01, 0xcd7); @@ -71,58 +61,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffff7b; // clear 2, 7 *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index f78cfba..e235e01 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 605c7d3..48229d0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index 4100f8f..3beb713 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index d20bc87..146c843 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -44,11 +43,8 @@ static void mainboard_enable(device_t dev) hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - else + if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); - } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 714743b..c05b87a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -13,76 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index f980a15..10ddfbd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -17,7 +17,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -35,7 +35,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; void *BrazosPcieComplexListPtr; @@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /** @@ -188,12 +187,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings. */ -const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index a91bd0f..782f5c2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -17,9 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include <vendorcode/amd/agesa/f14/AGESA.h> -#include <amdlib.h> - /** * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) * diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 07f985a..83daa6e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d8ad645..801d493 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 85a4343..189d1fb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -14,105 +14,15 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> - -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> - -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/car.h> -#include <sb_cimx.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <device/pnp_def.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index aac3a84..9d771ac 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 605c7d3..48229d0 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index 4100f8f..3beb713 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index bcc3cf2..579fbc0 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -44,9 +43,7 @@ static void mainboard_enable(device_t dev) hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - else + if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); } diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 714743b..c05b87a 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -13,76 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 63466b9..93d1463 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h index 9f99f32..0f0b41b 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 10b7504..a846528 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 37dc37f..8a54555 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -13,93 +13,25 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all - * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = agesawrapper_amdinitpost(); - if (val == 7) /* fatal, amdinitenv below is going to hang */ - outb(0x06, 0x0cf9); /* reset system harder instead */ - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } + +#if 0 + post_code(0x40); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all + * hang, looks like DRAM re-init goes wrong, don't know why. */ + val = agesawrapper_amdinitpost(); + if (val == 7) /* fatal, amdinitenv below is going to hang */ + outb(0x06, 0x0cf9); /* reset system harder instead */ + + post_code(0x42); + agesawrapper_amdinitenv(); +#endif diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index a5f4921..f8fc812 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index 50c8f08..017ea77 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index a80c9fd..7647ebe 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index adc2987..5128db0 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -13,94 +13,26 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all - * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = agesawrapper_amdinitpost(); - if (val == 7) /* fatal, amdinitenv below is going to hang */ - outb(0x06, 0x0cf9); /* reset system harder instead */ - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } + +#if 0 + post_code(0x40); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all + * hang, looks like DRAM re-init goes wrong, don't know why. */ + val = agesawrapper_amdinitpost(); + if (val == 7) /* fatal, amdinitenv below is going to hang */ + outb(0x06, 0x0cf9); /* reset system harder instead */ + + post_code(0x42); + agesawrapper_amdinitenv(); +#endif diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 90bc5a9..d082328 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -18,7 +18,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -146,7 +146,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -197,14 +197,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -218,7 +210,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -232,7 +224,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index 2d4ab69..53ad1bc 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 2566037..114db4d 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> @@ -46,9 +45,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 9ce47f2..b82dfa6 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -15,30 +15,18 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> +#include <device/pnp.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <southbridge/amd/agesa/hudson/smbus.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -#include <stdint.h> -#include <string.h> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff @@ -122,91 +110,40 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - -#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) - hudson_pci_port80(); -#endif -#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) - hudson_lpc_port80(); -#endif - - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Initialize GPIO registers */ - gpio_init(GPIO_DEV); - - /* Enable serial console */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Initialize GPIO registers */ + gpio_init(GPIO_DEV); + + /* Enable serial console */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 20acb27..3c24c2a 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -17,7 +17,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -35,7 +35,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -124,7 +124,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -138,7 +137,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), @@ -155,6 +154,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h index bb4ba86..64adf5c 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h @@ -17,11 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 055cd58..a678559 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include <smbios.h> #include <string.h> diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index a74d247..50b51cc 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,99 +15,16 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/cimx/cimx_util.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" +#include "SB800.h" #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -static void early_lpc_init(void); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - early_lpc_init(); - - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} - static void early_lpc_init(void) { u32 mmio_base; @@ -140,3 +57,9 @@ static void early_lpc_init(void) configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); } + +void board_BeforeAgesa(struct sysinfo *cb) +{ + early_lpc_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 9a91568..d89324c 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/supermicro/h8qgi/OemCustomize.c b/src/mainboard/supermicro/h8qgi/OemCustomize.c index 9f340c6..999709b 100644 --- a/src/mainboard/supermicro/h8qgi/OemCustomize.c +++ b/src/mainboard/supermicro/h8qgi/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -37,7 +41,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, @@ -65,5 +69,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 19ffbdf..9597f8d 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -17,14 +17,9 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/cpu.h> #include <console/console.h> -#include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> @@ -36,34 +31,15 @@ */ #define SIO_PORT 0x164e -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - post_code(0x35); - console_init(); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -76,16 +52,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -95,23 +72,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 2449b6c..4f89128 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/supermicro/h8scm/OemCustomize.c b/src/mainboard/supermicro/h8scm/OemCustomize.c index 634d06b..8554093 100644 --- a/src/mainboard/supermicro/h8scm/OemCustomize.c +++ b/src/mainboard/supermicro/h8scm/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -35,10 +39,10 @@ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. - * I am not sure whether DefaultPlatformMemoryConfiguration is necessary. + * I am not sure whether PlatformMemoryTable is necessary. * If I comment out these code, H8SCM will still pass mem training. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, @@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 918d9ad..43eb661 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -17,52 +17,29 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/cpu.h> #include <console/console.h> -#include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +/* though UARTs are on the NUVOTON BMC, port 0x164E + * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E + */ +#define SIO_PORT 0x164e -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); + wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -75,37 +52,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); - - post_code(0x3C); - nb_Ht_Init(); - - post_code(0x3D); - /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - distinguish_cpu_resets(0); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index fea32cb..83809a5 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/tyan/s8226/OemCustomize.c b/src/mainboard/tyan/s8226/OemCustomize.c index d3a8f4b..354ded4 100644 --- a/src/mainboard/tyan/s8226/OemCustomize.c +++ b/src/mainboard/tyan/s8226/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -37,7 +41,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, @@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index d43c04b..7670b04 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -20,11 +20,10 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> @@ -34,39 +33,19 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - /* For serial port. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ w83627dhg_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -79,16 +58,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -99,22 +79,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 62a5df1..1d153ac 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -23,8 +23,11 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += def_callouts.c agesawrapper.c eventlog.c -ramstage-y += def_callouts.c agesawrapper.c eventlog.c +romstage-y += def_callouts.c eventlog.c +ramstage-y += def_callouts.c eventlog.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c romstage-y += oem_s3.c ramstage-y += oem_s3.c diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h new file mode 100644 index 0000000..82963c1 --- /dev/null +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _AGESA_HELPER_H_ +#define _AGESA_HELPER_H_ + +#include <stddef.h> + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +void *agesawrapper_getlateinitptr (int pick); + +void amd_initcpuio(void); +void amd_initmmio(void); +void amd_initenv(void); + +void *GetHeapBase(void); +void EmptyHeap(void); +void ResumeHeap(void **heap, size_t *len); + +#define BSP_STACK_BASE_ADDR 0x30000 + +#if 1 +/* This covers node 0 only. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) +#else +/* This covers total of 8 nodes. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) +#endif + +#define HIGH_MEMORY_SCRATCH 0x30000 + + +#endif /* _AGESA_HELPER_H_ */ diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c deleted file mode 100644 index a72e239..0000000 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - -#include "heapManager.h" - -static const struct OEM_HOOK *OemHook = &OemCustomize; - -#if defined(__PRE_RAM__) - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitEarly) - OemHook->InitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitPost) - OemHook->InitPost(PostParams); - - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, &PostParams->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemInitResume(AmdResumeParamsPtr); - - status = AmdInitResume(AmdResumeParamsPtr); - - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; - - status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, &EnvParam->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; -#endif - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemS3LateRestore(AmdS3LateParamsPtr); - - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} - -#else /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitMid) - OemHook->InitMid(MidParam); - - status = AmdInitMid(MidParam); - AGESA_EVENTLOG(status, &MidParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - OemS3Save(AmdS3SaveParamsPtr); - - AmdReleaseStruct(&AmdInterfaceParams); - - return status; -} - -/* We will reference AmdLateParams later to copy ACPI tables. */ -static AMD_LATE_PARAMS *AmdLateParams = NULL; - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; -#endif - - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); - ASSERT(status == AGESA_SUCCESS); - - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ - return status; -} - -void *agesawrapper_getlateinitptr(int pick) -{ - ASSERT(AmdLateParams != NULL); - - switch (pick) { - case PICK_DMI: - return AmdLateParams->DmiTable; - case PICK_PSTATE: - return AmdLateParams->AcpiPState; - case PICK_SRAT: - return AmdLateParams->AcpiSrat; - case PICK_SLIT: - return AmdLateParams->AcpiSlit; - case PICK_WHEA_MCE: - return AmdLateParams->AcpiWheaMce; - case PICK_WHEA_CMC: - return AmdLateParams->AcpiWheaCmc; - case PICK_ALIB: - return AmdLateParams->AcpiAlib; - case PICK_IVRS: -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) - return NULL; -#else - return AmdLateParams->AcpiIvrs; -#endif - default: - return NULL; - } - return NULL; -} - -#endif /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) -{ - AGESA_STATUS status; - AP_EXE_PARAMS ApExeParams; - - memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status, &ApExeParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h deleted file mode 100644 index f5d52d6..0000000 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); -#define AGESA_EVENTLOG(status, stdheader) \ - agesawrapper_trace(status, stdheader, __func__) - -void amd_initcpuio(void); -void amd_initmmio(void); -void amd_initenv(void); - -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -struct OEM_HOOK -{ - /* romstage */ - AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *); - AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *); - - /* ramstage */ - AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *); -}; - -extern const struct OEM_HOOK OemCustomize; - -/* For suspend-to-ram support. */ -AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); -AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 0805c02..3d97c30 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -20,7 +20,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include "BiosCallOuts.h" #include "dimmSpd.h" diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 0a40672..1deca6c 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -15,12 +15,46 @@ #include <stdint.h> #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" #include "AGESA.h" #include "AMD.h" +#include <heapManager.h> + +static const char undefined[] = "undefined"; + +/* Match order of enum AGESA_STRUCT_NAME. */ +static const char *AgesaFunctionNameStr[] = { + "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", + "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", + "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", +}; + +/* heapManager.h */ +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +const char *agesa_struct_name(int state) +{ + if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) + return undefined; + + int index = state - AMD_INIT_RECOVERY; + return AgesaFunctionNameStr[index]; +} + +const char *heap_status_name(int status) +{ + if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) + return undefined; + + int index = status - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} /* * Possible AGESA_STATUS values: diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index cb67de1..48634ea 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -18,6 +18,7 @@ #ifndef _RESET_TEST_H_ #define _RESET_TEST_H_ +#include <arch/io.h> #include "amdfam10.h" /* NODE_PCI */ #define NODE_ID 0x60 diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc index 6b2ca78..ad39325 100644 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ b/src/northbridge/amd/agesa/family12/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c8198c9..7dba9a5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -32,7 +32,9 @@ #include <cpu/amd/mtrr.h> #include "sb_cimx.h" -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define FX_DEVS 1 @@ -632,24 +634,6 @@ static void domain_set_resources(device_t dev) } -static void domain_enable_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Must be called after PCI enumeration and resource allocation */ -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Mid_Post_Init(); -#endif - - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - /* Bus related code */ static void cpu_bus_init(device_t dev) @@ -790,7 +774,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c new file mode 100644 index 0000000..2fd6617 --- /dev/null +++ b/src/northbridge/amd/agesa/family12/state_machine.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <cpu/amd/agesa/s3_resume.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + Post->MemConfig.SaveMemContextCtl = 0; + Post->MemConfig.MemRestoreCtl = 0; +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); + + sb_before_pci_init(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + sb_After_Pci_Init(); +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + sb_Mid_Post_Init(); + + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} + diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 6b2ca78..ad39325 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b8d9c6f..2f04a01 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -31,10 +31,10 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#if CONFIG_AMD_SB_CIMX +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + #include <sb_cimx.h> -#endif #define FX_DEVS 1 @@ -614,30 +614,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) -{ -#if CONFIG_AMD_SB_CIMX - if (!acpi_is_wakeup_s3()) { - sb_After_Pci_Init(); - sb_Mid_Post_Init(); - } else { - sb_After_Pci_Restore_Init(); - } -#endif - - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - static const char *domain_acpi_name(struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -818,7 +794,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c new file mode 100644 index 0000000..b9af710 --- /dev/null +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + amd_initenv(); +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); + + sb_After_Pci_Restore_Init(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 3cf4ed1..3021ef4 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 9cfaed9..f1e6a99 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -632,21 +634,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); - -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); -#endif - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -849,7 +836,6 @@ static void f15_pci_domain_scan_bus(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = f15_pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c new file mode 100644 index 0000000..60d1810 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + Post->MemConfig.SaveMemContextCtl = 0; + Post->MemConfig.MemRestoreCtl = 0; +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ +} +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} + diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc index a188a91..9e9283c 100644 --- a/src/northbridge/amd/agesa/family15rl/Makefile.inc +++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d003be5..f0b9c38 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -38,7 +38,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -629,21 +631,6 @@ static void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(struct device *dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -842,7 +829,6 @@ static void domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15rl/state_machine.c b/src/northbridge/amd/agesa/family15rl/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family15rl/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index a188a91..9e9283c 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2f05334..e5a540c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -628,21 +630,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -839,7 +826,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 3cf4ed1..3021ef4 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28a4f91..8517e9a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -643,21 +645,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -858,7 +845,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index c7d23ff..5f1cc9e 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -19,8 +19,9 @@ #include <cbmem.h> #include <program_loading.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <AGESA.h> +#include <northbridge/amd/agesa/agesa_helper.h> typedef enum { S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/northbridge/amd/agesa/state_machine.c new file mode 100644 index 0000000..3a6daaa --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.c @@ -0,0 +1,372 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include <arch/acpi.h> +#include <bootstate.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +#include "AMD.h" +#include "heapManager.h" +#include "Dispatcher.h" + + +#if ENV_ROMSTAGE +#include <PlatformMemoryConfiguration.h> +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; +#endif + +#if ENV_RAMSTAGE +static void completion_InitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); +#endif + +struct agesa_state +{ + u8 apic_id; + AGESA_STATUS status; + + u32 func; + const char *function_name; + + struct sysinfo *sysinfo; + AMD_INTERFACE_PARAMS *aip; +}; + +static AGESA_STATUS amd_alloc(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + aip->StdHeader.Func = AMD_CREATE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = 0; + aip->NewStructPtr = NULL; + aip->NewStructSize = 0; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_release(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + /* Cannot release AMD_LATE_PARAMS until ACPI tables are done. */ + if (func == AMD_INIT_LATE) + return AGESA_SUCCESS; + + aip->StdHeader.Func = AMD_RELEASE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = 0; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_alloc_stack(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func, void *buf, size_t len) +{ + /* By design, each valid AGESA_STRUCT_NAME + * can be casted to AMD_CONFIG_PARAMS. + */ + AMD_CONFIG_PARAMS *call = buf; + memset(call, 0, len); + + aip->StdHeader.Func = AMD_CREATE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = ByHost; + aip->NewStructPtr = call; + aip->NewStructSize = len; + + /* AMD_CREATE_STRUCT with ByHost skips this. */ + *call = aip->StdHeader; + + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_release_stack(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + aip->StdHeader.Func = AMD_RELEASE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = ByHost; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_dispatch(struct agesa_state *task, AMD_CONFIG_PARAMS *call) +{ + struct sysinfo *cb = task->sysinfo; + + /* By design, for each valid AGESA_STRUCT_NAME, AMD_CONFIG_PARAMS + * can be evaluated to apply correct typecast based on Func field. + */ + + switch (call->Func) + { +#if ENV_ROMSTAGE + case AMD_INIT_RESET: + { + AMD_RESET_PARAMS *param = (void *)call; + platform_BeforeInitReset(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_EARLY: + { + AMD_EARLY_PARAMS *param = (void *)call; + platform_BeforeInitEarly(cb, param); + board_BeforeInitEarly(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_POST: + { + AMD_POST_PARAMS *param = (void *)call; + platform_BeforeInitPost(cb, param); + board_BeforeInitPost(cb, param); + task->status = AmdAgesaDispatcher(call); + platform_AfterInitPost(cb, param); + break; + } + + case AMD_INIT_RESUME: + { + AMD_RESUME_PARAMS *param = (void *)call; + platform_BeforeInitResume(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_ENV: + { + AMD_ENV_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterInitEnv(cb, param); + break; + } + + case AMD_S3LATE_RESTORE: + { + AMD_S3LATE_PARAMS *param = (void *)call; + platform_BeforeS3LateRestore(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } +#endif +#if ENV_RAMSTAGE + case AMD_INIT_MID: + { + AMD_MID_PARAMS *param = (void *)call; + platform_BeforeInitMid(cb, param); + board_BeforeInitMid(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_S3_SAVE: + { + AMD_S3SAVE_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterS3Save(cb, param); + break; + } + case AMD_INIT_LATE: + { + AMD_LATE_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterInitLate(cb, param); + completion_InitLate(cb, param); + break; + } +#endif + default: + { + task->status = AGESA_UNSUPPORTED; + break; + } + + } + return task->status; +} + +static void state_on_entry(struct sysinfo *cb, + struct agesa_state *params, AGESA_STRUCT_NAME func) +{ + memset(params, 0, sizeof(params)); + + params->aip = (AMD_INTERFACE_PARAMS *) cb->agesa_stash; + params->sysinfo = cb; + + params->apic_id = (u8) (cpuid_ebx(1) >> 24); + params->func = func; + params->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +static void state_on_exit(struct agesa_state *params) +{ + AMD_CONFIG_PARAMS *call = &params->aip->StdHeader; + + agesawrapper_trace(params->status, call, params->function_name); + + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + params->apic_id, heap_status_name(call->HeapStatus), call->HeapStatus, + (u32)call->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +static AGESA_STATUS agesa_task(struct sysinfo *cb, AGESA_STRUCT_NAME func) +{ + struct agesa_state params; + AMD_RESET_PARAMS reset; + AGESA_STATUS status; + + state_on_entry(cb, &params, func); + + AMD_INTERFACE_PARAMS *aip = params.aip; + + if (func == AMD_INIT_RESET) + status = amd_alloc_stack(aip, func, &reset, sizeof(reset)); + else + status = amd_alloc(aip, func); + ASSERT(status == AGESA_SUCCESS); + + AMD_CONFIG_PARAMS *call = aip->NewStructPtr; + /* Must call the function buffer was allocated for.*/ + ASSERT(call->Func == func); + + status = amd_dispatch(&params, call); + ASSERT(status < AGESA_FATAL); + + if (func == AMD_INIT_RESET) + status = amd_release_stack(aip, func); + else + status = amd_release(aip, func); + ASSERT(status == AGESA_SUCCESS); + + state_on_exit(&params); + return params.status; +} + +void agesa_set_interface(struct sysinfo *cb) +{ + AMD_INTERFACE_PARAMS *aip = (void *)cb->agesa_stash; + + ASSERT (sizeof(AMD_INTERFACE_PARAMS) < AGESA_STASH_SIZE); + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = GetBiosCallout; +} + +int agesa_execute_state(struct sysinfo *cb, int func) +{ + AGESA_STATUS ret = agesa_task(cb, (AGESA_STRUCT_NAME) func); + return (ret == AGESA_SUCCESS) ? 0 : -1; +} + +#if ENV_RAMSTAGE + +static struct sysinfo state_machine; + +static void agesa_mid(void *unused) +{ + agesa_set_interface(&state_machine); + + if (!acpi_is_wakeup_s3()) + agesa_execute_state(&state_machine, AMD_INIT_MID); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, agesa_mid, NULL); + +static void agesa_late(void *unused) +{ + if (acpi_is_wakeup_s3()) + return; + + agesa_execute_state(&state_machine, AMD_INIT_LATE); + + if (!acpi_s3_resume_allowed()) + return; + + agesa_execute_state(&state_machine, AMD_S3_SAVE); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesa_late, NULL); + + +/* We will reference AmdLateParams later to copy ACPI tables. */ +static AMD_LATE_PARAMS *AmdLateParams; + +static void completion_InitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + AmdLateParams = Late; +} + +void *agesawrapper_getlateinitptr(int pick) +{ + ASSERT(AmdLateParams != NULL); + + switch (pick) { + case PICK_DMI: + return AmdLateParams->DmiTable; + case PICK_PSTATE: + return AmdLateParams->AcpiPState; + case PICK_SRAT: + return AmdLateParams->AcpiSrat; + case PICK_SLIT: + return AmdLateParams->AcpiSlit; + case PICK_WHEA_MCE: + return AmdLateParams->AcpiWheaMce; + case PICK_WHEA_CMC: + return AmdLateParams->AcpiWheaCmc; + case PICK_ALIB: + return AmdLateParams->AcpiAlib; + case PICK_IVRS: +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) + return NULL; +#else + return AmdLateParams->AcpiIvrs; +#endif + default: + return NULL; + } + return NULL; +} + +#endif /* ENV_RAMSTAGE */ + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ +#if 0 + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); + ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; + + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); + ASSERT(status == AGESA_SUCCESS); + + return status; +#else + return AGESA_SUCCESS; +#endif +} diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h new file mode 100644 index 0000000..7c52a19 --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _STATE_MACHINE_H_ +#define _STATE_MACHINE_H_ + +#include <stdint.h> +#include <AGESA.h> + +/* eventlog */ +const char *agesa_struct_name(int state); +const char *heap_status_name(int status); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); + + +AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* For suspend-to-ram support. */ +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *Resume); +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3Late); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3Save); + +/* For FCH */ +static inline void fchs3earlyrestore(void) { } +static inline void fchs3laterestore(void) { } + +#define AGESA_STASH_SIZE 64 +struct sysinfo +{ + u8 agesa_stash[AGESA_STASH_SIZE]; + int s3resume; +}; + +void board_BeforeAgesa(struct sysinfo *cb); + +void platform_once(struct sysinfo *cb); +void agesa_main(struct sysinfo *cb); + +void agesa_set_interface(struct sysinfo *cb); +int agesa_execute_state(struct sysinfo *cb, int func); + +/* AGESA dispatchers */ + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset); + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early); +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early); + +/* Normal boot */ +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env); +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env); + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); + +/* S3 Resume */ +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); + +#endif /* _STATE_MACHINE_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 7595889..527c9be 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c -ramstage-y += agesawrapper.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c deleted file mode 100644 index 00c6518..0000000 --- a/src/southbridge/amd/agesa/hudson/agesawrapper.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#error Use of GetHeapBase() is incorrect or at least suspicious -#endif - -AGESA_STATUS agesawrapper_fchs3earlyrestore (void) -{ - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3EarlyRestore(&FchParams); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_fchs3laterestore (void) -{ - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 1701a21..7c16f7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1245,7 +1245,7 @@ fam15_disable_stack_remote_read_exit: _RDMSR btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - wbinvd # Clear the cache tag RAMs + invd # Clear the cache tag RAMs #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? cmp $01, %bh jz 4f diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 87e6090..6d3f4d1 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -597,8 +597,7 @@ fam16_disable_stack_remote_read_exit: _RDMSR btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - wbinvd # Clear the cache tag RAMs - #invd + invd # Clear the cache tag RAMs #Do Standard Family 16 work mov $HWCR, %ecx # MSR:C001_0015h

1 0

Patch set updated for coreboot: soc/intel/quark: Fix I2C driver
by Lee Leahy 06 Mar '17

06 Mar '17

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18029 -gerrit commit 879c81f71fa928d77b508d7c3452ec426a9ad575 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 3 16:00:15 2017 -0800 soc/intel/quark: Fix I2C driver Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/i2c.c | 284 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 211 insertions(+), 73 deletions(-) diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 4675295..e6f8455 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -23,6 +23,7 @@ #include <soc/i2c.h> #include <soc/ramstage.h> #include <soc/reg_access.h> +#include <timer.h> static void i2c_disable(I2C_REGS *regs) { @@ -46,17 +47,141 @@ static void i2c_disable(I2C_REGS *regs) status = regs->ic_clr_intr; } -int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) +static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length, + uint32_t stop, uint8_t *rx_buffer, struct stopwatch *timeout) +{ + int bytes_transferred; + uint32_t cmd; + I2C_REGS *regs; + uint32_t status; + + regs = get_i2c_address(); + + + /* Fill the FIFO with the write operation */ + bytes_transferred = 0; + do { + status = regs->ic_raw_intr_stat; + + /* Check for errors */ + if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER + | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { + i2c_disable(regs); + return -1; + } + + /* Check for timeout */ + if (stopwatch_expired(timeout)) + return -1; + + /* Receive any available data */ + status = regs->ic_status; + if (status & IC_STATUS_RFNE) { + while (status & IC_STATUS_RFNE) { + *rx_buffer++ = (uint8_t)regs->ic_data_cmd; + bytes_transferred++; + status = regs->ic_status; + } + } + + /* Determine if space is available in the FIFO */ + if (status & IC_STATUS_TFNF) { + /* End of the transaction? */ + cmd = IC_DATA_CMD_WRITE | *tx_buffer++ | restart; + if (length == 1) + cmd |= stop; + restart = 0; + + /* Place a data byte into the FIFO */ + regs->ic_data_cmd = cmd; + length--; + bytes_transferred++; + } + else + udelay(1); + } while (length > 0); + return bytes_transferred; +} + +static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length, + uint32_t stop, struct stopwatch *timeout) +{ + int bytes_transferred; + uint32_t cmd; + int fifo_bytes; + uint8_t junk; + I2C_REGS *regs; + uint32_t status; + + regs = get_i2c_address(); + + /* Empty the FIFO */ + status = regs->ic_status; + while (status & IC_STATUS_RFNE) { + junk = (uint8_t)regs->ic_data_cmd; + status = regs->ic_status; + } + + /* Fill the FIFO with read commands */ + fifo_bytes = min(length, 16); + bytes_transferred = 0; + while (length > 0) { + status = regs->ic_raw_intr_stat; + + /* Check for errors */ + if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER + | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { + i2c_disable(regs); + return -1; + } + + /* Check for timeout */ + if (stopwatch_expired(timeout)) + return -1; + + /* Receive any available data */ + status = regs->ic_status; + if (status & IC_STATUS_RFNE) { + /* Save the next data byte, removed from the RX FIFO */ + *rx_buffer++ = (uint8_t)regs->ic_data_cmd; + bytes_transferred++; + } + + if ((status & IC_STATUS_TFNF) + || ((status & IC_STATUS_RFNE) && (fifo_bytes > 0))) { + /* End of the transaction? */ + cmd = IC_DATA_CMD_READ | restart; + if (length == 1) + cmd |= stop; + restart = 0; + + /* Place a read command into the TX FIFO */ + regs->ic_data_cmd = cmd; + if (fifo_bytes > 0) + fifo_bytes--; + length--; + } + else + udelay(1); + } + return bytes_transferred; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segment, int count) { - uint8_t *buffer; int bytes_transferred; uint8_t chip; uint32_t cmd; + int data_bytes; int length; - int read_length; I2C_REGS *regs; + uint8_t *rx_buffer; uint32_t status; - uint32_t timeout; + uint32_t stop; + struct stopwatch timeout; + int total_bytes; + uint8_t *tx_buffer; + int tx_bytes; regs = get_i2c_address(); @@ -65,8 +190,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Set the slave address */ ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); + ASSERT (segment != NULL); /* Clear the start and stop detection */ status = regs->ic_clr_start_det; @@ -75,14 +199,29 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Set addressing mode to 7-bit and fast mode */ cmd = regs->ic_con; cmd &= ~(IC_CON_10B | IC_CON_SPEED); - cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz + cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_400_KHz | IC_CON_MASTER_MODE; regs->ic_con = cmd; /* Set the target chip address */ - chip = segments->chip; + chip = segment->chip; regs->ic_tar = chip; + /* Set the speed */ +/* + if (ENV_BOOTBLOCK || ENV_VERSTAGE) { + regs->ic_ss_scl_hcnt = (0x190 * 100) / 266; + regs->ic_ss_scl_lcnt = (0x1d6 * 100) / 266; + regs->ic_fs_scl_hcnt = (0x3c * 100) / 266; + regs->ic_fs_scl_lcnt = (0x82 * 100) / 266; + } else { + regs->ic_ss_scl_hcnt = 0x190; + regs->ic_ss_scl_lcnt = 0x1d6; + regs->ic_fs_scl_hcnt = 0x3c; + regs->ic_fs_scl_lcnt = 0x82; + } +*/ + /* Enable the I2C controller */ regs->ic_enable = IC_ENABLE_CONTROLLER; @@ -92,86 +231,85 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) status = regs->ic_clr_tx_over; status = regs->ic_clr_tx_abrt; + /* Start the timeout */ + stopwatch_init_msecs_expire(&timeout, 1000); + /* Process each of the segments */ + total_bytes = 0; + tx_bytes = 0; bytes_transferred = 0; - read_length = 0; - buffer = NULL; + rx_buffer = NULL; + int restart = 0; while (count-- > 0) { - buffer = segments->buf; - length = segments->len; - ASSERT (buffer != NULL); + length = segment->len; + total_bytes += length; + ASSERT (segment->buf != NULL); ASSERT (length >= 1); - ASSERT (segments->chip == chip); + ASSERT (segment->chip == chip); + + /* Determine if this is the last segment of the transaction */ + stop = (count == 0) ? IC_DATA_CMD_STOP : 0; - if (segments->read) { + /* Fill the FIFO with the necessary command bytes */ + if (segment->read) { /* Place read commands into the FIFO */ - read_length = length; - while (length > 0) { - /* Send stop bit after last byte */ - cmd = IC_DATA_CMD_READ; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place read command in transmit FIFO */ - regs->ic_data_cmd = cmd; - length--; - } + rx_buffer = segment->buf; + data_bytes = platform_i2c_read(restart, rx_buffer, + length, stop, &timeout); + + /* Return any detected error */ + if (data_bytes < 0) + return data_bytes; + bytes_transferred += data_bytes; } else { /* Write the data into the FIFO */ - while (length > 0) { - /* End of the transaction? */ - cmd = IC_DATA_CMD_WRITE | *buffer++; - if ((count == 0) && (length == 1)) - cmd |= IC_DATA_CMD_STOP; - - /* Place a data byte into the FIFO */ - regs->ic_data_cmd = cmd; - length--; - bytes_transferred++; - } + tx_buffer = segment->buf; + tx_bytes += length; + data_bytes = platform_i2c_write(restart, tx_buffer, + length, stop, rx_buffer, &timeout); + + /* Return any detected error */ + if (data_bytes < 0) + return data_bytes; + bytes_transferred += data_bytes; } - segments++; + segment++; + restart = IC_DATA_CMD_RESTART; } /* Wait for the end of the transaction */ - timeout = 1 * 1000 * 1000; + if (rx_buffer != NULL) + rx_buffer += bytes_transferred - tx_bytes; do { - status = regs->ic_raw_intr_stat; - if (status & IC_INTR_STOP_DET) - break; - if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER - | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) - || (timeout == 0)) { - if (timeout == 0) - printk (BIOS_ERR, - "ERROR - I2C stop bit not received!\n"); - if (status & IC_INTR_RX_OVER) - printk (BIOS_ERR, - "ERROR - I2C receive overrun!\n"); - if (status & IC_INTR_RX_UNDER) - printk (BIOS_ERR, - "ERROR - I2C receive underrun!\n"); - if (status & IC_INTR_TX_ABRT) - printk (BIOS_ERR, - "ERROR - I2C transmit abort!\n"); - if (status & IC_INTR_TX_OVER) - printk (BIOS_ERR, - "ERROR - I2C transmit overrun!\n"); - i2c_disable(regs); - return -1; + /* Receive any available data */ + status = regs->ic_status; + if (status & IC_STATUS_RFNE) { + *rx_buffer++ = (uint8_t)regs->ic_data_cmd; + bytes_transferred++; + } else { + status = regs->ic_raw_intr_stat; + if ((total_bytes == bytes_transferred) + && (status & IC_INTR_STOP_DET)) + break; + + /* Check for errors */ + if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER + | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { + i2c_disable(regs); + return -1; + } + + /* Check for timeout */ + if (stopwatch_expired(&timeout)) + return -1; + + /* Delay for a while */ + udelay(1); } - timeout--; - udelay(1); } while (1); + i2c_disable(regs); + regs->ic_tar = 0; - /* Finish reading the data bytes */ - while (read_length > 0) { - status = regs->ic_status; - *buffer++ = (uint8_t)regs->ic_data_cmd; - read_length--; - bytes_transferred++; - status = regs->ic_status; - } - + /* Return the number of bytes transferred */ return bytes_transferred; }

1 0

Patch set updated for coreboot: soc/intel/skylake: Add SKL SOC PCH H GPIO support
by Rahul KumarXX Gupta 06 Mar '17

06 Mar '17

Rahul KumarXX Gupta (rahul.kumarxx.gupta(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18027 -gerrit commit a78f4a179ebcf44ecd7075d864c3ec13366f78d4 Author: Li Cheng Sooi <li.cheng.sooi(a)intel.com> Date: Wed Jan 4 09:48:39 2017 +0800 soc/intel/skylake: Add SKL SOC PCH H GPIO support Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi(a)intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta(a)intel.com> --- src/soc/intel/skylake/acpi/gpio.asl | 21 +++ src/soc/intel/skylake/gpio.c | 13 ++ src/soc/intel/skylake/include/soc/gpio_defs.h | 72 +++------- .../intel/skylake/include/soc/gpio_pch_h_defs.h | 149 +++++++++++++++++++++ src/soc/intel/skylake/include/soc/gpio_soc_defs.h | 108 +++++++++++++++ 5 files changed, 306 insertions(+), 57 deletions(-) diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index c9116d0..0c5a793 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -75,6 +75,26 @@ Device (GPIO) */ Method (GADD, 1, NotSerialized) { +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 03 */ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } +#else /* GPIO Community 0 */ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) { @@ -93,6 +113,7 @@ Method (GADD, 1, NotSerialized) Store (PID_GPIOCOM3, Local0) Subtract (Arg0, GPP_F0, Local1) } +#endif /* CONFIG_SKYLAKE_SOC_PCH_H */ Store (PCRB (Local0), Local2) Add (Local2, PAD_CFG_DW_OFFSET, Local2) Return (Add (Local2, Multiply (Local1, 8))) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 6334b3e..f65b1c9 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -45,12 +45,21 @@ static const struct gpio_community communities[] = { { .port_id = PID_GPIOCOM1, .min = GPP_C0, +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + .max = GPP_H23, +#else .max = GPP_E23, +#endif }, { .port_id = PID_GPIOCOM3, +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + .min = GPP_I0, + .max = GPP_I10, +#else .min = GPP_F0, .max = GPP_G7, +#endif }, { .port_id = PID_GPIOCOM2, @@ -67,6 +76,10 @@ static const char *gpio_group_names[GPIO_NUM_GROUPS] = { "GPP_E", "GPP_F", "GPP_G", +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) + "GPP_H", + "GPP_I", +#endif "GPD", }; diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 42a409b..c6e0ab7 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -16,6 +16,12 @@ #ifndef _SOC_GPIO_DEFS_H_ #define _SOC_GPIO_DEFS_H_ +#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) +# include <soc/gpio_pch_h_defs.h> +#else +# include <soc/gpio_soc_defs.h> +#endif + /* * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case * where that group is not so generic. So most of the fixed numbers and macros @@ -29,8 +35,7 @@ #define GPP_E 4 #define GPP_F 5 #define GPP_G 6 -#define GPD 7 -#define GPIO_NUM_GROUPS 8 + #define GPIO_MAX_NUM_PER_GROUP 24 #define GPIO_DWx_COUNT 2 /* DW0 and DW1 */ @@ -152,64 +157,17 @@ #define GPP_E10 106 #define GPP_E11 107 #define GPP_E12 108 -#define GPP_E13 109 -#define GPP_E14 110 -#define GPP_E15 111 -#define GPP_E16 112 -#define GPP_E17 113 -#define GPP_E18 114 -#define GPP_E19 115 -#define GPP_E20 116 -#define GPP_E21 117 -#define GPP_E22 118 -#define GPP_E23 119 + +/* + * Some of define groups and defines are not generic so defined in + * _SOC_GPIO_SOC_DEFS_H and _SOC_GPIO_PCH_H_DEFS_H + */ + /* Group F */ -#define GPP_F0 120 -#define GPP_F1 121 -#define GPP_F2 122 -#define GPP_F3 123 -#define GPP_F4 124 -#define GPP_F5 125 -#define GPP_F6 126 -#define GPP_F7 127 -#define GPP_F8 128 -#define GPP_F9 129 -#define GPP_F10 130 -#define GPP_F11 131 -#define GPP_F12 132 -#define GPP_F13 133 -#define GPP_F14 134 -#define GPP_F15 135 -#define GPP_F16 136 -#define GPP_F17 137 -#define GPP_F18 138 -#define GPP_F19 139 -#define GPP_F20 140 -#define GPP_F21 141 -#define GPP_F22 142 -#define GPP_F23 143 + /* Group G */ -#define GPP_G0 144 -#define GPP_G1 145 -#define GPP_G2 146 -#define GPP_G3 147 -#define GPP_G4 148 -#define GPP_G5 149 -#define GPP_G6 150 -#define GPP_G7 151 + /* Group GPD */ -#define GPD0 152 -#define GPD1 153 -#define GPD2 154 -#define GPD3 155 -#define GPD4 156 -#define GPD5 157 -#define GPD6 158 -#define GPD7 159 -#define GPD8 160 -#define GPD9 161 -#define GPD10 162 -#define GPD11 163 /* * IOxAPIC IRQs for the GPIOs diff --git a/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h new file mode 100644 index 0000000..54a9978 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_pch_h_defs.h @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_PCH_H_DEFS_H_ +#define _SOC_GPIO_PCH_H_DEFS_H_ + +/* + * There are 10 GPIO groups. GPP_A -> GPP_I and GPD. GPD is the special case + * where that group is not so generic. So most of the fixed numbers and macros + * are based on the GPP groups. The GPIO groups are accessed through register + * blocks called communities. + */ + +#define GPP_H 7 +#define GPP_I 8 +#define GPD 9 +#define GPIO_NUM_GROUPS 10 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group A */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group B */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group C */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group D */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group E */ +/* Some of these are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group F */ +#define GPP_F0 109 +#define GPP_F1 110 +#define GPP_F2 111 +#define GPP_F3 112 +#define GPP_F4 113 +#define GPP_F5 114 +#define GPP_F6 115 +#define GPP_F7 116 +#define GPP_F8 117 +#define GPP_F9 118 +#define GPP_F10 119 +#define GPP_F11 120 +#define GPP_F12 121 +#define GPP_F13 122 +#define GPP_F14 123 +#define GPP_F15 124 +#define GPP_F16 125 +#define GPP_F17 126 +#define GPP_F18 127 +#define GPP_F19 128 +#define GPP_F20 129 +#define GPP_F21 130 +#define GPP_F22 131 +#define GPP_F23 132 +/* Group G */ +#define GPP_G0 133 +#define GPP_G1 134 +#define GPP_G2 135 +#define GPP_G3 136 +#define GPP_G4 137 +#define GPP_G5 138 +#define GPP_G6 139 +#define GPP_G7 140 +#define GPP_G8 141 +#define GPP_G9 142 +#define GPP_G10 143 +#define GPP_G11 144 +#define GPP_G12 145 +#define GPP_G13 146 +#define GPP_G14 147 +#define GPP_G15 148 +#define GPP_G16 149 +#define GPP_G17 150 +#define GPP_G18 151 +#define GPP_G19 152 +#define GPP_G20 153 +#define GPP_G21 154 +#define GPP_G22 155 +#define GPP_G23 156 +/* Group H */ +#define GPP_H0 157 +#define GPP_H1 158 +#define GPP_H2 159 +#define GPP_H3 160 +#define GPP_H4 161 +#define GPP_H5 162 +#define GPP_H6 163 +#define GPP_H7 164 +#define GPP_H8 165 +#define GPP_H9 166 +#define GPP_H10 167 +#define GPP_H11 168 +#define GPP_H12 169 +#define GPP_H13 170 +#define GPP_H14 171 +#define GPP_H15 172 +#define GPP_H16 173 +#define GPP_H17 174 +#define GPP_H18 175 +#define GPP_H19 176 +#define GPP_H20 177 +#define GPP_H21 178 +#define GPP_H22 179 +#define GPP_H23 180 +/* Group I */ +#define GPP_I0 181 +#define GPP_I1 182 +#define GPP_I2 183 +#define GPP_I3 184 +#define GPP_I4 185 +#define GPP_I5 186 +#define GPP_I6 187 +#define GPP_I7 188 +#define GPP_I8 189 +#define GPP_I9 190 +#define GPP_I10 191 +/* Group GPD */ +#define GPD0 192 +#define GPD1 193 +#define GPD2 194 +#define GPD3 195 +#define GPD4 196 +#define GPD5 197 +#define GPD6 198 +#define GPD7 199 +#define GPD8 200 +#define GPD9 201 +#define GPD10 202 +#define GPD11 203 +#endif /* _SOC_GPIO_PCH_H_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/gpio_soc_defs.h b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..62e5b5f --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_soc_defs.h @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_SOC_DEFS_H_ +#define _SOC_GPIO_SOC_DEFS_H_ + +/* + * There are 8 GPIO groups. GPP_A -> GPP_G and GPD. GPD is the special case + * where that group is not so generic. So most of the fixed numbers and macros + * are based on the GPP groups. The GPIO groups are accessed through register + * blocks called communities. + */ + +/* GPP_A -> GPP_G are generic so defined in _SOC_GPIO_DEFS_H_ */ + +#define GPD 7 +#define GPIO_NUM_GROUPS 8 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group B */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group C */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group D */ +/* These are generic so defined in _SOC_GPIO_DEFS_H */ + +/* Group E */ +/* Some of these are generic so defined in _SOC_GPIO_DEFS_H */ +#define GPP_E13 109 +#define GPP_E14 110 +#define GPP_E15 111 +#define GPP_E16 112 +#define GPP_E17 113 +#define GPP_E18 114 +#define GPP_E19 115 +#define GPP_E20 116 +#define GPP_E21 117 +#define GPP_E22 118 +#define GPP_E23 119 +/* Group F */ +#define GPP_F0 120 +#define GPP_F1 121 +#define GPP_F2 122 +#define GPP_F3 123 +#define GPP_F4 124 +#define GPP_F5 125 +#define GPP_F6 126 +#define GPP_F7 127 +#define GPP_F8 128 +#define GPP_F9 129 +#define GPP_F10 130 +#define GPP_F11 131 +#define GPP_F12 132 +#define GPP_F13 133 +#define GPP_F14 134 +#define GPP_F15 135 +#define GPP_F16 136 +#define GPP_F17 137 +#define GPP_F18 138 +#define GPP_F19 139 +#define GPP_F20 140 +#define GPP_F21 141 +#define GPP_F22 142 +#define GPP_F23 143 +/* Group G */ +#define GPP_G0 144 +#define GPP_G1 145 +#define GPP_G2 146 +#define GPP_G3 147 +#define GPP_G4 148 +#define GPP_G5 149 +#define GPP_G6 150 +#define GPP_G7 151 +/* Group GPD */ +#define GPD0 152 +#define GPD1 153 +#define GPD2 154 +#define GPD3 155 +#define GPD4 156 +#define GPD5 157 +#define GPD6 158 +#define GPD7 159 +#define GPD8 160 +#define GPD9 161 +#define GPD10 162 +#define GPD11 163 + +#endif /* _SOC_GPIO_SOC_DEFS_H_ */

1 0

New patch to review for coreboot: src/lib: Fix errors detected by checkpatch
by Lee Leahy 06 Mar '17

06 Mar '17

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18580 -gerrit commit 3f305fc2dfaa3ef167fe181d93d90db323e6a45f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Mar 5 10:41:20 2017 -0800 src/lib: Fix errors detected by checkpatch Fix most of the errors detected by checkpatch. The errors and warnings that remain are: ERROR: need consistent spacing around '*' (ctx:WxV) +void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), ^ ERROR: need consistent spacing around '*' (ctx:WxV) +void __gcov_merge_single(gcov_type *counters __attribute__ ((unused)), ^ ERROR: need consistent spacing around '*' (ctx:WxV) +void __gcov_merge_delta(gcov_type *counters __attribute__ ((unused)), ^ ERROR: need consistent spacing around '*' (ctx:WxV) +void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), ^ ERROR: open brace '{' following struct go on the same line +struct gcov_fn_buffer +{ ERROR: Macros with multiple statements should be enclosed in a do - while loop #85: FILE: src/lib/lzmadecode.c:85: +#define IfBit0(p) \ + RC_NORMALIZE; \ + bound = (Range >> kNumBitModelTotalBits) * *(p); \ + if (Code < bound) ERROR: Macros with complex values should be enclosed in parentheses #103: FILE: src/lib/lzmadecode.c:103: +#define RC_GET_BIT2(p, mi, A0, A1) \ + IfBit0(p) { \ + UpdateBit0(p); \ + mi <<= 1; \ + A0; \ + } else { \ + UpdateBit1(p); \ + mi = (mi + mi) + 1; \ + A1; \ + } ERROR: need consistent spacing around '*' (ctx:WxV) #178: FILE: src/lib/lzmadecode.c:178: +int LzmaDecodeProperties(CLzmaProperties *propsRes, ^ WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + fn_buffer->info.ident = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + fn_buffer->info.lineno_checksum = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + fn_buffer->info.cfg_checksum = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + if (gcov_read_unsigned() != GCOV_TAG_FOR_COUNTER(ix)) { WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = GCOV_TAG_COUNTER_NUM(gcov_read_unsigned()); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' +crc32_unsigned(gcov_unsigned_t crc32, gcov_unsigned_t value) WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + crc32 = crc32_unsigned(crc32, gi_ptr->stamp); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + crc32 = crc32_unsigned(crc32, gi_ptr->n_functions); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + crc32 = crc32_unsigned(crc32, gfi_ptr WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + crc32 = crc32_unsigned(crc32, WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + crc32 = crc32_unsigned(crc32, ci_ptr->num); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + tag = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + tag = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + f_ix++, tag = gcov_read_unsigned()) { WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + tag = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + length = gcov_read_unsigned(); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + gcov_write_unsigned(gi_ptr->stamp); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + gcov_write_unsigned(gfi_ptr->ident); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + gcov_write_unsigned(gfi_ptr->lineno_checksum); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + gcov_write_unsigned(gfi_ptr->cfg_checksum); WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + gcov_write_unsigned(0); WARNING: Macros with flow control statements should be avoided #64: FILE: src/lib/lzmadecode.c:64: +#define RC_TEST \ + do { \ + if (Buffer == BufferLim) \ + return LZMA_RESULT_DATA_ERROR; \ + } while (0) + WARNING: Too many leading tabs - consider code refactoring #269: FILE: src/lib/lzmadecode.c:269: + if (bit != 0) WARNING: Too many leading tabs - consider code refactoring #271: FILE: src/lib/lzmadecode.c:271: + if (bit == 0) WARNING: Too many leading tabs - consider code refactoring #308: FILE: src/lib/lzmadecode.c:308: + if (nowPos == 0) WARNING: line over 80 characters #309: FILE: src/lib/lzmadecode.c:309: + return LZMA_RESULT_DATA_ERROR; WARNING: Too many leading tabs - consider code refactoring #334: FILE: src/lib/lzmadecode.c:334: + } else { WARNING: Too many leading tabs - consider code refactoring #398: FILE: src/lib/lzmadecode.c:398: + do { WARNING: Too many leading tabs - consider code refactoring #402: FILE: src/lib/lzmadecode.c:402: + if (Code >= Range) { WARNING: Too many leading tabs - consider code refactoring #406: FILE: src/lib/lzmadecode.c:406: + } while (--numDirectBits != 0); WARNING: Too many leading tabs - consider code refactoring #414: FILE: src/lib/lzmadecode.c:414: + do { WARNING: Too many leading tabs - consider code refactoring #420: FILE: src/lib/lzmadecode.c:420: + } while (--numDirectBits != 0); WARNING: line over 80 characters #37: FILE: src/lib/malloc.c:37: + die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); WARNING: Avoid line continuations in quoted strings #32: FILE: src/lib/tpm_error_messages.h:32: + "An operation completed successfully\n\ WARNING: Avoid line continuations in quoted strings #35: FILE: src/lib/tpm_error_messages.h:35: + "The clear disable flag is set and all clear operations now require\n\ WARNING: line over 80 characters #68: FILE: src/lib/tpm_error_messages.h:68: + "The TPM has insufficient internal resources to perform the requested action"}, WARNING: Avoid line continuations in quoted strings #80: FILE: src/lib/tpm_error_messages.h:80: + "The calculation is unable to proceed because the existing SHA-1\n\ WARNING: Avoid line continuations in quoted strings #85: FILE: src/lib/tpm_error_messages.h:85: + "The authorization for the second key in a 2 key function\n\ WARNING: Avoid line continuations in quoted strings #104: FILE: src/lib/tpm_error_messages.h:104: + "The command was received in the wrong sequence relative to TPM_Init\n\ WARNING: Avoid line continuations in quoted strings #113: FILE: src/lib/tpm_error_messages.h:113: + "The signature or encryption scheme for this key is incorrect or not\n\ WARNING: Avoid line continuations in quoted strings #116: FILE: src/lib/tpm_error_messages.h:116: + "The size of the data (or blob) parameter is bad or inconsistent\n\ WARNING: Avoid line continuations in quoted strings #119: FILE: src/lib/tpm_error_messages.h:119: + "A mode parameter is bad, such as capArea or subCapArea for\n\ WARNING: Avoid line continuations in quoted strings #123: FILE: src/lib/tpm_error_messages.h:123: + "Either the physicalPresence or physicalPresenceLock bits\n\ WARNING: Avoid line continuations in quoted strings #130: FILE: src/lib/tpm_error_messages.h:130: + "TPM audit construction failed and the underlying command\n\ WARNING: Avoid line continuations in quoted strings #133: FILE: src/lib/tpm_error_messages.h:133: + "TPM audit construction failed and the underlying command\n\ WARNING: line over 80 characters #136: FILE: src/lib/tpm_error_messages.h:136: + "Attempt to reset a PCR register that does not have the resettable attribute"}, WARNING: Avoid line continuations in quoted strings #138: FILE: src/lib/tpm_error_messages.h:138: + "Attempt to reset a PCR register that requires locality\n\ WARNING: line over 80 characters #143: FILE: src/lib/tpm_error_messages.h:143: + "When saving context identified resource type does not match actual resource"}, WARNING: line over 80 characters #145: FILE: src/lib/tpm_error_messages.h:145: + "The TPM is attempting to execute a command only available when in FIPS mode"}, WARNING: Avoid line continuations in quoted strings #173: FILE: src/lib/tpm_error_messages.h:173: + "The key is under control of the TPM Owner and can only be evicted\n\ WARNING: line over 80 characters #194: FILE: src/lib/tpm_error_messages.h:194: + "There was a command executed outside of an exclusive transport session"}, WARNING: Avoid line continuations in quoted strings #208: FILE: src/lib/tpm_error_messages.h:208: + "The atomic process indicated by the submitted DAA command is not\n\ WARNING: Avoid line continuations in quoted strings #237: FILE: src/lib/tpm_error_messages.h:237: + "The TPM is too busy to respond to the command immediately, but\n\ WARNING: Avoid line continuations in quoted strings #243: FILE: src/lib/tpm_error_messages.h:243: + "The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ WARNING: Avoid line continuations in quoted strings #246: FILE: src/lib/tpm_error_messages.h:246: + "The TPM is defending against dictionary attacks and is in some\n\ TEST=Build and run on Galileo Gen2 Change-Id: Ic1fec68e9d0282e44c6b65e84872b2a0dc439bef Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/lib/libgcov.c | 1443 +++++++++++++++++++++---------------------- src/lib/lzma.c | 5 +- src/lib/lzmadecode.c | 672 ++++++++++---------- src/lib/lzmadecode.h | 31 +- src/lib/memcmp.c | 2 +- src/lib/memmove.c | 6 +- src/lib/memrange.c | 62 +- src/lib/mocked_tlcl.c | 41 +- src/lib/primitive_memtest.c | 4 +- src/lib/prog_loaders.c | 1 - src/lib/ramtest.c | 19 +- src/lib/reg_script.c | 20 +- src/lib/rmodule.c | 8 +- src/lib/selfboot.c | 121 ++-- src/lib/spd_bin.c | 12 +- src/lib/stack.c | 8 +- src/lib/thread.c | 17 +- src/lib/timer.c | 4 +- src/lib/timer_queue.c | 6 +- src/lib/timestamp.c | 2 +- src/lib/tlcl.c | 84 ++- src/lib/tlcl_internal.h | 13 +- src/lib/tlcl_structures.h | 234 ++++--- src/lib/tpm2_tlcl.c | 5 +- 24 files changed, 1468 insertions(+), 1352 deletions(-) diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index 1ad14c9..0ec3645 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -30,7 +30,7 @@ permissions described in the GCC Runtime Library Exception, version typedef s32 pid_t; #define gcc_assert(x) ASSERT(x) #define fprintf(file, x...) printk(BIOS_ERR, x) -#define alloca(size) __builtin_alloca (size) +#define alloca(size) __builtin_alloca(size) #include "gcov-glue.c" /* Define MACROs to be used by coreboot compilation. */ @@ -73,23 +73,23 @@ typedef s32 pid_t; /* If libc and its header files are not available, provide dummy functions. */ #ifdef L_gcov -void __gcov_init (struct gcov_info *p __attribute__ ((unused))) {} -void __gcov_flush (void) {} +void __gcov_init(struct gcov_info *p __attribute__ ((unused))) {} +void __gcov_flush(void) {} #endif #ifdef L_gcov_merge_add -void __gcov_merge_add (gcov_type *counters __attribute__ ((unused)), - unsigned n_counters __attribute__ ((unused))) {} +void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), + unsigned int n_counters __attribute__ ((unused))) {} #endif #ifdef L_gcov_merge_single -void __gcov_merge_single (gcov_type *counters __attribute__ ((unused)), - unsigned n_counters __attribute__ ((unused))) {} +void __gcov_merge_single(gcov_type *counters __attribute__ ((unused)), + unsigned int n_counters __attribute__ ((unused))) {} #endif #ifdef L_gcov_merge_delta -void __gcov_merge_delta (gcov_type *counters __attribute__ ((unused)), - unsigned n_counters __attribute__ ((unused))) {} +void __gcov_merge_delta(gcov_type *counters __attribute__ ((unused)), + unsigned int n_counters __attribute__ ((unused))) {} #endif #else @@ -103,7 +103,7 @@ void __gcov_merge_delta (gcov_type *counters __attribute__ ((unused)), #endif #else void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), - unsigned n_counters __attribute__ ((unused))) {} + unsigned int n_counters __attribute__ ((unused))) {} #endif /* __COREBOOT__ */ #ifdef L_gcov @@ -111,10 +111,10 @@ void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), struct gcov_fn_buffer { - struct gcov_fn_buffer *next; - unsigned fn_ix; - struct gcov_fn_info info; - /* note gcov_fn_info ends in a trailing array. */ + struct gcov_fn_buffer *next; + unsigned int fn_ix; + struct gcov_fn_info info; + /* note gcov_fn_info ends in a trailing array. */ }; /* Chain of per-object gcov structures. */ @@ -128,150 +128,148 @@ static size_t gcov_max_filename = 0; Returns zero on success, or -1 if an error occurred. */ static int -create_file_directory (char *filename) +create_file_directory(char *filename) { #ifdef __COREBOOT__ - (void) filename; - return 0; + (void)filename; + return 0; #else #if !defined(TARGET_POSIX_IO) && !defined(_WIN32) - (void) filename; - return -1; + (void)filename; + return -1; #else - char *s; - - s = filename; - - if (HAS_DRIVE_SPEC(s)) - s += 2; - if (IS_DIR_SEPARATOR(*s)) - ++s; - for (; *s != '\0'; s++) - if (IS_DIR_SEPARATOR(*s)) - { - char sep = *s; - *s = '\0'; - - /* Try to make directory if it doesn't already exist. */ - if (access (filename, F_OK) == -1 + char *s; + + s = filename; + + if (HAS_DRIVE_SPEC(s)) + s += 2; + if (IS_DIR_SEPARATOR(*s)) + ++s; + for (; *s != '\0'; s++) + if (IS_DIR_SEPARATOR(*s)) { + char sep = *s; + *s = '\0'; + + /* Try to make directory if it doesn't already exist. */ + if ((access(filename, F_OK) == -1) #ifdef TARGET_POSIX_IO - && mkdir (filename, 0755) == -1 + && (mkdir(filename, 0755) == -1) #else - && mkdir (filename) == -1 + && (mkdir(filename) == -1) #endif - /* The directory might have been made by another process. */ - && errno != EEXIST) - { - fprintf (stderr, "profiling:%s:Cannot create directory\n", - filename); - *s = sep; - return -1; - }; - - *s = sep; - }; - return 0; + /* The directory might have been made by another + * process. + */ + && (errno != EEXIST)) { + fprintf(stderr, + "profiling:%s:Cannot create directory\n", + filename); + *s = sep; + return -1; + }; + + *s = sep; + }; + return 0; #endif #endif } static struct gcov_fn_buffer * -free_fn_data (const struct gcov_info *gi_ptr, struct gcov_fn_buffer *buffer, - unsigned limit) +free_fn_data(const struct gcov_info *gi_ptr, struct gcov_fn_buffer *buffer, + unsigned int limit) { - struct gcov_fn_buffer *next; - unsigned ix, n_ctr = 0; - - if (!buffer) - return 0; - next = buffer->next; - - for (ix = 0; ix != limit; ix++) - if (gi_ptr->merge[ix]) - free (buffer->info.ctrs[n_ctr++].values); - free (buffer); - return next; + struct gcov_fn_buffer *next; + unsigned int ix, n_ctr = 0; + + if (!buffer) + return 0; + next = buffer->next; + + for (ix = 0; ix != limit; ix++) + if (gi_ptr->merge[ix]) + free(buffer->info.ctrs[n_ctr++].values); + free(buffer); + return next; } static struct gcov_fn_buffer ** -buffer_fn_data (const char *filename, const struct gcov_info *gi_ptr, - struct gcov_fn_buffer **end_ptr, unsigned fn_ix) +buffer_fn_data(const char *filename, const struct gcov_info *gi_ptr, + struct gcov_fn_buffer **end_ptr, unsigned int fn_ix) { - unsigned n_ctrs = 0, ix = 0; - struct gcov_fn_buffer *fn_buffer; - unsigned len; + unsigned int n_ctrs = 0, ix = 0; + struct gcov_fn_buffer *fn_buffer; + unsigned int len; - for (ix = GCOV_COUNTERS; ix--;) - if (gi_ptr->merge[ix]) - n_ctrs++; + for (ix = GCOV_COUNTERS; ix--;) + if (gi_ptr->merge[ix]) + n_ctrs++; - len = sizeof (*fn_buffer) + sizeof (fn_buffer->info.ctrs[0]) * n_ctrs; - fn_buffer = (struct gcov_fn_buffer *)malloc (len); + len = sizeof(*fn_buffer) + sizeof(fn_buffer->info.ctrs[0]) * n_ctrs; + fn_buffer = (struct gcov_fn_buffer *)malloc(len); - if (!fn_buffer) - goto fail; + if (!fn_buffer) + goto fail; - fn_buffer->next = 0; - fn_buffer->fn_ix = fn_ix; - fn_buffer->info.ident = gcov_read_unsigned (); - fn_buffer->info.lineno_checksum = gcov_read_unsigned (); - fn_buffer->info.cfg_checksum = gcov_read_unsigned (); + fn_buffer->next = 0; + fn_buffer->fn_ix = fn_ix; + fn_buffer->info.ident = gcov_read_unsigned(); + fn_buffer->info.lineno_checksum = gcov_read_unsigned(); + fn_buffer->info.cfg_checksum = gcov_read_unsigned(); - for (n_ctrs = ix = 0; ix != GCOV_COUNTERS; ix++) - { - gcov_unsigned_t length; - gcov_type *values; + for (n_ctrs = ix = 0; ix != GCOV_COUNTERS; ix++) { + gcov_unsigned_t length; + gcov_type *values; - if (!gi_ptr->merge[ix]) - continue; + if (!gi_ptr->merge[ix]) + continue; - if (gcov_read_unsigned () != GCOV_TAG_FOR_COUNTER (ix)) - { - len = 0; - goto fail; - } + if (gcov_read_unsigned() != GCOV_TAG_FOR_COUNTER(ix)) { + len = 0; + goto fail; + } - length = GCOV_TAG_COUNTER_NUM (gcov_read_unsigned ()); - len = length * sizeof (gcov_type); - values = (gcov_type *)malloc (len); - if (!values) - goto fail; + length = GCOV_TAG_COUNTER_NUM(gcov_read_unsigned()); + len = length * sizeof(gcov_type); + values = (gcov_type *)malloc(len); + if (!values) + goto fail; - fn_buffer->info.ctrs[n_ctrs].num = length; - fn_buffer->info.ctrs[n_ctrs].values = values; + fn_buffer->info.ctrs[n_ctrs].num = length; + fn_buffer->info.ctrs[n_ctrs].values = values; - while (length--) - *values++ = gcov_read_counter (); - n_ctrs++; - } + while (length--) + *values++ = gcov_read_counter(); + n_ctrs++; + } - *end_ptr = fn_buffer; - return &fn_buffer->next; + *end_ptr = fn_buffer; + return &fn_buffer->next; fail: - fprintf (stderr, "profiling:%s:Function %u %s %u \n", filename, fn_ix, - len ? "cannot allocate" : "counter mismatch", len ? len : ix); + fprintf(stderr, "profiling:%s:Function %u %s %u\n", filename, fn_ix, + len ? "cannot allocate" : "counter mismatch", len ? len : ix); - return (struct gcov_fn_buffer **)free_fn_data (gi_ptr, fn_buffer, ix); + return (struct gcov_fn_buffer **)free_fn_data(gi_ptr, fn_buffer, ix); } /* Add an unsigned value to the current crc */ static gcov_unsigned_t -crc32_unsigned (gcov_unsigned_t crc32, gcov_unsigned_t value) +crc32_unsigned(gcov_unsigned_t crc32, gcov_unsigned_t value) { - unsigned ix; + unsigned int ix; - for (ix = 32; ix--; value <<= 1) - { - unsigned feedback; + for (ix = 32; ix--; value <<= 1) { + unsigned int feedback; - feedback = (value ^ crc32) & 0x80000000 ? 0x04c11db7 : 0; - crc32 <<= 1; - crc32 ^= feedback; - } + feedback = (value ^ crc32) & 0x80000000 ? 0x04c11db7 : 0; + crc32 <<= 1; + crc32 ^= feedback; + } - return crc32; + return crc32; } /* Check if VERSION of the info block PTR matches libgcov one. @@ -280,22 +278,21 @@ crc32_unsigned (gcov_unsigned_t crc32, gcov_unsigned_t value) instead of value from the info block. */ static int -gcov_version (struct gcov_info *ptr, gcov_unsigned_t version, - const char *filename) +gcov_version(struct gcov_info *ptr, gcov_unsigned_t version, + const char *filename) { - if (version != GCOV_VERSION) - { - char v[4], e[4]; - - GCOV_UNSIGNED2STRING (v, version); - GCOV_UNSIGNED2STRING (e, GCOV_VERSION); - - fprintf (stderr, - "profiling:%s:Version mismatch - expected %.4s got %.4s\n", - filename? filename : ptr->filename, e, v); - return 0; - } - return 1; + if (version != GCOV_VERSION) { + char v[4], e[4]; + + GCOV_UNSIGNED2STRING(v, version); + GCOV_UNSIGNED2STRING(e, GCOV_VERSION); + + fprintf(stderr, + "profiling:%s:Version mismatch - expected %.4s got %.4s\n", + filename ? filename : ptr->filename, e, v); + return 0; + } + return 1; } /* Dump the coverage counts. We merge with existing counts when @@ -306,443 +303,443 @@ gcov_version (struct gcov_info *ptr, gcov_unsigned_t version, summaries separate. */ static void -gcov_exit (void) +gcov_exit(void) { - struct gcov_info *gi_ptr; - const struct gcov_fn_info *gfi_ptr; - struct gcov_summary this_prg; /* summary for program. */ - struct gcov_summary all_prg; /* summary for all instances of program. */ - struct gcov_ctr_summary *cs_ptr; - const struct gcov_ctr_info *ci_ptr; - unsigned t_ix; - int f_ix = 0; - gcov_unsigned_t c_num; - const char *gcov_prefix; - int gcov_prefix_strip = 0; - size_t prefix_length; - char *gi_filename, *gi_filename_up; - gcov_unsigned_t crc32 = 0; - - memset (&all_prg, 0, sizeof (all_prg)); - /* Find the totals for this execution. */ - memset (&this_prg, 0, sizeof (this_prg)); - for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) - { - crc32 = crc32_unsigned (crc32, gi_ptr->stamp); - crc32 = crc32_unsigned (crc32, gi_ptr->n_functions); - - for (f_ix = 0; (unsigned)f_ix != gi_ptr->n_functions; f_ix++) - { - gfi_ptr = gi_ptr->functions[f_ix]; - - if (gfi_ptr && gfi_ptr->key != gi_ptr) - gfi_ptr = 0; - - crc32 = crc32_unsigned (crc32, gfi_ptr ? gfi_ptr->cfg_checksum : 0); - crc32 = crc32_unsigned (crc32, + struct gcov_info *gi_ptr; + const struct gcov_fn_info *gfi_ptr; + struct gcov_summary this_prg; /* summary for program. */ + struct gcov_summary all_prg; /* summary for all instances of program */ + struct gcov_ctr_summary *cs_ptr; + const struct gcov_ctr_info *ci_ptr; + unsigned int t_ix; + int f_ix = 0; + gcov_unsigned_t c_num; + const char *gcov_prefix; + int gcov_prefix_strip = 0; + size_t prefix_length; + char *gi_filename, *gi_filename_up; + gcov_unsigned_t crc32 = 0; + + memset(&all_prg, 0, sizeof(all_prg)); + /* Find the totals for this execution. */ + memset(&this_prg, 0, sizeof(this_prg)); + for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) { + crc32 = crc32_unsigned(crc32, gi_ptr->stamp); + crc32 = crc32_unsigned(crc32, gi_ptr->n_functions); + + for (f_ix = 0; (unsigned int)f_ix != gi_ptr->n_functions; + f_ix++) { + gfi_ptr = gi_ptr->functions[f_ix]; + + if (gfi_ptr && gfi_ptr->key != gi_ptr) + gfi_ptr = 0; + + crc32 = crc32_unsigned(crc32, gfi_ptr + ? gfi_ptr->cfg_checksum : 0); + crc32 = crc32_unsigned(crc32, gfi_ptr ? gfi_ptr->lineno_checksum : 0); - if (!gfi_ptr) - continue; - - ci_ptr = gfi_ptr->ctrs; - for (t_ix = 0; t_ix != GCOV_COUNTERS_SUMMABLE; t_ix++) - { - if (!gi_ptr->merge[t_ix]) - continue; - - cs_ptr = &this_prg.ctrs[t_ix]; - cs_ptr->num += ci_ptr->num; - crc32 = crc32_unsigned (crc32, ci_ptr->num); - - for (c_num = 0; c_num < ci_ptr->num; c_num++) - { - cs_ptr->sum_all += ci_ptr->values[c_num]; - if (cs_ptr->run_max < ci_ptr->values[c_num]) - cs_ptr->run_max = ci_ptr->values[c_num]; + if (!gfi_ptr) + continue; + + ci_ptr = gfi_ptr->ctrs; + for (t_ix = 0; t_ix != GCOV_COUNTERS_SUMMABLE; t_ix++) { + if (!gi_ptr->merge[t_ix]) + continue; + + cs_ptr = &this_prg.ctrs[t_ix]; + cs_ptr->num += ci_ptr->num; + crc32 = crc32_unsigned(crc32, ci_ptr->num); + + for (c_num = 0; c_num < ci_ptr->num; c_num++) { + cs_ptr->sum_all += + ci_ptr->values[c_num]; + if (cs_ptr->run_max < + ci_ptr->values[c_num]) + cs_ptr->run_max = + ci_ptr->values[c_num]; + } + ci_ptr++; + } } - ci_ptr++; - } } - } #ifndef __COREBOOT__ - { - /* Check if the level of dirs to strip off specified. */ - char *tmp = getenv("GCOV_PREFIX_STRIP"); - if (tmp) - { - gcov_prefix_strip = atoi (tmp); - /* Do not consider negative values. */ - if (gcov_prefix_strip < 0) - gcov_prefix_strip = 0; - } - } - - /* Get file name relocation prefix. Non-absolute values are ignored. */ - gcov_prefix = getenv("GCOV_PREFIX"); - if (gcov_prefix) - { - prefix_length = strlen(gcov_prefix); - - /* Remove an unnecessary trailing '/' */ - if (IS_DIR_SEPARATOR (gcov_prefix[prefix_length - 1])) - prefix_length--; - } - else -#endif - prefix_length = 0; - - /* If no prefix was specified and a prefix strip, then we assume - relative. */ - if (gcov_prefix_strip != 0 && prefix_length == 0) - { - gcov_prefix = "."; - prefix_length = 1; - } - /* Allocate and initialize the filename scratch space plus one. */ - gi_filename = (char *) alloca (prefix_length + gcov_max_filename + 2); - if (prefix_length) - memcpy (gi_filename, gcov_prefix, prefix_length); - gi_filename_up = gi_filename + prefix_length; - - /* Now merge each file. */ - for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) - { - unsigned n_counts; - struct gcov_summary prg; /* summary for this object over all - program. */ - struct gcov_ctr_summary *cs_prg, *cs_tprg, *cs_all; - int error = 0; - gcov_unsigned_t tag, length; - gcov_position_t summary_pos = 0; - gcov_position_t eof_pos = 0; - const char *fname, *s; - struct gcov_fn_buffer *fn_buffer = 0; - struct gcov_fn_buffer **fn_tail = &fn_buffer; - - fname = gi_ptr->filename; - - /* Avoid to add multiple drive letters into combined path. */ - if (prefix_length != 0 && HAS_DRIVE_SPEC(fname)) - fname += 2; - - /* Build relocated filename, stripping off leading - directories from the initial filename if requested. */ - if (gcov_prefix_strip > 0) - { - int level = 0; - s = fname; - if (IS_DIR_SEPARATOR(*s)) - ++s; - - /* Skip selected directory levels. */ - for (; (*s != '\0') && (level < gcov_prefix_strip); s++) - if (IS_DIR_SEPARATOR(*s)) - { - fname = s; - level++; - } - } - - /* Update complete filename with stripped original. */ - if (prefix_length != 0 && !IS_DIR_SEPARATOR (*fname)) - { - /* If prefix is given, add directory separator. */ - strcpy (gi_filename_up, "/"); - strcpy (gi_filename_up + 1, fname); + { + /* Check if the level of dirs to strip off specified. */ + char *tmp = getenv("GCOV_PREFIX_STRIP"); + if (tmp) { + gcov_prefix_strip = atoi(tmp); + /* Do not consider negative values. */ + if (gcov_prefix_strip < 0) + gcov_prefix_strip = 0; + } } - else - strcpy (gi_filename_up, fname); - if (!gcov_open (gi_filename)) - { - /* Open failed likely due to missed directory. - Create directory and retry to open file. */ - if (create_file_directory (gi_filename)) - { - fprintf (stderr, "profiling:%s:Skip\n", gi_filename); - continue; - } - if (!gcov_open (gi_filename)) - { - fprintf (stderr, "profiling:%s:Cannot open\n", gi_filename); - continue; - } + /* Get file name relocation prefix. Non-absolute values are ignored. */ + gcov_prefix = getenv("GCOV_PREFIX"); + if (gcov_prefix) { + prefix_length = strlen(gcov_prefix); + + /* Remove an unnecessary trailing '/' */ + if (IS_DIR_SEPARATOR(gcov_prefix[prefix_length - 1])) + prefix_length--; + } else +#endif + prefix_length = 0; + + /* If no prefix was specified and a prefix strip, then we assume + * relative. + */ + if (gcov_prefix_strip != 0 && prefix_length == 0) { + gcov_prefix = "."; + prefix_length = 1; } + /* Allocate and initialize the filename scratch space plus one. */ + gi_filename = (char *)alloca(prefix_length + gcov_max_filename + 2); + if (prefix_length) + memcpy(gi_filename, gcov_prefix, prefix_length); + gi_filename_up = gi_filename + prefix_length; + + /* Now merge each file. */ + for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) { + unsigned int n_counts; + /* summary for this object over all program. */ + struct gcov_summary prg; + struct gcov_ctr_summary *cs_prg, *cs_tprg, *cs_all; + int error = 0; + gcov_unsigned_t tag, length; + gcov_position_t summary_pos = 0; + gcov_position_t eof_pos = 0; + const char *fname, *s; + struct gcov_fn_buffer *fn_buffer = 0; + struct gcov_fn_buffer **fn_tail = &fn_buffer; + + fname = gi_ptr->filename; + + /* Avoid to add multiple drive letters into combined path. */ + if (prefix_length != 0 && HAS_DRIVE_SPEC(fname)) + fname += 2; + + /* Build relocated filename, stripping off leading + * directories from the initial filename if requested. + */ + if (gcov_prefix_strip > 0) { + int level = 0; + s = fname; + if (IS_DIR_SEPARATOR(*s)) + ++s; + + /* Skip selected directory levels. */ + for (; (*s != '\0') && (level < gcov_prefix_strip); s++) + if (IS_DIR_SEPARATOR(*s)) { + fname = s; + level++; + } + } - tag = gcov_read_unsigned (); - if (tag) - { - /* Merge data from file. */ - if (tag != GCOV_DATA_MAGIC) - { - fprintf (stderr, "profiling:%s:Not a gcov data file\n", - gi_filename); - goto read_fatal; - } - length = gcov_read_unsigned (); - if (!gcov_version (gi_ptr, length, gi_filename)) - goto read_fatal; - - length = gcov_read_unsigned (); - if (length != gi_ptr->stamp) - /* Read from a different compilation. Overwrite the file. */ - goto rewrite; - - /* Look for program summary. */ - for (f_ix = 0;;) - { - struct gcov_summary tmp; - - eof_pos = gcov_position (); - tag = gcov_read_unsigned (); - if (tag != GCOV_TAG_PROGRAM_SUMMARY) - break; - - f_ix--; - length = gcov_read_unsigned (); - if (length != GCOV_TAG_SUMMARY_LENGTH) - goto read_mismatch; - gcov_read_summary (&tmp); - if ((error = gcov_is_error ())) - goto read_error; - if (summary_pos || tmp.checksum != crc32) - goto next_summary; - - for (t_ix = 0; t_ix != GCOV_COUNTERS_SUMMABLE; t_ix++) - if (tmp.ctrs[t_ix].num != this_prg.ctrs[t_ix].num) - goto next_summary; - prg = tmp; - summary_pos = eof_pos; - - next_summary:; - } - - /* Merge execution counts for each function. */ - for (f_ix = 0; (unsigned)f_ix != gi_ptr->n_functions; - f_ix++, tag = gcov_read_unsigned ()) - { - gfi_ptr = gi_ptr->functions[f_ix]; - - if (tag != GCOV_TAG_FUNCTION) - goto read_mismatch; - - length = gcov_read_unsigned (); - if (!length) - /* This function did not appear in the other program. - We have nothing to merge. */ - continue; - - if (length != GCOV_TAG_FUNCTION_LENGTH) - goto read_mismatch; - - if (!gfi_ptr || gfi_ptr->key != gi_ptr) - { - /* This function appears in the other program. We - need to buffer the information in order to write - it back out -- we'll be inserting data before - this point, so cannot simply keep the data in the - file. */ - fn_tail = buffer_fn_data (gi_filename, - gi_ptr, fn_tail, f_ix); - if (!fn_tail) - goto read_mismatch; - continue; + /* Update complete filename with stripped original. */ + if (prefix_length != 0 && !IS_DIR_SEPARATOR(*fname)) { + /* If prefix is given, add directory separator. */ + strcpy(gi_filename_up, "/"); + strcpy(gi_filename_up + 1, fname); + } else + strcpy(gi_filename_up, fname); + + if (!gcov_open(gi_filename)) { + /* Open failed likely due to missed directory. + * Create directory and retry to open file. + */ + if (create_file_directory(gi_filename)) { + fprintf(stderr, "profiling:%s:Skip\n", + gi_filename); + continue; + } + if (!gcov_open(gi_filename)) { + fprintf(stderr, "profiling:%s:Cannot open\n", + gi_filename); + continue; + } } - length = gcov_read_unsigned (); - if (length != gfi_ptr->ident) - goto read_mismatch; - - length = gcov_read_unsigned (); - if (length != gfi_ptr->lineno_checksum) - goto read_mismatch; - - length = gcov_read_unsigned (); - if (length != gfi_ptr->cfg_checksum) - goto read_mismatch; - - ci_ptr = gfi_ptr->ctrs; - for (t_ix = 0; t_ix < GCOV_COUNTERS; t_ix++) - { - gcov_merge_fn merge = gi_ptr->merge[t_ix]; - - if (!merge) - continue; - - tag = gcov_read_unsigned (); - length = gcov_read_unsigned (); - if (tag != GCOV_TAG_FOR_COUNTER (t_ix) - || length != GCOV_TAG_COUNTER_LENGTH (ci_ptr->num)) - goto read_mismatch; - (*merge) (ci_ptr->values, ci_ptr->num); - ci_ptr++; + tag = gcov_read_unsigned(); + if (tag) { + /* Merge data from file. */ + if (tag != GCOV_DATA_MAGIC) { + fprintf(stderr, + "profiling:%s:Not a gcov data file\n", + gi_filename); + goto read_fatal; + } + length = gcov_read_unsigned(); + if (!gcov_version(gi_ptr, length, gi_filename)) + goto read_fatal; + + length = gcov_read_unsigned(); + if (length != gi_ptr->stamp) + /* Read from a different compilation. Overwrite + * the file. + */ + goto rewrite; + + /* Look for program summary. */ + for (f_ix = 0;;) { + struct gcov_summary tmp; + + eof_pos = gcov_position(); + tag = gcov_read_unsigned(); + if (tag != GCOV_TAG_PROGRAM_SUMMARY) + break; + + f_ix--; + length = gcov_read_unsigned(); + if (length != GCOV_TAG_SUMMARY_LENGTH) + goto read_mismatch; + gcov_read_summary(&tmp); + error = gcov_is_error(); + if (error) + goto read_error; + if (summary_pos || tmp.checksum != crc32) + goto next_summary; + + for (t_ix = 0; t_ix != GCOV_COUNTERS_SUMMABLE; + t_ix++) + if (tmp.ctrs[t_ix].num != + this_prg.ctrs[t_ix].num) + goto next_summary; + prg = tmp; + summary_pos = eof_pos; + +next_summary: + } + + /* Merge execution counts for each function. */ + for (f_ix = 0; (unsigned int)f_ix != + gi_ptr->n_functions; + f_ix++, tag = gcov_read_unsigned()) { + gfi_ptr = gi_ptr->functions[f_ix]; + + if (tag != GCOV_TAG_FUNCTION) + goto read_mismatch; + + length = gcov_read_unsigned(); + if (!length) + /* This function did not appear in the + * other program. We have nothing to + * merge. + */ + continue; + + if (length != GCOV_TAG_FUNCTION_LENGTH) + goto read_mismatch; + + if (!gfi_ptr || gfi_ptr->key != gi_ptr) { + /* This function appears in the other + * program. We need to buffer the + * information in order to write it back + * out -- we'll be inserting data before + * this point, so cannot simply keep the + * data in the file. + */ + fn_tail = buffer_fn_data(gi_filename, + gi_ptr, fn_tail, f_ix); + if (!fn_tail) + goto read_mismatch; + continue; + } + + length = gcov_read_unsigned(); + if (length != gfi_ptr->ident) + goto read_mismatch; + + length = gcov_read_unsigned(); + if (length != gfi_ptr->lineno_checksum) + goto read_mismatch; + + length = gcov_read_unsigned(); + if (length != gfi_ptr->cfg_checksum) + goto read_mismatch; + + ci_ptr = gfi_ptr->ctrs; + for (t_ix = 0; t_ix < GCOV_COUNTERS; t_ix++) { + gcov_merge_fn merge = + gi_ptr->merge[t_ix]; + + if (!merge) + continue; + + tag = gcov_read_unsigned(); + length = gcov_read_unsigned(); + if (tag != GCOV_TAG_FOR_COUNTER(t_ix) + || length != + GCOV_TAG_COUNTER_LENGTH( + ci_ptr->num)) + goto read_mismatch; + (*merge)(ci_ptr->values, ci_ptr->num); + ci_ptr++; + } + error = gcov_is_error(); + if (error) + goto read_error; + } + + if (tag) { +read_mismatch: + fprintf(stderr, + "profiling:%s:Merge mismatch for %s %u\n", + gi_filename, f_ix >= 0 ? "function" : + "summary", f_ix < 0 ? -1 - f_ix : f_ix); + goto read_fatal; + } } - if ((error = gcov_is_error ())) - goto read_error; - } - - if (tag) - { - read_mismatch:; - fprintf (stderr, "profiling:%s:Merge mismatch for %s %u\n", - gi_filename, f_ix >= 0 ? "function" : "summary", - f_ix < 0 ? -1 - f_ix : f_ix); - goto read_fatal; - } - } - goto rewrite; + goto rewrite; - read_error:; - fprintf (stderr, "profiling:%s:%s merging\n", gi_filename, - error < 0 ? "Overflow": "Error"); +read_error: + fprintf(stderr, "profiling:%s:%s merging\n", gi_filename, + error < 0 ? "Overflow" : "Error"); - goto read_fatal; + goto read_fatal; - rewrite:; - gcov_rewrite (); - if (!summary_pos) - { - memset (&prg, 0, sizeof (prg)); - summary_pos = eof_pos; - } +rewrite: + gcov_rewrite(); + if (!summary_pos) { + memset(&prg, 0, sizeof(prg)); + summary_pos = eof_pos; + } - /* Merge the summaries. */ - for (t_ix = 0; t_ix < GCOV_COUNTERS_SUMMABLE; t_ix++) - { - cs_prg = &prg.ctrs[t_ix]; - cs_tprg = &this_prg.ctrs[t_ix]; - cs_all = &all_prg.ctrs[t_ix]; - - if (gi_ptr->merge[t_ix]) - { - if (!cs_prg->runs++) - cs_prg->num = cs_tprg->num; - cs_prg->sum_all += cs_tprg->sum_all; - if (cs_prg->run_max < cs_tprg->run_max) - cs_prg->run_max = cs_tprg->run_max; - cs_prg->sum_max += cs_tprg->run_max; - } - else if (cs_prg->runs) - goto read_mismatch; - - if (!cs_all->runs && cs_prg->runs) - memcpy (cs_all, cs_prg, sizeof (*cs_all)); - else if (!all_prg.checksum - && (!GCOV_LOCKED || cs_all->runs == cs_prg->runs) - && memcmp (cs_all, cs_prg, sizeof (*cs_all))) - { - fprintf (stderr, "profiling:%s:Invocation mismatch - some data files may have been removed%s\n", - gi_filename, GCOV_LOCKED - ? "" : " or concurrently updated without locking support"); - all_prg.checksum = ~0u; - } - } + /* Merge the summaries. */ + for (t_ix = 0; t_ix < GCOV_COUNTERS_SUMMABLE; t_ix++) { + cs_prg = &prg.ctrs[t_ix]; + cs_tprg = &this_prg.ctrs[t_ix]; + cs_all = &all_prg.ctrs[t_ix]; + + if (gi_ptr->merge[t_ix]) { + if (!cs_prg->runs++) + cs_prg->num = cs_tprg->num; + cs_prg->sum_all += cs_tprg->sum_all; + if (cs_prg->run_max < cs_tprg->run_max) + cs_prg->run_max = cs_tprg->run_max; + cs_prg->sum_max += cs_tprg->run_max; + } else if (cs_prg->runs) + goto read_mismatch; + + if (!cs_all->runs && cs_prg->runs) + memcpy(cs_all, cs_prg, sizeof(*cs_all)); + else if (!all_prg.checksum + && (!GCOV_LOCKED || cs_all->runs == + cs_prg->runs) + && memcmp(cs_all, cs_prg, sizeof(*cs_all))) { + fprintf(stderr, + "profiling:%s:Invocation mismatch - some data files may have been removed%s\n", + gi_filename, GCOV_LOCKED + ? "" : + " or concurrently updated without locking support"); + all_prg.checksum = ~0u; + } + } - prg.checksum = crc32; + prg.checksum = crc32; - /* Write out the data. */ - if (!eof_pos) - { - gcov_write_tag_length (GCOV_DATA_MAGIC, GCOV_VERSION); - gcov_write_unsigned (gi_ptr->stamp); - } + /* Write out the data. */ + if (!eof_pos) { + gcov_write_tag_length(GCOV_DATA_MAGIC, GCOV_VERSION); + gcov_write_unsigned(gi_ptr->stamp); + } - if (summary_pos) - gcov_seek (summary_pos); + if (summary_pos) + gcov_seek(summary_pos); + + /* Generate whole program statistics. */ + gcov_write_summary(GCOV_TAG_PROGRAM_SUMMARY, &prg); + + if (summary_pos < eof_pos) + gcov_seek(eof_pos); + + /* Write execution counts for each function. */ + for (f_ix = 0; (unsigned int)f_ix != gi_ptr->n_functions; + f_ix++) { + unsigned int buffered = 0; + + if (fn_buffer && fn_buffer->fn_ix == + (unsigned int)f_ix) { + /* Buffered data from another program. */ + buffered = 1; + gfi_ptr = &fn_buffer->info; + length = GCOV_TAG_FUNCTION_LENGTH; + } else { + gfi_ptr = gi_ptr->functions[f_ix]; + if (gfi_ptr && gfi_ptr->key == gi_ptr) + length = GCOV_TAG_FUNCTION_LENGTH; + else + length = 0; + } + + gcov_write_tag_length(GCOV_TAG_FUNCTION, length); + if (!length) + continue; + + gcov_write_unsigned(gfi_ptr->ident); + gcov_write_unsigned(gfi_ptr->lineno_checksum); + gcov_write_unsigned(gfi_ptr->cfg_checksum); + + ci_ptr = gfi_ptr->ctrs; + for (t_ix = 0; t_ix < GCOV_COUNTERS; t_ix++) { + if (!gi_ptr->merge[t_ix]) + continue; + + n_counts = ci_ptr->num; + gcov_write_tag_length( + GCOV_TAG_FOR_COUNTER(t_ix), + GCOV_TAG_COUNTER_LENGTH(n_counts)); + gcov_type *c_ptr = ci_ptr->values; + while (n_counts--) + gcov_write_counter(*c_ptr++); + ci_ptr++; + } + if (buffered) + fn_buffer = free_fn_data(gi_ptr, fn_buffer, + GCOV_COUNTERS); + } - /* Generate whole program statistics. */ - gcov_write_summary (GCOV_TAG_PROGRAM_SUMMARY, &prg); + gcov_write_unsigned(0); - if (summary_pos < eof_pos) - gcov_seek (eof_pos); +read_fatal: + while (fn_buffer) + fn_buffer = free_fn_data(gi_ptr, fn_buffer, + GCOV_COUNTERS); - /* Write execution counts for each function. */ - for (f_ix = 0; (unsigned)f_ix != gi_ptr->n_functions; f_ix++) - { - unsigned buffered = 0; - - if (fn_buffer && fn_buffer->fn_ix == (unsigned)f_ix) - { - /* Buffered data from another program. */ - buffered = 1; - gfi_ptr = &fn_buffer->info; - length = GCOV_TAG_FUNCTION_LENGTH; - } - else - { - gfi_ptr = gi_ptr->functions[f_ix]; - if (gfi_ptr && gfi_ptr->key == gi_ptr) - length = GCOV_TAG_FUNCTION_LENGTH; - else - length = 0; - } - - gcov_write_tag_length (GCOV_TAG_FUNCTION, length); - if (!length) - continue; - - gcov_write_unsigned (gfi_ptr->ident); - gcov_write_unsigned (gfi_ptr->lineno_checksum); - gcov_write_unsigned (gfi_ptr->cfg_checksum); - - ci_ptr = gfi_ptr->ctrs; - for (t_ix = 0; t_ix < GCOV_COUNTERS; t_ix++) - { - if (!gi_ptr->merge[t_ix]) - continue; - - n_counts = ci_ptr->num; - gcov_write_tag_length (GCOV_TAG_FOR_COUNTER (t_ix), - GCOV_TAG_COUNTER_LENGTH (n_counts)); - gcov_type *c_ptr = ci_ptr->values; - while (n_counts--) - gcov_write_counter (*c_ptr++); - ci_ptr++; - } - if (buffered) - fn_buffer = free_fn_data (gi_ptr, fn_buffer, GCOV_COUNTERS); + error = gcov_close(); + if (error) + fprintf(stderr, error < 0 ? + "profiling:%s:Overflow writing\n" : + "profiling:%s:Error writing\n", + gi_filename); } - - gcov_write_unsigned (0); - - read_fatal:; - while (fn_buffer) - fn_buffer = free_fn_data (gi_ptr, fn_buffer, GCOV_COUNTERS); - - if ((error = gcov_close ())) - fprintf (stderr, error < 0 ? - "profiling:%s:Overflow writing\n" : - "profiling:%s:Error writing\n", - gi_filename); - } } /* Add a new object file onto the bb chain. Invoked automatically when running an object file's global ctors. */ void -__gcov_init (struct gcov_info *info) +__gcov_init(struct gcov_info *info) { - if (!info->version || !info->n_functions) - return; - if (gcov_version (info, info->version, 0)) - { - size_t filename_length = strlen(info->filename); + if (!info->version || !info->n_functions) + return; + if (gcov_version(info, info->version, 0)) { + size_t filename_length = strlen(info->filename); - /* Refresh the longest file name information */ - if (filename_length > gcov_max_filename) - gcov_max_filename = filename_length; + /* Refresh the longest file name information */ + if (filename_length > gcov_max_filename) + gcov_max_filename = filename_length; #ifndef __COREBOOT__ - if (!gcov_list) - atexit (gcov_exit); + if (!gcov_list) + atexit(gcov_exit); #endif - info->next = gcov_list; - gcov_list = info; - } - info->version = 0; + info->next = gcov_list; + gcov_list = info; + } + info->version = 0; } /* Called before fork or exec - write out profile information gathered so @@ -750,33 +747,32 @@ __gcov_init (struct gcov_info *info) profile information gathered so far. */ void -__gcov_flush (void) +__gcov_flush(void) { - const struct gcov_info *gi_ptr; - - gcov_exit (); - for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) - { - unsigned f_ix; - - for (f_ix = 0; f_ix < gi_ptr->n_functions; f_ix++) - { - unsigned t_ix; - const struct gcov_fn_info *gfi_ptr = gi_ptr->functions[f_ix]; - - if (!gfi_ptr || gfi_ptr->key != gi_ptr) - continue; - const struct gcov_ctr_info *ci_ptr = gfi_ptr->ctrs; - for (t_ix = 0; t_ix != GCOV_COUNTERS; t_ix++) - { - if (!gi_ptr->merge[t_ix]) - continue; - - memset (ci_ptr->values, 0, sizeof (gcov_type) * ci_ptr->num); - ci_ptr++; - } + const struct gcov_info *gi_ptr; + + gcov_exit(); + for (gi_ptr = gcov_list; gi_ptr; gi_ptr = gi_ptr->next) { + unsigned int f_ix; + + for (f_ix = 0; f_ix < gi_ptr->n_functions; f_ix++) { + unsigned int t_ix; + const struct gcov_fn_info *gfi_ptr = + gi_ptr->functions[f_ix]; + + if (!gfi_ptr || gfi_ptr->key != gi_ptr) + continue; + const struct gcov_ctr_info *ci_ptr = gfi_ptr->ctrs; + for (t_ix = 0; t_ix != GCOV_COUNTERS; t_ix++) { + if (!gi_ptr->merge[t_ix]) + continue; + + memset(ci_ptr->values, 0, sizeof(gcov_type) + * ci_ptr->num); + ci_ptr++; + } + } } - } } #endif /* L_gcov */ @@ -786,10 +782,10 @@ __gcov_flush (void) an array COUNTERS of N_COUNTERS old counters and it reads the same number of counters from the gcov file. */ void -__gcov_merge_add (gcov_type *counters, unsigned n_counters) +__gcov_merge_add(gcov_type *counters, unsigned int n_counters) { - for (; n_counters; counters++, n_counters--) - *counters += gcov_read_counter (); + for (; n_counters; counters++, n_counters--) + *counters += gcov_read_counter(); } #endif /* L_gcov_merge_add */ @@ -798,10 +794,10 @@ __gcov_merge_add (gcov_type *counters, unsigned n_counters) an array COUNTERS of N_COUNTERS old counters and it reads the same number of counters from the gcov file. */ void -__gcov_merge_ior (gcov_type *counters, unsigned n_counters) +__gcov_merge_ior(gcov_type *counters, unsigned int n_counters) { - for (; n_counters; counters++, n_counters--) - *counters |= gcov_read_counter (); + for (; n_counters; counters++, n_counters--) + *counters |= gcov_read_counter(); } #endif @@ -817,30 +813,27 @@ __gcov_merge_ior (gcov_type *counters, unsigned n_counters) * -- total number of evaluations of the value */ void -__gcov_merge_single (gcov_type *counters, unsigned n_counters) +__gcov_merge_single(gcov_type *counters, unsigned int n_counters) { - unsigned i, n_measures; - gcov_type value, counter, all; - - gcc_assert (!(n_counters % 3)); - n_measures = n_counters / 3; - for (i = 0; i < n_measures; i++, counters += 3) - { - value = gcov_read_counter (); - counter = gcov_read_counter (); - all = gcov_read_counter (); - - if (counters[0] == value) - counters[1] += counter; - else if (counter > counters[1]) - { - counters[0] = value; - counters[1] = counter - counters[1]; + unsigned int i, n_measures; + gcov_type value, counter, all; + + gcc_assert(!(n_counters % 3)); + n_measures = n_counters / 3; + for (i = 0; i < n_measures; i++, counters += 3) { + value = gcov_read_counter(); + counter = gcov_read_counter(); + all = gcov_read_counter(); + + if (counters[0] == value) + counters[1] += counter; + else if (counter > counters[1]) { + counters[0] = value; + counters[1] = counter - counters[1]; + } else + counters[1] -= counter; + counters[2] += all; } - else - counters[1] -= counter; - counters[2] += all; - } } #endif /* L_gcov_merge_single */ @@ -857,31 +850,29 @@ __gcov_merge_single (gcov_type *counters, unsigned n_counters) * -- total number of evaluations of the value */ void -__gcov_merge_delta (gcov_type *counters, unsigned n_counters) +__gcov_merge_delta(gcov_type *counters, unsigned int n_counters) { - unsigned i, n_measures; - gcov_type value, counter, all; - - gcc_assert (!(n_counters % 4)); - n_measures = n_counters / 4; - for (i = 0; i < n_measures; i++, counters += 4) - { - /* last = */ gcov_read_counter (); - value = gcov_read_counter (); - counter = gcov_read_counter (); - all = gcov_read_counter (); - - if (counters[1] == value) - counters[2] += counter; - else if (counter > counters[2]) - { - counters[1] = value; - counters[2] = counter - counters[2]; + unsigned int i, n_measures; + gcov_type value, counter, all; + + gcc_assert(!(n_counters % 4)); + n_measures = n_counters / 4; + for (i = 0; i < n_measures; i++, counters += 4) { + /* last = */ + gcov_read_counter(); + value = gcov_read_counter(); + counter = gcov_read_counter(); + all = gcov_read_counter(); + + if (counters[1] == value) + counters[2] += counter; + else if (counter > counters[2]) { + counters[1] = value; + counters[2] = counter - counters[2]; + } else + counters[2] -= counter; + counters[3] += all; } - else - counters[2] -= counter; - counters[3] += all; - } } #endif /* L_gcov_merge_delta */ @@ -892,16 +883,16 @@ __gcov_merge_delta (gcov_type *counters, unsigned n_counters) instead. */ void -__gcov_interval_profiler (gcov_type *counters, gcov_type value, - int start, unsigned steps) +__gcov_interval_profiler(gcov_type *counters, gcov_type value, + int start, unsigned int steps) { - gcov_type delta = value - start; - if (delta < 0) - counters[steps + 1]++; - else if (delta >= steps) - counters[steps]++; - else - counters[delta]++; + gcov_type delta = value - start; + if (delta < 0) + counters[steps + 1]++; + else if (delta >= steps) + counters[steps]++; + else + counters[delta]++; } #endif @@ -910,12 +901,12 @@ __gcov_interval_profiler (gcov_type *counters, gcov_type value, COUNTERS[0] is incremented. */ void -__gcov_pow2_profiler (gcov_type *counters, gcov_type value) +__gcov_pow2_profiler(gcov_type *counters, gcov_type value) { - if (value & (value - 1)) - counters[0]++; - else - counters[1]++; + if (value & (value - 1)) + counters[0]++; + else + counters[1]++; } #endif @@ -930,25 +921,23 @@ __gcov_pow2_profiler (gcov_type *counters, gcov_type value) In any case, COUNTERS[2] is incremented. */ static inline void -__gcov_one_value_profiler_body (gcov_type *counters, gcov_type value) +__gcov_one_value_profiler_body(gcov_type *counters, gcov_type value) { - if (value == counters[0]) - counters[1]++; - else if (counters[1] == 0) - { - counters[1] = 1; - counters[0] = value; - } - else - counters[1]--; - counters[2]++; + if (value == counters[0]) + counters[1]++; + else if (counters[1] == 0) { + counters[1] = 1; + counters[0] = value; + } else + counters[1]--; + counters[2]++; } #ifdef L_gcov_one_value_profiler void -__gcov_one_value_profiler (gcov_type *counters, gcov_type value) +__gcov_one_value_profiler(gcov_type *counters, gcov_type value) { - __gcov_one_value_profiler_body (counters, value); + __gcov_one_value_profiler_body(counters, value); } #endif @@ -973,16 +962,16 @@ __gcov_one_value_profiler (gcov_type *counters, gcov_type value) /* Tries to determine the most common value among its inputs. */ void -__gcov_indirect_call_profiler (gcov_type* counter, gcov_type value, - void* cur_func, void* callee_func) +__gcov_indirect_call_profiler(gcov_type *counter, gcov_type value, + void *cur_func, void *callee_func) { - /* If the C++ virtual tables contain function descriptors then one - function may have multiple descriptors and we need to dereference - the descriptors to see if they point to the same function. */ - if (cur_func == callee_func - || (VTABLE_USES_DESCRIPTORS && callee_func - && *(void **) cur_func == *(void **) callee_func)) - __gcov_one_value_profiler_body (counter, value); + /* If the C++ virtual tables contain function descriptors then one + * function may have multiple descriptors and we need to dereference + * the descriptors to see if they point to the same function. + */ + if (cur_func == callee_func || (VTABLE_USES_DESCRIPTORS && callee_func + && *(void **)cur_func == *(void **)callee_func)) + __gcov_one_value_profiler_body(counter, value); } #endif @@ -992,10 +981,10 @@ __gcov_indirect_call_profiler (gcov_type* counter, gcov_type value, to saturate up. */ void -__gcov_average_profiler (gcov_type *counters, gcov_type value) +__gcov_average_profiler(gcov_type *counters, gcov_type value) { - counters[0] += value; - counters[1] ++; + counters[0] += value; + counters[1]++; } #endif @@ -1004,9 +993,9 @@ __gcov_average_profiler (gcov_type *counters, gcov_type value) to saturate up. */ void -__gcov_ior_profiler (gcov_type *counters, gcov_type value) +__gcov_ior_profiler(gcov_type *counters, gcov_type value) { - *counters |= value; + *counters |= value; } #endif @@ -1015,10 +1004,10 @@ __gcov_ior_profiler (gcov_type *counters, gcov_type value) that they are not counted twice. */ pid_t -__gcov_fork (void) +__gcov_fork(void) { - __gcov_flush (); - return fork (); + __gcov_flush(); + return fork(); } #endif @@ -1027,93 +1016,93 @@ __gcov_fork (void) that they are not lost. */ int -__gcov_execl (const char *path, char *arg, ...) +__gcov_execl(const char *path, char *arg, ...) { - va_list ap, aq; - unsigned i, length; - char **args; + va_list ap, aq; + unsigned int i, length; + char **args; - __gcov_flush (); + __gcov_flush(); - va_start (ap, arg); - va_copy (aq, ap); + va_start(ap, arg); + va_copy(aq, ap); - length = 2; - while (va_arg (ap, char *)) - length++; - va_end (ap); + length = 2; + while (va_arg(ap, char *)) + length++; + va_end(ap); - args = (char **) alloca (length * sizeof (void *)); - args[0] = arg; - for (i = 1; i < length; i++) - args[i] = va_arg (aq, char *); - va_end (aq); + args = (char **)alloca(length * sizeof(void *)); + args[0] = arg; + for (i = 1; i < length; i++) + args[i] = va_arg(aq, char *); + va_end(aq); - return execv (path, args); + return execv(path, args); } #endif #ifdef L_gcov_execlp -/* A wrapper for the execlp function. Flushes the accumulated profiling data, so - that they are not lost. */ - +/* A wrapper for the execlp function. Flushes the accumulated profiling data, + * so that they are not lost. + */ int -__gcov_execlp (const char *path, char *arg, ...) +__gcov_execlp(const char *path, char *arg, ...) { - va_list ap, aq; - unsigned i, length; - char **args; + va_list ap, aq; + unsigned int i, length; + char **args; - __gcov_flush (); + __gcov_flush(); - va_start (ap, arg); - va_copy (aq, ap); + va_start(ap, arg); + va_copy(aq, ap); - length = 2; - while (va_arg (ap, char *)) - length++; - va_end (ap); + length = 2; + while (va_arg(ap, char *)) + length++; + va_end(ap); - args = (char **) alloca (length * sizeof (void *)); - args[0] = arg; - for (i = 1; i < length; i++) - args[i] = va_arg (aq, char *); - va_end (aq); + args = (char **)alloca(length * sizeof(void *)); + args[0] = arg; + for (i = 1; i < length; i++) + args[i] = va_arg(aq, char *); + va_end(aq); - return execvp (path, args); + return execvp(path, args); } #endif #ifdef L_gcov_execle -/* A wrapper for the execle function. Flushes the accumulated profiling data, so - that they are not lost. */ - +/* A wrapper for the execle function. Flushes the accumulated profiling data, + * so that they are not lost. + */ int -__gcov_execle (const char *path, char *arg, ...) +__gcov_execle(const char *path, char *arg, ...) { - va_list ap, aq; - unsigned i, length; - char **args; - char **envp; + va_list ap, aq; + unsigned int i, length; + char **args; + char **envp; - __gcov_flush (); + __gcov_flush(); - va_start (ap, arg); - va_copy (aq, ap); + va_start(ap, arg); + va_copy(aq, ap); - length = 2; - while (va_arg (ap, char *)) - length++; - va_end (ap); + length = 2; + while (va_arg(ap, char *)) + length++; + va_end(ap); - args = (char **) alloca (length * sizeof (void *)); - args[0] = arg; - for (i = 1; i < length; i++) - args[i] = va_arg (aq, char *); - envp = va_arg (aq, char **); - va_end (aq); + args = (char **)alloca(length * sizeof(void *)); + args[0] = arg; + for (i = 1; i < length; i++) + args[i] = va_arg(aq, char *); + envp = va_arg(aq, char **); + va_end(aq); - return execve (path, args, envp); + return execve(path, args, envp); } #endif @@ -1122,34 +1111,34 @@ __gcov_execle (const char *path, char *arg, ...) that they are not lost. */ int -__gcov_execv (const char *path, char *const argv[]) +__gcov_execv(const char *path, char *const argv[]) { - __gcov_flush (); - return execv (path, argv); + __gcov_flush(); + return execv(path, argv); } #endif #ifdef L_gcov_execvp -/* A wrapper for the execvp function. Flushes the accumulated profiling data, so - that they are not lost. */ - +/* A wrapper for the execvp function. Flushes the accumulated profiling data, + * so that they are not lost. + */ int -__gcov_execvp (const char *path, char *const argv[]) +__gcov_execvp(const char *path, char *const argv[]) { - __gcov_flush (); - return execvp (path, argv); + __gcov_flush(); + return execvp(path, argv); } #endif #ifdef L_gcov_execve -/* A wrapper for the execve function. Flushes the accumulated profiling data, so - that they are not lost. */ - +/* A wrapper for the execve function. Flushes the accumulated profiling data, + * so that they are not lost. + */ int -__gcov_execve (const char *path, char *const argv[], char *const envp[]) +__gcov_execve(const char *path, char *const argv[], char *const envp[]) { - __gcov_flush (); - return execve (path, argv, envp); + __gcov_flush(); + return execve(path, argv, envp); } #endif #endif /* inhibit_libc */ diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 3efcbc0..f727553 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -4,8 +4,9 @@ * Copyright (C) 2006 Carl-Daniel Hailfinger * Released under the GNU GPL v2 or later * - * Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA - * SDK 4.42, which is written and distributed to public domain by Igor Pavlov. + * Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the + * LZMA SDK 4.42, which is written and distributed to public domain by Igor + * Pavlov. * */ diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index fbf1596..1c2f71b 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -33,36 +33,97 @@ * to byte reads for last 4 bytes since RC_TEST returns an error when BufferLim * is *reached* (not surpassed!), meaning we can't allow that to happen while * there are still bytes to decode from the algorithm's point of view. */ -#define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ - : ((((uintptr_t) Buffer & 3) || ((SizeT) (BufferLim - Buffer) <= 4)) ? (*Buffer++) \ - : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) - -#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ - { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - - -#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } - -#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - - -#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } - -#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) -#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; -#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; - -#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ - { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) - -#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ - { int i = numLevels; res = 1; \ - do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \ - res -= (1 << numLevels); } - +#define RC_READ_BYTE \ + (look_ahead_ptr < 4 \ + ? look_ahead.raw[look_ahead_ptr++] \ + : ((((uintptr_t) Buffer & 3) \ + || ((SizeT)(BufferLim - Buffer) <= 4)) \ + ? (*Buffer++) \ + : (( \ + look_ahead.dw = *(UInt32 *)Buffer), \ + (Buffer += 4), \ + (look_ahead_ptr = 1), \ + look_ahead.raw[0] \ + ) \ + ) \ + ) + +#define RC_INIT2 \ + do { \ + Code = 0; \ + Range = 0xFFFFFFFF; \ + { \ + int i; \ + \ + for (i = 0; i < 5; i++) { \ + RC_TEST; Code = (Code << 8) | RC_READ_BYTE; \ + } \ + } \ + } while (0) + +#define RC_TEST \ + do { \ + if (Buffer == BufferLim) \ + return LZMA_RESULT_DATA_ERROR; \ + } while (0) + +#define RC_INIT(buffer, bufferSize) \ + do { \ + Buffer = buffer; \ + BufferLim = buffer + bufferSize; \ + RC_INIT2; \ + } while (0) + +#define RC_NORMALIZE \ + do { \ + if (Range < kTopValue) { \ + RC_TEST; Range <<= 8; \ + Code = (Code << 8) | RC_READ_BYTE; \ + } \ + } while (0) + +#define IfBit0(p) \ + RC_NORMALIZE; \ + bound = (Range >> kNumBitModelTotalBits) * *(p); \ + if (Code < bound) + +#define UpdateBit0(p) \ + do { \ + Range = bound; \ + *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; \ + } while (0) + +#define UpdateBit1(p) \ + do { \ + Range -= bound; \ + Code -= bound; \ + *(p) -= (*(p)) >> kNumMoveBits; \ + } while (0) + +#define RC_GET_BIT2(p, mi, A0, A1) \ + IfBit0(p) { \ + UpdateBit0(p); \ + mi <<= 1; \ + A0; \ + } else { \ + UpdateBit1(p); \ + mi = (mi + mi) + 1; \ + A1; \ + } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ;, ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + do { \ + int i = numLevels; \ + \ + res = 1; \ + do { \ + CProb *cp = probs + res; \ + RC_GET_BIT(cp, res) \ + } while (--i != 0); \ + res -= (1 << numLevels); \ + } while (0) #define kNumPosBitsMax 4 #define kNumPosStatesMax (1 << kNumPosBitsMax) @@ -114,298 +175,275 @@ StopCompilingDueBUG #endif -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +int LzmaDecodeProperties(CLzmaProperties *propsRes, + const unsigned char *propsData, int size) { - unsigned char prop0; - if (size < LZMA_PROPERTIES_SIZE) - return LZMA_RESULT_DATA_ERROR; - prop0 = propsData[0]; - if (prop0 >= (9 * 5 * 5)) - return LZMA_RESULT_DATA_ERROR; - { - for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); - for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); - propsRes->lc = prop0; - /* - unsigned char remainder = (unsigned char)(prop0 / 9); - propsRes->lc = prop0 % 9; - propsRes->pb = remainder / 5; - propsRes->lp = remainder % 5; - */ - } - - return LZMA_RESULT_OK; + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + for (propsRes->pb = 0; prop0 >= (9 * 5); + propsRes->pb++, prop0 -= (9 * 5)) + ; + for (propsRes->lp = 0; prop0 >= 9; + propsRes->lp++, prop0 -= 9) + ; + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 + / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + + return LZMA_RESULT_OK; } #define kLzmaStreamWasFinishedId (-1) int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) { - CProb *p = vs->Probs; - SizeT nowPos = 0; - Byte previousByte = 0; - UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; - UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; - int lc = vs->Properties.lc; - - - int state = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - int len = 0; - const Byte *Buffer; - const Byte *BufferLim; - int look_ahead_ptr = 4; - union - { - Byte raw[4]; - UInt32 dw; - } look_ahead; - UInt32 Range; - UInt32 Code; - - *inSizeProcessed = 0; - *outSizeProcessed = 0; - - { - UInt32 i; - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - } - - RC_INIT(inStream, inSize); - - - while(nowPos < outSize) - { - CProb *prob; - UInt32 bound; - int posState = (int)( - (nowPos - ) - & posStateMask); - - prob = p + IsMatch + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - int symbol = 1; - UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state >= kNumLitStates) - { - int matchByte; - matchByte = outStream[nowPos - rep0]; - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); - } - while (symbol < 0x100) - { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) - } - previousByte = (Byte)symbol; - - outStream[nowPos++] = previousByte; - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - } - else - { - UpdateBit1(prob); - prob = p + IsRep + state; - IfBit0(prob) - { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - UpdateBit0(prob); - - if (nowPos == 0) - return LZMA_RESULT_DATA_ERROR; - - state = state < kNumLitStates ? 9 : 11; - previousByte = outStream[nowPos - rep0]; - outStream[nowPos++] = previousByte; - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; - } - { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; - } - - if (state < 4) - { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } - } - - len += kMatchMinLen; - if (rep0 > nowPos) - return LZMA_RESULT_DATA_ERROR; - - - do - { - previousByte = outStream[nowPos - rep0]; - len--; - outStream[nowPos++] = previousByte; - } - while(len != 0 && nowPos < outSize); - } - } - RC_NORMALIZE; - - - *inSizeProcessed = (SizeT)(Buffer - inStream); - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + int look_ahead_ptr = 4; + union { + Byte raw[4]; + UInt32 dw; + } look_ahead; + UInt32 Range; + UInt32 Code; + + *inSizeProcessed = 0; + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + RC_INIT(inStream, inSize); + + + while (nowPos < outSize) { + CProb *prob; + UInt32 bound; + int posState = (int)((nowPos) & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) { + int symbol = 1; + UpdateBit0(prob); + prob = p + Literal + (LZMA_LIT_SIZE * ((((nowPos) + & literalPosMask) << lc) + + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) { + int matchByte; + matchByte = outStream[nowPos - rep0]; + do { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, + if (bit != 0) + break, + if (bit == 0) + break) + } while (symbol < 0x100); + } + while (symbol < 0x100) { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + if (state < 4) + state = 0; + else if (state < 10) + state -= 3; + else + state -= 6; + } else { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } else { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << + kNumPosBitsMax) + posState; + IfBit0(prob) { + UpdateBit0(prob); + + if (nowPos == 0) + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates + ? 9 : 11; + previousByte = outStream[nowPos + - rep0]; + outStream[nowPos++] = + previousByte; + + continue; + } else + UpdateBit1(prob); + } else { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) { + UpdateBit0(prob); + distance = rep1; + } else { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) { + UpdateBit0(prob); + distance = rep2; + } else { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState + << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } else { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) { + UpdateBit0(probLen); + probLen = prob + LenMid + + (posState << + kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } else { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, + len); + len += offset; + } + + if (state < 4) { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? + len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, + posSlot); + if (posSlot >= kStartPosModelIndex) { + int numDirectBits = ((posSlot >> 1) + - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 + - posSlot - 1; + } else { + numDirectBits -= kNumAlignBits; + do { + RC_NORMALIZE; + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) { + Code -= Range; + rep0 |= 1; + } + } while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do { + CProb *prob3 = prob + + mi; + RC_GET_BIT2(prob3, mi, + ;, rep0 |= i); + i <<= 1; + } while (--numDirectBits != 0); + } + } else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + if (rep0 > nowPos) + return LZMA_RESULT_DATA_ERROR; + + + do { + previousByte = outStream[nowPos - rep0]; + len--; + outStream[nowPos++] = previousByte; + } while (len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + + *inSizeProcessed = (SizeT)(Buffer - inStream); + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; } diff --git a/src/lib/lzmadecode.h b/src/lib/lzmadecode.h index 34c9f14..69f5b3d 100644 --- a/src/lib/lzmadecode.h +++ b/src/lib/lzmadecode.h @@ -38,30 +38,29 @@ typedef UInt32 SizeT; #define LZMA_PROPERTIES_SIZE 5 -typedef struct _CLzmaProperties -{ - int lc; - int lp; - int pb; -}CLzmaProperties; +typedef struct _CLzmaProperties { + int lc; + int lp; + int pb; +} CLzmaProperties; -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); +int LzmaDecodeProperties(CLzmaProperties *propsRes, + const unsigned char *propsData, int size); -#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) +#define LzmaGetNumProbs(Properties) \ + (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc \ + + (Properties)->lp))) #define kLzmaNeedInitId (-2) -typedef struct _CLzmaDecoderState -{ - CLzmaProperties Properties; - CProb *Probs; - - +typedef struct _CLzmaDecoderState { + CLzmaProperties Properties; + CProb *Probs; } CLzmaDecoderState; int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); #endif diff --git a/src/lib/memcmp.c b/src/lib/memcmp.c index 46f13a4..89059a1 100644 --- a/src/lib/memcmp.c +++ b/src/lib/memcmp.c @@ -7,7 +7,7 @@ int memcmp(const void *src1, const void *src2, size_t bytes) s1 = src1; s2 = src2; result = 0; - while((bytes > 0) && (result == 0)) { + while ((bytes > 0) && (result == 0)) { result = *s1 - *s2; bytes--; s1++; diff --git a/src/lib/memmove.c b/src/lib/memmove.c index 241917c..fd75135 100644 --- a/src/lib/memmove.c +++ b/src/lib/memmove.c @@ -5,15 +5,13 @@ void *memmove(void *vdest, const void *vsrc, size_t count) char *dest = vdest; if (dest <= src) { - while (count--) { + while (count--) *dest++ = *src++; - } } else { src += count - 1; dest += count - 1; - while(count--) { + while (count--) *dest-- = *src--; - } } return vdest; } diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 489b562..75e10b8 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -17,22 +17,22 @@ #include <memrange.h> static inline void range_entry_link(struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry *r) { r->next = *prev_ptr; *prev_ptr = r; } static inline void range_entry_unlink(struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry *r) { *prev_ptr = r->next; r->next = NULL; } static inline void range_entry_unlink_and_free(struct memranges *ranges, - struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry **prev_ptr, + struct range_entry *r) { range_entry_unlink(prev_ptr, r); range_entry_link(&ranges->free_list, r); @@ -54,7 +54,7 @@ static struct range_entry *alloc_range(struct memranges *ranges) static inline struct range_entry * range_list_add(struct memranges *ranges, struct range_entry **prev_ptr, - resource_t begin, resource_t end, unsigned long tag) + resource_t begin, resource_t end, unsigned long tag) { struct range_entry *new_entry; @@ -102,8 +102,8 @@ static void merge_neighbor_entries(struct memranges *ranges) } static void remove_memranges(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long unused) + resource_t begin, resource_t end, + unsigned long unused) { struct range_entry *cur; struct range_entry *next; @@ -136,7 +136,7 @@ static void remove_memranges(struct memranges *ranges, if (end >= cur->end) { begin = cur->end + 1; range_entry_unlink_and_free(ranges, prev_ptr, - cur); + cur); continue; } } @@ -152,7 +152,7 @@ static void remove_memranges(struct memranges *ranges, /* Hole punched in middle of entry. */ if (begin > cur->begin && tmp_end < cur->end) { range_list_add(ranges, &cur->next, end + 1, cur->end, - cur->tag); + cur->tag); cur->end = begin - 1; break; } @@ -168,8 +168,8 @@ static void remove_memranges(struct memranges *ranges, } static void merge_add_memranges(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long tag) + resource_t begin, resource_t end, + unsigned long tag) { struct range_entry *cur; struct range_entry **prev_ptr; @@ -202,7 +202,7 @@ static void merge_add_memranges(struct memranges *ranges, } void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, - unsigned long new_tag) + unsigned long new_tag) { struct range_entry *r; @@ -215,12 +215,12 @@ void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, } typedef void (*range_action_t)(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long tag); + resource_t begin, resource_t end, + unsigned long tag); static void do_action(struct memranges *ranges, - resource_t base, resource_t size, unsigned long tag, - range_action_t action) + resource_t base, resource_t size, unsigned long tag, + range_action_t action) { resource_t end; resource_t begin; @@ -238,13 +238,13 @@ static void do_action(struct memranges *ranges, } void memranges_create_hole(struct memranges *ranges, - resource_t base, resource_t size) + resource_t base, resource_t size) { do_action(ranges, base, size, -1, remove_memranges); } void memranges_insert(struct memranges *ranges, - resource_t base, resource_t size, unsigned long tag) + resource_t base, resource_t size, unsigned long tag) { do_action(ranges, base, size, tag, merge_add_memranges); } @@ -267,9 +267,9 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res) } void memranges_add_resources_filter(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag, - memrange_filter_t filter) + unsigned long mask, unsigned long match, + unsigned long tag, + memrange_filter_t filter) { struct collect_context context; @@ -284,14 +284,14 @@ void memranges_add_resources_filter(struct memranges *ranges, } void memranges_add_resources(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) + unsigned long mask, unsigned long match, + unsigned long tag) { memranges_add_resources_filter(ranges, mask, match, tag, NULL); } void memranges_init_empty(struct memranges *ranges, struct range_entry *to_free, - size_t num_free) + size_t num_free) { size_t i; @@ -303,8 +303,8 @@ void memranges_init_empty(struct memranges *ranges, struct range_entry *to_free, } void memranges_init(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) + unsigned long mask, unsigned long match, + unsigned long tag) { memranges_init_empty(ranges, NULL, 0); memranges_add_resources(ranges, mask, match, tag); @@ -314,12 +314,12 @@ void memranges_teardown(struct memranges *ranges) { while (ranges->entries != NULL) { range_entry_unlink_and_free(ranges, &ranges->entries, - ranges->entries); + ranges->entries); } } void memranges_fill_holes_up_to(struct memranges *ranges, - resource_t limit, unsigned long tag) + resource_t limit, unsigned long tag) { struct range_entry *cur; struct range_entry *prev; @@ -341,7 +341,7 @@ void memranges_fill_holes_up_to(struct memranges *ranges, if (end >= limit) end = limit - 1; range_list_add(ranges, &prev->next, - range_entry_end(prev), end, tag); + range_entry_end(prev), end, tag); } prev = cur; @@ -356,14 +356,14 @@ void memranges_fill_holes_up_to(struct memranges *ranges, * to be added to cover the range up to the limit. */ if (prev != NULL && range_entry_end(prev) < limit) range_list_add(ranges, &prev->next, range_entry_end(prev), - limit - 1, tag); + limit - 1, tag); /* Merge all entries that were newly added. */ merge_neighbor_entries(ranges); } struct range_entry *memranges_next_entry(struct memranges *ranges, - const struct range_entry *r) + const struct range_entry *r) { return r->next; } diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c index 8dfcfab..86c232e 100644 --- a/src/lib/mocked_tlcl.c +++ b/src/lib/mocked_tlcl.c @@ -23,17 +23,20 @@ #define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) #endif -uint32_t tlcl_lib_init(void) { +uint32_t tlcl_lib_init(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_startup(void) { +uint32_t tlcl_startup(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_resume(void) { +uint32_t tlcl_resume(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } @@ -56,45 +59,51 @@ uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) return TPM_E_NO_DEVICE; } -uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) +uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) { VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) +uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) { VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_assert_physical_presence(void) { +uint32_t tlcl_assert_physical_presence(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_physical_presence_cmd_enable(void) { +uint32_t tlcl_physical_presence_cmd_enable(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_finalize_physical_presence(void) { +uint32_t tlcl_finalize_physical_presence(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_set_nv_locked(void) { +uint32_t tlcl_set_nv_locked(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_force_clear(void) { +uint32_t tlcl_force_clear(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_set_enable(void) { +uint32_t tlcl_set_enable(void) +{ VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } @@ -105,14 +114,14 @@ uint32_t tlcl_set_deactivated(uint8_t flag) return TPM_E_NO_DEVICE; } -uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags) { VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } -uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, - uint8_t *nvlocked) +uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated, + uint8_t *nvlocked) { VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; @@ -124,8 +133,8 @@ uint32_t tlcl_set_global_lock(void) return TPM_E_NO_DEVICE; } -uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, - uint8_t* out_digest) +uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, + uint8_t *out_digest) { VBDEBUG("MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; diff --git a/src/lib/primitive_memtest.c b/src/lib/primitive_memtest.c index 6e58233..c699e89 100644 --- a/src/lib/primitive_memtest.c +++ b/src/lib/primitive_memtest.c @@ -25,7 +25,7 @@ int primitive_memtest(uintptr_t base, uintptr_t size) printk(BIOS_SPEW, "Performing primitive memory test.\n"); printk(BIOS_SPEW, "DRAM start: 0x%08x, DRAM size: 0x%08x", base, size); - for(i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { + for (i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { if (i % 0x100000 == 0) { if ((i % 0x800000) == 0) printk(BIOS_SPEW, "\n"); @@ -38,7 +38,7 @@ int primitive_memtest(uintptr_t base, uintptr_t size) } printk(BIOS_SPEW, "\n\nReading back DRAM content"); - for(i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { + for (i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { if (i % 0x100000 == 0) { if ((i % 0x800000) == 0) printk(BIOS_SPEW, "\n"); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 58c1a8a..128869b 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -166,7 +166,6 @@ static struct prog global_payload = void __attribute__((weak)) mirror_payload(struct prog *payload) { - return; } void payload_load(void) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 6d12060..419d0eb 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -84,7 +84,7 @@ static int ram_bitset_nodie(unsigned long start) uint8_t verbose = 0; printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); - for (idx=0; idx<0x400; idx+=4) { + for (idx = 0; idx < 0x400; idx += 4) { test_pattern(idx, &addr, &value); write_phys(start + addr, value); } @@ -94,7 +94,7 @@ static int ram_bitset_nodie(unsigned long start) printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); failures = 0; - for (idx=0; idx<0x400; idx+=4) { + for (idx = 0; idx < 0x400; idx += 4) { test_pattern(idx, &addr, &value); value2 = read_phys(start + addr); @@ -120,9 +120,8 @@ static int ram_bitset_nodie(unsigned long start) post_code(0xea); printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); return 1; - } else { - printk(BIOS_DEBUG, "\nDRAM range verified.\n"); } + printk(BIOS_DEBUG, "\nDRAM range verified.\n"); return 0; } @@ -162,7 +161,7 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) unsigned short int idx; unsigned char failed, failures; - for (idx=0; idx<0x400; idx+=4) { + for (idx = 0; idx < 0x400; idx += 4) { test_pattern(idx, &addr, &value); write_phys(start + addr, value); } @@ -171,7 +170,7 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop) phys_memory_barrier(); failures = 0; - for (idx=0; idx<0x400; idx+=4) { + for (idx = 0; idx < 0x400; idx += 4) { test_pattern(idx, &addr, &value); value2 = read_phys(start + addr); @@ -189,19 +188,19 @@ static void __quick_ram_check(uintptr_t dst) write_phys(dst, 0x55555555); phys_memory_barrier(); if (read_phys(dst) != 0x55555555) - fail=1; + fail = 1; write_phys(dst, 0xaaaaaaaa); phys_memory_barrier(); if (read_phys(dst) != 0xaaaaaaaa) - fail=1; + fail = 1; write_phys(dst, 0x00000000); phys_memory_barrier(); if (read_phys(dst) != 0x00000000) - fail=1; + fail = 1; write_phys(dst, 0xffffffff); phys_memory_barrier(); if (read_phys(dst) != 0xffffffff) - fail=1; + fail = 1; write_phys(dst, backup); if (fail) { diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 16efa36..78301dc 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -41,14 +41,14 @@ #endif static inline void reg_script_set_dev(struct reg_script_context *ctx, - device_t dev) + device_t dev) { ctx->dev = dev; ctx->res = NULL; } static inline void reg_script_set_step(struct reg_script_context *ctx, - const struct reg_script *step) + const struct reg_script *step) { ctx->step = step; } @@ -192,8 +192,7 @@ static uint32_t reg_script_read_res(struct reg_script_context *ctx) }; reg_script_set_step(ctx, &io_step); val = reg_script_read_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { + } else if (res->flags & IORESOURCE_MEM) { const struct reg_script mmio_step = { .size = step->size, .reg = res->base + step->reg, @@ -223,8 +222,7 @@ static void reg_script_write_res(struct reg_script_context *ctx) }; reg_script_set_step(ctx, &io_step); reg_script_write_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { + } else if (res->flags & IORESOURCE_MEM) { const struct reg_script mmio_step = { .size = step->size, .reg = res->base + step->reg, @@ -399,7 +397,7 @@ static const struct reg_script_bus_entry { extern const struct reg_script_bus_entry *_rsbe_init_begin[]; extern const struct reg_script_bus_entry *_ersbe_init_begin[]; - const struct reg_script_bus_entry * const * bus; + const struct reg_script_bus_entry * const *bus; size_t table_entries; size_t i; @@ -478,7 +476,7 @@ static uint64_t reg_script_read(struct reg_script_context *ctx) /* Read from the platform specific bus */ bus = find_bus(step); - if (NULL != bus) { + if (bus != NULL) { value = bus->reg_script_read(ctx); break; } @@ -532,7 +530,7 @@ static void reg_script_write(struct reg_script_context *ctx) /* Write to the platform specific bus */ bus = find_bus(step); - if (NULL != bus) { + if (bus != NULL) { bus->reg_script_write(ctx); break; } @@ -603,7 +601,7 @@ static void reg_script_rxw(struct reg_script_context *ctx) * as the previous one. That will run to completion and then move on to the * next step of the previous context. */ static void reg_script_run_next(struct reg_script_context *ctx, - const struct reg_script *step); + const struct reg_script *step); static void reg_script_run_step(struct reg_script_context *ctx, @@ -670,7 +668,7 @@ static void reg_script_run_with_context(struct reg_script_context *ctx) } static void reg_script_run_next(struct reg_script_context *prev_ctx, - const struct reg_script *step) + const struct reg_script *step) { struct reg_script_context ctx; diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 7043157..3cb80f1 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -33,7 +33,7 @@ static inline int rmodule_is_loaded(const struct rmodule *module) /* Calculate a loaded program address based on the blob address. */ static inline void *rmodule_load_addr(const struct rmodule *module, - uintptr_t blob_addr) + uintptr_t blob_addr) { char *loc = module->location; return &loc[blob_addr - module->header->module_link_start_address]; @@ -66,7 +66,7 @@ int rmodule_parse(void *ptr, struct rmodule *module) /* The payload lives after the header. */ module->payload = &base[rhdr->payload_begin_offset]; module->payload_size = rhdr->payload_end_offset - - rhdr->payload_begin_offset; + rhdr->payload_begin_offset; module->relocations = &base[rhdr->relocations_begin_offset]; return 0; @@ -204,7 +204,7 @@ int rmodule_load(void *base, struct rmodule *module) } int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, - size_t *region_size, int *load_offset) + size_t *region_size, int *load_offset) { /* region_alignment must be a power of 2. */ if (region_alignment & (region_alignment - 1)) @@ -270,7 +270,7 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) rmodule_offset = rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, - stage.memlen, &region_size, &load_offset); + stage.memlen, &region_size, &load_offset); stage_region = cbmem_add(rsl->cbmem_id, region_size); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 162a034..5808dac 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -135,7 +135,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) return 0; if (!arch_supports_bounce_buffer()) - die ("bounce buffer not supported"); + die("bounce buffer not supported"); start = seg->s_dstaddr; middle = start + seg->s_filesz; @@ -170,7 +170,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) /* compute the new value of start */ start = seg->s_dstaddr; - printk(BIOS_SPEW, " early: [0x%016lx, 0x%016lx, 0x%016lx)\n", + printk(BIOS_SPEW, + " early: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); @@ -199,7 +200,8 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) /* Order by stream offset */ segment_insert_after(seg, new); - printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", + printk(BIOS_SPEW, + " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); @@ -274,8 +276,10 @@ static int build_self_segment_list( + segment.offset; new->s_filesz = segment.len; - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, + " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_srcaddr, + new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { @@ -369,7 +373,7 @@ static int load_self_segments(struct segment *head, struct prog *payload, return 0; } - for(ptr = head->next; ptr != head; ptr = ptr->next) { + for (ptr = head->next; ptr != head; ptr = ptr->next) { /* * Add segments to bootmem memory map before a bounce buffer is * allocated so that there aren't conflicts with the actual @@ -391,20 +395,23 @@ static int load_self_segments(struct segment *head, struct prog *payload, return 0; } - for(ptr = head->next; ptr != head; ptr = ptr->next) { + for (ptr = head->next; ptr != head; ptr = ptr->next) { unsigned char *dest, *src, *middle, *end; size_t len, memsz; - printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", + printk(BIOS_DEBUG, + "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); - /* Modify the segment to load onto the bounce_buffer if necessary. + /* Modify the segment to load onto the bounce_buffer if + * necessary. */ if (relocate_segment(bounce_buffer, ptr)) { ptr = (ptr->prev)->prev; continue; } - printk(BIOS_DEBUG, "Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", + printk(BIOS_DEBUG, + "Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); /* Compute the boundaries of the segment */ @@ -415,33 +422,35 @@ static int load_self_segments(struct segment *head, struct prog *payload, end = dest + memsz; /* Copy data from the initial buffer */ - switch(ptr->compression) { - case CBFS_COMPRESS_LZMA: { - printk(BIOS_DEBUG, "using LZMA\n"); - timestamp_add_now(TS_START_ULZMA); - len = ulzman(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZMA); - if (!len) /* Decompression Error. */ - return 0; - break; - } - case CBFS_COMPRESS_LZ4: { - printk(BIOS_DEBUG, "using LZ4\n"); - timestamp_add_now(TS_START_ULZ4F); - len = ulz4fn(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZ4F); - if (!len) /* Decompression Error. */ - return 0; - break; - } - case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); - break; - } - default: - printk(BIOS_INFO, "CBFS: Unknown compression type %d\n", ptr->compression); - return -1; + switch (ptr->compression) { + case CBFS_COMPRESS_LZMA: { + printk(BIOS_DEBUG, "using LZMA\n"); + timestamp_add_now(TS_START_ULZMA); + len = ulzman(src, len, dest, memsz); + timestamp_add_now(TS_END_ULZMA); + if (!len) /* Decompression Error. */ + return 0; + break; + } + case CBFS_COMPRESS_LZ4: { + printk(BIOS_DEBUG, "using LZ4\n"); + timestamp_add_now(TS_START_ULZ4F); + len = ulz4fn(src, len, dest, memsz); + timestamp_add_now(TS_END_ULZ4F); + if (!len) /* Decompression Error. */ + return 0; + break; + } + case CBFS_COMPRESS_NONE: { + printk(BIOS_DEBUG, "it's not compressed!\n"); + memcpy(dest, src, len); + break; + } + default: + printk(BIOS_INFO, + "CBFS: Unknown compression type %d\n", + ptr->compression); + return -1; } /* Calculate middle after any changes to len. */ middle = dest + len; @@ -453,29 +462,43 @@ static int load_self_segments(struct segment *head, struct prog *payload, /* Zero the extra bytes between middle & end */ if (middle < end) { - printk(BIOS_DEBUG, "Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", - (unsigned long)middle, (unsigned long)(end - middle)); + printk(BIOS_DEBUG, + "Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", + (unsigned long)middle, + (unsigned long)(end - middle)); /* Zero the extra bytes */ memset(middle, 0, end - middle); } - /* Copy the data that's outside the area that shadows ramstage */ - printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer); + /* Copy the data that's outside the area that shadows + * ramstage + */ + printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, + end, bounce_buffer); if ((unsigned long)end > bounce_buffer) { if ((unsigned long)dest < bounce_buffer) { unsigned char *from = dest; - unsigned char *to = (unsigned char*)(lb_start-(bounce_buffer-(unsigned long)dest)); - unsigned long amount = bounce_buffer-(unsigned long)dest; - printk(BIOS_DEBUG, "move prefix around: from %p, to %p, amount: %lx\n", from, to, amount); + unsigned char *to = (unsigned char *)(lb_start - + (bounce_buffer - (unsigned long)dest)); + unsigned long amount = bounce_buffer - + (unsigned long)dest; + printk(BIOS_DEBUG, + "move prefix around: from %p, to %p, amount: %lx\n", + from, to, amount); memcpy(to, from, amount); } - if ((unsigned long)end > bounce_buffer + (lb_end - lb_start)) { - unsigned long from = bounce_buffer + (lb_end - lb_start); + if ((unsigned long)end > bounce_buffer + (lb_end - + lb_start)) { + unsigned long from = bounce_buffer + (lb_end - + lb_start); unsigned long to = lb_end; - unsigned long amount = (unsigned long)end - from; - printk(BIOS_DEBUG, "move suffix around: from %lx, to %lx, amount: %lx\n", from, to, amount); - memcpy((char*)to, (char*)from, amount); + unsigned long amount = (unsigned long)end - + from; + printk(BIOS_DEBUG, + "move suffix around: from %lx, to %lx, amount: %lx\n", + from, to, amount); + memcpy((char *)to, (char *)from, amount); } } diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 8f358bb..1e03698 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -185,26 +185,28 @@ int read_ddr3_spd_from_cbfs(u8 *buf, int idx) if (!spd_file || spd_file_len < min_len) return -1; - memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), + CONFIG_DIMM_SPD_SIZE); u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) || (buf[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + printk(BIOS_WARNING, + "SPD CRC %02x%02x is invalid, should be %04x\n", buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); buf[SPD_CRC_LO] = crc & 0xff; buf[SPD_CRC_HI] = crc >> 8; u16 i; printk(BIOS_WARNING, "\nDisplay the SPD"); for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { - if((i % 16) == 0x00) + if ((i % 16) == 0x00) printk(BIOS_WARNING, "\n%02x: ", i); printk(BIOS_WARNING, "%02x ", buf[i]); } printk(BIOS_WARNING, "\n"); - } - return 0; + } + return 0; } #endif diff --git a/src/lib/stack.c b/src/lib/stack.c index bebeea2..7aafa8f 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -18,7 +18,8 @@ it with the version available from LANL. */ /* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL * rminnich(a)lanl.gov - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, + * Raptor Engineering */ #include <assert.h> @@ -33,7 +34,7 @@ int checkstack(void *top_of_stack, int core) int i; u32 *stack = (u32 *) (top_of_stack - stack_size); - if (stack[0] != 0xDEADBEEF){ + if (stack[0] != 0xDEADBEEF) { printk(BIOS_ERR, "Stack overrun on CPU%d (address %p overwritten). " "Increase stack from current %zu bytes\n", core, stack, stack_size); @@ -41,7 +42,7 @@ int checkstack(void *top_of_stack, int core) return -1; } - for(i = 1; i < stack_size/sizeof(stack[0]); i++){ + for (i = 1; i < stack_size/sizeof(stack[0]); i++) { if (stack[i] == 0xDEADBEEF) continue; printk(BIOS_SPEW, "CPU%d: stack: %p - %p, ", @@ -54,5 +55,4 @@ int checkstack(void *top_of_stack, int core) } return 0; - } diff --git a/src/lib/thread.c b/src/lib/thread.c index 75d0cfc..f3cbd91 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -121,9 +121,8 @@ static void idle_thread(void *unused) { /* This thread never voluntarily yields. */ thread_prevent_coop(); - while (1) { + while (1) timers_run(); - } } static void schedule(struct thread *t) @@ -187,8 +186,8 @@ static void asmlinkage call_wrapper_block_state(void *arg) /* Prepare a thread so that it starts by executing thread_entry(thread_arg). * Within thread_entry() it will call func(arg). */ static void prepare_thread(struct thread *t, void *func, void *arg, - void asmlinkage (*thread_entry)(void *), - void *thread_arg) + asmlinkage void (*thread_entry)(void *), + void *thread_arg) { /* Stash the function and argument to run. */ t->entry = func; @@ -214,9 +213,8 @@ static void idle_thread_init(void) t = get_free_thread(); - if (t == NULL) { + if (t == NULL) die("No threads available for idle thread!\n"); - } /* Queue idle thread to run once all other threads have yielded. */ prepare_thread(t, idle_thread, NULL, call_wrapper, NULL); @@ -228,7 +226,8 @@ static void idle_thread_init(void) /* Don't inline this function so the timeout_callback won't have its storage * space on the stack cleaned up before the call to schedule(). */ static int __attribute__((noinline)) -thread_yield_timed_callback(struct timeout_callback *tocb, unsigned microsecs) +thread_yield_timed_callback(struct timeout_callback *tocb, + unsigned int microsecs) { tocb->priv = current_thread(); tocb->callback = thread_resume_from_timeout; @@ -307,7 +306,7 @@ int thread_run(void (*func)(void *), void *arg) } int thread_run_until(void (*func)(void *), void *arg, - boot_state_t state, boot_state_sequence_t seq) + boot_state_t state, boot_state_sequence_t seq) { struct thread *current; struct thread *t; @@ -337,7 +336,7 @@ int thread_run_until(void (*func)(void *), void *arg, return 0; } -int thread_yield_microseconds(unsigned microsecs) +int thread_yield_microseconds(unsigned int microsecs) { struct thread *current; struct timeout_callback tocb; diff --git a/src/lib/timer.c b/src/lib/timer.c index da24067..58d32ee 100644 --- a/src/lib/timer.c +++ b/src/lib/timer.c @@ -18,9 +18,9 @@ #include <delay.h> #include <thread.h> -__attribute__((weak)) void init_timer() { /* do nothing */ } +__attribute__((weak)) void init_timer(void) { /* do nothing */ } -void udelay(unsigned usec) +void udelay(unsigned int usec) { struct stopwatch sw; diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index fe3e8b5..06872a8 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -49,7 +49,7 @@ static inline struct timeout_callback *timer_queue_head(struct timer_queue *tq) } static int timer_queue_insert(struct timer_queue *tq, - struct timeout_callback *tocb) + struct timeout_callback *tocb) { int index; @@ -99,7 +99,7 @@ static int timer_queue_min_child_index(struct timer_queue *tq, int index) return left_child_index; if (mono_time_cmp(&tq->queue[left_child_index]->expiration, - &tq->queue[right_child_index]->expiration) < 0) { + &tq->queue[right_child_index]->expiration) < 0) { return left_child_index; } return right_child_index; @@ -165,7 +165,7 @@ int timer_sched_callback(struct timeout_callback *tocb, unsigned long us) { struct mono_time current_time; - if ((long)us< 0) + if ((long)us < 0) return -1; timer_monotonic_get(&current_time); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 2f2a5d8..5f84cf4 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -92,7 +92,7 @@ static struct timestamp_cache *timestamp_cache_get(void) static struct timestamp_table *timestamp_alloc_cbmem_table(void) { - struct timestamp_table* tst; + struct timestamp_table *tst; tst = cbmem_add(CBMEM_ID_TIMESTAMP, sizeof(struct timestamp_table) + diff --git a/src/lib/tlcl.c b/src/lib/tlcl.c index 0a4706b..e3620ea 100644 --- a/src/lib/tlcl.c +++ b/src/lib/tlcl.c @@ -47,41 +47,46 @@ static int tpm_send_receive(const uint8_t *request, } /* Sets the size field of a TPM command. */ -static inline void set_tpm_command_size(uint8_t* buffer, uint32_t size) { +static inline void set_tpm_command_size(uint8_t *buffer, uint32_t size) +{ to_tpm_uint32(buffer + sizeof(uint16_t), size); } /* Gets the size field of a TPM command. */ __attribute__((unused)) -static inline int tpm_command_size(const uint8_t* buffer) { +static inline int tpm_command_size(const uint8_t *buffer) +{ uint32_t size; from_tpm_uint32(buffer + sizeof(uint16_t), &size); return (int) size; } /* Gets the code field of a TPM command. */ -static inline int tpm_command_code(const uint8_t* buffer) { +static inline int tpm_command_code(const uint8_t *buffer) +{ uint32_t code; from_tpm_uint32(buffer + sizeof(uint16_t) + sizeof(uint32_t), &code); return code; } /* Gets the return code field of a TPM result. */ -static inline int tpm_return_code(const uint8_t* buffer) { +static inline int tpm_return_code(const uint8_t *buffer) +{ return tpm_command_code(buffer); } /* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or * DOING_SELFTEST errors are returned. */ -static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, - uint8_t* response, int max_length) { +static uint32_t tlcl_send_receive_no_retry(const uint8_t *request, + uint8_t *response, int max_length) +{ uint32_t response_length = max_length; uint32_t result; result = tpm_send_receive(request, tpm_command_size(request), response, &response_length); - if (0 != result) { + if (result != 0) { /* Communication with TPM failed, so response is garbage */ VBDEBUG("TPM: command 0x%x send/receive failed: 0x%x\n", tpm_command_code(request), result); @@ -103,8 +108,9 @@ return result; /* Sends a TPM command and gets a response. Returns 0 if success or the TPM * error code if error. Waits for the self test to complete if needed. */ -uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, - int max_length) { +uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response, + int max_length) +{ uint32_t result = tlcl_send_receive_no_retry(request, response, max_length); /* If the command fails because the self test has not completed, try it @@ -116,7 +122,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, #if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) /* Retry only once */ result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); #else /* This needs serious testing. The TPM specification says: "iii. * The caller MUST wait for the actions of TPM_ContinueSelfTest @@ -125,7 +131,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, * actions have completed other than trying again? */ do { result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); } while (result == TPM_E_DOING_SELFTEST); #endif } @@ -133,7 +139,8 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, } /* Sends a command and returns the error code. */ -static uint32_t send(const uint8_t* command) { +static uint32_t send(const uint8_t *command) +{ uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; return tlcl_send_receive(command, response, sizeof(response)); } @@ -142,7 +149,8 @@ static uint32_t send(const uint8_t* command) { static uint8_t tlcl_init_done CAR_GLOBAL; -uint32_t tlcl_lib_init(void) { +uint32_t tlcl_lib_init(void) +{ uint8_t done = car_get_var(tlcl_init_done); if (done) return VB2_SUCCESS; @@ -157,14 +165,16 @@ uint32_t tlcl_lib_init(void) { return VB2_SUCCESS; } -uint32_t tlcl_startup(void) { +uint32_t tlcl_startup(void) +{ VBDEBUG("TPM: Startup\n"); return send(tpm_startup_cmd.buffer); } -uint32_t tlcl_resume(void) { - VBDEBUG("TPM: Resume\n"); - return send(tpm_resume_cmd.buffer); +uint32_t tlcl_resume(void) +{ + VBDEBUG("TPM: Resume\n"); + return send(tpm_resume_cmd.buffer); } uint32_t tlcl_self_test_full(void) @@ -179,7 +189,7 @@ uint32_t tlcl_continue_self_test(void) VBDEBUG("TPM: Continue self test\n"); /* Call the No Retry version of SendReceive to avoid recursion. */ return tlcl_send_receive_no_retry(tpm_continueselftest_cmd.buffer, - response, sizeof(response)); + response, sizeof(response)); } uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) @@ -193,7 +203,7 @@ uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) return send(cmd.buffer); } -uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) +uint32_t tlcl_write(uint32_t index, const void *data, uint32_t length) { struct s_tpm_nv_write_cmd cmd; uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; @@ -212,7 +222,7 @@ uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) return tlcl_send_receive(cmd.buffer, response, sizeof(response)); } -uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) +uint32_t tlcl_read(uint32_t index, void *data, uint32_t length) { struct s_tpm_nv_read_cmd cmd; uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; @@ -226,7 +236,7 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) result = tlcl_send_receive(cmd.buffer, response, sizeof(response)); if (result == TPM_SUCCESS && length > 0) { - uint8_t* nv_read_cursor = response + kTpmResponseHeaderLength; + uint8_t *nv_read_cursor = response + kTpmResponseHeaderLength; from_tpm_uint32(nv_read_cursor, &result_length); nv_read_cursor += sizeof(uint32_t); memcpy(data, nv_read_cursor, result_length); @@ -236,32 +246,38 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) } -uint32_t tlcl_assert_physical_presence(void) { +uint32_t tlcl_assert_physical_presence(void) +{ VBDEBUG("TPM: Asserting physical presence\n"); return send(tpm_ppassert_cmd.buffer); } -uint32_t tlcl_physical_presence_cmd_enable(void) { +uint32_t tlcl_physical_presence_cmd_enable(void) +{ VBDEBUG("TPM: Enable the physical presence command\n"); return send(tpm_ppenable_cmd.buffer); } -uint32_t tlcl_finalize_physical_presence(void) { +uint32_t tlcl_finalize_physical_presence(void) +{ VBDEBUG("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); return send(tpm_finalizepp_cmd.buffer); } -uint32_t tlcl_set_nv_locked(void) { +uint32_t tlcl_set_nv_locked(void) +{ VBDEBUG("TPM: Set NV locked\n"); return tlcl_define_space(TPM_NV_INDEX_LOCK, 0, 0); } -uint32_t tlcl_force_clear(void) { +uint32_t tlcl_force_clear(void) +{ VBDEBUG("TPM: Force clear\n"); return send(tpm_forceclear_cmd.buffer); } -uint32_t tlcl_set_enable(void) { +uint32_t tlcl_set_enable(void) +{ VBDEBUG("TPM: Enabling TPM\n"); return send(tpm_physicalenable_cmd.buffer); } @@ -275,12 +291,12 @@ uint32_t tlcl_set_deactivated(uint8_t flag) return send(cmd.buffer); } -uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS *pflags) { uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; uint32_t size; uint32_t result = tlcl_send_receive(tpm_getflags_cmd.buffer, response, - sizeof(response)); + sizeof(response)); if (result != TPM_SUCCESS) return result; from_tpm_uint32(response + kTpmResponseHeaderLength, &size); @@ -290,8 +306,8 @@ uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) return result; } -uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, - uint8_t *nvlocked) +uint32_t tlcl_get_flags(uint8_t *disable, uint8_t *deactivated, + uint8_t *nvlocked) { TPM_PERMANENT_FLAGS pflags; uint32_t result = tlcl_get_permanent_flags(&pflags); @@ -312,11 +328,11 @@ uint32_t tlcl_set_global_lock(void) { uint32_t x; VBDEBUG("TPM: Set global lock\n"); - return tlcl_write(TPM_NV_INDEX0, (uint8_t*) &x, 0); + return tlcl_write(TPM_NV_INDEX0, (uint8_t *)&x, 0); } -uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, - uint8_t* out_digest) +uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, + uint8_t *out_digest) { struct s_tpm_extend_cmd cmd; uint8_t response[kTpmResponseHeaderLength + kPcrDigestLength]; diff --git a/src/lib/tlcl_internal.h b/src/lib/tlcl_internal.h index 8261b0d..f6c5014 100644 --- a/src/lib/tlcl_internal.h +++ b/src/lib/tlcl_internal.h @@ -16,14 +16,14 @@ #define kEncAuthLength 20 #define kPcrDigestLength 20 - /* * Conversion functions. to_tpm_TYPE puts a value of type TYPE into a TPM * command buffer. from_tpm_TYPE gets a value of type TYPE from a TPM command * buffer into a variable. */ __attribute__((unused)) -static inline void to_tpm_uint32(uint8_t *buffer, uint32_t x) { +static inline void to_tpm_uint32(uint8_t *buffer, uint32_t x) +{ buffer[0] = (uint8_t)(x >> 24); buffer[1] = (uint8_t)((x >> 16) & 0xff); buffer[2] = (uint8_t)((x >> 8) & 0xff); @@ -34,7 +34,8 @@ static inline void to_tpm_uint32(uint8_t *buffer, uint32_t x) { * See comment for above function. */ __attribute__((unused)) -static inline void from_tpm_uint32(const uint8_t *buffer, uint32_t *x) { +static inline void from_tpm_uint32(const uint8_t *buffer, uint32_t *x) +{ *x = ((buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | @@ -45,7 +46,8 @@ static inline void from_tpm_uint32(const uint8_t *buffer, uint32_t *x) { * See comment for above function. */ __attribute__((unused)) -static inline void to_tpm_uint16(uint8_t *buffer, uint16_t x) { +static inline void to_tpm_uint16(uint8_t *buffer, uint16_t x) +{ buffer[0] = (uint8_t)(x >> 8); buffer[1] = (uint8_t)(x & 0xff); } @@ -54,7 +56,8 @@ static inline void to_tpm_uint16(uint8_t *buffer, uint16_t x) { * See comment for above function. */ __attribute__((unused)) -static inline void from_tpm_uint16(const uint8_t *buffer, uint16_t *x) { +static inline void from_tpm_uint16(const uint8_t *buffer, uint16_t *x) +{ *x = (buffer[0] << 8) | buffer[1]; } diff --git a/src/lib/tlcl_structures.h b/src/lib/tlcl_structures.h index 36c1bb9..5a725bd 100644 --- a/src/lib/tlcl_structures.h +++ b/src/lib/tlcl_structures.h @@ -1,138 +1,180 @@ /* This file is automatically generated */ -const struct s_tpm_extend_cmd{ - uint8_t buffer[34]; - uint16_t pcrNum; - uint16_t inDigest; -} tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, -10, 14, }; +const struct s_tpm_extend_cmd { + uint8_t buffer[34]; + uint16_t pcrNum; + uint16_t inDigest; +} tpm_extend_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, + 10, 14, +}; -const struct s_tpm_get_random_cmd{ - uint8_t buffer[14]; - uint16_t bytesRequested; -} tpm_get_random_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x46, }, -10, }; +const struct s_tpm_get_random_cmd { + uint8_t buffer[14]; + uint16_t bytesRequested; +} tpm_get_random_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x46, }, + 10, +}; -const struct s_tpm_getownership_cmd{ - uint8_t buffer[22]; -} tpm_getownership_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x11, }, +const struct s_tpm_getownership_cmd { + uint8_t buffer[22]; +} tpm_getownership_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, + 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x11, }, }; -const struct s_tpm_getpermissions_cmd{ - uint8_t buffer[22]; - uint16_t index; -} tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, -18, }; +const struct s_tpm_getpermissions_cmd { + uint8_t buffer[22]; + uint16_t index; +} tpm_getpermissions_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, + 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, + 18, +}; -const struct s_tpm_getstclearflags_cmd{ - uint8_t buffer[22]; -} tpm_getstclearflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x9, }, +const struct s_tpm_getstclearflags_cmd { + uint8_t buffer[22]; +} tpm_getstclearflags_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, + 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x9, }, }; -const struct s_tpm_getflags_cmd{ - uint8_t buffer[22]; -} tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, +const struct s_tpm_getflags_cmd { + uint8_t buffer[22]; +} tpm_getflags_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, + 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, }; -const struct s_tpm_physicalsetdeactivated_cmd{ - uint8_t buffer[11]; - uint16_t deactivated; -} tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, }, -10, }; +const struct s_tpm_physicalsetdeactivated_cmd { + uint8_t buffer[11]; + uint16_t deactivated; +} tpm_physicalsetdeactivated_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, }, + 10, +}; -const struct s_tpm_physicalenable_cmd{ - uint8_t buffer[10]; -} tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, }, +const struct s_tpm_physicalenable_cmd { + uint8_t buffer[10]; +} tpm_physicalenable_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, }, }; -const struct s_tpm_physicaldisable_cmd{ - uint8_t buffer[10]; -} tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, }, +const struct s_tpm_physicaldisable_cmd { + uint8_t buffer[10]; +} tpm_physicaldisable_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, }, }; -const struct s_tpm_forceclear_cmd{ - uint8_t buffer[10]; -} tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, +const struct s_tpm_forceclear_cmd { + uint8_t buffer[10]; +} tpm_forceclear_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, }; -const struct s_tpm_readpubek_cmd{ - uint8_t buffer[30]; -} tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, +const struct s_tpm_readpubek_cmd { + uint8_t buffer[30]; +} tpm_readpubek_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, }; -const struct s_tpm_continueselftest_cmd{ - uint8_t buffer[10]; -} tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, }, +const struct s_tpm_continueselftest_cmd { + uint8_t buffer[10]; +} tpm_continueselftest_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, }, }; -const struct s_tpm_selftestfull_cmd{ - uint8_t buffer[10]; -} tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }, +const struct s_tpm_selftestfull_cmd { + uint8_t buffer[10]; +} tpm_selftestfull_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }, }; -const struct s_tpm_resume_cmd{ - uint8_t buffer[12]; -} tpm_resume_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2, }, +const struct s_tpm_resume_cmd { + uint8_t buffer[12]; +} tpm_resume_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2, }, }; -const struct s_tpm_savestate_cmd{ - uint8_t buffer[10]; -} tpm_savestate_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x98, }, +const struct s_tpm_savestate_cmd { + uint8_t buffer[10]; +} tpm_savestate_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x98, }, }; -const struct s_tpm_startup_cmd{ - uint8_t buffer[12]; -} tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1, }, +const struct s_tpm_startup_cmd { + uint8_t buffer[12]; +} tpm_startup_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1, }, }; -const struct s_tpm_finalizepp_cmd{ - uint8_t buffer[12]; -} tpm_finalizepp_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, }, +const struct s_tpm_finalizepp_cmd { + uint8_t buffer[12]; +} tpm_finalizepp_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, }, }; -const struct s_tpm_pplock_cmd{ - uint8_t buffer[12]; -} tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x4, }, +const struct s_tpm_pplock_cmd { + uint8_t buffer[12]; +} tpm_pplock_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x4, }, }; -const struct s_tpm_ppenable_cmd{ - uint8_t buffer[12]; -} tpm_ppenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x20, }, +const struct s_tpm_ppenable_cmd { + uint8_t buffer[12]; +} tpm_ppenable_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x20, }, }; -const struct s_tpm_ppassert_cmd{ - uint8_t buffer[12]; -} tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x8, }, +const struct s_tpm_ppassert_cmd { + uint8_t buffer[12]; +} tpm_ppassert_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x8, }, }; -const struct s_tpm_pcr_read_cmd{ - uint8_t buffer[14]; - uint16_t pcrNum; +const struct s_tpm_pcr_read_cmd { + uint8_t buffer[14]; + uint16_t pcrNum; } tpm_pcr_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, }, -10, }; - -const struct s_tpm_nv_read_cmd{ - uint8_t buffer[22]; - uint16_t index; - uint16_t length; -} tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, -10, 18, }; - -const struct s_tpm_nv_write_cmd{ - uint8_t buffer[256]; - uint16_t index; - uint16_t length; - uint16_t data; -} tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, -10, 18, 22, }; - -const struct s_tpm_nv_definespace_cmd{ - uint8_t buffer[101]; - uint16_t index; - uint16_t perm; - uint16_t size; -} tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, }, -12, 70, 77, }; + 10, +}; + +const struct s_tpm_nv_read_cmd { + uint8_t buffer[22]; + uint16_t index; + uint16_t length; +} tpm_nv_read_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, + 10, 18, +}; + +const struct s_tpm_nv_write_cmd { + uint8_t buffer[256]; + uint16_t index; + uint16_t length; + uint16_t data; +} tpm_nv_write_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, + 10, 18, 22, +}; + +const struct s_tpm_nv_definespace_cmd { + uint8_t buffer[101]; + uint16_t index; + uint16_t perm; + uint16_t size; +} tpm_nv_definespace_cmd = { + {0, 0xc1, 0, 0, 0, 0x65, 0, 0, 0, 0xcc, + 0, 0x18, 0, 0, 0, 0, 0, 3, 0, 0, + 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 3, 0, 0, 0, 0x1f, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x17, + }, + 12, 70, 77, +}; const int kWriteInfoLength = 12; const int kNvDataPublicPermissionsOffset = 60; diff --git a/src/lib/tpm2_tlcl.c b/src/lib/tpm2_tlcl.c index 6c0cd6e..5300262 100644 --- a/src/lib/tpm2_tlcl.c +++ b/src/lib/tpm2_tlcl.c @@ -347,7 +347,8 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size) * value has been extended from default. */ nvds_cmd.publicInfo.authPolicy.t.buffer = pcr0_unchanged_policy; - nvds_cmd.publicInfo.authPolicy.t.size = sizeof(pcr0_unchanged_policy); + nvds_cmd.publicInfo.authPolicy.t.size = + sizeof(pcr0_unchanged_policy); } else { nvds_cmd.publicInfo.attributes = default_space_attributes; } @@ -360,7 +361,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size) return TPM_E_NO_DEVICE; /* Map TPM2 retrun codes into common vboot represenation. */ - switch(response->hdr.tpm_code) { + switch (response->hdr.tpm_code) { case TPM2_RC_SUCCESS: return TPM_SUCCESS; case TPM2_RC_NV_DEFINED:

1 0

Patch merged into coreboot/master: util/docker: Update dockerfiles & build method
by gerrit＠coreboot.org 05 Mar '17

05 Mar '17

the following patch was just integrated into master: commit 561f368a2f2bb9042878e40b1f34bf605b956a33 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Dec 30 17:00:19 2016 -0700 util/docker: Update dockerfiles & build method All files: - Previously, various things were hardcoded into the docker containers that made it necessary to update the Dockerfile files for each new version of the sdk. Turn those into 'Variables" that are updated during the build step. Because the makefile is piping the dockerfile through the sed command and back into the docker build command, the normal docker "COPY" keyword doesn't work. coreboot-jenkins-node changes: - Run ssh-keygen -A to explicitly generate the ssh keys. This fixes an error: Could not load host key: /etc/ssh/ssh_host_dsa_key coreboot-sdk changes: - Remove apt-get upgrade command - The Dockerfile guide recommends not to run this. - Change libssl-dev to libssl1.0-dev. libssl-dev's header files won't build the Chrome-EC codebase. - Add libisl-dev, needed to build the riscv toolchain. - Build the toolchain using the -b option - Add environment variables containing the version and commit that the coreboot-sdk was built from. Makefile: - Update targets to use the version and commit variables Change-Id: I2c1376fe4b791da2a62fca11bc92c4774cbef1c8 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/18001 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> See https://review.coreboot.org/18001 for details. -gerrit

1 0

New patch to review for coreboot: elog: Fix duplicate event type
by Duncan Laurie 05 Mar '17

05 Mar '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18579 -gerrit commit e8a581898c5517b09551eb0b8e4f02e045a9f4c5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sun Mar 5 14:35:57 2017 -0800 elog: Fix duplicate event type The current elog implementation has two event types defined for 0xa7, apparently the result of divergent coreboot trees on chromium where some events were added to ARM systems but not upstreamed until later. Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7. BUG=b:35977516 TEST=check for proper "CPU Thermal Trip" event when investigating a device that is unexpectedly powering down. Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/elog.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index 501e30d..2734612 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -146,9 +146,6 @@ struct elog_event_data_me_extended { /* EC Shutdown Reason */ #define ELOG_TYPE_EC_SHUTDOWN 0xa5 -/* CPU Thermal Trip */ -#define ELOG_TYPE_THERM_TRIP 0xa7 - /* ARM/generic versions of sleep/wake - These came from another firmware * apparently, but not all the firmware sources were updated so that the * elog namespace was coherent. */ @@ -168,6 +165,9 @@ struct elog_event_mem_cache_update { u8 status; } __attribute__ ((packed)); +/* CPU Thermal Trip */ +#define ELOG_TYPE_THERM_TRIP 0xab + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void);

1 0

Patch set updated for coreboot: board-status/to-wiki: Add freedom level to table
by Timothy Pearson 05 Mar '17

05 Mar '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18169 -gerrit commit dd4487abbfa4f7fdaa29668a6b8454fc23276903 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed Jan 18 16:13:18 2017 -0600 board-status/to-wiki: Add freedom level to table Add a freedom level column to the board-status table on the Wiki Change-Id: I88b04159cfe51fd056bfe9cdbf11af43c71374e4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- util/board_status/to-wiki/towiki.sh | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 8b2d1af..e9edd6f 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -56,7 +56,8 @@ cat <<EOF ! align="left" | P 2 ! align="left" | S 3 ! align="left" | F 4 -! align="left" | VCS5 +! align="left" | FL5 +! align="left" | VCS6 EOF for category in laptop server desktop half mini settop "eval" sbc emulation misc unclass; do @@ -173,6 +174,7 @@ EOF rom_protocol="$(sed -n "/^[[:space:]]*ROM protocol:/ s,^[[:space:]]*ROM protocol:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" rom_socketed="$(sed -n "/^[[:space:]]*ROM socketed:/ s,^[[:space:]]*ROM socketed:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" flashrom_support="$(sed -n "/^[[:space:]]*Flashrom support:/ s,^[[:space:]]*Flashrom support:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" + freedom_level="$(sed -n "/^[[:space:]]*Freedom level:/ s,^[[:space:]]*Freedom level:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" vendor_cooperation_score="$(sed -n "/^[[:space:]]*Vendor cooperation score:/ s,^[[:space:]]*Vendor cooperation score:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" vendor_cooperation_page="$(sed -n "/^[[:space:]]*Vendor cooperation page:/ s,^[[:space:]]*Vendor cooperation page:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" board_url="$(sed -n "/^[[:space:]]*Board URL:/ s,^[[:space:]]*Board URL:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" @@ -184,6 +186,7 @@ EOF rom_protocol= rom_socketed= flashrom_support= + freedom_level= vendor_cooperation_score= vendor_cooperation_page= board_url= @@ -457,7 +460,7 @@ EOF elif [ "$rom_socketed" = "n" ]; then echo "| style=\"background:red\" | N" elif [ "$flashrom_support" = "variable" ]; then - echo "| ...7" + echo "| ...8" elif [ "$rom_socketed" = "" ]; then echo "| ?" else @@ -468,12 +471,27 @@ EOF elif [ "$flashrom_support" = "n" ]; then echo "| style=\"background:red\" | N" elif [ "$flashrom_support" = "coreboot-only" ]; then - echo "| style=\"background:yellow\" | ...6" + echo "| style=\"background:yellow\" | ...7" elif [ "$flashrom_support" = "" ]; then echo "| ?" else echo "| $flashrom_support" fi + if [ "$freedom_level" = "platinum" ]; then + echo "| style=\"background:white\" | Platinum" + elif [ "$freedom_level" = "gold" ]; then + echo "| style=\"background:#ffd700\" | Gold" + elif [ "$freedom_level" = "silver" ]; then + echo "| style=\"background:#c0c0c0\" | Silver" + elif [ "$freedom_level" = "bronze" ]; then + echo "| style=\"background:#dca570\" | Bronze" + elif [ "$freedom_level" = "vendorlock" ]; then + echo "| style=\"background:red\" | Vendor Controlled" + elif [ "$freedom_level" = "" ]; then + echo "| ?" + else + echo "| $freedom_level" + fi if [ "$vendor_cooperation_score" = "4" ]; then echo -n "| style=\"background:lime\"" elif [ "$vendor_cooperatio_scoren" = "3" ]; then @@ -497,9 +515,10 @@ cat <<EOF 2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 3 ROM chip socketed (Y/N)? 4 Board supported by [http://www.flashrom.org flashrom] (Y/N)? -5 Vendor Cooperation Score. -6 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. -7 Some boards have ROM sockets, others are soldered. +5 [[Board_freedom_levels|Freedom Level]]. +6 Vendor Cooperation Score. +7 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. +8 Some boards have ROM sockets, others are soldered. EOF

1 0

Patch set updated for coreboot: board-info: Add initial freedom levels for select boards
by Timothy Pearson 05 Mar '17

05 Mar '17

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18168 -gerrit commit 93286fa78cea5a492ea4c9cd8aa1ca477bde326b Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed Jan 18 16:02:10 2017 -0600 board-info: Add initial freedom levels for select boards Coreboot supports a wide variety of hardware, some that allows fully libre fimware to be used, and some where coreboot is a simple shim on top of signed vendor-controlled firmware blobs. An initial ranking system has been created here: https://www.coreboot.org/Board_freedom_levels These mainboards have been ranked according to the criteria in that list. Change-Id: If694825a704ee8ac5d12aa023471c88d845f7a25 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/asus/kcma-d8/board_info.txt | 1 + src/mainboard/asus/kfsn4-dre/board_info.txt | 1 + src/mainboard/asus/kgpe-d16/board_info.txt | 1 + src/mainboard/google/slippy/board_info.txt | 1 + src/mainboard/google/veyron/board_info.txt | 1 + src/mainboard/lenovo/t400/board_info.txt | 1 + src/mainboard/lenovo/t500/board_info.txt | 1 + src/mainboard/lenovo/x200/board_info.txt | 1 + 8 files changed, 8 insertions(+) diff --git a/src/mainboard/asus/kcma-d8/board_info.txt b/src/mainboard/asus/kcma-d8/board_info.txt index e69d31a..0f0045d 100644 --- a/src/mainboard/asus/kcma-d8/board_info.txt +++ b/src/mainboard/asus/kcma-d8/board_info.txt @@ -3,3 +3,4 @@ ROM package: DIP-8 ROM protocol: SPI ROM socketed: y Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/asus/kfsn4-dre/board_info.txt b/src/mainboard/asus/kfsn4-dre/board_info.txt index 678373a..c3f32b5 100644 --- a/src/mainboard/asus/kfsn4-dre/board_info.txt +++ b/src/mainboard/asus/kfsn4-dre/board_info.txt @@ -3,4 +3,5 @@ ROM package: PLCC-32 ROM protocol: LPC ROM socketed: y Flashrom support: y +Freedom level: gold Release year: 2007 diff --git a/src/mainboard/asus/kgpe-d16/board_info.txt b/src/mainboard/asus/kgpe-d16/board_info.txt index e69d31a..0f0045d 100644 --- a/src/mainboard/asus/kgpe-d16/board_info.txt +++ b/src/mainboard/asus/kgpe-d16/board_info.txt @@ -3,3 +3,4 @@ ROM package: DIP-8 ROM protocol: SPI ROM socketed: y Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/google/slippy/board_info.txt b/src/mainboard/google/slippy/board_info.txt index 4e2fd7d..0e26a82 100644 --- a/src/mainboard/google/slippy/board_info.txt +++ b/src/mainboard/google/slippy/board_info.txt @@ -5,3 +5,4 @@ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y +Freedom level: vendorlock diff --git a/src/mainboard/google/veyron/board_info.txt b/src/mainboard/google/veyron/board_info.txt index 5ee07fb..0904de3 100644 --- a/src/mainboard/google/veyron/board_info.txt +++ b/src/mainboard/google/veyron/board_info.txt @@ -4,3 +4,4 @@ Category: misc ROM protocol: SPI ROM socketed: n Flashrom support: y +Freedom level: gold diff --git a/src/mainboard/lenovo/t400/board_info.txt b/src/mainboard/lenovo/t400/board_info.txt index a78a21b..f92fe7f 100644 --- a/src/mainboard/lenovo/t400/board_info.txt +++ b/src/mainboard/lenovo/t400/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Release year: 2008 +Freedom level: bronze diff --git a/src/mainboard/lenovo/t500/board_info.txt b/src/mainboard/lenovo/t500/board_info.txt index 007ec6c..656fe7f 100644 --- a/src/mainboard/lenovo/t500/board_info.txt +++ b/src/mainboard/lenovo/t500/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Clone of: lenovo/t400 +Freedom level: silver diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index c9cc003..0c83fbe 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -4,3 +4,4 @@ ROM protocol: SPI ROM socketed: n Flashrom support: n Release year: 2008 +Freedom level: bronze

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Patch set updated for coreboot: [NOTFORMERGE] agesa-wrapper-killer
by Kyösti Mälkki 05 Mar '17

05 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18477 -gerrit commit ae6c516403705ac452839ecfb9da401cc82a43e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 20:50:53 2017 +0200 [NOTFORMERGE] agesa-wrapper-killer Change-Id: I5fcfed645ccc6f3c78b5050535d97dc95e82ed94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/agesa/amd_late_init.c | 42 --- src/cpu/amd/agesa/cache_as_ram.inc | 92 ++--- src/cpu/amd/agesa/family12/Makefile.inc | 1 + src/cpu/amd/agesa/family12/fixme.c | 3 +- src/cpu/amd/agesa/family12/romstage.c | 37 ++ src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/cpu/amd/agesa/family14/fixme.c | 4 +- src/cpu/amd/agesa/family14/romstage.c | 33 ++ src/cpu/amd/agesa/family15/Makefile.inc | 1 + src/cpu/amd/agesa/family15/fixme.c | 3 +- src/cpu/amd/agesa/family15/romstage.c | 56 ++++ src/cpu/amd/agesa/family15rl/Makefile.inc | 1 + src/cpu/amd/agesa/family15rl/fixme.c | 3 +- src/cpu/amd/agesa/family15rl/romstage.c | 29 ++ src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/fixme.c | 3 +- src/cpu/amd/agesa/family15tn/romstage.c | 30 ++ src/cpu/amd/agesa/family16kb/Makefile.inc | 1 + src/cpu/amd/agesa/family16kb/fixme.c | 3 +- src/cpu/amd/agesa/family16kb/romstage.c | 29 ++ src/cpu/amd/agesa/heapmanager.c | 2 +- src/cpu/amd/agesa/romstage.c | 101 ++++++ src/cpu/amd/agesa/s3_resume.c | 45 +-- src/cpu/amd/agesa/s3_resume.h | 18 +- src/include/cpu/amd/car.h | 11 +- src/mainboard/amd/dinar/BiosCallOuts.c | 2 +- src/mainboard/amd/dinar/Kconfig | 1 + src/mainboard/amd/dinar/OemCustomize.c | 19 +- src/mainboard/amd/dinar/acpi_tables.c | 1 - src/mainboard/amd/dinar/romstage.c | 72 +--- src/mainboard/amd/inagua/OemCustomize.c | 18 +- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/inagua/acpi_tables.c | 1 - src/mainboard/amd/inagua/romstage.c | 65 +--- src/mainboard/amd/olivehill/Kconfig | 1 + src/mainboard/amd/olivehill/OemCustomize.c | 28 +- src/mainboard/amd/olivehill/acpi_tables.c | 1 - src/mainboard/amd/olivehill/mainboard.c | 6 +- src/mainboard/amd/olivehill/romstage.c | 82 +---- src/mainboard/amd/parmer/Kconfig | 1 + src/mainboard/amd/parmer/OemCustomize.c | 28 +- src/mainboard/amd/parmer/acpi_tables.c | 1 - src/mainboard/amd/parmer/mainboard.c | 5 +- src/mainboard/amd/parmer/romstage.c | 76 +---- src/mainboard/amd/persimmon/OemCustomize.c | 18 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 5 - src/mainboard/amd/persimmon/acpi_tables.c | 1 - src/mainboard/amd/persimmon/mainboard.c | 1 - src/mainboard/amd/persimmon/romstage.c | 82 +---- src/mainboard/amd/south_station/OemCustomize.c | 18 +- .../amd/south_station/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/south_station/acpi_tables.c | 1 - src/mainboard/amd/south_station/romstage.c | 63 +--- src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/thatcher/OemCustomize.c | 28 +- src/mainboard/amd/thatcher/acpi_tables.c | 1 - src/mainboard/amd/thatcher/mainboard.c | 5 +- src/mainboard/amd/thatcher/romstage.c | 81 +---- src/mainboard/amd/torpedo/OemCustomize.c | 18 +- src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/torpedo/acpi_tables.c | 1 - src/mainboard/amd/torpedo/romstage.c | 75 +---- src/mainboard/amd/union_station/OemCustomize.c | 18 +- .../amd/union_station/PlatformGnbPcieComplex.h | 4 - src/mainboard/amd/union_station/acpi_tables.c | 1 - src/mainboard/amd/union_station/romstage.c | 64 +--- src/mainboard/asrock/e350m1/OemCustomize.c | 18 +- .../asrock/e350m1/PlatformGnbPcieComplex.h | 4 - src/mainboard/asrock/e350m1/acpi_tables.c | 1 - src/mainboard/asrock/e350m1/romstage.c | 81 +---- src/mainboard/asrock/imb-a180/Kconfig | 1 + src/mainboard/asrock/imb-a180/OemCustomize.c | 29 +- src/mainboard/asrock/imb-a180/acpi_tables.c | 1 - src/mainboard/asrock/imb-a180/mainboard.c | 6 +- src/mainboard/asrock/imb-a180/romstage.c | 91 +---- src/mainboard/asus/f2a85-m/Kconfig | 1 + src/mainboard/asus/f2a85-m/OemCustomize.c | 39 ++- src/mainboard/asus/f2a85-m/acpi_tables.c | 1 - src/mainboard/asus/f2a85-m/mainboard.c | 6 +- src/mainboard/asus/f2a85-m/romstage.c | 151 +++------ src/mainboard/asus/f2a85-m_le/Kconfig | 1 + src/mainboard/asus/f2a85-m_le/OemCustomize.c | 27 -- src/mainboard/bap/ode_e20XX/OemCustomize.c | 28 +- src/mainboard/bap/ode_e20XX/acpi_tables.c | 1 - src/mainboard/bap/ode_e20XX/mainboard.c | 6 +- src/mainboard/bap/ode_e20XX/romstage.c | 80 +---- src/mainboard/biostar/am1ml/Kconfig | 1 + src/mainboard/biostar/am1ml/OemCustomize.c | 28 +- src/mainboard/biostar/am1ml/acpi_tables.c | 1 - src/mainboard/biostar/am1ml/mainboard.c | 6 +- src/mainboard/biostar/am1ml/romstage.c | 106 ++---- src/mainboard/elmex/pcm205400/OemCustomize.c | 18 +- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 5 - src/mainboard/elmex/pcm205400/acpi_tables.c | 1 - src/mainboard/elmex/pcm205400/mainboard.c | 1 - src/mainboard/elmex/pcm205400/romstage.c | 83 +---- src/mainboard/gizmosphere/gizmo/OemCustomize.c | 18 +- .../gizmosphere/gizmo/PlatformGnbPcieComplex.h | 5 - src/mainboard/gizmosphere/gizmo/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo/mainboard.c | 1 - src/mainboard/gizmosphere/gizmo/romstage.c | 80 +---- src/mainboard/gizmosphere/gizmo2/Kconfig | 1 + src/mainboard/gizmosphere/gizmo2/OemCustomize.c | 28 +- src/mainboard/gizmosphere/gizmo2/acpi_tables.c | 1 - src/mainboard/gizmosphere/gizmo2/mainboard.c | 7 +- src/mainboard/gizmosphere/gizmo2/romstage.c | 84 +---- src/mainboard/hp/abm/OemCustomize.c | 28 +- src/mainboard/hp/abm/acpi_tables.c | 1 - src/mainboard/hp/abm/mainboard.c | 6 +- src/mainboard/hp/abm/romstage.c | 96 ++---- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 + src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c | 28 +- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 8 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 70 +--- src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c | 18 +- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 3 - src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 1 - src/mainboard/jetway/nf81-t56n-lf/romstage.c | 96 +----- src/mainboard/lenovo/g505s/Kconfig | 1 + src/mainboard/lenovo/g505s/OemCustomize.c | 28 +- src/mainboard/lenovo/g505s/acpi_tables.c | 1 - src/mainboard/lenovo/g505s/mainboard.c | 7 +- src/mainboard/lenovo/g505s/romstage.c | 70 +--- .../lippert/frontrunner-af/OemCustomize.c | 18 +- .../frontrunner-af/PlatformGnbPcieComplex.h | 5 - src/mainboard/lippert/frontrunner-af/acpi_tables.c | 1 - src/mainboard/lippert/frontrunner-af/mainboard.c | 1 - src/mainboard/lippert/frontrunner-af/romstage.c | 80 +---- src/mainboard/lippert/toucan-af/OemCustomize.c | 18 +- .../lippert/toucan-af/PlatformGnbPcieComplex.h | 5 - src/mainboard/lippert/toucan-af/acpi_tables.c | 1 - src/mainboard/lippert/toucan-af/mainboard.c | 1 - src/mainboard/lippert/toucan-af/romstage.c | 79 +---- src/mainboard/msi/ms7721/OemCustomize.c | 29 +- src/mainboard/msi/ms7721/acpi_tables.c | 1 - src/mainboard/msi/ms7721/mainboard.c | 6 +- src/mainboard/msi/ms7721/romstage.c | 135 ++------ src/mainboard/pcengines/apu1/OemCustomize.c | 18 +- .../pcengines/apu1/PlatformGnbPcieComplex.h | 5 - src/mainboard/pcengines/apu1/acpi_tables.c | 1 - src/mainboard/pcengines/apu1/mainboard.c | 1 - src/mainboard/pcengines/apu1/romstage.c | 93 +----- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/OemCustomize.c | 18 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 1 - src/mainboard/supermicro/h8qgi/romstage.c | 62 +--- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8scm/OemCustomize.c | 20 +- src/mainboard/supermicro/h8scm/acpi_tables.c | 1 - src/mainboard/supermicro/h8scm/romstage.c | 78 +---- src/mainboard/tyan/s8226/BiosCallOuts.c | 2 +- src/mainboard/tyan/s8226/OemCustomize.c | 18 +- src/mainboard/tyan/s8226/acpi_tables.c | 1 - src/mainboard/tyan/s8226/romstage.c | 60 +--- src/northbridge/amd/agesa/Makefile.inc | 7 +- src/northbridge/amd/agesa/agesa_helper.h | 55 +++ src/northbridge/amd/agesa/agesawrapper.c | 352 ------------------- src/northbridge/amd/agesa/agesawrapper.h | 75 ----- src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/agesa/eventlog.c | 36 +- src/northbridge/amd/agesa/family12/Makefile.inc | 3 + src/northbridge/amd/agesa/family12/northbridge.c | 23 +- src/northbridge/amd/agesa/family12/state_machine.c | 78 +++++ src/northbridge/amd/agesa/family14/Makefile.inc | 3 + src/northbridge/amd/agesa/family14/northbridge.c | 31 +- src/northbridge/amd/agesa/family14/state_machine.c | 86 +++++ src/northbridge/amd/agesa/family15/northbridge.c | 20 +- src/northbridge/amd/agesa/family15/state_machine.c | 51 +++ src/northbridge/amd/agesa/family15rl/Makefile.inc | 3 + src/northbridge/amd/agesa/family15rl/northbridge.c | 20 +- .../amd/agesa/family15rl/state_machine.c | 84 +++++ src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 + src/northbridge/amd/agesa/family15tn/northbridge.c | 20 +- .../amd/agesa/family15tn/state_machine.c | 84 +++++ src/northbridge/amd/agesa/family16kb/Makefile.inc | 3 + src/northbridge/amd/agesa/family16kb/northbridge.c | 20 +- .../amd/agesa/family16kb/state_machine.c | 84 +++++ src/northbridge/amd/agesa/oem_s3.c | 3 +- src/northbridge/amd/agesa/state_machine.c | 372 +++++++++++++++++++++ src/northbridge/amd/agesa/state_machine.h | 83 +++++ src/southbridge/amd/agesa/hudson/Makefile.inc | 2 - src/southbridge/amd/agesa/hudson/agesawrapper.c | 92 ----- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 3 +- 187 files changed, 2113 insertions(+), 3322 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 60bae12..b9dae57 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,10 +24,10 @@ romstage-y += s3_resume.c ramstage-y += s3_mtrr.c cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +romstage-y += romstage.c romstage-y += heapmanager.c ramstage-y += heapmanager.c -ramstage-y += amd_late_init.c ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c deleted file mode 100644 index a55ebd8..0000000 --- a/src/cpu/amd/agesa/amd_late_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <bootstate.h> - -#include <northbridge/amd/agesa/agesawrapper.h> - -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif - -static void agesawrapper_post_device(void *unused) -{ - if (acpi_is_wakeup_s3()) - return; - - agesawrapper_amdinitlate(); - -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif - if (!acpi_s3_resume_allowed()) - return; - - agesawrapper_amdS3Save(); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 24db600..f43e6a4 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -26,43 +26,24 @@ #include "gcccar.inc" #include <cpu/x86/cache.h> -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup, cache_as_ram_setup_out cache_as_ram_setup: - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ + /* Preserve BIST. */ + movl %eax, %ebp - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 + post_code(0xa0) post_code(0xa1) + /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK + /* Align the stack to 128 bits. No harm on i386, required on x86_64? */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -105,42 +86,36 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the cpu_init_detected */ - cvtsd2si %xmm1, %esi - /* Pass the BIST result */ - cvtsd2si %xmm0, %edi + .code64 + + /* Calling conventions preserve BIST in %ebp. */ - /* align the stack */ - and $0xFFFFFFF0, %esp + call early_all_cores + + movl %ebp, %edi + call romstage_main + movl %eax, %ebx - .code64 - call cache_as_ram_main .code32 #else - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx + /* Calling conventions preserve BIST in %ebp. */ - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx + call early_all_cores + + pushl %ebp + call romstage_main + movl %eax, %ebx - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main #endif - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop +/* Register %ebx is new stacktop for remaining of romstage. + * It is the only register preserved in AMD_DISABLE_STACK. + */ disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -152,13 +127,20 @@ disable_cache_as_ram: movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0 - xorl %eax, %eax - /* Restore the return stack */ wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret + +#ifdef __x86_64__ +.code64 +#endif + + movl %ebx, %esp + call romstage_after_car + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop cache_as_ram_setup_out: #ifdef __x86_64__ diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 578e178..1a7465d 100644 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,6 +28,7 @@ #***************************************************************************** romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index deeb8b9..d946e1b 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c new file mode 100644 index 0000000..e803f60 --- /dev/null +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include "sb_cimx.h" +#include "SbPlatform.h" +#include "platform_cfg.h" + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + gpioEarlyInit(); + + sb_poweron_init(); + + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 9b4e76b..3da8dd5 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 9a171ed..7d59585 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -14,7 +14,9 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c new file mode 100644 index 0000000..67affbf --- /dev/null +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + sb_Poweron_Init(); + + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index 5742e7a..d01cb2a 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c index 7b8598d..03f4dff 100644 --- a/src/cpu/amd/agesa/family15/fixme.c +++ b/src/cpu/amd/agesa/family15/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" UINT64 diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c new file mode 100644 index 0000000..d7f6d38 --- /dev/null +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include "northbridge/amd/agesa/family10/reset_test.h" +#include <nb_cimx.h> +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + nb_Poweron_Init(); + + sb_Poweron_Init(); + + board_BeforeAgesa(cb); +} + +#if 0 + /* after AMD_INIT_EARLY, before AMD_INIT_POST */ + nb_Ht_Init(); + + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + distinguish_cpu_resets(0); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } +#endif diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15rl/Makefile.inc +++ b/src/cpu/amd/agesa/family15rl/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15rl/fixme.c b/src/cpu/amd/agesa/family15rl/fixme.c index b35d115..2eb9689 100644 --- a/src/cpu/amd/agesa/family15rl/fixme.c +++ b/src/cpu/amd/agesa/family15rl/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c new file mode 100644 index 0000000..d7c7c11 --- /dev/null +++ b/src/cpu/amd/agesa/family15rl/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index b35d115..2eb9689 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c new file mode 100644 index 0000000..2cf436d --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 9367b45..5c2ba8f 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index d1bc4bc..4ea52cc 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -14,7 +14,8 @@ */ #include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c new file mode 100644 index 0000000..d7c7c11 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void platform_once(struct sysinfo *cb) +{ + board_BeforeAgesa(cb); +} diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 087959d..9acd0bd 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -17,7 +17,7 @@ #include "heapManager.h" #include <cbmem.h> -#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c new file mode 100644 index 0000000..1c5ef12 --- /dev/null +++ b/src/cpu/amd/agesa/romstage.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/amd/car.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <halt.h> +#include <program_loading.h> +#include <smp/node.h> +#include <string.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/state_machine.h> + +static void fill_sysinfo(struct sysinfo *cb) +{ + memset(cb, 0, sizeof(*cb)); + cb->s3resume = acpi_is_wakeup_s3(); + + agesa_set_interface(cb); +} + +void * asmlinkage romstage_main(unsigned long bist) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); + + fill_sysinfo(cb); + + if ((initial_apic_id == 0) && boot_cpu()) { + + platform_once(cb); + + console_init(); + } + + printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + initial_apic_id, cpuid_eax(1)); + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + if (!cb->s3resume) + agesa_execute_state(cb, AMD_INIT_POST); + else + agesa_execute_state(cb, AMD_INIT_RESUME); + + uintptr_t stack_top = CACHE_TMP_RAMTOP; + if (cb->s3resume) { + if (!cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } + stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += HIGH_ROMSTAGE_STACK_SIZE; + } + + printk(BIOS_DEBUG, "Move CAR stack.\n"); + return (void*)stack_top; +} + +void asmlinkage romstage_after_car(void) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + printk(BIOS_DEBUG, "CAR disabled.\n"); + + fill_sysinfo(cb); + + if (!cb->s3resume) + agesa_execute_state(cb, AMD_INIT_ENV); + else + agesa_execute_state(cb, AMD_S3LATE_RESTORE); + + if (cb->s3resume) + set_resume_cache(); + + run_ramstage(); +} diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 1e4aadb..34717b9 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -25,32 +25,9 @@ #include <string.h> #include <halt.h> #include "s3_resume.h" +#include <northbridge/amd/agesa/agesa_helper.h> -static void move_stack_high_mem(void) -{ - uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - if (!high_stack) - halt(); - - /* TODO: Make the switch with empty stack instead. */ - memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); - - /* TODO: We only switch stack on BSP. */ -#ifdef __x86_64__ - __asm__ - volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#else - __asm__ - volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#endif -} - -static void set_resume_cache(void) +void set_resume_cache(void) { msr_t msr; @@ -74,21 +51,3 @@ static void set_resume_cache(void) enable_cache(); } - -void prepare_for_resume(void) -{ - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - -} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index ff23966..37ce0d5 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -17,25 +17,9 @@ #define S3_RESUME_H void restore_mtrr(void); -void prepare_for_resume(void); +void set_resume_cache(void); void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); -void *GetHeapBase(void); -void EmptyHeap(void); -void ResumeHeap(void **heap, size_t *len); - -#define BSP_STACK_BASE_ADDR 0x30000 - -#if 1 -/* This covers node 0 only. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) -#else -/* This covers total of 8 nodes. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) -#endif - -#define HIGH_MEMORY_SCRATCH 0x30000 - #endif diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 6950a38..f0ba31c 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,7 +1,11 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H +#include <arch/cpu.h> + +#if IS_ENABLED(CONFIG_CPU_AMD_GEODE_GX2) void main(unsigned long bist); +#endif void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void done_cache_as_ram_main(void); @@ -10,8 +14,13 @@ void post_cache_as_ram(void); void cache_as_ram_switch_stack(void *stacktop); void cache_as_ram_new_stack(void); -#if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI +#if IS_ENABLED(CONFIG_CPU_AMD_PI) void disable_cache_as_ram(void); #endif +void asmlinkage early_all_cores(void); + +void * asmlinkage romstage_main(unsigned long bist); +void asmlinkage romstage_after_car(void); + #endif diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 004fe3e..21e066b 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index b80af9c..32142fe 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES + #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID select GFXUMA diff --git a/src/mainboard/amd/dinar/OemCustomize.c b/src/mainboard/amd/dinar/OemCustomize.c index 84866de..dfd5189 100644 --- a/src/mainboard/amd/dinar/OemCustomize.c +++ b/src/mainboard/amd/dinar/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -27,7 +31,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { // Dinar has the following routing: // CS0 M[B,A]_CLK_H/L[0] // CS1 M[B,A]_CLK_H/L[2] @@ -38,15 +42,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; - -static AGESA_STATUS OemInitPost(AMD_POST_PARAMS *InitPost) +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; InitPost->MemConfig.UmaMode = UMA_AUTO; InitPost->MemConfig.BottomIo = 0xE0; InitPost->MemConfig.UmaSize = 0xE0-0xC0; - return AGESA_SUCCESS; } -const struct OEM_HOOK OemCustomize = { - .InitPost = OemInitPost, -}; +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index c205d08..5e2b22f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam15.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 0edc346..1303493 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -24,35 +24,24 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> +#include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include <cpu/x86/lapic.h> +#include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + sch4037_early_init(0x2e); + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { - - post_code(0x30); - - sch4037_early_init(0x2e); - - sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - post_code(0x31); - console_init(); - /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. @@ -60,47 +49,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr56x0_rd890_disable_pcie_bridge(); } - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - if(boot_cpu()) { - post_code(0x34); - sb_Poweron_Init(); - } - - post_code(0x35); - agesawrapper_amdinitreset(); - - post_code(0x36); - agesawrapper_amdinitearly(); - - post_code(0x37); - nb_Poweron_Init(); - post_code(0x38); - nb_Ht_Init(); - - - post_code(0x39); - agesawrapper_amdinitpost(); - - post_code(0x40); - agesawrapper_amdinitenv(); - - - post_code(0x43); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x44); - copy_and_run(); - - post_code(0x45); // Should never see this post code. -} +#endif diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index d1f715c..092acf8 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -38,7 +38,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -126,7 +126,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -140,12 +139,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 60045e1..30f674a 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3d0eecf..cce664f 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -13,71 +13,12 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 37fb43f..2f3b849 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c index 70c5035..b55b4d5 100644 --- a/src/mainboard/amd/olivehill/OemCustomize.c +++ b/src/mainboard/amd/olivehill/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 61272d0..3560c85 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -22,8 +22,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /********************************************** * enable the dedicated function in mainboard. @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index bb1ad30..f52f9d4 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,29 +17,21 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -49,67 +41,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index aecf065..ab92d8c 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index fb6177a..33a49da 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -157,7 +157,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -189,14 +189,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -221,7 +213,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index a902bad..d8003f8 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index c519772..1e471bc 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /************************************************* * enable the dedicated function in parmer board. @@ -31,9 +31,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 1f251ab..1736d48 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -13,83 +13,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - post_code(0x54); /* Should never see this post code. */ + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); } diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364e..abc20ed 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -36,7 +36,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index 4132c7c..0342e8e 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index e0440f2..c2fc613 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index c8a8d74..c5749f7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -13,90 +13,12 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index 74b0aa8..25e129e 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -38,7 +38,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -134,7 +134,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,12 +147,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 95f6dde..c5749f7 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -13,71 +13,12 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 73487b0..2ce919a 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_SMSC_LPC47N217 select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index 66058f2..81318ce 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -163,7 +163,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -215,14 +215,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -236,7 +228,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), @@ -247,7 +239,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index a902bad..d8003f8 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index c89ce5a..2ee8ba5 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /************************************************* * enable the dedicated function in thatcher board. @@ -46,9 +46,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 147f31a..4f7a872 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -22,88 +22,41 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> + #include <superio/smsc/lpc47n217/lpc47n217.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); + byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - *(u8 *)0xfed80101 = 0x98; - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - post_code(0x50); - copy_and_run(); + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - post_code(0x54); /* Should never see this post code. */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; } diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 3c20047..6721a25 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -105,7 +105,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *LlanoPcieComplexListPtr; @@ -159,7 +159,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -173,12 +172,17 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index a0b3933..050b311 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam12.h> extern u32 apicid_sb900; diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index d28608e..cce664f 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -13,81 +13,12 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> -#include "sb_cimx.h" -#include "SbPlatform.h" -#include <arch/cpu.h> -#include "platform_cfg.h" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x35); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - gpioEarlyInit(); - sb_poweron_init(); - - post_code(0x31); - - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - post_code(0x32); - post_code(0x33); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x36); - agesawrapper_amdinitreset(); - - post_code(0x37); - agesawrapper_amdinitearly(); - - post_code(0x38); - agesawrapper_amdinitpost(); - - post_code(0x39); - printk(BIOS_DEBUG, "sb_before_pci_init "); - sb_before_pci_init(); - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x40); - agesawrapper_amdinitenv(); - - post_code(0x43); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run returned!\n"); - - post_code(0x44); // Should never see this post code. + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 6f4dbfc..d97ba65 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -140,7 +140,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -154,12 +153,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7a5d348..40ada8e 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -13,68 +13,6 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index ab563ae..4f4baa9 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -120,7 +120,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -134,12 +133,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 001ed16..ee8e499 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -16,10 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 07f985a..83daa6e 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 82fbecf..292ecf2 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -13,87 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ +void board_BeforeAgesa(struct sysinfo *cb) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index e118bfb..e666549 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c index aec1343..aa0b1ef 100644 --- a/src/mainboard/asrock/imb-a180/OemCustomize.c +++ b/src/mainboard/asrock/imb-a180/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( @@ -183,7 +175,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} + diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 61272d0..3560c85 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -22,8 +22,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /********************************************** * enable the dedicated function in mainboard. @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 29d831d..ff401c6 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -21,45 +21,26 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val, t32; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7); - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + volatile u32* addr32; + u32 t32; /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); @@ -76,64 +57,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); +#endif - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 04eb936..5d1a00c 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 6348d5a..ccd955a 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -139,7 +139,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -190,14 +190,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -205,14 +197,13 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) *---------------------------------------------------------------------------------------- */ -#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -225,9 +216,25 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ PSO_END }; -#endif /* CONFIG_BOARD_ASUS_F2A85_M */ -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, +static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + PSO_END }; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M; + else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} + diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index 2d4ab69..53ad1bc 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 2566037..114db4d 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> @@ -46,9 +45,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 51cadc7..4217f66 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -14,29 +14,19 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smbus.h> -#include <stdint.h> -#include <string.h> + #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) @@ -58,97 +48,50 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - -#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) - hudson_pci_port80(); -#endif -#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) - hudson_lpc_port80(); -#endif - - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(GPIO_DEV); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - - /* set DDR3 voltage */ - byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - - /* default is byte = 0x0, so no need to set it in this case */ - if (byte) - do_smbus_write_byte(0xb20, 0x15, 0x3, byte); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(GPIO_DEV); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } diff --git a/src/mainboard/asus/f2a85-m_le/Kconfig b/src/mainboard/asus/f2a85-m_le/Kconfig index a81f700..d771e6c 100644 --- a/src/mainboard/asus/f2a85-m_le/Kconfig +++ b/src/mainboard/asus/f2a85-m_le/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/asus/f2a85-m_le/OemCustomize.c b/src/mainboard/asus/f2a85-m_le/OemCustomize.c index ea1c871..c8a48d9 100644 --- a/src/mainboard/asus/f2a85-m_le/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m_le/OemCustomize.c @@ -1,28 +1 @@ #include "../f2a85-m/OemCustomize.c" -/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE - *---------------------------------------------------------------------------------------- - */ - -#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE) -/* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. - */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), - -/* - TODO: is this OK for DDR3 socket FM2? - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - */ - PSO_END -}; -#endif /* CONFIG_BOARD_ASUS_F2A85M_LE */ diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 752293a..dabd778 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -105,7 +105,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -127,14 +127,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,7 +140,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -174,7 +166,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/bap/ode_e20XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index baddf0b..7e729f0 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -28,8 +28,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -121,9 +120,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index a43d035..5c3328e 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -15,36 +15,21 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> -#include "cbmem.h" + #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); +#if 0 /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -52,62 +37,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 1b131dd..513975d 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c index c44a994..f54fd69 100644 --- a/src/mainboard/biostar/am1ml/OemCustomize.c +++ b/src/mainboard/biostar/am1ml/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -120,7 +120,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -142,14 +142,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -163,7 +155,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -182,7 +174,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/biostar/am1ml/acpi_tables.c b/src/mainboard/biostar/am1ml/acpi_tables.c index 1818e08..430aeb3 100644 --- a/src/mainboard/biostar/am1ml/acpi_tables.c +++ b/src/mainboard/biostar/am1ml/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index 7dc9f4d..f4ea2f3 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -25,8 +25,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> #include <southbridge/amd/common/amd_pci_util.h> @@ -112,9 +111,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 1672349..eecd7f5 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -14,26 +14,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> + #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" + #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -105,17 +93,18 @@ static void ite_gpio_conf(pnp_devfn_t dev) ite_exit_conf (dev); } - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if 0 u32 val, t32; u8 byte; pci_devfn_t dev; u32 *addr32; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -146,83 +135,36 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - post_code(0x30); - post_code(0x31); - - /* run ite */ - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - printk(BIOS_DEBUG, "Console inited!\n"); - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + +#endif + +#if 0 /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); + /* This functions configure SIO as it been done under vendor bios */ printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); ite_evc_conf(ENVC_DEV); printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); ite_gpio_conf(GPIO_DEV); printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 825364e..71f4b80 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -36,7 +36,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -146,12 +145,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h index 0f3fdc6..0bea897 100644 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - /* * GNB GPP Port4 * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable diff --git a/src/mainboard/elmex/pcm205400/acpi_tables.c b/src/mainboard/elmex/pcm205400/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/elmex/pcm205400/acpi_tables.c +++ b/src/mainboard/elmex/pcm205400/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index e0440f2..c2fc613 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index c8a8d74..1fbdd4b 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -13,90 +13,13 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index 2184fb2..2cd31ed 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -23,7 +23,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*---------------------------------------------------------------------------------------*/ /** @@ -41,7 +41,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -137,7 +137,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -151,7 +150,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), @@ -168,6 +167,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h index 66618ae..acdb655 100644 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h @@ -17,11 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 49f4e1f..5992401 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -21,7 +21,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 00847e0..98cafae 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include <delay.h> diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 6d06621..8dec7fe 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -14,84 +14,8 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/state_machine.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index f5509f6..e07e584 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c index 933b036..9bcff35 100644 --- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -114,7 +114,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -136,14 +136,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -157,7 +149,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -183,7 +175,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/gizmosphere/gizmo2/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo2/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index baddf0b..ad4f9c9 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -28,8 +28,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -120,10 +119,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index bb1ad30..38d696b 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -17,29 +17,21 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <console/loglevel.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -49,67 +41,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c index 730c97e..7b3a7b2 100644 --- a/src/mainboard/hp/abm/OemCustomize.c +++ b/src/mainboard/hp/abm/OemCustomize.c @@ -21,7 +21,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -116,7 +116,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -138,14 +138,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -159,7 +151,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -178,7 +170,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/abm/acpi_tables.c b/src/mainboard/hp/abm/acpi_tables.c index a1abe74..943a461 100644 --- a/src/mainboard/hp/abm/acpi_tables.c +++ b/src/mainboard/hp/abm/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <cpu/amd/amdfam16.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index 45e2f81..4af8678 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -20,8 +20,7 @@ #include <arch/io.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/pci_devs.h> #include <northbridge/amd/agesa/family16kb/pci_devs.h> @@ -114,9 +113,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 02ebbc9..dac7894 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -14,45 +14,33 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> + #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val, t32; - u32 *addr32; - - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ + /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x01, 0xcd7); @@ -71,58 +59,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffff7b; // clear 2, 7 *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); +} - post_code(0x61); - prepare_for_resume(); - } +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index f78cfba..e235e01 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c index 605c7d3..48229d0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index 4100f8f..3beb713 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index d20bc87..146c843 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -44,11 +43,8 @@ static void mainboard_enable(device_t dev) hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - else + if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); - } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 714743b..24ec37a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -13,76 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); +void board_BeforeAgesa(struct sysinfo *cb) +{ hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c index f980a15..10ddfbd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c +++ b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c @@ -17,7 +17,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -35,7 +35,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; void *BrazosPcieComplexListPtr; @@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /** @@ -188,12 +187,17 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings. */ -const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index a91bd0f..782f5c2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -17,9 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include <vendorcode/amd/agesa/f14/AGESA.h> -#include <amdlib.h> - /** * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) * diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 07f985a..83daa6e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d8ad645..801d493 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 85a4343..3620e27 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -14,105 +14,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> - -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> - -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/car.h> -#include <sb_cimx.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index aac3a84..9d771ac 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c index 605c7d3..48229d0 100644 --- a/src/mainboard/lenovo/g505s/OemCustomize.c +++ b/src/mainboard/lenovo/g505s/OemCustomize.c @@ -17,7 +17,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -156,7 +156,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -188,14 +188,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr->DdiLinkList = DdiList; InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -210,7 +202,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * If PlatformSpecificTable is populated, AGESA will base its settings on the * data from the table. Otherwise, it will use its default conservative settings */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -222,7 +214,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index 4100f8f..3beb713 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index bcc3cf2..579fbc0 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -44,9 +43,7 @@ static void mainboard_enable(device_t dev) hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - else + if (!acpi_is_wakeup_s3()) pavilion_cold_boot_init(); } diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 714743b..c05b87a 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -13,76 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 63466b9..93d1463 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h index 9f99f32..0f0b41b 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 10b7504..a846528 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 37dc37f..9e647b5 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -13,67 +13,16 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { +#if 0 post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ @@ -83,23 +32,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index a5f4921..f8fc812 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -22,7 +22,7 @@ #include "Filecode.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -42,7 +42,7 @@ **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -152,13 +151,18 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index 50c8f08..017ea77 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -16,11 +16,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index eebe8e6..3f8a4ae 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index a80c9fd..7647ebe 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -23,7 +23,6 @@ #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index adc2987..05b1330 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -13,68 +13,18 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { +#if 0 post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ @@ -84,23 +34,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 90bc5a9..d082328 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -18,7 +18,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -146,7 +146,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *TrinityPcieComplexListPtr; @@ -197,14 +197,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -218,7 +210,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -232,7 +224,14 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/msi/ms7721/acpi_tables.c b/src/mainboard/msi/ms7721/acpi_tables.c index 2d4ab69..53ad1bc 100644 --- a/src/mainboard/msi/ms7721/acpi_tables.c +++ b/src/mainboard/msi/ms7721/acpi_tables.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index 2566037..114db4d 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> @@ -46,9 +45,6 @@ static void mainboard_enable(device_t dev) msr = rdmsr(0xC0011023); msr.lo &= ~(1 << 23); wrmsr(0xC0011023, msr); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 9ce47f2..b82dfa6 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -15,30 +15,18 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> +#include <device/pnp.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <southbridge/amd/agesa/hudson/smbus.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -#include <stdint.h> -#include <string.h> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff @@ -122,91 +110,40 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - -#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) - hudson_pci_port80(); -#endif -#if IS_ENABLED(CONFIG_POST_DEVICE_LPC) - hudson_lpc_port80(); -#endif - - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Initialize GPIO registers */ - gpio_init(GPIO_DEV); - - /* Enable serial console */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Initialize GPIO registers */ + gpio_init(GPIO_DEV); + + /* Enable serial console */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 20acb27..3c24c2a 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -17,7 +17,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -35,7 +35,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -124,7 +124,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -138,7 +137,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), @@ -155,6 +154,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *p) +{ +} diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h index bb4ba86..64adf5c 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h @@ -17,11 +17,6 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 diff --git a/src/mainboard/pcengines/apu1/acpi_tables.c b/src/mainboard/pcengines/apu1/acpi_tables.c index b36cef0..a902653 100644 --- a/src/mainboard/pcengines/apu1/acpi_tables.c +++ b/src/mainboard/pcengines/apu1/acpi_tables.c @@ -20,7 +20,6 @@ #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 055cd58..a678559 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,6 @@ #include <southbridge/amd/cimx/cimx_util.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include <smbios.h> #include <string.h> diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index a74d247..50b51cc 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,99 +15,16 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/cimx/cimx_util.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" +#include "SB800.h" #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -static void early_lpc_init(void); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - early_lpc_init(); - - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} - static void early_lpc_init(void) { u32 mmio_base; @@ -140,3 +57,9 @@ static void early_lpc_init(void) configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); } + +void board_BeforeAgesa(struct sysinfo *cb) +{ + early_lpc_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 9a91568..d89324c 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/supermicro/h8qgi/OemCustomize.c b/src/mainboard/supermicro/h8qgi/OemCustomize.c index 9f340c6..999709b 100644 --- a/src/mainboard/supermicro/h8qgi/OemCustomize.c +++ b/src/mainboard/supermicro/h8qgi/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -37,7 +41,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, @@ -65,5 +69,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 19ffbdf..58d448a 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -20,11 +20,10 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> @@ -36,34 +35,15 @@ */ #define SIO_PORT 0x164e -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - post_code(0x35); - console_init(); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -76,16 +56,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -95,23 +76,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 2449b6c..4f89128 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/supermicro/h8scm/OemCustomize.c b/src/mainboard/supermicro/h8scm/OemCustomize.c index 634d06b..8554093 100644 --- a/src/mainboard/supermicro/h8scm/OemCustomize.c +++ b/src/mainboard/supermicro/h8scm/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -35,10 +39,10 @@ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. - * I am not sure whether DefaultPlatformMemoryConfiguration is necessary. + * I am not sure whether PlatformMemoryTable is necessary. * If I comment out these code, H8SCM will still pass mem training. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, @@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 918d9ad..39d2962 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -20,49 +20,30 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +/* though UARTs are on the NUVOTON BMC, port 0x164E + * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E + */ +#define SIO_PORT 0x164e -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); + wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -75,37 +56,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); - - post_code(0x3C); - nb_Ht_Init(); - - post_code(0x3D); - /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - distinguish_cpu_resets(0); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index fea32cb..83809a5 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "Ids.h" #include "heapManager.h" diff --git a/src/mainboard/tyan/s8226/OemCustomize.c b/src/mainboard/tyan/s8226/OemCustomize.c index d3a8f4b..354ded4 100644 --- a/src/mainboard/tyan/s8226/OemCustomize.c +++ b/src/mainboard/tyan/s8226/OemCustomize.c @@ -13,9 +13,13 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <PlatformMemoryConfiguration.h> +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ +} + /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- @@ -37,7 +41,7 @@ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, @@ -66,5 +70,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ +} diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index 8166d47..3c9ec95 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index d43c04b..415c71c 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -20,11 +20,10 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include <northbridge/amd/agesa/state_machine.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> @@ -34,39 +33,21 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - /* For serial port. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ w83627dhg_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -79,16 +60,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -99,22 +81,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 62a5df1..1d153ac 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -23,8 +23,11 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += def_callouts.c agesawrapper.c eventlog.c -ramstage-y += def_callouts.c agesawrapper.c eventlog.c +romstage-y += def_callouts.c eventlog.c +ramstage-y += def_callouts.c eventlog.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c romstage-y += oem_s3.c ramstage-y += oem_s3.c diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h new file mode 100644 index 0000000..82963c1 --- /dev/null +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _AGESA_HELPER_H_ +#define _AGESA_HELPER_H_ + +#include <stddef.h> + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +void *agesawrapper_getlateinitptr (int pick); + +void amd_initcpuio(void); +void amd_initmmio(void); +void amd_initenv(void); + +void *GetHeapBase(void); +void EmptyHeap(void); +void ResumeHeap(void **heap, size_t *len); + +#define BSP_STACK_BASE_ADDR 0x30000 + +#if 1 +/* This covers node 0 only. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) +#else +/* This covers total of 8 nodes. */ +#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR) +#endif + +#define HIGH_MEMORY_SCRATCH 0x30000 + + +#endif /* _AGESA_HELPER_H_ */ diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c deleted file mode 100644 index a72e239..0000000 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - -#include "heapManager.h" - -static const struct OEM_HOOK *OemHook = &OemCustomize; - -#if defined(__PRE_RAM__) - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitEarly) - OemHook->InitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitPost) - OemHook->InitPost(PostParams); - - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, &PostParams->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemInitResume(AmdResumeParamsPtr); - - status = AmdInitResume(AmdResumeParamsPtr); - - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; - - status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, &EnvParam->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; -#endif - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemS3LateRestore(AmdS3LateParamsPtr); - - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} - -#else /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitMid) - OemHook->InitMid(MidParam); - - status = AmdInitMid(MidParam); - AGESA_EVENTLOG(status, &MidParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - OemS3Save(AmdS3SaveParamsPtr); - - AmdReleaseStruct(&AmdInterfaceParams); - - return status; -} - -/* We will reference AmdLateParams later to copy ACPI tables. */ -static AMD_LATE_PARAMS *AmdLateParams = NULL; - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; -#endif - - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); - ASSERT(status == AGESA_SUCCESS); - - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ - return status; -} - -void *agesawrapper_getlateinitptr(int pick) -{ - ASSERT(AmdLateParams != NULL); - - switch (pick) { - case PICK_DMI: - return AmdLateParams->DmiTable; - case PICK_PSTATE: - return AmdLateParams->AcpiPState; - case PICK_SRAT: - return AmdLateParams->AcpiSrat; - case PICK_SLIT: - return AmdLateParams->AcpiSlit; - case PICK_WHEA_MCE: - return AmdLateParams->AcpiWheaMce; - case PICK_WHEA_CMC: - return AmdLateParams->AcpiWheaCmc; - case PICK_ALIB: - return AmdLateParams->AcpiAlib; - case PICK_IVRS: -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) - return NULL; -#else - return AmdLateParams->AcpiIvrs; -#endif - default: - return NULL; - } - return NULL; -} - -#endif /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) -{ - AGESA_STATUS status; - AP_EXE_PARAMS ApExeParams; - - memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status, &ApExeParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h deleted file mode 100644 index f5d52d6..0000000 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); -#define AGESA_EVENTLOG(status, stdheader) \ - agesawrapper_trace(status, stdheader, __func__) - -void amd_initcpuio(void); -void amd_initmmio(void); -void amd_initenv(void); - -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -struct OEM_HOOK -{ - /* romstage */ - AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *); - AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *); - - /* ramstage */ - AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *); -}; - -extern const struct OEM_HOOK OemCustomize; - -/* For suspend-to-ram support. */ -AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); -AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 0805c02..3d97c30 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -20,7 +20,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include "BiosCallOuts.h" #include "dimmSpd.h" diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 0a40672..1deca6c 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -15,12 +15,46 @@ #include <stdint.h> #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" #include "AGESA.h" #include "AMD.h" +#include <heapManager.h> + +static const char undefined[] = "undefined"; + +/* Match order of enum AGESA_STRUCT_NAME. */ +static const char *AgesaFunctionNameStr[] = { + "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", + "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", + "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", +}; + +/* heapManager.h */ +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +const char *agesa_struct_name(int state) +{ + if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) + return undefined; + + int index = state - AMD_INIT_RECOVERY; + return AgesaFunctionNameStr[index]; +} + +const char *heap_status_name(int status) +{ + if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) + return undefined; + + int index = status - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} /* * Possible AGESA_STATUS values: diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc index 6b2ca78..ad39325 100644 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ b/src/northbridge/amd/agesa/family12/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c8198c9..7dba9a5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -32,7 +32,9 @@ #include <cpu/amd/mtrr.h> #include "sb_cimx.h" -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define FX_DEVS 1 @@ -632,24 +634,6 @@ static void domain_set_resources(device_t dev) } -static void domain_enable_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Must be called after PCI enumeration and resource allocation */ -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Mid_Post_Init(); -#endif - - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - /* Bus related code */ static void cpu_bus_init(device_t dev) @@ -790,7 +774,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c new file mode 100644 index 0000000..4eda2c3 --- /dev/null +++ b/src/northbridge/amd/agesa/family12/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <cpu/amd/agesa/s3_resume.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + Post->MemConfig.SaveMemContextCtl = 0; + Post->MemConfig.MemRestoreCtl = 0; +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); + + sb_before_pci_init(); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + sb_After_Pci_Init(); +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(AmdS3Late); + + sb_After_Pci_Restore_Init(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + sb_Mid_Post_Init(); + + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 6b2ca78..ad39325 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b8d9c6f..2f04a01 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -31,10 +31,10 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#if CONFIG_AMD_SB_CIMX +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + #include <sb_cimx.h> -#endif #define FX_DEVS 1 @@ -614,30 +614,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) -{ -#if CONFIG_AMD_SB_CIMX - if (!acpi_is_wakeup_s3()) { - sb_After_Pci_Init(); - sb_Mid_Post_Init(); - } else { - sb_After_Pci_Restore_Init(); - } -#endif - - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - static const char *domain_acpi_name(struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -818,7 +794,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c new file mode 100644 index 0000000..b9af710 --- /dev/null +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + amd_initenv(); +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); + + sb_After_Pci_Restore_Init(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 9cfaed9..f1e6a99 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -632,21 +634,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); - -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); -#endif - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -849,7 +836,6 @@ static void f15_pci_domain_scan_bus(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = f15_pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c new file mode 100644 index 0000000..d88400b --- /dev/null +++ b/src/northbridge/amd/agesa/family15/state_machine.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + Post->MemConfig.SaveMemContextCtl = 0; + Post->MemConfig.MemRestoreCtl = 0; +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + cached_late_params = LateParams; +} diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc index a188a91..9e9283c 100644 --- a/src/northbridge/amd/agesa/family15rl/Makefile.inc +++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d003be5..f0b9c38 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -38,7 +38,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -629,21 +631,6 @@ static void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(struct device *dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -842,7 +829,6 @@ static void domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15rl/state_machine.c b/src/northbridge/amd/agesa/family15rl/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family15rl/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index a188a91..9e9283c 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -17,3 +17,6 @@ romstage-y += dimmSpd.c ramstage-y += iommu.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2f05334..e5a540c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -628,21 +630,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -839,7 +826,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 3cf4ed1..3021ef4 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28a4f91..8517e9a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -37,7 +37,9 @@ #include <Topology.h> #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> -#include <northbridge/amd/agesa/agesawrapper.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -643,21 +645,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -858,7 +845,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..ce6baee --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); + + OemS3LateRestore(S3Late); + + fchs3earlyrestore(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + /* FIXME: not reached S3 path */ + if (cb->s3resume) + fchs3laterestore(); +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index c7d23ff..5f1cc9e 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -19,8 +19,9 @@ #include <cbmem.h> #include <program_loading.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <AGESA.h> +#include <northbridge/amd/agesa/agesa_helper.h> typedef enum { S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/northbridge/amd/agesa/state_machine.c new file mode 100644 index 0000000..3a6daaa --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.c @@ -0,0 +1,372 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include <arch/acpi.h> +#include <bootstate.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +#include "AMD.h" +#include "heapManager.h" +#include "Dispatcher.h" + + +#if ENV_ROMSTAGE +#include <PlatformMemoryConfiguration.h> +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; +#endif + +#if ENV_RAMSTAGE +static void completion_InitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); +#endif + +struct agesa_state +{ + u8 apic_id; + AGESA_STATUS status; + + u32 func; + const char *function_name; + + struct sysinfo *sysinfo; + AMD_INTERFACE_PARAMS *aip; +}; + +static AGESA_STATUS amd_alloc(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + aip->StdHeader.Func = AMD_CREATE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = 0; + aip->NewStructPtr = NULL; + aip->NewStructSize = 0; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_release(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + /* Cannot release AMD_LATE_PARAMS until ACPI tables are done. */ + if (func == AMD_INIT_LATE) + return AGESA_SUCCESS; + + aip->StdHeader.Func = AMD_RELEASE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = 0; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_alloc_stack(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func, void *buf, size_t len) +{ + /* By design, each valid AGESA_STRUCT_NAME + * can be casted to AMD_CONFIG_PARAMS. + */ + AMD_CONFIG_PARAMS *call = buf; + memset(call, 0, len); + + aip->StdHeader.Func = AMD_CREATE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = ByHost; + aip->NewStructPtr = call; + aip->NewStructSize = len; + + /* AMD_CREATE_STRUCT with ByHost skips this. */ + *call = aip->StdHeader; + + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_release_stack(AMD_INTERFACE_PARAMS *aip, AGESA_STRUCT_NAME func) +{ + aip->StdHeader.Func = AMD_RELEASE_STRUCT; + aip->AgesaFunctionName = func; + aip->AllocationMethod = ByHost; + return AmdAgesaDispatcher(aip); +} + +static AGESA_STATUS amd_dispatch(struct agesa_state *task, AMD_CONFIG_PARAMS *call) +{ + struct sysinfo *cb = task->sysinfo; + + /* By design, for each valid AGESA_STRUCT_NAME, AMD_CONFIG_PARAMS + * can be evaluated to apply correct typecast based on Func field. + */ + + switch (call->Func) + { +#if ENV_ROMSTAGE + case AMD_INIT_RESET: + { + AMD_RESET_PARAMS *param = (void *)call; + platform_BeforeInitReset(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_EARLY: + { + AMD_EARLY_PARAMS *param = (void *)call; + platform_BeforeInitEarly(cb, param); + board_BeforeInitEarly(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_POST: + { + AMD_POST_PARAMS *param = (void *)call; + platform_BeforeInitPost(cb, param); + board_BeforeInitPost(cb, param); + task->status = AmdAgesaDispatcher(call); + platform_AfterInitPost(cb, param); + break; + } + + case AMD_INIT_RESUME: + { + AMD_RESUME_PARAMS *param = (void *)call; + platform_BeforeInitResume(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_ENV: + { + AMD_ENV_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterInitEnv(cb, param); + break; + } + + case AMD_S3LATE_RESTORE: + { + AMD_S3LATE_PARAMS *param = (void *)call; + platform_BeforeS3LateRestore(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } +#endif +#if ENV_RAMSTAGE + case AMD_INIT_MID: + { + AMD_MID_PARAMS *param = (void *)call; + platform_BeforeInitMid(cb, param); + board_BeforeInitMid(cb, param); + task->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_S3_SAVE: + { + AMD_S3SAVE_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterS3Save(cb, param); + break; + } + case AMD_INIT_LATE: + { + AMD_LATE_PARAMS *param = (void *)call; + task->status = AmdAgesaDispatcher(call); + platform_AfterInitLate(cb, param); + completion_InitLate(cb, param); + break; + } +#endif + default: + { + task->status = AGESA_UNSUPPORTED; + break; + } + + } + return task->status; +} + +static void state_on_entry(struct sysinfo *cb, + struct agesa_state *params, AGESA_STRUCT_NAME func) +{ + memset(params, 0, sizeof(params)); + + params->aip = (AMD_INTERFACE_PARAMS *) cb->agesa_stash; + params->sysinfo = cb; + + params->apic_id = (u8) (cpuid_ebx(1) >> 24); + params->func = func; + params->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +static void state_on_exit(struct agesa_state *params) +{ + AMD_CONFIG_PARAMS *call = &params->aip->StdHeader; + + agesawrapper_trace(params->status, call, params->function_name); + + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + params->apic_id, heap_status_name(call->HeapStatus), call->HeapStatus, + (u32)call->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +static AGESA_STATUS agesa_task(struct sysinfo *cb, AGESA_STRUCT_NAME func) +{ + struct agesa_state params; + AMD_RESET_PARAMS reset; + AGESA_STATUS status; + + state_on_entry(cb, &params, func); + + AMD_INTERFACE_PARAMS *aip = params.aip; + + if (func == AMD_INIT_RESET) + status = amd_alloc_stack(aip, func, &reset, sizeof(reset)); + else + status = amd_alloc(aip, func); + ASSERT(status == AGESA_SUCCESS); + + AMD_CONFIG_PARAMS *call = aip->NewStructPtr; + /* Must call the function buffer was allocated for.*/ + ASSERT(call->Func == func); + + status = amd_dispatch(&params, call); + ASSERT(status < AGESA_FATAL); + + if (func == AMD_INIT_RESET) + status = amd_release_stack(aip, func); + else + status = amd_release(aip, func); + ASSERT(status == AGESA_SUCCESS); + + state_on_exit(&params); + return params.status; +} + +void agesa_set_interface(struct sysinfo *cb) +{ + AMD_INTERFACE_PARAMS *aip = (void *)cb->agesa_stash; + + ASSERT (sizeof(AMD_INTERFACE_PARAMS) < AGESA_STASH_SIZE); + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = GetBiosCallout; +} + +int agesa_execute_state(struct sysinfo *cb, int func) +{ + AGESA_STATUS ret = agesa_task(cb, (AGESA_STRUCT_NAME) func); + return (ret == AGESA_SUCCESS) ? 0 : -1; +} + +#if ENV_RAMSTAGE + +static struct sysinfo state_machine; + +static void agesa_mid(void *unused) +{ + agesa_set_interface(&state_machine); + + if (!acpi_is_wakeup_s3()) + agesa_execute_state(&state_machine, AMD_INIT_MID); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, agesa_mid, NULL); + +static void agesa_late(void *unused) +{ + if (acpi_is_wakeup_s3()) + return; + + agesa_execute_state(&state_machine, AMD_INIT_LATE); + + if (!acpi_s3_resume_allowed()) + return; + + agesa_execute_state(&state_machine, AMD_S3_SAVE); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesa_late, NULL); + + +/* We will reference AmdLateParams later to copy ACPI tables. */ +static AMD_LATE_PARAMS *AmdLateParams; + +static void completion_InitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ + AmdLateParams = Late; +} + +void *agesawrapper_getlateinitptr(int pick) +{ + ASSERT(AmdLateParams != NULL); + + switch (pick) { + case PICK_DMI: + return AmdLateParams->DmiTable; + case PICK_PSTATE: + return AmdLateParams->AcpiPState; + case PICK_SRAT: + return AmdLateParams->AcpiSrat; + case PICK_SLIT: + return AmdLateParams->AcpiSlit; + case PICK_WHEA_MCE: + return AmdLateParams->AcpiWheaMce; + case PICK_WHEA_CMC: + return AmdLateParams->AcpiWheaCmc; + case PICK_ALIB: + return AmdLateParams->AcpiAlib; + case PICK_IVRS: +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) + return NULL; +#else + return AmdLateParams->AcpiIvrs; +#endif + default: + return NULL; + } + return NULL; +} + +#endif /* ENV_RAMSTAGE */ + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ +#if 0 + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); + ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; + + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); + ASSERT(status == AGESA_SUCCESS); + + return status; +#else + return AGESA_SUCCESS; +#endif +} diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h new file mode 100644 index 0000000..7c52a19 --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _STATE_MACHINE_H_ +#define _STATE_MACHINE_H_ + +#include <stdint.h> +#include <AGESA.h> + +/* eventlog */ +const char *agesa_struct_name(int state); +const char *heap_status_name(int status); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); + + +AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* For suspend-to-ram support. */ +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *Resume); +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3Late); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3Save); + +/* For FCH */ +static inline void fchs3earlyrestore(void) { } +static inline void fchs3laterestore(void) { } + +#define AGESA_STASH_SIZE 64 +struct sysinfo +{ + u8 agesa_stash[AGESA_STASH_SIZE]; + int s3resume; +}; + +void board_BeforeAgesa(struct sysinfo *cb); + +void platform_once(struct sysinfo *cb); +void agesa_main(struct sysinfo *cb); + +void agesa_set_interface(struct sysinfo *cb); +int agesa_execute_state(struct sysinfo *cb, int func); + +/* AGESA dispatchers */ + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset); + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early); +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early); + +/* Normal boot */ +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post); + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env); +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env); + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid); + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late); + +/* S3 Resume */ +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); + +#endif /* _STATE_MACHINE_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 7595889..527c9be 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -10,8 +10,6 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c -ramstage-y += agesawrapper.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c deleted file mode 100644 index 00c6518..0000000 --- a/src/southbridge/amd/agesa/hudson/agesawrapper.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#error Use of GetHeapBase() is incorrect or at least suspicious -#endif - -AGESA_STATUS agesawrapper_fchs3earlyrestore (void) -{ - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3EarlyRestore(&FchParams); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_fchs3laterestore (void) -{ - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return AGESA_SUCCESS; -} diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 1701a21..7c16f7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1245,7 +1245,7 @@ fam15_disable_stack_remote_read_exit: _RDMSR btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - wbinvd # Clear the cache tag RAMs + invd # Clear the cache tag RAMs #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? cmp $01, %bh jz 4f diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 87e6090..6d3f4d1 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -597,8 +597,7 @@ fam16_disable_stack_remote_read_exit: _RDMSR btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - wbinvd # Clear the cache tag RAMs - #invd + invd # Clear the cache tag RAMs #Do Standard Family 16 work mov $HWCR, %ecx # MSR:C001_0015h

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New patch to review for coreboot: MAINTAINERS: Update list
by Martin Roth 05 Mar '17

05 Mar '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18578 -gerrit commit c13520dfd16e6ffbdae6596de795db0ce6af8db2 Author: Martin Roth <martinroth(a)google.com> Date: Sun Mar 5 11:20:18 2017 -0700 MAINTAINERS: Update list - Fix whitespace: Change some spaces to tabs - Add myself as an abuild maintainer - Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section - Add new sections for utilities: docker, toolchain, and git - Remove GENERIC DRAM section - Remove the mailing list. We don't want it to be added as a reviewer. Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index e672fd7..70439e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -144,7 +144,7 @@ F: src/ec/lenovo/ LENOVO MAINBOARDS M: Alexander Couzens <lynxis(a)fe80.eu> -M: Patrick Rudolph <siro(a)das-labor.org> +M: Patrick Rudolph <siro(a)das-labor.org> S: Maintained F: src/mainboard/lenovo/ @@ -306,6 +306,7 @@ F: src/drivers/ati/mach64/ ABUILD M: Patrick Georgi <patrick(a)georgi-clan.de> +M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/abuild/ @@ -348,8 +349,8 @@ F: src/include/pc80/ F: src/include/cpu/x86/ INTEL SUPPORT -M: Patrick Rudolph <siro(a)das-labor.org> -S: Maintained +M: Patrick Rudolph <siro(a)das-labor.org> +S: Maintained F: src/vendorcode/intel/ F: src/cpu/intel/ F: src/northbridge/intel/ @@ -404,6 +405,8 @@ F: *.inc F: src/include/kconfig.h F: util/kconfig/ F: util/sconfig/ +F: util/xcompile/ +F: util/genbuild_h/ BOARD STATUS M: Martin Roth <gaumless(a)gmail.com> @@ -472,6 +475,22 @@ F: src/security/tpm12/ F: src/security/tpm20/ F: util/tss-generator/ +DOCKER +M: Martin Roth <gaumless(a)gmail.com> +S: Supported +F: util/docker/ + +TOOLCHAIN +M: Martin Roth <gaumless(a)gmail.com> +S: Supported +F: util/crossgcc/ + +GIT +M: Martin Roth <gaumless(a)gmail.com> +S: Supported +F: .git* +F: /util/gitconfig + MISSING: TIMERS / DELAYS MISSING: TIMESTAMPS @@ -490,13 +509,10 @@ MISSING: DMP / QEMU-X86 MISSING: ELOG -MISSING: GENERIC DRAM (should drop) - MISSING: SPI THE REST M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> -L: coreboot(a)coreboot.org T: git http://review.coreboot.org/coreboot S: Buried alive in mainboards F: *

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coreboot-gerrit March 2017