coreboot-gerrit December 2017

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Change in coreboot[master]: /soc/intel/skylake: make tcc_offset take effect
by Marx Wang (Code Review) 11 Dec '17

11 Dec '17

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/22818 Change subject: /soc/intel/skylake: make tcc_offset take effect ...................................................................... /soc/intel/skylake: make tcc_offset take effect Currently, the "tcc_offset" defined in devicetree is overwritted by Intel FSP-S UPD "TccActivationOffset". This patch will make "TccActivationOffset" refer to "tcc_offset". TEST=check if MSR(0x1a[29:24]) value is updated with "tcc_offset" by iotools in ChromeOS. Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Signed-off-by: marxwang <marx.wang(a)intel.com> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/22818/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8e5cc2a..f04647d 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -290,6 +290,9 @@ /* Enable/Disable EIST */ tconfig->Eist = config->eist_enable; + /* Set TccActivationOffset */ + tconfig->TccActivationOffset = config->tcc_offset; + soc_irq_settings(params); } -- To view, visit https://review.coreboot.org/22818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Gerrit-Change-Number: 22818 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com>

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Change in coreboot[master]: mb/google/fizz: Enable 2nd NIC leds
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22817 ) Change subject: mb/google/fizz: Enable 2nd NIC leds ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19181/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64367/ : SUCCESS -- To view, visit https://review.coreboot.org/22817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Gerrit-Change-Number: 22817 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:53:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable 2nd NIC leds
by David Wu (Code Review) 11 Dec '17

11 Dec '17

David Wu has posted comments on this change. ( https://review.coreboot.org/22817 ) Change subject: mb/google/fizz: Enable 2nd NIC leds ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/22817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Gerrit-Change-Number: 22817 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:47:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/rcven.c: Fix programming coarse offset
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22816 ) Change subject: nb/intel/x4x/rcven.c: Fix programming coarse offset ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19180/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64366/ : SUCCESS -- To view, visit https://review.coreboot.org/22816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Gerrit-Change-Number: 22816 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:44:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable 2nd NIC leds
by David Wu (Code Review) 11 Dec '17

11 Dec '17

David Wu has uploaded this change for review. ( https://review.coreboot.org/22817 Change subject: mb/google/fizz: Enable 2nd NIC leds ...................................................................... mb/google/fizz: Enable 2nd NIC leds This patch enables customized NIC leds as follows: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:69950854 TEST=Make sure the registers are programmed as expected and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Signed-off-by: David Wu <david_wu(a)quantatw.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/22817/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 55d59fe..194a2e5 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -308,7 +308,12 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 for BtoB + device pci 1d.0 on # PCI Express Port 9 for 2nd LAN + chip drivers/net + register "customized_leds" = "0x0fa7" + device pci 00.0 on end + end + end # PCI Express Port 9 for BtoB device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 -- To view, visit https://review.coreboot.org/22817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Gerrit-Change-Number: 22817 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com>

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Change in coreboot[master]: nb/intel/x4x/rcven.c: Fix programming coarse offset
by Arthur Heymans (Code Review) 11 Dec '17

11 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22816 Change subject: nb/intel/x4x/rcven.c: Fix programming coarse offset ...................................................................... nb/intel/x4x/rcven.c: Fix programming coarse offset This fixes some bitwise logic errors that caused the coarse offset not to be programmed. Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/rcven.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/22816/1 diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 23f8d52..cc45aa9 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -365,8 +365,9 @@ "medium: %d; tap: %d\n", channel, lane, reg8, timing[lane].medium, timing[lane].tap); - MCHBAR16(0x400 * channel + 0x5fa) &= - ~(3 << (lane * 2)) | (reg8 << (lane * 2)); + MCHBAR16(0x400 * channel + 0x5fa) = + (MCHBAR16(0x400 * channel + 0x5fa) & + ~(3 << (lane * 2))) | (reg8 << (lane * 2)); } /* simply use timing[0] to program mincoarse */ timing[0].coarse = mincoarse; -- To view, visit https://review.coreboot.org/22816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Gerrit-Change-Number: 22816 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/google/fizz: Enable SATA on port 0
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22815 ) Change subject: mb/google/fizz: Enable SATA on port 0 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19179/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64365/ : SUCCESS -- To view, visit https://review.coreboot.org/22815 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Gerrit-Change-Number: 22815 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:35:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable SATA on port 0
by David Wu (Code Review) 11 Dec '17

11 Dec '17

David Wu has posted comments on this change. ( https://review.coreboot.org/22815 ) Change subject: mb/google/fizz: Enable SATA on port 0 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/22815 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Gerrit-Change-Number: 22815 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:31:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add option to have subsystem_id in common pci...
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22768 ) Change subject: soc/intel/common/block: Add option to have subsystem_id in common pci driver ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19176/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64362/ : SUCCESS -- To view, visit https://review.coreboot.org/22768 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46307b0db78c8864c85865bd0f3328d5141971be Gerrit-Change-Number: 22768 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 11 Dec 2017 06:29:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable SATA on port 0
by David Wu (Code Review) 11 Dec '17

11 Dec '17

David Wu has uploaded this change for review. ( https://review.coreboot.org/22815 Change subject: mb/google/fizz: Enable SATA on port 0 ...................................................................... mb/google/fizz: Enable SATA on port 0 Enable SATA port 0 to support SATA HDD. BUG=b:69950854 BRANCH=None TEST=emerge-fizz coreboot and boot on fizz dut Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Signed-off-by: David Wu <david_wu(a)quantatw.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/22815/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 55d59fe..d0449d9 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -56,6 +56,7 @@ register "EnableSata" = "1" register "SataSalpSupport" = "1" register "SataMode" = "1" + register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "EnableAzalia" = "1" -- To view, visit https://review.coreboot.org/22815 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9 Gerrit-Change-Number: 22815 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quantatw.com>

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coreboot-gerrit December 2017