coreboot-gerrit December 2017

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Change in coreboot[master]: mb/lenovo/t430/acpi_tables: Don't set flvl
by Arthur Heymans (Code Review) 11 Dec '17

11 Dec '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/22796 ) Change subject: mb/lenovo/t430/acpi_tables: Don't set flvl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/22796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6 Gerrit-Change-Number: 22796 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 12:13:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AMD fam10: Link southbridge/amd/rs780/early_setup.c
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20297 ) Change subject: AMD fam10: Link southbridge/amd/rs780/early_setup.c ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19184/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64374/ : SUCCESS -- To view, visit https://review.coreboot.org/20297 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f Gerrit-Change-Number: 20297 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 12:02:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/fizz: Enable 2nd NIC leds
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22817 ) Change subject: mb/google/fizz: Enable 2nd NIC leds ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64373/ : SUCCESS -- To view, visit https://review.coreboot.org/22817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Gerrit-Change-Number: 22817 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 11:53:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/rcven.c: Fix programming coarse offset
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22816 ) Change subject: nb/intel/x4x/rcven.c: Fix programming coarse offset ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64372/ : SUCCESS -- To view, visit https://review.coreboot.org/22816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Gerrit-Change-Number: 22816 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 10:55:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: make tcc_offset take effect
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22818 ) Change subject: soc/intel/skylake: make tcc_offset take effect ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64371/ : SUCCESS -- To view, visit https://review.coreboot.org/22818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Gerrit-Change-Number: 22818 Gerrit-PatchSet: 2 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 08:14:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable LPC IO Decoding on PCR
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22819 ) Change subject: soc/intel/skylake: Enable LPC IO Decoding on PCR ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19183/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64370/ : SUCCESS -- To view, visit https://review.coreboot.org/22819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Gerrit-Change-Number: 22819 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 07:27:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable LPC IO Decoding on PCR
by PraveenX Hodagatta Pranesh (Code Review) 11 Dec '17

11 Dec '17

PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/22819 ) Change subject: soc/intel/skylake: Enable LPC IO Decoding on PCR ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/22819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Gerrit-Change-Number: 22819 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Comment-Date: Mon, 11 Dec 2017 07:26:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable LPC IO Decoding on PCR
by PraveenX Hodagatta Pranesh (Code Review) 11 Dec '17

11 Dec '17

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/22819 Change subject: soc/intel/skylake: Enable LPC IO Decoding on PCR ...................................................................... soc/intel/skylake: Enable LPC IO Decoding on PCR According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4), section 2.5.1.6, it is a requirement to program the same value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h" to fully enable the Lpc IO enable decoding which is missing in current source. Without above changes, Skylake Saddlebrook platform with using SIO does not able to boot. Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Signed-off-by: praveen <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/skylake/lpc.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/22819/1 diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index bd6fbc4..b5105e4 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -31,6 +31,7 @@ #include <reg_script.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> +#include <soc/intel/common/block/lpc/lpc_def.h> /** PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF @@ -81,11 +82,17 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) { + uint16_t lpc_en; + /* Mirror these same settings in DMI PCR */ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); + + /* LPC IO Decode Enable */ + lpc_en = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, lpc_en); } static const struct reg_script pch_misc_init_script[] = { -- To view, visit https://review.coreboot.org/22819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173 Gerrit-Change-Number: 22819 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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Change in coreboot[master]: /soc/intel/skylake: make tcc_offset take effect
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22818 ) Change subject: /soc/intel/skylake: make tcc_offset take effect ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19182/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64369/ : SUCCESS -- To view, visit https://review.coreboot.org/22818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Gerrit-Change-Number: 22818 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 07:18:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/rcven.c: Fix programming coarse offset
by build bot (Jenkins) (Code Review) 11 Dec '17

11 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22816 ) Change subject: nb/intel/x4x/rcven.c: Fix programming coarse offset ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64368/ : SUCCESS -- To view, visit https://review.coreboot.org/22816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41869815f782a2ea1178bdea006e3a7587441323 Gerrit-Change-Number: 22816 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 11 Dec 2017 07:10:41 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017