coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/google/kahlee: Update PCIe port map
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22750 ) Change subject: mainboard/google/kahlee: Update PCIe port map ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19123/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64307/ : SUCCESS -- To view, visit https://review.coreboot.org/22750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Gerrit-Change-Number: 22750 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 20:17:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/soraka: Tune I2C5 params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22788 ) Change subject: mb/google/poppy/variants/soraka: Tune I2C5 params ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19122/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64306/ : SUCCESS -- To view, visit https://review.coreboot.org/22788 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Gerrit-Change-Number: 22788 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 20:16:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/kahlee: Update GPIOs
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22751 ) Change subject: mainboard/google/kahlee: Update GPIOs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19124/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64308/ : SUCCESS -- To view, visit https://review.coreboot.org/22751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Gerrit-Change-Number: 22751 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 20:12:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/common/psp: Add BootDone command
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22787 ) Change subject: amd/common/psp: Add BootDone command ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19121/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64305/ : SUCCESS -- To view, visit https://review.coreboot.org/22787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Gerrit-Change-Number: 22787 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 20:01:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/soraka: Tune I2C5 params
by Furquan Shaikh (Code Review) 08 Dec '17

08 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22788 Change subject: mb/google/poppy/variants/soraka: Tune I2C5 params ...................................................................... mb/google/poppy/variants/soraka: Tune I2C5 params This change updates scl_lcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:65062416 TEST=Verified that I2C5 frequency is between 389-396kHz. Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22788/1 diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index f71a1eb..22349d6 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -226,7 +226,7 @@ .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 195, + .scl_lcnt = 190, .scl_hcnt = 90, .sda_hold = 36, }, -- To view, visit https://review.coreboot.org/22788 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43 Gerrit-Change-Number: 22788 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: amd/common/psp: Add BootDone command
by Marshall Dawson (Code Review) 08 Dec '17

08 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22787 Change subject: amd/common/psp: Add BootDone command ...................................................................... amd/common/psp: Add BootDone command After the PSP receives the MboxBiosCmdBootDone, it will no longer honor any command where the command-response buffer exists outside of SMM memory. Add the command and automatically execute it before booting the payload. BUG=b:69971683 TEST=Boot Kahlee and observe console log Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22787/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 5aedfc1..f4aca79 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -18,6 +18,7 @@ #include <region_file.h> #include <timer.h> #include <device/pci_def.h> +#include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> @@ -203,6 +204,33 @@ } /* + * Notify the PSP that the system is completing the boot process. Upon + * receiving this command, the PSP will only honor commands where the buffer + * is in SMM space. + */ +static void psp_notify_boot_done(void *unused) +{ + struct mbox_default_buffer buffer; + int cmd_status; + + printk(BIOS_DEBUG, "PSP: Notify that POST is finishing... "); + + buffer.header.size = sizeof(struct mbox_default_buffer); + buffer.header.status = 0; /* PSP does not report status for this cmd */ + + cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + if (rd_resp_sts(&buffer)) + printk(BIOS_DEBUG, "buffer status=0x%x ", + rd_resp_sts(&buffer)); + if (cmd_status) + printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + else + printk(BIOS_DEBUG, "OK\n"); +} + +/* * Tell the PSP to load a firmware blob from a location in the BIOS image. */ static int psp_load_blob(int type, void *addr) @@ -256,3 +284,6 @@ } return r; } + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, + psp_notify_boot_done, NULL); -- To view, visit https://review.coreboot.org/22787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Gerrit-Change-Number: 22787 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: buildgcc: Add patch to work around Musl libc issue
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22786 ) Change subject: buildgcc: Add patch to work around Musl libc issue ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-toolchain/394/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19120/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64304/ : SUCCESS -- To view, visit https://review.coreboot.org/22786 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c Gerrit-Change-Number: 22786 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 19:33:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: buildgcc: Add patch to work around Musl libc issue
by Nico Huber (Code Review) 08 Dec '17

08 Dec '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22786 Change subject: buildgcc: Add patch to work around Musl libc issue ...................................................................... buildgcc: Add patch to work around Musl libc issue GCC includes `sched.h` after poisoning calloc(). This results in a build failure with Musl libc. We work around the issue by including `sched.h` earlier and throw around some void pointers so we only have to do it in one place. Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A util/crossgcc/patches/gcc-6.3.0_ada-musl_workaround.patch 1 file changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/22786/1 diff --git a/util/crossgcc/patches/gcc-6.3.0_ada-musl_workaround.patch b/util/crossgcc/patches/gcc-6.3.0_ada-musl_workaround.patch new file mode 100644 index 0000000..a500343 --- /dev/null +++ b/util/crossgcc/patches/gcc-6.3.0_ada-musl_workaround.patch @@ -0,0 +1,107 @@ +Only in gcc-6.3.0: .unpack_success +--- gcc-6.3.0.bak/gcc/ada/adaint.c ++++ gcc-6.3.0/gcc/ada/adaint.c +@@ -103,6 +103,15 @@ + #define xmalloc(S) malloc (S) + #define xrealloc(V,S) realloc (V,S) + #else ++#if !defined(__ANDROID__) && defined(__linux__) ++#ifdef __cplusplus ++extern "C" { ++#endif ++#include <sched.h> ++#ifdef __cplusplus ++} ++#endif ++#endif + #include "config.h" + #include "system.h" + #include "version.h" +@@ -3096,7 +3105,7 @@ + + /* Dynamic cpu sets */ + +-cpu_set_t * ++void * + __gnat_cpu_alloc (size_t count) + { + return CPU_ALLOC (count); +@@ -3109,19 +3118,19 @@ + } + + void +-__gnat_cpu_free (cpu_set_t *set) ++__gnat_cpu_free (void *set) + { + CPU_FREE (set); + } + + void +-__gnat_cpu_zero (size_t count, cpu_set_t *set) ++__gnat_cpu_zero (size_t count, void *set) + { + CPU_ZERO_S (count, set); + } + + void +-__gnat_cpu_set (int cpu, size_t count, cpu_set_t *set) ++__gnat_cpu_set (int cpu, size_t count, void *set) + { + /* Ada handles CPU numbers starting from 1, while C identifies the first + CPU by a 0, so we need to adjust. */ +@@ -3132,10 +3141,10 @@ + + /* Static cpu sets */ + +-cpu_set_t * ++void * + __gnat_cpu_alloc (size_t count ATTRIBUTE_UNUSED) + { +- return (cpu_set_t *) xmalloc (sizeof (cpu_set_t)); ++ return xmalloc (sizeof (cpu_set_t)); + } + + size_t +@@ -3145,19 +3154,19 @@ + } + + void +-__gnat_cpu_free (cpu_set_t *set) ++__gnat_cpu_free (void *set) + { + free (set); + } + + void +-__gnat_cpu_zero (size_t count ATTRIBUTE_UNUSED, cpu_set_t *set) ++__gnat_cpu_zero (size_t count ATTRIBUTE_UNUSED, void *set) + { + CPU_ZERO (set); + } + + void +-__gnat_cpu_set (int cpu, size_t count ATTRIBUTE_UNUSED, cpu_set_t *set) ++__gnat_cpu_set (int cpu, size_t count ATTRIBUTE_UNUSED, void *set) + { + /* Ada handles CPU numbers starting from 1, while C identifies the first + CPU by a 0, so we need to adjust. */ +--- gcc-6.3.0.bak/gcc/ada/adaint.h ++++ gcc-6.3.0/gcc/ada/adaint.h +@@ -287,13 +287,11 @@ + + /* Routines for interface to required CPU set primitives */ + +-#include <sched.h> +- +-extern cpu_set_t *__gnat_cpu_alloc (size_t); ++extern void *__gnat_cpu_alloc (size_t); + extern size_t __gnat_cpu_alloc_size (size_t); +-extern void __gnat_cpu_free (cpu_set_t *); +-extern void __gnat_cpu_zero (size_t, cpu_set_t *); +-extern void __gnat_cpu_set (int, size_t, cpu_set_t *); ++extern void __gnat_cpu_free (void *); ++extern void __gnat_cpu_zero (size_t, void *); ++extern void __gnat_cpu_set (int, size_t, void *); + #endif + + #if defined (_WIN32) -- To view, visit https://review.coreboot.org/22786 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c Gerrit-Change-Number: 22786 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64303/ : SUCCESS -- To view, visit https://review.coreboot.org/22604 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 18:43:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Make timC training more robust.
by Patrick Rudolph (Code Review) 08 Dec '17

08 Dec '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 2: I'll test it on my platform. Do you know why it has training errors ? Did you change one of the other timings until no more training erros occur ? Could try to change reg_c14_offset to see if it fixes the problem ? -- To view, visit https://review.coreboot.org/22776 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 18:25:25 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017