coreboot-gerrit December 2017

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Change in coreboot[master]: commonlib: Add timestamp codes for AGESA
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22797 ) Change subject: commonlib: Add timestamp codes for AGESA ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19146/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64332/ : SUCCESS -- To view, visit https://review.coreboot.org/22797 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Gerrit-Change-Number: 22797 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 17:59:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: commonlib: Add timestamp codes for AGESA
by Martin Roth (Code Review) 09 Dec '17

09 Dec '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22797 Change subject: commonlib: Add timestamp codes for AGESA ...................................................................... commonlib: Add timestamp codes for AGESA BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22797/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 6c8d955..82ca064 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -77,6 +77,22 @@ TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, + /* 900-920 reserved for vendorcode extensions (900-920: AMD AGESA) */ + TS_AGESA_INIT_RESET_START = 900, + TS_AGESA_INIT_RESET_DONE = 901, + TS_AGESA_INIT_EARLY_START = 902, + TS_AGESA_INIT_EARLY_DONE = 903, + TS_AGESA_INIT_POST_START = 904, + TS_AGESA_INIT_POST_DONE = 905, + TS_AGESA_INIT_ENV_START = 906, + TS_AGESA_INIT_ENV_DONE = 907, + TS_AGESA_INIT_MID_START = 908, + TS_AGESA_INIT_MID_DONE = 909, + TS_AGESA_INIT_LATE_START = 910, + TS_AGESA_INIT_LATE_DONE = 911, + TS_AGESA_INIT_RTB_START = 912, + TS_AGESA_INIT_RTB_DONE = 913, + /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ TS_ME_INFORM_DRAM_WAIT = 940, TS_ME_INFORM_DRAM_DONE = 941, @@ -181,6 +197,22 @@ { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, { TS_START_KERNEL, "jumping to kernel" }, + /* AMD AGESA related timestamps */ + { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" }, + { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" }, + { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" }, + { TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" }, + { TS_AGESA_INIT_POST_START, "calling AmdInitPost" }, + { TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" }, + { TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" }, + { TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" }, + { TS_AGESA_INIT_MID_START, "calling AmdInitMid" }, + { TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" }, + { TS_AGESA_INIT_LATE_START, "calling AmdInitLate" }, + { TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" }, + { TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" }, + { TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" }, + /* Intel ME related timestamps */ { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, -- To view, visit https://review.coreboot.org/22797 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6 Gerrit-Change-Number: 22797 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/common: Collect timestamps before and after AGESA calls
by Martin Roth (Code Review) 09 Dec '17

09 Dec '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22798 Change subject: soc/amd/common: Collect timestamps before and after AGESA calls ...................................................................... soc/amd/common: Collect timestamps before and after AGESA calls BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/agesawrapper.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/22798/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index b939183..6d8796c 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -20,6 +20,7 @@ #include <cpu/x86/mtrr.h> #include <BiosCallOuts.h> #include <string.h> +#include <timestamp.h> void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -62,7 +63,10 @@ AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); + timestamp_add_now(TS_AGESA_INIT_RESET_START); status = AmdInitReset(&AmdResetParams); + timestamp_add_now(TS_AGESA_INIT_RESET_DONE); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -88,7 +92,10 @@ OemCustomizeInitEarly (AmdEarlyParamsPtr); AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; + + timestamp_add_now(TS_AGESA_INIT_EARLY_START); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); @@ -127,7 +134,9 @@ "unknown" ); + timestamp_add_now(TS_AGESA_INIT_POST_START); status = AmdInitPost (PostParams); + timestamp_add_now(TS_AGESA_INIT_POST_DONE); /* If UMA is enabled we currently have it below TOP_MEM as well. * UMA may or may not be cacheable, so Sub4GCacheTop could be @@ -189,7 +198,10 @@ EnvParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3); EnvParam->GnbEnvConfiguration.IommuSupport = FALSE; + timestamp_add_now(TS_AGESA_INIT_ENV_START); status = AmdInitEnv (EnvParam); + timestamp_add_now(TS_AGESA_INIT_ENV_DONE); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code @@ -257,7 +269,10 @@ MidParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); MidParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3); + timestamp_add_now(TS_AGESA_INIT_MID_START); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + timestamp_add_now(TS_AGESA_INIT_MID_DONE); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); @@ -284,7 +299,11 @@ /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + + timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = AmdInitLate(AmdLateParams); + timestamp_add_now(TS_AGESA_INIT_LATE_DONE); + if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); -- To view, visit https://review.coreboot.org/22798 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be Gerrit-Change-Number: 22798 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/intel/glkrvp: Add gpio.h in dsdt.asl file
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22760 ) Change subject: mb/intel/glkrvp: Add gpio.h in dsdt.asl file ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64331/ : SUCCESS -- To view, visit https://review.coreboot.org/22760 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9 Gerrit-Change-Number: 22760 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 17:23:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: inteltool: Support for nasty Primary to Sideband Bridge (P2SB)
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19588 ) Change subject: inteltool: Support for nasty Primary to Sideband Bridge (P2SB) ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19145/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64330/ : SUCCESS -- To view, visit https://review.coreboot.org/19588 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Gerrit-Change-Number: 19588 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 16:38:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: inteltool: Dump Sunrise Point PCH-H GPIO groups
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19589 ) Change subject: inteltool: Dump Sunrise Point PCH-H GPIO groups ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19144/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64329/ : SUCCESS -- To view, visit https://review.coreboot.org/19589 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Gerrit-Change-Number: 19589 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 16:32:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8/acpi: Move ACPI HKEY device to new file
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22463 ) Change subject: ec/lenovo/h8/acpi: Move ACPI HKEY device to new file ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64327/ : SUCCESS -- To view, visit https://review.coreboot.org/22463 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e Gerrit-Change-Number: 22463 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 12:03:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add Dell Inspiron 660s
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22682 ) Change subject: mainboard: Add Dell Inspiron 660s ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19143/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64328/ : SUCCESS -- To view, visit https://review.coreboot.org/22682 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Gerrit-Change-Number: 22682 Gerrit-PatchSet: 7 Gerrit-Owner: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 11:59:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t430/acpi_tables: Don't set flvl
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22796 ) Change subject: mb/lenovo/t430/acpi_tables: Don't set flvl ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19142/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64326/ : SUCCESS -- To view, visit https://review.coreboot.org/22796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6 Gerrit-Change-Number: 22796 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 11:41:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t430/acpi_tables: Don't set flvl
by Patrick Rudolph (Code Review) 09 Dec '17

09 Dec '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22796 Change subject: mb/lenovo/t430/acpi_tables: Don't set flvl ...................................................................... mb/lenovo/t430/acpi_tables: Don't set flvl The current fan level should be zero at boot and only be modified by ACPI or SMI code. Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/t430/acpi_tables.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/22796/1 diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c index c5559af..5caa3d4 100644 --- a/src/mainboard/lenovo/t430/acpi_tables.c +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -29,7 +29,6 @@ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 5; } void acpi_create_gnvs(global_nvs_t *gnvs) -- To view, visit https://review.coreboot.org/22796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6 Gerrit-Change-Number: 22796 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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coreboot-gerrit December 2017