coreboot-gerrit December 2017

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Change in coreboot[master]: sb/intel/i82801ix: Automatically generate pirq ACPI
by Arthur Heymans (Code Review) 10 Dec '17

10 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22802 to look at the new patch set (#2). Change subject: sb/intel/i82801ix: Automatically generate pirq ACPI ...................................................................... sb/intel/i82801ix: Automatically generate pirq ACPI This is quite generic and could probably be used for most Intel Southbridges. Change-Id: Iee38eaee8d443286cdcecc4f9df0b713639da669 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/southbridge/intel/i82801ix/lpc.c 5 files changed, 91 insertions(+), 243 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/22802/2 -- To view, visit https://review.coreboot.org/22802 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iee38eaee8d443286cdcecc4f9df0b713639da669 Gerrit-Change-Number: 22802 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP/NOTFORMERGE]sb/intel/i82801ix: Automatically generate pirq ACPI
by build bot (Jenkins) (Code Review) 10 Dec '17

10 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22802 ) Change subject: [WIP/NOTFORMERGE]sb/intel/i82801ix: Automatically generate pirq ACPI ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19151/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64337/ : SUCCESS -- To view, visit https://review.coreboot.org/22802 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee38eaee8d443286cdcecc4f9df0b713639da669 Gerrit-Change-Number: 22802 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Dec 2017 12:05:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP/NOTFORMERGE]sb/intel/i82801ix: Automatically generate pirq ACPI
by Arthur Heymans (Code Review) 10 Dec '17

10 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22802 Change subject: [WIP/NOTFORMERGE]sb/intel/i82801ix: Automatically generate pirq ACPI ...................................................................... [WIP/NOTFORMERGE]sb/intel/i82801ix: Automatically generate pirq ACPI Does not work at all... Change-Id: Iee38eaee8d443286cdcecc4f9df0b713639da669 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801ix/lpc.c 1 file changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/22802/1 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bc45b9d..65d6dae 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -562,8 +562,53 @@ { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; + device_t irq_dev; + u8 int_pin; + + const char *link_list[4] = {"\\_SB.PCI0.LPCB.LNKA", + "\\_SB.PCI0.LPCB.LNKB", + "\\_SB.PCI0.LPCB.LNKC", + "\\_SB.PCI0.LPCB.LNKD"}; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + + acpigen_write_scope("\\_SB"); + acpigen_write_device("PCI0"); + acpigen_write_method("_PRT", 0); + acpigen_write_if(); + acpigen_emit_namestring("PICM"); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(PACKAGE_OP); + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + acpigen_write_package(4); + acpigen_emit_dword((((irq_dev->bus->secondary >> 11) & 0x1f) << 16) & 0xffff); + acpigen_emit_dword(int_pin); + acpigen_emit_dword(0); + acpigen_emit_dword(16 + (int_pin - 1)); + acpigen_pop_len(); + } + acpigen_pop_len(); /* package */ + acpigen_pop_len(); /* return PICM */ + acpigen_pop_len(); /* if PICM */ + acpigen_write_else(); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(PACKAGE_OP); + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + acpigen_write_package(4); + acpigen_emit_dword((((irq_dev->bus->secondary >> 11) & 0x1f) << 16) & 0xffff); + acpigen_emit_dword(int_pin); + acpigen_write_string(link_list[int_pin - 1]); + acpigen_emit_dword(0); + acpigen_pop_len(); + } + acpigen_pop_len(); /* package */ + acpigen_pop_len(); /* return else PICM */ + acpigen_pop_len(); /* else PICM*/ + acpigen_pop_len(); /* _PRT */ + acpigen_pop_len(); /* PCI0 */ + acpigen_pop_len(); /* \_SB */ } static struct pci_operations pci_ops = { -- To view, visit https://review.coreboot.org/22802 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee38eaee8d443286cdcecc4f9df0b713639da669 Gerrit-Change-Number: 22802 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre...
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19149/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64335/ : SUCCESS -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 2 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 22:22:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre...
by Abhay Kumar (Code Review) 09 Dec '17

09 Dec '17

Hello build bot (Jenkins), Lijian Zhao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/22799 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics ...................................................................... soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics Incase of Normal mode or when Pre-os graphics not Loaded. Enabled DDI-A (eDP). TEST=Edp should come up in normal mode. Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- M src/soc/intel/cannonlake/graphics.c 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/22799/2 -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 2 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS grap...
by Lijian Zhao (Code Review) 09 Dec '17

09 Dec '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/22799/1/src/soc/intel/cannonlake/graphics.c File src/soc/intel/cannonlake/graphics.c: https://review.coreboot.org/#/c/22799/1/src/soc/intel/cannonlake/graphics.c… PS1, Line 33: u32 ddi_buf_ctl; uint32_t https://review.coreboot.org/#/c/22799/1/src/soc/intel/cannonlake/graphics.c… PS1, Line 59: u32 reg32 = pci_read_config32(dev, PCI_COMMAND); uint32_t -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 1 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 21:55:26 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS grap...
by Lijian Zhao (Code Review) 09 Dec '17

09 Dec '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/22799/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/22799/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. More than 80 col. https://review.coreboot.org/#/c/22799/1//COMMIT_MSG@8 PS1, Line 8: Please add detail explanation here. -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 1 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 21:54:18 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS grap...
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19148/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64334/ : SUCCESS -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 1 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 18:21:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS grap...
by Abhay Kumar (Code Review) 09 Dec '17

09 Dec '17

Abhay Kumar has uploaded this change for review. ( https://review.coreboot.org/22799 Change subject: soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. ...................................................................... soc/intel/cannonlake: Initialize DDI-A lane in absence of Pre-OS graphics. TEST=Edp should come up in normal mode. Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- M src/soc/intel/cannonlake/graphics.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/22799/1 diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 5cf0ec8..6e1142a 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -21,12 +21,49 @@ #include <device/pci.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> +#include <drivers/intel/gma/i915_reg.h> uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } +void graphics_soc_init(struct device *dev) +{ + u32 ddi_buf_ctl; + + /* + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. + * This will allow the kernel to use 4-lane eDP links properly + * if the VBIOS or GOP driver does not execute. + */ + ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { + ddi_buf_ctl |= DDI_A_4_LANES; + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); + } + + /* + * GFX PEIM module inside FSP binary is taking care of graphics + * initialization based on INTEL_GMA_ADD_VBT_DATA_FILE Kconfig + * option and input VBT file. Hence no need to load/execute legacy VGA + * OpROM in order to initialize GFX. + * + * In case of non-FSP solution, SoC need to select VGA_ROM_RUN + * Kconfig to perform GFX initialization through VGA OpRom. + */ + if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) + return; + + /* IGD needs to Bus Master */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); +} + uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { -- To view, visit https://review.coreboot.org/22799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 1 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com>

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Change in coreboot[master]: soc/amd/common: Collect timestamps before and after AGESA calls
by build bot (Jenkins) (Code Review) 09 Dec '17

09 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22798 ) Change subject: soc/amd/common: Collect timestamps before and after AGESA calls ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19147/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64333/ : SUCCESS -- To view, visit https://review.coreboot.org/22798 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be Gerrit-Change-Number: 22798 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Dec 2017 18:02:22 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017